Commit | Line | Data |
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b504882d | 1 | /* |
58c559e6 | 2 | * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc. |
ea437f39 | 3 | * All rights reserved. |
b504882d LY |
4 | * |
5 | * Author: Li Yang <leoli@freescale.com> | |
6 | * Jiang Bo <tanya.jiang@freescale.com> | |
7 | * | |
8 | * Description: | |
9 | * Freescale high-speed USB SOC DR module device controller driver. | |
2ea6698d | 10 | * This can be found on MPC8349E/MPC8313E/MPC5121E cpus. |
b504882d LY |
11 | * The driver is previously named as mpc_udc. Based on bare board |
12 | * code from Dave Liu and Shlomi Gridish. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of the GNU General Public License as published by the | |
16 | * Free Software Foundation; either version 2 of the License, or (at your | |
17 | * option) any later version. | |
18 | */ | |
19 | ||
20 | #undef VERBOSE | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/errno.h> | |
ded017ee | 27 | #include <linux/err.h> |
b504882d LY |
28 | #include <linux/slab.h> |
29 | #include <linux/init.h> | |
b504882d LY |
30 | #include <linux/list.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/proc_fs.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/device.h> | |
36 | #include <linux/usb/ch9.h> | |
9454a57a | 37 | #include <linux/usb/gadget.h> |
b504882d LY |
38 | #include <linux/usb/otg.h> |
39 | #include <linux/dma-mapping.h> | |
40 | #include <linux/platform_device.h> | |
41 | #include <linux/fsl_devices.h> | |
42 | #include <linux/dmapool.h> | |
54e4026b | 43 | #include <linux/delay.h> |
b504882d LY |
44 | |
45 | #include <asm/byteorder.h> | |
46 | #include <asm/io.h> | |
b504882d LY |
47 | #include <asm/unaligned.h> |
48 | #include <asm/dma.h> | |
b504882d LY |
49 | |
50 | #include "fsl_usb2_udc.h" | |
51 | ||
52 | #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver" | |
53 | #define DRIVER_AUTHOR "Li Yang/Jiang Bo" | |
54 | #define DRIVER_VERSION "Apr 20, 2007" | |
55 | ||
56 | #define DMA_ADDR_INVALID (~(dma_addr_t)0) | |
57 | ||
58 | static const char driver_name[] = "fsl-usb2-udc"; | |
59 | static const char driver_desc[] = DRIVER_DESC; | |
60 | ||
7483cff8 | 61 | static struct usb_dr_device *dr_regs; |
58c559e6 | 62 | |
7483cff8 | 63 | static struct usb_sys_interface *usb_sys_regs; |
b504882d LY |
64 | |
65 | /* it is initialized in probe() */ | |
66 | static struct fsl_udc *udc_controller = NULL; | |
67 | ||
68 | static const struct usb_endpoint_descriptor | |
69 | fsl_ep0_desc = { | |
70 | .bLength = USB_DT_ENDPOINT_SIZE, | |
71 | .bDescriptorType = USB_DT_ENDPOINT, | |
72 | .bEndpointAddress = 0, | |
73 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
74 | .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD, | |
75 | }; | |
76 | ||
b504882d LY |
77 | static void fsl_ep_fifo_flush(struct usb_ep *_ep); |
78 | ||
79 | #ifdef CONFIG_PPC32 | |
09ba0def AG |
80 | /* |
81 | * On some SoCs, the USB controller registers can be big or little endian, | |
82 | * depending on the version of the chip. In order to be able to run the | |
83 | * same kernel binary on 2 different versions of an SoC, the BE/LE decision | |
84 | * must be made at run time. _fsl_readl and fsl_writel are pointers to the | |
85 | * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel() | |
86 | * call through those pointers. Platform code for SoCs that have BE USB | |
87 | * registers should set pdata->big_endian_mmio flag. | |
88 | * | |
89 | * This also applies to controller-to-cpu accessors for the USB descriptors, | |
90 | * since their endianness is also SoC dependant. Platform code for SoCs that | |
91 | * have BE USB descriptors should set pdata->big_endian_desc flag. | |
92 | */ | |
93 | static u32 _fsl_readl_be(const unsigned __iomem *p) | |
94 | { | |
95 | return in_be32(p); | |
96 | } | |
97 | ||
98 | static u32 _fsl_readl_le(const unsigned __iomem *p) | |
99 | { | |
100 | return in_le32(p); | |
101 | } | |
102 | ||
103 | static void _fsl_writel_be(u32 v, unsigned __iomem *p) | |
104 | { | |
105 | out_be32(p, v); | |
106 | } | |
107 | ||
108 | static void _fsl_writel_le(u32 v, unsigned __iomem *p) | |
109 | { | |
110 | out_le32(p, v); | |
111 | } | |
112 | ||
113 | static u32 (*_fsl_readl)(const unsigned __iomem *p); | |
114 | static void (*_fsl_writel)(u32 v, unsigned __iomem *p); | |
115 | ||
116 | #define fsl_readl(p) (*_fsl_readl)((p)) | |
117 | #define fsl_writel(v, p) (*_fsl_writel)((v), (p)) | |
118 | ||
3140d5b2 AG |
119 | static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) |
120 | { | |
121 | if (pdata->big_endian_mmio) { | |
122 | _fsl_readl = _fsl_readl_be; | |
123 | _fsl_writel = _fsl_writel_be; | |
124 | } else { | |
125 | _fsl_readl = _fsl_readl_le; | |
126 | _fsl_writel = _fsl_writel_le; | |
127 | } | |
128 | } | |
129 | ||
09ba0def AG |
130 | static inline u32 cpu_to_hc32(const u32 x) |
131 | { | |
132 | return udc_controller->pdata->big_endian_desc | |
133 | ? (__force u32)cpu_to_be32(x) | |
134 | : (__force u32)cpu_to_le32(x); | |
135 | } | |
136 | ||
137 | static inline u32 hc32_to_cpu(const u32 x) | |
138 | { | |
139 | return udc_controller->pdata->big_endian_desc | |
140 | ? be32_to_cpu((__force __be32)x) | |
141 | : le32_to_cpu((__force __le32)x); | |
142 | } | |
143 | #else /* !CONFIG_PPC32 */ | |
3140d5b2 AG |
144 | static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {} |
145 | ||
b504882d | 146 | #define fsl_readl(addr) readl(addr) |
c93eebbe | 147 | #define fsl_writel(val32, addr) writel(val32, addr) |
09ba0def AG |
148 | #define cpu_to_hc32(x) cpu_to_le32(x) |
149 | #define hc32_to_cpu(x) le32_to_cpu(x) | |
150 | #endif /* CONFIG_PPC32 */ | |
b504882d LY |
151 | |
152 | /******************************************************************** | |
153 | * Internal Used Function | |
154 | ********************************************************************/ | |
155 | /*----------------------------------------------------------------- | |
156 | * done() - retire a request; caller blocked irqs | |
157 | * @status : request status to be set, only works when | |
158 | * request is still in progress. | |
159 | *--------------------------------------------------------------*/ | |
160 | static void done(struct fsl_ep *ep, struct fsl_req *req, int status) | |
161 | { | |
162 | struct fsl_udc *udc = NULL; | |
163 | unsigned char stopped = ep->stopped; | |
164 | struct ep_td_struct *curr_td, *next_td; | |
165 | int j; | |
166 | ||
167 | udc = (struct fsl_udc *)ep->udc; | |
168 | /* Removed the req from fsl_ep->queue */ | |
169 | list_del_init(&req->queue); | |
170 | ||
171 | /* req.status should be set as -EINPROGRESS in ep_queue() */ | |
172 | if (req->req.status == -EINPROGRESS) | |
173 | req->req.status = status; | |
174 | else | |
175 | status = req->req.status; | |
176 | ||
177 | /* Free dtd for the request */ | |
178 | next_td = req->head; | |
179 | for (j = 0; j < req->dtd_count; j++) { | |
180 | curr_td = next_td; | |
181 | if (j != req->dtd_count - 1) { | |
182 | next_td = curr_td->next_td_virt; | |
183 | } | |
184 | dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma); | |
185 | } | |
186 | ||
187 | if (req->mapped) { | |
188 | dma_unmap_single(ep->udc->gadget.dev.parent, | |
189 | req->req.dma, req->req.length, | |
190 | ep_is_in(ep) | |
191 | ? DMA_TO_DEVICE | |
192 | : DMA_FROM_DEVICE); | |
193 | req->req.dma = DMA_ADDR_INVALID; | |
194 | req->mapped = 0; | |
195 | } else | |
196 | dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, | |
197 | req->req.dma, req->req.length, | |
198 | ep_is_in(ep) | |
199 | ? DMA_TO_DEVICE | |
200 | : DMA_FROM_DEVICE); | |
201 | ||
202 | if (status && (status != -ESHUTDOWN)) | |
203 | VDBG("complete %s req %p stat %d len %u/%u", | |
204 | ep->ep.name, &req->req, status, | |
205 | req->req.actual, req->req.length); | |
206 | ||
207 | ep->stopped = 1; | |
208 | ||
209 | spin_unlock(&ep->udc->lock); | |
210 | /* complete() is from gadget layer, | |
211 | * eg fsg->bulk_in_complete() */ | |
212 | if (req->req.complete) | |
213 | req->req.complete(&ep->ep, &req->req); | |
214 | ||
215 | spin_lock(&ep->udc->lock); | |
216 | ep->stopped = stopped; | |
217 | } | |
218 | ||
219 | /*----------------------------------------------------------------- | |
220 | * nuke(): delete all requests related to this ep | |
221 | * called with spinlock held | |
222 | *--------------------------------------------------------------*/ | |
223 | static void nuke(struct fsl_ep *ep, int status) | |
224 | { | |
225 | ep->stopped = 1; | |
226 | ||
227 | /* Flush fifo */ | |
228 | fsl_ep_fifo_flush(&ep->ep); | |
229 | ||
230 | /* Whether this eq has request linked */ | |
231 | while (!list_empty(&ep->queue)) { | |
232 | struct fsl_req *req = NULL; | |
233 | ||
234 | req = list_entry(ep->queue.next, struct fsl_req, queue); | |
235 | done(ep, req, status); | |
236 | } | |
237 | } | |
238 | ||
239 | /*------------------------------------------------------------------ | |
240 | Internal Hardware related function | |
241 | ------------------------------------------------------------------*/ | |
242 | ||
243 | static int dr_controller_setup(struct fsl_udc *udc) | |
244 | { | |
ea437f39 RM |
245 | unsigned int tmp, portctrl, ep_num; |
246 | unsigned int max_no_of_ep; | |
54e4026b | 247 | unsigned int ctrl; |
b504882d | 248 | unsigned long timeout; |
58c559e6 | 249 | |
b504882d LY |
250 | #define FSL_UDC_RESET_TIMEOUT 1000 |
251 | ||
54e4026b GL |
252 | /* Config PHY interface */ |
253 | portctrl = fsl_readl(&dr_regs->portsc1); | |
254 | portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH); | |
255 | switch (udc->phy_mode) { | |
256 | case FSL_USB2_PHY_ULPI: | |
58c559e6 RM |
257 | if (udc->pdata->have_sysif_regs) { |
258 | if (udc->pdata->controller_ver) { | |
259 | /* controller version 1.6 or above */ | |
260 | ctrl = __raw_readl(&usb_sys_regs->control); | |
261 | ctrl &= ~USB_CTRL_UTMI_PHY_EN; | |
262 | ctrl |= USB_CTRL_USB_EN; | |
263 | __raw_writel(ctrl, &usb_sys_regs->control); | |
264 | } | |
265 | } | |
54e4026b GL |
266 | portctrl |= PORTSCX_PTS_ULPI; |
267 | break; | |
268 | case FSL_USB2_PHY_UTMI_WIDE: | |
269 | portctrl |= PORTSCX_PTW_16BIT; | |
270 | /* fall through */ | |
271 | case FSL_USB2_PHY_UTMI: | |
58c559e6 RM |
272 | if (udc->pdata->have_sysif_regs) { |
273 | if (udc->pdata->controller_ver) { | |
274 | /* controller version 1.6 or above */ | |
275 | ctrl = __raw_readl(&usb_sys_regs->control); | |
276 | ctrl |= (USB_CTRL_UTMI_PHY_EN | | |
277 | USB_CTRL_USB_EN); | |
278 | __raw_writel(ctrl, &usb_sys_regs->control); | |
279 | mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI | |
280 | PHY CLK to become stable - 10ms*/ | |
281 | } | |
282 | } | |
54e4026b GL |
283 | portctrl |= PORTSCX_PTS_UTMI; |
284 | break; | |
285 | case FSL_USB2_PHY_SERIAL: | |
286 | portctrl |= PORTSCX_PTS_FSLS; | |
287 | break; | |
288 | default: | |
289 | return -EINVAL; | |
290 | } | |
291 | fsl_writel(portctrl, &dr_regs->portsc1); | |
292 | ||
b504882d LY |
293 | /* Stop and reset the usb controller */ |
294 | tmp = fsl_readl(&dr_regs->usbcmd); | |
295 | tmp &= ~USB_CMD_RUN_STOP; | |
296 | fsl_writel(tmp, &dr_regs->usbcmd); | |
297 | ||
298 | tmp = fsl_readl(&dr_regs->usbcmd); | |
299 | tmp |= USB_CMD_CTRL_RESET; | |
300 | fsl_writel(tmp, &dr_regs->usbcmd); | |
301 | ||
302 | /* Wait for reset to complete */ | |
303 | timeout = jiffies + FSL_UDC_RESET_TIMEOUT; | |
304 | while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { | |
305 | if (time_after(jiffies, timeout)) { | |
bf7409a2 | 306 | ERR("udc reset timeout!\n"); |
b504882d LY |
307 | return -ETIMEDOUT; |
308 | } | |
309 | cpu_relax(); | |
310 | } | |
311 | ||
312 | /* Set the controller as device mode */ | |
313 | tmp = fsl_readl(&dr_regs->usbmode); | |
2ea6698d | 314 | tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */ |
b504882d LY |
315 | tmp |= USB_MODE_CTRL_MODE_DEVICE; |
316 | /* Disable Setup Lockout */ | |
317 | tmp |= USB_MODE_SETUP_LOCK_OFF; | |
2ea6698d AG |
318 | if (udc->pdata->es) |
319 | tmp |= USB_MODE_ES; | |
b504882d LY |
320 | fsl_writel(tmp, &dr_regs->usbmode); |
321 | ||
322 | /* Clear the setup status */ | |
323 | fsl_writel(0, &dr_regs->usbsts); | |
324 | ||
325 | tmp = udc->ep_qh_dma; | |
326 | tmp &= USB_EP_LIST_ADDRESS_MASK; | |
327 | fsl_writel(tmp, &dr_regs->endpointlistaddr); | |
328 | ||
329 | VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x", | |
6ef65a7f | 330 | udc->ep_qh, (int)tmp, |
b504882d LY |
331 | fsl_readl(&dr_regs->endpointlistaddr)); |
332 | ||
ea437f39 RM |
333 | max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams)); |
334 | for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) { | |
335 | tmp = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
336 | tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE); | |
337 | tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT) | |
338 | | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT); | |
339 | fsl_writel(tmp, &dr_regs->endptctrl[ep_num]); | |
340 | } | |
b504882d | 341 | /* Config control enable i/o output, cpu endian register */ |
54e4026b | 342 | #ifndef CONFIG_ARCH_MXC |
2ea6698d AG |
343 | if (udc->pdata->have_sysif_regs) { |
344 | ctrl = __raw_readl(&usb_sys_regs->control); | |
345 | ctrl |= USB_CTRL_IOENB; | |
346 | __raw_writel(ctrl, &usb_sys_regs->control); | |
347 | } | |
54e4026b | 348 | #endif |
b504882d LY |
349 | |
350 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
351 | /* Turn on cache snooping hardware, since some PowerPC platforms | |
352 | * wholly rely on hardware to deal with cache coherent. */ | |
353 | ||
2ea6698d AG |
354 | if (udc->pdata->have_sysif_regs) { |
355 | /* Setup Snooping for all the 4GB space */ | |
356 | tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */ | |
357 | __raw_writel(tmp, &usb_sys_regs->snoop1); | |
358 | tmp |= 0x80000000; /* starts from 0x8000000, size 2G */ | |
359 | __raw_writel(tmp, &usb_sys_regs->snoop2); | |
360 | } | |
b504882d LY |
361 | #endif |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | /* Enable DR irq and set controller to run state */ | |
367 | static void dr_controller_run(struct fsl_udc *udc) | |
368 | { | |
369 | u32 temp; | |
370 | ||
371 | /* Enable DR irq reg */ | |
372 | temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN | |
373 | | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN | |
374 | | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN; | |
375 | ||
376 | fsl_writel(temp, &dr_regs->usbintr); | |
377 | ||
378 | /* Clear stopped bit */ | |
379 | udc->stopped = 0; | |
380 | ||
381 | /* Set the controller as device mode */ | |
382 | temp = fsl_readl(&dr_regs->usbmode); | |
383 | temp |= USB_MODE_CTRL_MODE_DEVICE; | |
384 | fsl_writel(temp, &dr_regs->usbmode); | |
385 | ||
386 | /* Set controller to Run */ | |
387 | temp = fsl_readl(&dr_regs->usbcmd); | |
388 | temp |= USB_CMD_RUN_STOP; | |
389 | fsl_writel(temp, &dr_regs->usbcmd); | |
b504882d LY |
390 | } |
391 | ||
392 | static void dr_controller_stop(struct fsl_udc *udc) | |
393 | { | |
394 | unsigned int tmp; | |
395 | ||
83722bc9 AG |
396 | pr_debug("%s\n", __func__); |
397 | ||
398 | /* if we're in OTG mode, and the Host is currently using the port, | |
399 | * stop now and don't rip the controller out from under the | |
400 | * ehci driver | |
401 | */ | |
402 | if (udc->gadget.is_otg) { | |
403 | if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) { | |
404 | pr_debug("udc: Leaving early\n"); | |
405 | return; | |
406 | } | |
407 | } | |
408 | ||
b504882d LY |
409 | /* disable all INTR */ |
410 | fsl_writel(0, &dr_regs->usbintr); | |
411 | ||
412 | /* Set stopped bit for isr */ | |
413 | udc->stopped = 1; | |
414 | ||
415 | /* disable IO output */ | |
416 | /* usb_sys_regs->control = 0; */ | |
417 | ||
418 | /* set controller to Stop */ | |
419 | tmp = fsl_readl(&dr_regs->usbcmd); | |
420 | tmp &= ~USB_CMD_RUN_STOP; | |
421 | fsl_writel(tmp, &dr_regs->usbcmd); | |
b504882d LY |
422 | } |
423 | ||
9c94155e WN |
424 | static void dr_ep_setup(unsigned char ep_num, unsigned char dir, |
425 | unsigned char ep_type) | |
b504882d LY |
426 | { |
427 | unsigned int tmp_epctrl = 0; | |
428 | ||
429 | tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
430 | if (dir) { | |
431 | if (ep_num) | |
432 | tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; | |
433 | tmp_epctrl |= EPCTRL_TX_ENABLE; | |
ea437f39 | 434 | tmp_epctrl &= ~EPCTRL_TX_TYPE; |
b504882d LY |
435 | tmp_epctrl |= ((unsigned int)(ep_type) |
436 | << EPCTRL_TX_EP_TYPE_SHIFT); | |
437 | } else { | |
438 | if (ep_num) | |
439 | tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; | |
440 | tmp_epctrl |= EPCTRL_RX_ENABLE; | |
ea437f39 | 441 | tmp_epctrl &= ~EPCTRL_RX_TYPE; |
b504882d LY |
442 | tmp_epctrl |= ((unsigned int)(ep_type) |
443 | << EPCTRL_RX_EP_TYPE_SHIFT); | |
444 | } | |
445 | ||
446 | fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); | |
447 | } | |
448 | ||
449 | static void | |
450 | dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value) | |
451 | { | |
452 | u32 tmp_epctrl = 0; | |
453 | ||
454 | tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
455 | ||
456 | if (value) { | |
457 | /* set the stall bit */ | |
458 | if (dir) | |
459 | tmp_epctrl |= EPCTRL_TX_EP_STALL; | |
460 | else | |
461 | tmp_epctrl |= EPCTRL_RX_EP_STALL; | |
462 | } else { | |
463 | /* clear the stall bit and reset data toggle */ | |
464 | if (dir) { | |
465 | tmp_epctrl &= ~EPCTRL_TX_EP_STALL; | |
466 | tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; | |
467 | } else { | |
468 | tmp_epctrl &= ~EPCTRL_RX_EP_STALL; | |
469 | tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; | |
470 | } | |
471 | } | |
472 | fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); | |
473 | } | |
474 | ||
475 | /* Get stall status of a specific ep | |
476 | Return: 0: not stalled; 1:stalled */ | |
477 | static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir) | |
478 | { | |
479 | u32 epctrl; | |
480 | ||
481 | epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
482 | if (dir) | |
483 | return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0; | |
484 | else | |
485 | return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0; | |
486 | } | |
487 | ||
488 | /******************************************************************** | |
489 | Internal Structure Build up functions | |
490 | ********************************************************************/ | |
491 | ||
492 | /*------------------------------------------------------------------ | |
493 | * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH | |
494 | * @zlt: Zero Length Termination Select (1: disable; 0: enable) | |
495 | * @mult: Mult field | |
496 | ------------------------------------------------------------------*/ | |
497 | static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num, | |
498 | unsigned char dir, unsigned char ep_type, | |
499 | unsigned int max_pkt_len, | |
500 | unsigned int zlt, unsigned char mult) | |
501 | { | |
502 | struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir]; | |
503 | unsigned int tmp = 0; | |
504 | ||
505 | /* set the Endpoint Capabilites in QH */ | |
506 | switch (ep_type) { | |
507 | case USB_ENDPOINT_XFER_CONTROL: | |
508 | /* Interrupt On Setup (IOS). for control ep */ | |
509 | tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) | |
510 | | EP_QUEUE_HEAD_IOS; | |
511 | break; | |
512 | case USB_ENDPOINT_XFER_ISOC: | |
513 | tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) | |
514 | | (mult << EP_QUEUE_HEAD_MULT_POS); | |
515 | break; | |
516 | case USB_ENDPOINT_XFER_BULK: | |
517 | case USB_ENDPOINT_XFER_INT: | |
518 | tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS; | |
519 | break; | |
520 | default: | |
521 | VDBG("error ep type is %d", ep_type); | |
522 | return; | |
523 | } | |
524 | if (zlt) | |
525 | tmp |= EP_QUEUE_HEAD_ZLT_SEL; | |
9a6e184c | 526 | |
09ba0def | 527 | p_QH->max_pkt_length = cpu_to_hc32(tmp); |
9a6e184c LY |
528 | p_QH->next_dtd_ptr = 1; |
529 | p_QH->size_ioc_int_sts = 0; | |
b504882d LY |
530 | } |
531 | ||
532 | /* Setup qh structure and ep register for ep0. */ | |
533 | static void ep0_setup(struct fsl_udc *udc) | |
534 | { | |
535 | /* the intialization of an ep includes: fields in QH, Regs, | |
536 | * fsl_ep struct */ | |
537 | struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL, | |
538 | USB_MAX_CTRL_PAYLOAD, 0, 0); | |
539 | struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL, | |
540 | USB_MAX_CTRL_PAYLOAD, 0, 0); | |
541 | dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL); | |
542 | dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL); | |
543 | ||
544 | return; | |
545 | ||
546 | } | |
547 | ||
548 | /*********************************************************************** | |
549 | Endpoint Management Functions | |
550 | ***********************************************************************/ | |
551 | ||
552 | /*------------------------------------------------------------------------- | |
553 | * when configurations are set, or when interface settings change | |
554 | * for example the do_set_interface() in gadget layer, | |
555 | * the driver will enable or disable the relevant endpoints | |
556 | * ep0 doesn't use this routine. It is always enabled. | |
557 | -------------------------------------------------------------------------*/ | |
558 | static int fsl_ep_enable(struct usb_ep *_ep, | |
559 | const struct usb_endpoint_descriptor *desc) | |
560 | { | |
561 | struct fsl_udc *udc = NULL; | |
562 | struct fsl_ep *ep = NULL; | |
563 | unsigned short max = 0; | |
564 | unsigned char mult = 0, zlt; | |
565 | int retval = -EINVAL; | |
566 | unsigned long flags = 0; | |
567 | ||
568 | ep = container_of(_ep, struct fsl_ep, ep); | |
569 | ||
570 | /* catch various bogus parameters */ | |
1fa75972 | 571 | if (!_ep || !desc |
b504882d LY |
572 | || (desc->bDescriptorType != USB_DT_ENDPOINT)) |
573 | return -EINVAL; | |
574 | ||
575 | udc = ep->udc; | |
576 | ||
577 | if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) | |
578 | return -ESHUTDOWN; | |
579 | ||
29cc8897 | 580 | max = usb_endpoint_maxp(desc); |
b504882d | 581 | |
25985edc | 582 | /* Disable automatic zlp generation. Driver is responsible to indicate |
b504882d LY |
583 | * explicitly through req->req.zero. This is needed to enable multi-td |
584 | * request. */ | |
585 | zlt = 1; | |
586 | ||
587 | /* Assume the max packet size from gadget is always correct */ | |
588 | switch (desc->bmAttributes & 0x03) { | |
589 | case USB_ENDPOINT_XFER_CONTROL: | |
590 | case USB_ENDPOINT_XFER_BULK: | |
591 | case USB_ENDPOINT_XFER_INT: | |
592 | /* mult = 0. Execute N Transactions as demonstrated by | |
593 | * the USB variable length packet protocol where N is | |
594 | * computed using the Maximum Packet Length (dQH) and | |
595 | * the Total Bytes field (dTD) */ | |
596 | mult = 0; | |
597 | break; | |
598 | case USB_ENDPOINT_XFER_ISOC: | |
599 | /* Calculate transactions needed for high bandwidth iso */ | |
600 | mult = (unsigned char)(1 + ((max >> 11) & 0x03)); | |
88e3b59b | 601 | max = max & 0x7ff; /* bit 0~10 */ |
b504882d LY |
602 | /* 3 transactions at most */ |
603 | if (mult > 3) | |
604 | goto en_done; | |
605 | break; | |
606 | default: | |
607 | goto en_done; | |
608 | } | |
609 | ||
610 | spin_lock_irqsave(&udc->lock, flags); | |
611 | ep->ep.maxpacket = max; | |
79149b8b | 612 | ep->ep.desc = desc; |
b504882d LY |
613 | ep->stopped = 0; |
614 | ||
615 | /* Controller related setup */ | |
616 | /* Init EPx Queue Head (Ep Capabilites field in QH | |
617 | * according to max, zlt, mult) */ | |
618 | struct_ep_qh_setup(udc, (unsigned char) ep_index(ep), | |
619 | (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) | |
620 | ? USB_SEND : USB_RECV), | |
621 | (unsigned char) (desc->bmAttributes | |
622 | & USB_ENDPOINT_XFERTYPE_MASK), | |
623 | max, zlt, mult); | |
624 | ||
625 | /* Init endpoint ctrl register */ | |
626 | dr_ep_setup((unsigned char) ep_index(ep), | |
627 | (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) | |
628 | ? USB_SEND : USB_RECV), | |
629 | (unsigned char) (desc->bmAttributes | |
630 | & USB_ENDPOINT_XFERTYPE_MASK)); | |
631 | ||
632 | spin_unlock_irqrestore(&udc->lock, flags); | |
633 | retval = 0; | |
634 | ||
635 | VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name, | |
79149b8b | 636 | ep->ep.desc->bEndpointAddress & 0x0f, |
b504882d LY |
637 | (desc->bEndpointAddress & USB_DIR_IN) |
638 | ? "in" : "out", max); | |
639 | en_done: | |
640 | return retval; | |
641 | } | |
642 | ||
643 | /*--------------------------------------------------------------------- | |
644 | * @ep : the ep being unconfigured. May not be ep0 | |
645 | * Any pending and uncomplete req will complete with status (-ESHUTDOWN) | |
646 | *---------------------------------------------------------------------*/ | |
647 | static int fsl_ep_disable(struct usb_ep *_ep) | |
648 | { | |
649 | struct fsl_udc *udc = NULL; | |
650 | struct fsl_ep *ep = NULL; | |
651 | unsigned long flags = 0; | |
652 | u32 epctrl; | |
653 | int ep_num; | |
654 | ||
655 | ep = container_of(_ep, struct fsl_ep, ep); | |
79149b8b | 656 | if (!_ep || !ep->ep.desc) { |
b504882d LY |
657 | VDBG("%s not enabled", _ep ? ep->ep.name : NULL); |
658 | return -EINVAL; | |
659 | } | |
660 | ||
661 | /* disable ep on controller */ | |
662 | ep_num = ep_index(ep); | |
663 | epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
ea437f39 RM |
664 | if (ep_is_in(ep)) { |
665 | epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE); | |
666 | epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT; | |
667 | } else { | |
668 | epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE); | |
669 | epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT; | |
670 | } | |
b504882d LY |
671 | fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); |
672 | ||
673 | udc = (struct fsl_udc *)ep->udc; | |
674 | spin_lock_irqsave(&udc->lock, flags); | |
675 | ||
676 | /* nuke all pending requests (does flush) */ | |
677 | nuke(ep, -ESHUTDOWN); | |
678 | ||
f9c56cdd | 679 | ep->ep.desc = NULL; |
b504882d LY |
680 | ep->stopped = 1; |
681 | spin_unlock_irqrestore(&udc->lock, flags); | |
682 | ||
683 | VDBG("disabled %s OK", _ep->name); | |
684 | return 0; | |
685 | } | |
686 | ||
687 | /*--------------------------------------------------------------------- | |
688 | * allocate a request object used by this endpoint | |
689 | * the main operation is to insert the req->queue to the eq->queue | |
690 | * Returns the request, or null if one could not be allocated | |
691 | *---------------------------------------------------------------------*/ | |
692 | static struct usb_request * | |
693 | fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) | |
694 | { | |
695 | struct fsl_req *req = NULL; | |
696 | ||
697 | req = kzalloc(sizeof *req, gfp_flags); | |
698 | if (!req) | |
699 | return NULL; | |
700 | ||
701 | req->req.dma = DMA_ADDR_INVALID; | |
702 | INIT_LIST_HEAD(&req->queue); | |
703 | ||
704 | return &req->req; | |
705 | } | |
706 | ||
707 | static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
708 | { | |
709 | struct fsl_req *req = NULL; | |
710 | ||
711 | req = container_of(_req, struct fsl_req, req); | |
712 | ||
713 | if (_req) | |
714 | kfree(req); | |
715 | } | |
716 | ||
6414e94c LY |
717 | /* Actually add a dTD chain to an empty dQH and let go */ |
718 | static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td) | |
719 | { | |
720 | struct ep_queue_head *qh = get_qh_by_ep(ep); | |
721 | ||
722 | /* Write dQH next pointer and terminate bit to 0 */ | |
723 | qh->next_dtd_ptr = cpu_to_hc32(td->td_dma | |
724 | & EP_QUEUE_HEAD_NEXT_POINTER_MASK); | |
725 | ||
726 | /* Clear active and halt bit */ | |
727 | qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE | |
728 | | EP_QUEUE_HEAD_STATUS_HALT)); | |
729 | ||
730 | /* Ensure that updates to the QH will occur before priming. */ | |
731 | wmb(); | |
732 | ||
733 | /* Prime endpoint by writing correct bit to ENDPTPRIME */ | |
734 | fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16)) | |
735 | : (1 << (ep_index(ep))), &dr_regs->endpointprime); | |
736 | } | |
737 | ||
738 | /* Add dTD chain to the dQH of an EP */ | |
224b5039 | 739 | static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) |
b504882d | 740 | { |
b504882d | 741 | u32 temp, bitmask, tmp_stat; |
b504882d LY |
742 | |
743 | /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr); | |
744 | VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */ | |
745 | ||
746 | bitmask = ep_is_in(ep) | |
747 | ? (1 << (ep_index(ep) + 16)) | |
748 | : (1 << (ep_index(ep))); | |
749 | ||
750 | /* check if the pipe is empty */ | |
f79a60b8 | 751 | if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) { |
b504882d LY |
752 | /* Add td to the end */ |
753 | struct fsl_req *lastreq; | |
754 | lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); | |
755 | lastreq->tail->next_td_ptr = | |
09ba0def | 756 | cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK); |
4d0947de PC |
757 | /* Ensure dTD's next dtd pointer to be updated */ |
758 | wmb(); | |
b504882d LY |
759 | /* Read prime bit, if 1 goto done */ |
760 | if (fsl_readl(&dr_regs->endpointprime) & bitmask) | |
6414e94c | 761 | return; |
b504882d LY |
762 | |
763 | do { | |
764 | /* Set ATDTW bit in USBCMD */ | |
765 | temp = fsl_readl(&dr_regs->usbcmd); | |
766 | fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd); | |
767 | ||
768 | /* Read correct status bit */ | |
769 | tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask; | |
770 | ||
771 | } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW)); | |
772 | ||
773 | /* Write ATDTW bit to 0 */ | |
774 | temp = fsl_readl(&dr_regs->usbcmd); | |
775 | fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd); | |
776 | ||
777 | if (tmp_stat) | |
6414e94c | 778 | return; |
b504882d LY |
779 | } |
780 | ||
6414e94c | 781 | fsl_prime_ep(ep, req->head); |
b504882d LY |
782 | } |
783 | ||
784 | /* Fill in the dTD structure | |
785 | * @req: request that the transfer belongs to | |
786 | * @length: return actually data length of the dTD | |
787 | * @dma: return dma address of the dTD | |
788 | * @is_last: return flag if it is the last dTD of the request | |
789 | * return: pointer to the built dTD */ | |
790 | static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length, | |
c5cc5ed8 | 791 | dma_addr_t *dma, int *is_last, gfp_t gfp_flags) |
b504882d LY |
792 | { |
793 | u32 swap_temp; | |
794 | struct ep_td_struct *dtd; | |
795 | ||
796 | /* how big will this transfer be? */ | |
797 | *length = min(req->req.length - req->req.actual, | |
798 | (unsigned)EP_MAX_LENGTH_TRANSFER); | |
799 | ||
c5cc5ed8 | 800 | dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma); |
b504882d LY |
801 | if (dtd == NULL) |
802 | return dtd; | |
803 | ||
804 | dtd->td_dma = *dma; | |
805 | /* Clear reserved field */ | |
09ba0def | 806 | swap_temp = hc32_to_cpu(dtd->size_ioc_sts); |
b504882d | 807 | swap_temp &= ~DTD_RESERVED_FIELDS; |
09ba0def | 808 | dtd->size_ioc_sts = cpu_to_hc32(swap_temp); |
b504882d LY |
809 | |
810 | /* Init all of buffer page pointers */ | |
811 | swap_temp = (u32) (req->req.dma + req->req.actual); | |
09ba0def AG |
812 | dtd->buff_ptr0 = cpu_to_hc32(swap_temp); |
813 | dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000); | |
814 | dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000); | |
815 | dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000); | |
816 | dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000); | |
b504882d LY |
817 | |
818 | req->req.actual += *length; | |
819 | ||
820 | /* zlp is needed if req->req.zero is set */ | |
821 | if (req->req.zero) { | |
822 | if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) | |
823 | *is_last = 1; | |
824 | else | |
825 | *is_last = 0; | |
826 | } else if (req->req.length == req->req.actual) | |
827 | *is_last = 1; | |
828 | else | |
829 | *is_last = 0; | |
830 | ||
831 | if ((*is_last) == 0) | |
bf7409a2 | 832 | VDBG("multi-dtd request!"); |
b504882d LY |
833 | /* Fill in the transfer size; set active bit */ |
834 | swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE); | |
835 | ||
836 | /* Enable interrupt for the last dtd of a request */ | |
837 | if (*is_last && !req->req.no_interrupt) | |
838 | swap_temp |= DTD_IOC; | |
839 | ||
09ba0def | 840 | dtd->size_ioc_sts = cpu_to_hc32(swap_temp); |
b504882d LY |
841 | |
842 | mb(); | |
843 | ||
844 | VDBG("length = %d address= 0x%x", *length, (int)*dma); | |
845 | ||
846 | return dtd; | |
847 | } | |
848 | ||
849 | /* Generate dtd chain for a request */ | |
c5cc5ed8 | 850 | static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags) |
b504882d LY |
851 | { |
852 | unsigned count; | |
853 | int is_last; | |
854 | int is_first =1; | |
855 | struct ep_td_struct *last_dtd = NULL, *dtd; | |
856 | dma_addr_t dma; | |
857 | ||
858 | do { | |
c5cc5ed8 | 859 | dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags); |
b504882d LY |
860 | if (dtd == NULL) |
861 | return -ENOMEM; | |
862 | ||
863 | if (is_first) { | |
864 | is_first = 0; | |
865 | req->head = dtd; | |
866 | } else { | |
09ba0def | 867 | last_dtd->next_td_ptr = cpu_to_hc32(dma); |
b504882d LY |
868 | last_dtd->next_td_virt = dtd; |
869 | } | |
870 | last_dtd = dtd; | |
871 | ||
872 | req->dtd_count++; | |
873 | } while (!is_last); | |
874 | ||
09ba0def | 875 | dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE); |
b504882d LY |
876 | |
877 | req->tail = dtd; | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
882 | /* queues (submits) an I/O request to an endpoint */ | |
883 | static int | |
884 | fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |
885 | { | |
886 | struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); | |
887 | struct fsl_req *req = container_of(_req, struct fsl_req, req); | |
888 | struct fsl_udc *udc; | |
889 | unsigned long flags; | |
b504882d LY |
890 | |
891 | /* catch various bogus parameters */ | |
892 | if (!_req || !req->req.complete || !req->req.buf | |
893 | || !list_empty(&req->queue)) { | |
bf7409a2 | 894 | VDBG("%s, bad params", __func__); |
b504882d LY |
895 | return -EINVAL; |
896 | } | |
79149b8b | 897 | if (unlikely(!_ep || !ep->ep.desc)) { |
bf7409a2 | 898 | VDBG("%s, bad ep", __func__); |
b504882d LY |
899 | return -EINVAL; |
900 | } | |
79149b8b | 901 | if (usb_endpoint_xfer_isoc(ep->ep.desc)) { |
b504882d LY |
902 | if (req->req.length > ep->ep.maxpacket) |
903 | return -EMSGSIZE; | |
b504882d LY |
904 | } |
905 | ||
906 | udc = ep->udc; | |
907 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) | |
908 | return -ESHUTDOWN; | |
909 | ||
910 | req->ep = ep; | |
911 | ||
912 | /* map virtual address to hardware */ | |
913 | if (req->req.dma == DMA_ADDR_INVALID) { | |
914 | req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, | |
915 | req->req.buf, | |
916 | req->req.length, ep_is_in(ep) | |
917 | ? DMA_TO_DEVICE | |
918 | : DMA_FROM_DEVICE); | |
919 | req->mapped = 1; | |
920 | } else { | |
921 | dma_sync_single_for_device(ep->udc->gadget.dev.parent, | |
922 | req->req.dma, req->req.length, | |
923 | ep_is_in(ep) | |
924 | ? DMA_TO_DEVICE | |
925 | : DMA_FROM_DEVICE); | |
926 | req->mapped = 0; | |
927 | } | |
928 | ||
929 | req->req.status = -EINPROGRESS; | |
930 | req->req.actual = 0; | |
931 | req->dtd_count = 0; | |
932 | ||
b504882d | 933 | /* build dtds and push them to device queue */ |
c5cc5ed8 PC |
934 | if (!fsl_req_to_dtd(req, gfp_flags)) { |
935 | spin_lock_irqsave(&udc->lock, flags); | |
b504882d LY |
936 | fsl_queue_td(ep, req); |
937 | } else { | |
b504882d LY |
938 | return -ENOMEM; |
939 | } | |
940 | ||
b504882d LY |
941 | /* irq handler advances the queue */ |
942 | if (req != NULL) | |
943 | list_add_tail(&req->queue, &ep->queue); | |
944 | spin_unlock_irqrestore(&udc->lock, flags); | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | /* dequeues (cancels, unlinks) an I/O request from an endpoint */ | |
950 | static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
951 | { | |
952 | struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); | |
953 | struct fsl_req *req; | |
954 | unsigned long flags; | |
955 | int ep_num, stopped, ret = 0; | |
956 | u32 epctrl; | |
957 | ||
958 | if (!_ep || !_req) | |
959 | return -EINVAL; | |
960 | ||
961 | spin_lock_irqsave(&ep->udc->lock, flags); | |
962 | stopped = ep->stopped; | |
963 | ||
964 | /* Stop the ep before we deal with the queue */ | |
965 | ep->stopped = 1; | |
966 | ep_num = ep_index(ep); | |
967 | epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
968 | if (ep_is_in(ep)) | |
969 | epctrl &= ~EPCTRL_TX_ENABLE; | |
970 | else | |
971 | epctrl &= ~EPCTRL_RX_ENABLE; | |
972 | fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); | |
973 | ||
974 | /* make sure it's actually queued on this endpoint */ | |
975 | list_for_each_entry(req, &ep->queue, queue) { | |
976 | if (&req->req == _req) | |
977 | break; | |
978 | } | |
979 | if (&req->req != _req) { | |
980 | ret = -EINVAL; | |
981 | goto out; | |
982 | } | |
983 | ||
984 | /* The request is in progress, or completed but not dequeued */ | |
985 | if (ep->queue.next == &req->queue) { | |
986 | _req->status = -ECONNRESET; | |
987 | fsl_ep_fifo_flush(_ep); /* flush current transfer */ | |
988 | ||
989 | /* The request isn't the last request in this ep queue */ | |
990 | if (req->queue.next != &ep->queue) { | |
b504882d LY |
991 | struct fsl_req *next_req; |
992 | ||
b504882d LY |
993 | next_req = list_entry(req->queue.next, struct fsl_req, |
994 | queue); | |
995 | ||
6414e94c LY |
996 | /* prime with dTD of next request */ |
997 | fsl_prime_ep(ep, next_req->head); | |
b504882d | 998 | } |
6414e94c | 999 | /* The request hasn't been processed, patch up the TD chain */ |
b504882d LY |
1000 | } else { |
1001 | struct fsl_req *prev_req; | |
1002 | ||
1003 | prev_req = list_entry(req->queue.prev, struct fsl_req, queue); | |
6414e94c | 1004 | prev_req->tail->next_td_ptr = req->tail->next_td_ptr; |
b504882d LY |
1005 | } |
1006 | ||
1007 | done(ep, req, -ECONNRESET); | |
1008 | ||
1009 | /* Enable EP */ | |
1010 | out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
1011 | if (ep_is_in(ep)) | |
1012 | epctrl |= EPCTRL_TX_ENABLE; | |
1013 | else | |
1014 | epctrl |= EPCTRL_RX_ENABLE; | |
1015 | fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); | |
1016 | ep->stopped = stopped; | |
1017 | ||
1018 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1019 | return ret; | |
1020 | } | |
1021 | ||
1022 | /*-------------------------------------------------------------------------*/ | |
1023 | ||
1024 | /*----------------------------------------------------------------- | |
1025 | * modify the endpoint halt feature | |
1026 | * @ep: the non-isochronous endpoint being stalled | |
1027 | * @value: 1--set halt 0--clear halt | |
1028 | * Returns zero, or a negative error code. | |
1029 | *----------------------------------------------------------------*/ | |
1030 | static int fsl_ep_set_halt(struct usb_ep *_ep, int value) | |
1031 | { | |
1032 | struct fsl_ep *ep = NULL; | |
1033 | unsigned long flags = 0; | |
1034 | int status = -EOPNOTSUPP; /* operation not supported */ | |
1035 | unsigned char ep_dir = 0, ep_num = 0; | |
1036 | struct fsl_udc *udc = NULL; | |
1037 | ||
1038 | ep = container_of(_ep, struct fsl_ep, ep); | |
1039 | udc = ep->udc; | |
79149b8b | 1040 | if (!_ep || !ep->ep.desc) { |
b504882d LY |
1041 | status = -EINVAL; |
1042 | goto out; | |
1043 | } | |
1044 | ||
79149b8b | 1045 | if (usb_endpoint_xfer_isoc(ep->ep.desc)) { |
b504882d LY |
1046 | status = -EOPNOTSUPP; |
1047 | goto out; | |
1048 | } | |
1049 | ||
1050 | /* Attempt to halt IN ep will fail if any transfer requests | |
1051 | * are still queue */ | |
1052 | if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { | |
1053 | status = -EAGAIN; | |
1054 | goto out; | |
1055 | } | |
1056 | ||
1057 | status = 0; | |
1058 | ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; | |
1059 | ep_num = (unsigned char)(ep_index(ep)); | |
1060 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1061 | dr_ep_change_stall(ep_num, ep_dir, value); | |
1062 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1063 | ||
1064 | if (ep_index(ep) == 0) { | |
1065 | udc->ep0_state = WAIT_FOR_SETUP; | |
1066 | udc->ep0_dir = 0; | |
1067 | } | |
1068 | out: | |
1069 | VDBG(" %s %s halt stat %d", ep->ep.name, | |
1070 | value ? "set" : "clear", status); | |
1071 | ||
1072 | return status; | |
1073 | } | |
1074 | ||
2ea6698d AG |
1075 | static int fsl_ep_fifo_status(struct usb_ep *_ep) |
1076 | { | |
1077 | struct fsl_ep *ep; | |
1078 | struct fsl_udc *udc; | |
1079 | int size = 0; | |
1080 | u32 bitmask; | |
6414e94c | 1081 | struct ep_queue_head *qh; |
2ea6698d AG |
1082 | |
1083 | ep = container_of(_ep, struct fsl_ep, ep); | |
79149b8b | 1084 | if (!_ep || (!ep->ep.desc && ep_index(ep) != 0)) |
2ea6698d AG |
1085 | return -ENODEV; |
1086 | ||
1087 | udc = (struct fsl_udc *)ep->udc; | |
1088 | ||
1089 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) | |
1090 | return -ESHUTDOWN; | |
1091 | ||
6414e94c | 1092 | qh = get_qh_by_ep(ep); |
2ea6698d AG |
1093 | |
1094 | bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) : | |
1095 | (1 << (ep_index(ep))); | |
1096 | ||
1097 | if (fsl_readl(&dr_regs->endptstatus) & bitmask) | |
6414e94c | 1098 | size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE) |
2ea6698d AG |
1099 | >> DTD_LENGTH_BIT_POS; |
1100 | ||
1101 | pr_debug("%s %u\n", __func__, size); | |
1102 | return size; | |
1103 | } | |
1104 | ||
b504882d LY |
1105 | static void fsl_ep_fifo_flush(struct usb_ep *_ep) |
1106 | { | |
1107 | struct fsl_ep *ep; | |
1108 | int ep_num, ep_dir; | |
1109 | u32 bits; | |
1110 | unsigned long timeout; | |
1111 | #define FSL_UDC_FLUSH_TIMEOUT 1000 | |
1112 | ||
1113 | if (!_ep) { | |
1114 | return; | |
1115 | } else { | |
1116 | ep = container_of(_ep, struct fsl_ep, ep); | |
79149b8b | 1117 | if (!ep->ep.desc) |
b504882d LY |
1118 | return; |
1119 | } | |
1120 | ep_num = ep_index(ep); | |
1121 | ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; | |
1122 | ||
1123 | if (ep_num == 0) | |
1124 | bits = (1 << 16) | 1; | |
1125 | else if (ep_dir == USB_SEND) | |
1126 | bits = 1 << (16 + ep_num); | |
1127 | else | |
1128 | bits = 1 << ep_num; | |
1129 | ||
1130 | timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT; | |
1131 | do { | |
1132 | fsl_writel(bits, &dr_regs->endptflush); | |
1133 | ||
1134 | /* Wait until flush complete */ | |
1135 | while (fsl_readl(&dr_regs->endptflush)) { | |
1136 | if (time_after(jiffies, timeout)) { | |
1137 | ERR("ep flush timeout\n"); | |
1138 | return; | |
1139 | } | |
1140 | cpu_relax(); | |
1141 | } | |
1142 | /* See if we need to flush again */ | |
1143 | } while (fsl_readl(&dr_regs->endptstatus) & bits); | |
1144 | } | |
1145 | ||
1146 | static struct usb_ep_ops fsl_ep_ops = { | |
1147 | .enable = fsl_ep_enable, | |
1148 | .disable = fsl_ep_disable, | |
1149 | ||
1150 | .alloc_request = fsl_alloc_request, | |
1151 | .free_request = fsl_free_request, | |
1152 | ||
b504882d LY |
1153 | .queue = fsl_ep_queue, |
1154 | .dequeue = fsl_ep_dequeue, | |
1155 | ||
1156 | .set_halt = fsl_ep_set_halt, | |
2ea6698d | 1157 | .fifo_status = fsl_ep_fifo_status, |
b504882d LY |
1158 | .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */ |
1159 | }; | |
1160 | ||
1161 | /*------------------------------------------------------------------------- | |
1162 | Gadget Driver Layer Operations | |
1163 | -------------------------------------------------------------------------*/ | |
1164 | ||
1165 | /*---------------------------------------------------------------------- | |
1166 | * Get the current frame number (from DR frame_index Reg ) | |
1167 | *----------------------------------------------------------------------*/ | |
1168 | static int fsl_get_frame(struct usb_gadget *gadget) | |
1169 | { | |
1170 | return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS); | |
1171 | } | |
1172 | ||
1173 | /*----------------------------------------------------------------------- | |
1174 | * Tries to wake up the host connected to this gadget | |
1175 | -----------------------------------------------------------------------*/ | |
1176 | static int fsl_wakeup(struct usb_gadget *gadget) | |
1177 | { | |
1178 | struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget); | |
1179 | u32 portsc; | |
1180 | ||
1181 | /* Remote wakeup feature not enabled by host */ | |
1182 | if (!udc->remote_wakeup) | |
1183 | return -ENOTSUPP; | |
1184 | ||
1185 | portsc = fsl_readl(&dr_regs->portsc1); | |
1186 | /* not suspended? */ | |
1187 | if (!(portsc & PORTSCX_PORT_SUSPEND)) | |
1188 | return 0; | |
1189 | /* trigger force resume */ | |
1190 | portsc |= PORTSCX_PORT_FORCE_RESUME; | |
1191 | fsl_writel(portsc, &dr_regs->portsc1); | |
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | static int can_pullup(struct fsl_udc *udc) | |
1196 | { | |
1197 | return udc->driver && udc->softconnect && udc->vbus_active; | |
1198 | } | |
1199 | ||
1200 | /* Notify controller that VBUS is powered, Called by whatever | |
1201 | detects VBUS sessions */ | |
1202 | static int fsl_vbus_session(struct usb_gadget *gadget, int is_active) | |
1203 | { | |
1204 | struct fsl_udc *udc; | |
1205 | unsigned long flags; | |
1206 | ||
1207 | udc = container_of(gadget, struct fsl_udc, gadget); | |
1208 | spin_lock_irqsave(&udc->lock, flags); | |
bf7409a2 | 1209 | VDBG("VBUS %s", is_active ? "on" : "off"); |
b504882d LY |
1210 | udc->vbus_active = (is_active != 0); |
1211 | if (can_pullup(udc)) | |
1212 | fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), | |
1213 | &dr_regs->usbcmd); | |
1214 | else | |
1215 | fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), | |
1216 | &dr_regs->usbcmd); | |
1217 | spin_unlock_irqrestore(&udc->lock, flags); | |
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | /* constrain controller's VBUS power usage | |
1222 | * This call is used by gadget drivers during SET_CONFIGURATION calls, | |
1223 | * reporting how much power the device may consume. For example, this | |
1224 | * could affect how quickly batteries are recharged. | |
1225 | * | |
1226 | * Returns zero on success, else negative errno. | |
1227 | */ | |
1228 | static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1229 | { | |
b504882d LY |
1230 | struct fsl_udc *udc; |
1231 | ||
1232 | udc = container_of(gadget, struct fsl_udc, gadget); | |
ded017ee | 1233 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
b96d3b08 | 1234 | return usb_phy_set_power(udc->transceiver, mA); |
b504882d LY |
1235 | return -ENOTSUPP; |
1236 | } | |
1237 | ||
1238 | /* Change Data+ pullup status | |
1239 | * this func is used by usb_gadget_connect/disconnet | |
1240 | */ | |
1241 | static int fsl_pullup(struct usb_gadget *gadget, int is_on) | |
1242 | { | |
1243 | struct fsl_udc *udc; | |
1244 | ||
1245 | udc = container_of(gadget, struct fsl_udc, gadget); | |
1246 | udc->softconnect = (is_on != 0); | |
1247 | if (can_pullup(udc)) | |
1248 | fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), | |
1249 | &dr_regs->usbcmd); | |
1250 | else | |
1251 | fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), | |
1252 | &dr_regs->usbcmd); | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
0f91349b SAS |
1257 | static int fsl_start(struct usb_gadget_driver *driver, |
1258 | int (*bind)(struct usb_gadget *)); | |
1259 | static int fsl_stop(struct usb_gadget_driver *driver); | |
9454a57a | 1260 | /* defined in gadget.h */ |
b504882d LY |
1261 | static struct usb_gadget_ops fsl_gadget_ops = { |
1262 | .get_frame = fsl_get_frame, | |
1263 | .wakeup = fsl_wakeup, | |
1264 | /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */ | |
1265 | .vbus_session = fsl_vbus_session, | |
1266 | .vbus_draw = fsl_vbus_draw, | |
1267 | .pullup = fsl_pullup, | |
0f91349b SAS |
1268 | .start = fsl_start, |
1269 | .stop = fsl_stop, | |
b504882d LY |
1270 | }; |
1271 | ||
1272 | /* Set protocol stall on ep0, protocol stall will automatically be cleared | |
1273 | on new transaction */ | |
1274 | static void ep0stall(struct fsl_udc *udc) | |
1275 | { | |
1276 | u32 tmp; | |
1277 | ||
1278 | /* must set tx and rx to stall at the same time */ | |
1279 | tmp = fsl_readl(&dr_regs->endptctrl[0]); | |
1280 | tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL; | |
1281 | fsl_writel(tmp, &dr_regs->endptctrl[0]); | |
1282 | udc->ep0_state = WAIT_FOR_SETUP; | |
1283 | udc->ep0_dir = 0; | |
1284 | } | |
1285 | ||
1286 | /* Prime a status phase for ep0 */ | |
1287 | static int ep0_prime_status(struct fsl_udc *udc, int direction) | |
1288 | { | |
1289 | struct fsl_req *req = udc->status_req; | |
1290 | struct fsl_ep *ep; | |
b504882d LY |
1291 | |
1292 | if (direction == EP_DIR_IN) | |
1293 | udc->ep0_dir = USB_DIR_IN; | |
1294 | else | |
1295 | udc->ep0_dir = USB_DIR_OUT; | |
1296 | ||
1297 | ep = &udc->eps[0]; | |
f79a60b8 PC |
1298 | if (udc->ep0_state != DATA_STATE_XMIT) |
1299 | udc->ep0_state = WAIT_FOR_OUT_STATUS; | |
b504882d LY |
1300 | |
1301 | req->ep = ep; | |
1302 | req->req.length = 0; | |
1303 | req->req.status = -EINPROGRESS; | |
1304 | req->req.actual = 0; | |
1305 | req->req.complete = NULL; | |
1306 | req->dtd_count = 0; | |
1307 | ||
3140d5b2 AG |
1308 | req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, |
1309 | req->req.buf, req->req.length, | |
1310 | ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
1311 | req->mapped = 1; | |
1312 | ||
c5cc5ed8 | 1313 | if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0) |
224b5039 | 1314 | fsl_queue_td(ep, req); |
b504882d LY |
1315 | else |
1316 | return -ENOMEM; | |
1317 | ||
b504882d LY |
1318 | list_add_tail(&req->queue, &ep->queue); |
1319 | ||
224b5039 | 1320 | return 0; |
b504882d LY |
1321 | } |
1322 | ||
825bee3a | 1323 | static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe) |
b504882d LY |
1324 | { |
1325 | struct fsl_ep *ep = get_ep_by_pipe(udc, pipe); | |
1326 | ||
825bee3a WN |
1327 | if (ep->name) |
1328 | nuke(ep, -ESHUTDOWN); | |
b504882d LY |
1329 | } |
1330 | ||
1331 | /* | |
1332 | * ch9 Set address | |
1333 | */ | |
1334 | static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length) | |
1335 | { | |
1336 | /* Save the new address to device struct */ | |
1337 | udc->device_address = (u8) value; | |
1338 | /* Update usb state */ | |
1339 | udc->usb_state = USB_STATE_ADDRESS; | |
1340 | /* Status phase */ | |
1341 | if (ep0_prime_status(udc, EP_DIR_IN)) | |
1342 | ep0stall(udc); | |
1343 | } | |
1344 | ||
1345 | /* | |
1346 | * ch9 Get status | |
1347 | */ | |
1348 | static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, | |
1349 | u16 index, u16 length) | |
1350 | { | |
1351 | u16 tmp = 0; /* Status, cpu endian */ | |
b504882d LY |
1352 | struct fsl_req *req; |
1353 | struct fsl_ep *ep; | |
b504882d LY |
1354 | |
1355 | ep = &udc->eps[0]; | |
1356 | ||
1357 | if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { | |
1358 | /* Get device status */ | |
1359 | tmp = 1 << USB_DEVICE_SELF_POWERED; | |
1360 | tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; | |
1361 | } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { | |
1362 | /* Get interface status */ | |
1363 | /* We don't have interface information in udc driver */ | |
1364 | tmp = 0; | |
1365 | } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { | |
1366 | /* Get endpoint status */ | |
1367 | struct fsl_ep *target_ep; | |
1368 | ||
1369 | target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index)); | |
1370 | ||
1371 | /* stall if endpoint doesn't exist */ | |
79149b8b | 1372 | if (!target_ep->ep.desc) |
b504882d LY |
1373 | goto stall; |
1374 | tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep)) | |
1375 | << USB_ENDPOINT_HALT; | |
1376 | } | |
1377 | ||
1378 | udc->ep0_dir = USB_DIR_IN; | |
1379 | /* Borrow the per device status_req */ | |
1380 | req = udc->status_req; | |
1381 | /* Fill in the reqest structure */ | |
1382 | *((u16 *) req->req.buf) = cpu_to_le16(tmp); | |
2ea6698d | 1383 | |
b504882d LY |
1384 | req->ep = ep; |
1385 | req->req.length = 2; | |
1386 | req->req.status = -EINPROGRESS; | |
1387 | req->req.actual = 0; | |
1388 | req->req.complete = NULL; | |
1389 | req->dtd_count = 0; | |
1390 | ||
3140d5b2 AG |
1391 | req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, |
1392 | req->req.buf, req->req.length, | |
1393 | ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
1394 | req->mapped = 1; | |
1395 | ||
b504882d | 1396 | /* prime the data phase */ |
c5cc5ed8 | 1397 | if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0)) |
224b5039 | 1398 | fsl_queue_td(ep, req); |
b504882d LY |
1399 | else /* no mem */ |
1400 | goto stall; | |
1401 | ||
b504882d LY |
1402 | list_add_tail(&req->queue, &ep->queue); |
1403 | udc->ep0_state = DATA_STATE_XMIT; | |
f79a60b8 PC |
1404 | if (ep0_prime_status(udc, EP_DIR_OUT)) |
1405 | ep0stall(udc); | |
1406 | ||
b504882d LY |
1407 | return; |
1408 | stall: | |
1409 | ep0stall(udc); | |
1410 | } | |
1411 | ||
1412 | static void setup_received_irq(struct fsl_udc *udc, | |
1413 | struct usb_ctrlrequest *setup) | |
1414 | { | |
1415 | u16 wValue = le16_to_cpu(setup->wValue); | |
1416 | u16 wIndex = le16_to_cpu(setup->wIndex); | |
1417 | u16 wLength = le16_to_cpu(setup->wLength); | |
1418 | ||
1419 | udc_reset_ep_queue(udc, 0); | |
1420 | ||
39d1f8c9 | 1421 | /* We process some stardard setup requests here */ |
b504882d | 1422 | switch (setup->bRequest) { |
b504882d | 1423 | case USB_REQ_GET_STATUS: |
39d1f8c9 LY |
1424 | /* Data+Status phase from udc */ |
1425 | if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) | |
b504882d LY |
1426 | != (USB_DIR_IN | USB_TYPE_STANDARD)) |
1427 | break; | |
1428 | ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength); | |
39d1f8c9 | 1429 | return; |
b504882d | 1430 | |
b504882d | 1431 | case USB_REQ_SET_ADDRESS: |
39d1f8c9 | 1432 | /* Status phase from udc */ |
b504882d LY |
1433 | if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
1434 | | USB_RECIP_DEVICE)) | |
1435 | break; | |
1436 | ch9setaddress(udc, wValue, wIndex, wLength); | |
39d1f8c9 | 1437 | return; |
b504882d | 1438 | |
b504882d LY |
1439 | case USB_REQ_CLEAR_FEATURE: |
1440 | case USB_REQ_SET_FEATURE: | |
39d1f8c9 LY |
1441 | /* Status phase from udc */ |
1442 | { | |
b504882d | 1443 | int rc = -EOPNOTSUPP; |
2ea6698d | 1444 | u16 ptc = 0; |
b504882d | 1445 | |
39d1f8c9 LY |
1446 | if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) |
1447 | == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { | |
b504882d LY |
1448 | int pipe = get_pipe_by_windex(wIndex); |
1449 | struct fsl_ep *ep; | |
1450 | ||
118d63f7 | 1451 | if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep) |
b504882d LY |
1452 | break; |
1453 | ep = get_ep_by_pipe(udc, pipe); | |
1454 | ||
1455 | spin_unlock(&udc->lock); | |
1456 | rc = fsl_ep_set_halt(&ep->ep, | |
1457 | (setup->bRequest == USB_REQ_SET_FEATURE) | |
1458 | ? 1 : 0); | |
1459 | spin_lock(&udc->lock); | |
1460 | ||
39d1f8c9 LY |
1461 | } else if ((setup->bRequestType & (USB_RECIP_MASK |
1462 | | USB_TYPE_MASK)) == (USB_RECIP_DEVICE | |
1463 | | USB_TYPE_STANDARD)) { | |
b504882d LY |
1464 | /* Note: The driver has not include OTG support yet. |
1465 | * This will be set when OTG support is added */ | |
2ea6698d AG |
1466 | if (wValue == USB_DEVICE_TEST_MODE) |
1467 | ptc = wIndex >> 8; | |
1468 | else if (gadget_is_otg(&udc->gadget)) { | |
1469 | if (setup->bRequest == | |
1470 | USB_DEVICE_B_HNP_ENABLE) | |
1471 | udc->gadget.b_hnp_enable = 1; | |
1472 | else if (setup->bRequest == | |
1473 | USB_DEVICE_A_HNP_SUPPORT) | |
1474 | udc->gadget.a_hnp_support = 1; | |
1475 | else if (setup->bRequest == | |
1476 | USB_DEVICE_A_ALT_HNP_SUPPORT) | |
1477 | udc->gadget.a_alt_hnp_support = 1; | |
1478 | } | |
b504882d | 1479 | rc = 0; |
39d1f8c9 LY |
1480 | } else |
1481 | break; | |
1482 | ||
b504882d LY |
1483 | if (rc == 0) { |
1484 | if (ep0_prime_status(udc, EP_DIR_IN)) | |
1485 | ep0stall(udc); | |
1486 | } | |
2ea6698d AG |
1487 | if (ptc) { |
1488 | u32 tmp; | |
1489 | ||
1490 | mdelay(10); | |
1491 | tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16); | |
1492 | fsl_writel(tmp, &dr_regs->portsc1); | |
1493 | printk(KERN_INFO "udc: switch to test mode %d.\n", ptc); | |
1494 | } | |
1495 | ||
39d1f8c9 | 1496 | return; |
b504882d | 1497 | } |
b504882d | 1498 | |
39d1f8c9 | 1499 | default: |
b504882d LY |
1500 | break; |
1501 | } | |
39d1f8c9 LY |
1502 | |
1503 | /* Requests handled by gadget */ | |
1504 | if (wLength) { | |
1505 | /* Data phase from gadget, status phase from udc */ | |
1506 | udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) | |
1507 | ? USB_DIR_IN : USB_DIR_OUT; | |
1508 | spin_unlock(&udc->lock); | |
1509 | if (udc->driver->setup(&udc->gadget, | |
1510 | &udc->local_setup_buff) < 0) | |
1511 | ep0stall(udc); | |
1512 | spin_lock(&udc->lock); | |
1513 | udc->ep0_state = (setup->bRequestType & USB_DIR_IN) | |
1514 | ? DATA_STATE_XMIT : DATA_STATE_RECV; | |
f79a60b8 PC |
1515 | /* |
1516 | * If the data stage is IN, send status prime immediately. | |
1517 | * See 2.0 Spec chapter 8.5.3.3 for detail. | |
1518 | */ | |
1519 | if (udc->ep0_state == DATA_STATE_XMIT) | |
1520 | if (ep0_prime_status(udc, EP_DIR_OUT)) | |
1521 | ep0stall(udc); | |
1522 | ||
39d1f8c9 LY |
1523 | } else { |
1524 | /* No data phase, IN status from gadget */ | |
1525 | udc->ep0_dir = USB_DIR_IN; | |
1526 | spin_unlock(&udc->lock); | |
1527 | if (udc->driver->setup(&udc->gadget, | |
1528 | &udc->local_setup_buff) < 0) | |
1529 | ep0stall(udc); | |
1530 | spin_lock(&udc->lock); | |
1531 | udc->ep0_state = WAIT_FOR_OUT_STATUS; | |
1532 | } | |
b504882d LY |
1533 | } |
1534 | ||
1535 | /* Process request for Data or Status phase of ep0 | |
1536 | * prime status phase if needed */ | |
1537 | static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, | |
1538 | struct fsl_req *req) | |
1539 | { | |
1540 | if (udc->usb_state == USB_STATE_ADDRESS) { | |
1541 | /* Set the new address */ | |
1542 | u32 new_address = (u32) udc->device_address; | |
1543 | fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS, | |
1544 | &dr_regs->deviceaddr); | |
1545 | } | |
1546 | ||
1547 | done(ep0, req, 0); | |
1548 | ||
1549 | switch (udc->ep0_state) { | |
1550 | case DATA_STATE_XMIT: | |
f79a60b8 PC |
1551 | /* already primed at setup_received_irq */ |
1552 | udc->ep0_state = WAIT_FOR_OUT_STATUS; | |
b504882d LY |
1553 | break; |
1554 | case DATA_STATE_RECV: | |
1555 | /* send status phase */ | |
1556 | if (ep0_prime_status(udc, EP_DIR_IN)) | |
1557 | ep0stall(udc); | |
1558 | break; | |
1559 | case WAIT_FOR_OUT_STATUS: | |
1560 | udc->ep0_state = WAIT_FOR_SETUP; | |
1561 | break; | |
1562 | case WAIT_FOR_SETUP: | |
bf7409a2 | 1563 | ERR("Unexpect ep0 packets\n"); |
b504882d LY |
1564 | break; |
1565 | default: | |
1566 | ep0stall(udc); | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | ||
1571 | /* Tripwire mechanism to ensure a setup packet payload is extracted without | |
1572 | * being corrupted by another incoming setup packet */ | |
1573 | static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr) | |
1574 | { | |
1575 | u32 temp; | |
1576 | struct ep_queue_head *qh; | |
09ba0def | 1577 | struct fsl_usb2_platform_data *pdata = udc->pdata; |
b504882d LY |
1578 | |
1579 | qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT]; | |
1580 | ||
1581 | /* Clear bit in ENDPTSETUPSTAT */ | |
1582 | temp = fsl_readl(&dr_regs->endptsetupstat); | |
1583 | fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat); | |
1584 | ||
1585 | /* while a hazard exists when setup package arrives */ | |
1586 | do { | |
1587 | /* Set Setup Tripwire */ | |
1588 | temp = fsl_readl(&dr_regs->usbcmd); | |
1589 | fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd); | |
1590 | ||
1591 | /* Copy the setup packet to local buffer */ | |
09ba0def AG |
1592 | if (pdata->le_setup_buf) { |
1593 | u32 *p = (u32 *)buffer_ptr; | |
1594 | u32 *s = (u32 *)qh->setup_buffer; | |
1595 | ||
1596 | /* Convert little endian setup buffer to CPU endian */ | |
1597 | *p++ = le32_to_cpu(*s++); | |
1598 | *p = le32_to_cpu(*s); | |
1599 | } else { | |
1600 | memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); | |
1601 | } | |
b504882d LY |
1602 | } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW)); |
1603 | ||
1604 | /* Clear Setup Tripwire */ | |
1605 | temp = fsl_readl(&dr_regs->usbcmd); | |
1606 | fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd); | |
1607 | } | |
1608 | ||
1609 | /* process-ep_req(): free the completed Tds for this req */ | |
1610 | static int process_ep_req(struct fsl_udc *udc, int pipe, | |
1611 | struct fsl_req *curr_req) | |
1612 | { | |
1613 | struct ep_td_struct *curr_td; | |
1614 | int td_complete, actual, remaining_length, j, tmp; | |
1615 | int status = 0; | |
1616 | int errors = 0; | |
1617 | struct ep_queue_head *curr_qh = &udc->ep_qh[pipe]; | |
1618 | int direction = pipe % 2; | |
1619 | ||
1620 | curr_td = curr_req->head; | |
1621 | td_complete = 0; | |
1622 | actual = curr_req->req.length; | |
1623 | ||
1624 | for (j = 0; j < curr_req->dtd_count; j++) { | |
09ba0def | 1625 | remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts) |
b504882d LY |
1626 | & DTD_PACKET_SIZE) |
1627 | >> DTD_LENGTH_BIT_POS; | |
1628 | actual -= remaining_length; | |
1629 | ||
09ba0def AG |
1630 | errors = hc32_to_cpu(curr_td->size_ioc_sts); |
1631 | if (errors & DTD_ERROR_MASK) { | |
b504882d LY |
1632 | if (errors & DTD_STATUS_HALTED) { |
1633 | ERR("dTD error %08x QH=%d\n", errors, pipe); | |
1634 | /* Clear the errors and Halt condition */ | |
09ba0def | 1635 | tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts); |
b504882d | 1636 | tmp &= ~errors; |
09ba0def | 1637 | curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp); |
b504882d LY |
1638 | status = -EPIPE; |
1639 | /* FIXME: continue with next queued TD? */ | |
1640 | ||
1641 | break; | |
1642 | } | |
1643 | if (errors & DTD_STATUS_DATA_BUFF_ERR) { | |
1644 | VDBG("Transfer overflow"); | |
1645 | status = -EPROTO; | |
1646 | break; | |
1647 | } else if (errors & DTD_STATUS_TRANSACTION_ERR) { | |
1648 | VDBG("ISO error"); | |
1649 | status = -EILSEQ; | |
1650 | break; | |
1651 | } else | |
25985edc | 1652 | ERR("Unknown error has occurred (0x%x)!\n", |
b504882d LY |
1653 | errors); |
1654 | ||
09ba0def | 1655 | } else if (hc32_to_cpu(curr_td->size_ioc_sts) |
b504882d LY |
1656 | & DTD_STATUS_ACTIVE) { |
1657 | VDBG("Request not complete"); | |
1658 | status = REQ_UNCOMPLETE; | |
1659 | return status; | |
1660 | } else if (remaining_length) { | |
1661 | if (direction) { | |
1662 | VDBG("Transmit dTD remaining length not zero"); | |
1663 | status = -EPROTO; | |
1664 | break; | |
1665 | } else { | |
1666 | td_complete++; | |
1667 | break; | |
1668 | } | |
1669 | } else { | |
1670 | td_complete++; | |
bf7409a2 | 1671 | VDBG("dTD transmitted successful"); |
b504882d LY |
1672 | } |
1673 | ||
1674 | if (j != curr_req->dtd_count - 1) | |
1675 | curr_td = (struct ep_td_struct *)curr_td->next_td_virt; | |
1676 | } | |
1677 | ||
1678 | if (status) | |
1679 | return status; | |
1680 | ||
1681 | curr_req->req.actual = actual; | |
1682 | ||
1683 | return 0; | |
1684 | } | |
1685 | ||
1686 | /* Process a DTD completion interrupt */ | |
1687 | static void dtd_complete_irq(struct fsl_udc *udc) | |
1688 | { | |
1689 | u32 bit_pos; | |
1690 | int i, ep_num, direction, bit_mask, status; | |
1691 | struct fsl_ep *curr_ep; | |
1692 | struct fsl_req *curr_req, *temp_req; | |
1693 | ||
1694 | /* Clear the bits in the register */ | |
1695 | bit_pos = fsl_readl(&dr_regs->endptcomplete); | |
1696 | fsl_writel(bit_pos, &dr_regs->endptcomplete); | |
1697 | ||
1698 | if (!bit_pos) | |
1699 | return; | |
1700 | ||
118d63f7 | 1701 | for (i = 0; i < udc->max_ep; i++) { |
b504882d LY |
1702 | ep_num = i >> 1; |
1703 | direction = i % 2; | |
1704 | ||
1705 | bit_mask = 1 << (ep_num + 16 * direction); | |
1706 | ||
1707 | if (!(bit_pos & bit_mask)) | |
1708 | continue; | |
1709 | ||
1710 | curr_ep = get_ep_by_pipe(udc, i); | |
1711 | ||
1712 | /* If the ep is configured */ | |
1713 | if (curr_ep->name == NULL) { | |
b6c63937 | 1714 | WARNING("Invalid EP?"); |
b504882d LY |
1715 | continue; |
1716 | } | |
1717 | ||
1718 | /* process the req queue until an uncomplete request */ | |
1719 | list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue, | |
1720 | queue) { | |
1721 | status = process_ep_req(udc, i, curr_req); | |
1722 | ||
1723 | VDBG("status of process_ep_req= %d, ep = %d", | |
1724 | status, ep_num); | |
1725 | if (status == REQ_UNCOMPLETE) | |
1726 | break; | |
1727 | /* write back status to req */ | |
1728 | curr_req->req.status = status; | |
1729 | ||
1730 | if (ep_num == 0) { | |
1731 | ep0_req_complete(udc, curr_ep, curr_req); | |
1732 | break; | |
1733 | } else | |
1734 | done(curr_ep, curr_req, status); | |
1735 | } | |
1736 | } | |
1737 | } | |
1738 | ||
e538dfda MN |
1739 | static inline enum usb_device_speed portscx_device_speed(u32 reg) |
1740 | { | |
0e042be3 | 1741 | switch (reg & PORTSCX_PORT_SPEED_MASK) { |
e538dfda MN |
1742 | case PORTSCX_PORT_SPEED_HIGH: |
1743 | return USB_SPEED_HIGH; | |
1744 | case PORTSCX_PORT_SPEED_FULL: | |
1745 | return USB_SPEED_FULL; | |
1746 | case PORTSCX_PORT_SPEED_LOW: | |
1747 | return USB_SPEED_LOW; | |
1748 | default: | |
1749 | return USB_SPEED_UNKNOWN; | |
1750 | } | |
1751 | } | |
1752 | ||
b504882d LY |
1753 | /* Process a port change interrupt */ |
1754 | static void port_change_irq(struct fsl_udc *udc) | |
1755 | { | |
83722bc9 AG |
1756 | if (udc->bus_reset) |
1757 | udc->bus_reset = 0; | |
1758 | ||
b504882d | 1759 | /* Bus resetting is finished */ |
e538dfda | 1760 | if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) |
b504882d | 1761 | /* Get the speed */ |
e538dfda MN |
1762 | udc->gadget.speed = |
1763 | portscx_device_speed(fsl_readl(&dr_regs->portsc1)); | |
b504882d LY |
1764 | |
1765 | /* Update USB state */ | |
1766 | if (!udc->resume_state) | |
1767 | udc->usb_state = USB_STATE_DEFAULT; | |
1768 | } | |
1769 | ||
1770 | /* Process suspend interrupt */ | |
1771 | static void suspend_irq(struct fsl_udc *udc) | |
1772 | { | |
1773 | udc->resume_state = udc->usb_state; | |
1774 | udc->usb_state = USB_STATE_SUSPENDED; | |
1775 | ||
1776 | /* report suspend to the driver, serial.c does not support this */ | |
1777 | if (udc->driver->suspend) | |
1778 | udc->driver->suspend(&udc->gadget); | |
1779 | } | |
1780 | ||
1781 | static void bus_resume(struct fsl_udc *udc) | |
1782 | { | |
1783 | udc->usb_state = udc->resume_state; | |
1784 | udc->resume_state = 0; | |
1785 | ||
1786 | /* report resume to the driver, serial.c does not support this */ | |
1787 | if (udc->driver->resume) | |
1788 | udc->driver->resume(&udc->gadget); | |
1789 | } | |
1790 | ||
1791 | /* Clear up all ep queues */ | |
1792 | static int reset_queues(struct fsl_udc *udc) | |
1793 | { | |
1794 | u8 pipe; | |
1795 | ||
1796 | for (pipe = 0; pipe < udc->max_pipes; pipe++) | |
1797 | udc_reset_ep_queue(udc, pipe); | |
1798 | ||
1799 | /* report disconnect; the driver is already quiesced */ | |
185e3dea | 1800 | spin_unlock(&udc->lock); |
b504882d | 1801 | udc->driver->disconnect(&udc->gadget); |
185e3dea | 1802 | spin_lock(&udc->lock); |
b504882d LY |
1803 | |
1804 | return 0; | |
1805 | } | |
1806 | ||
1807 | /* Process reset interrupt */ | |
1808 | static void reset_irq(struct fsl_udc *udc) | |
1809 | { | |
1810 | u32 temp; | |
1811 | unsigned long timeout; | |
1812 | ||
1813 | /* Clear the device address */ | |
1814 | temp = fsl_readl(&dr_regs->deviceaddr); | |
1815 | fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr); | |
1816 | ||
1817 | udc->device_address = 0; | |
1818 | ||
1819 | /* Clear usb state */ | |
1820 | udc->resume_state = 0; | |
1821 | udc->ep0_dir = 0; | |
1822 | udc->ep0_state = WAIT_FOR_SETUP; | |
1823 | udc->remote_wakeup = 0; /* default to 0 on reset */ | |
1824 | udc->gadget.b_hnp_enable = 0; | |
1825 | udc->gadget.a_hnp_support = 0; | |
1826 | udc->gadget.a_alt_hnp_support = 0; | |
1827 | ||
1828 | /* Clear all the setup token semaphores */ | |
1829 | temp = fsl_readl(&dr_regs->endptsetupstat); | |
1830 | fsl_writel(temp, &dr_regs->endptsetupstat); | |
1831 | ||
1832 | /* Clear all the endpoint complete status bits */ | |
1833 | temp = fsl_readl(&dr_regs->endptcomplete); | |
1834 | fsl_writel(temp, &dr_regs->endptcomplete); | |
1835 | ||
1836 | timeout = jiffies + 100; | |
1837 | while (fsl_readl(&dr_regs->endpointprime)) { | |
1838 | /* Wait until all endptprime bits cleared */ | |
1839 | if (time_after(jiffies, timeout)) { | |
1840 | ERR("Timeout for reset\n"); | |
1841 | break; | |
1842 | } | |
1843 | cpu_relax(); | |
1844 | } | |
1845 | ||
1846 | /* Write 1s to the flush register */ | |
1847 | fsl_writel(0xffffffff, &dr_regs->endptflush); | |
1848 | ||
1849 | if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) { | |
1850 | VDBG("Bus reset"); | |
83722bc9 AG |
1851 | /* Bus is reseting */ |
1852 | udc->bus_reset = 1; | |
b504882d LY |
1853 | /* Reset all the queues, include XD, dTD, EP queue |
1854 | * head and TR Queue */ | |
1855 | reset_queues(udc); | |
1856 | udc->usb_state = USB_STATE_DEFAULT; | |
1857 | } else { | |
1858 | VDBG("Controller reset"); | |
1859 | /* initialize usb hw reg except for regs for EP, not | |
1860 | * touch usbintr reg */ | |
1861 | dr_controller_setup(udc); | |
1862 | ||
1863 | /* Reset all internal used Queues */ | |
1864 | reset_queues(udc); | |
1865 | ||
1866 | ep0_setup(udc); | |
1867 | ||
1868 | /* Enable DR IRQ reg, Set Run bit, change udc state */ | |
1869 | dr_controller_run(udc); | |
1870 | udc->usb_state = USB_STATE_ATTACHED; | |
1871 | } | |
1872 | } | |
1873 | ||
1874 | /* | |
1875 | * USB device controller interrupt handler | |
1876 | */ | |
1877 | static irqreturn_t fsl_udc_irq(int irq, void *_udc) | |
1878 | { | |
1879 | struct fsl_udc *udc = _udc; | |
1880 | u32 irq_src; | |
1881 | irqreturn_t status = IRQ_NONE; | |
1882 | unsigned long flags; | |
1883 | ||
1884 | /* Disable ISR for OTG host mode */ | |
1885 | if (udc->stopped) | |
1886 | return IRQ_NONE; | |
1887 | spin_lock_irqsave(&udc->lock, flags); | |
1888 | irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr); | |
1889 | /* Clear notification bits */ | |
1890 | fsl_writel(irq_src, &dr_regs->usbsts); | |
1891 | ||
1892 | /* VDBG("irq_src [0x%8x]", irq_src); */ | |
1893 | ||
1894 | /* Need to resume? */ | |
1895 | if (udc->usb_state == USB_STATE_SUSPENDED) | |
1896 | if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0) | |
1897 | bus_resume(udc); | |
1898 | ||
1899 | /* USB Interrupt */ | |
1900 | if (irq_src & USB_STS_INT) { | |
1901 | VDBG("Packet int"); | |
1902 | /* Setup package, we only support ep0 as control ep */ | |
1903 | if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) { | |
1904 | tripwire_handler(udc, 0, | |
1905 | (u8 *) (&udc->local_setup_buff)); | |
1906 | setup_received_irq(udc, &udc->local_setup_buff); | |
1907 | status = IRQ_HANDLED; | |
1908 | } | |
1909 | ||
1910 | /* completion of dtd */ | |
1911 | if (fsl_readl(&dr_regs->endptcomplete)) { | |
1912 | dtd_complete_irq(udc); | |
1913 | status = IRQ_HANDLED; | |
1914 | } | |
1915 | } | |
1916 | ||
1917 | /* SOF (for ISO transfer) */ | |
1918 | if (irq_src & USB_STS_SOF) { | |
1919 | status = IRQ_HANDLED; | |
1920 | } | |
1921 | ||
1922 | /* Port Change */ | |
1923 | if (irq_src & USB_STS_PORT_CHANGE) { | |
1924 | port_change_irq(udc); | |
1925 | status = IRQ_HANDLED; | |
1926 | } | |
1927 | ||
1928 | /* Reset Received */ | |
1929 | if (irq_src & USB_STS_RESET) { | |
83722bc9 | 1930 | VDBG("reset int"); |
b504882d LY |
1931 | reset_irq(udc); |
1932 | status = IRQ_HANDLED; | |
1933 | } | |
1934 | ||
1935 | /* Sleep Enable (Suspend) */ | |
1936 | if (irq_src & USB_STS_SUSPEND) { | |
1937 | suspend_irq(udc); | |
1938 | status = IRQ_HANDLED; | |
1939 | } | |
1940 | ||
1941 | if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) { | |
bf7409a2 | 1942 | VDBG("Error IRQ %x", irq_src); |
b504882d LY |
1943 | } |
1944 | ||
1945 | spin_unlock_irqrestore(&udc->lock, flags); | |
1946 | return status; | |
1947 | } | |
1948 | ||
1949 | /*----------------------------------------------------------------* | |
1950 | * Hook to gadget drivers | |
1951 | * Called by initialization code of gadget drivers | |
1952 | *----------------------------------------------------------------*/ | |
0f91349b | 1953 | static int fsl_start(struct usb_gadget_driver *driver, |
b0fca50f | 1954 | int (*bind)(struct usb_gadget *)) |
b504882d LY |
1955 | { |
1956 | int retval = -ENODEV; | |
1957 | unsigned long flags = 0; | |
1958 | ||
1959 | if (!udc_controller) | |
1960 | return -ENODEV; | |
1961 | ||
7177aed4 | 1962 | if (!driver || driver->max_speed < USB_SPEED_FULL |
b0fca50f | 1963 | || !bind || !driver->disconnect || !driver->setup) |
b504882d LY |
1964 | return -EINVAL; |
1965 | ||
1966 | if (udc_controller->driver) | |
1967 | return -EBUSY; | |
1968 | ||
1969 | /* lock is needed but whether should use this lock or another */ | |
1970 | spin_lock_irqsave(&udc_controller->lock, flags); | |
1971 | ||
7483cff8 | 1972 | driver->driver.bus = NULL; |
b504882d LY |
1973 | /* hook up the driver */ |
1974 | udc_controller->driver = driver; | |
1975 | udc_controller->gadget.dev.driver = &driver->driver; | |
1976 | spin_unlock_irqrestore(&udc_controller->lock, flags); | |
1977 | ||
1978 | /* bind udc driver to gadget driver */ | |
b0fca50f | 1979 | retval = bind(&udc_controller->gadget); |
b504882d LY |
1980 | if (retval) { |
1981 | VDBG("bind to %s --> %d", driver->driver.name, retval); | |
7483cff8 WN |
1982 | udc_controller->gadget.dev.driver = NULL; |
1983 | udc_controller->driver = NULL; | |
b504882d LY |
1984 | goto out; |
1985 | } | |
1986 | ||
ded017ee | 1987 | if (!IS_ERR_OR_NULL(udc_controller->transceiver)) { |
83722bc9 AG |
1988 | /* Suspend the controller until OTG enable it */ |
1989 | udc_controller->stopped = 1; | |
1990 | printk(KERN_INFO "Suspend udc for OTG auto detect\n"); | |
1991 | ||
1992 | /* connect to bus through transceiver */ | |
ded017ee | 1993 | if (!IS_ERR_OR_NULL(udc_controller->transceiver)) { |
6e13c650 HK |
1994 | retval = otg_set_peripheral( |
1995 | udc_controller->transceiver->otg, | |
83722bc9 AG |
1996 | &udc_controller->gadget); |
1997 | if (retval < 0) { | |
1998 | ERR("can't bind to transceiver\n"); | |
1999 | driver->unbind(&udc_controller->gadget); | |
2000 | udc_controller->gadget.dev.driver = 0; | |
2001 | udc_controller->driver = 0; | |
2002 | return retval; | |
2003 | } | |
2004 | } | |
2005 | } else { | |
2006 | /* Enable DR IRQ reg and set USBCMD reg Run bit */ | |
2007 | dr_controller_run(udc_controller); | |
2008 | udc_controller->usb_state = USB_STATE_ATTACHED; | |
2009 | udc_controller->ep0_state = WAIT_FOR_SETUP; | |
2010 | udc_controller->ep0_dir = 0; | |
2011 | } | |
bf7409a2 | 2012 | printk(KERN_INFO "%s: bind to driver %s\n", |
b504882d LY |
2013 | udc_controller->gadget.name, driver->driver.name); |
2014 | ||
2015 | out: | |
2016 | if (retval) | |
6f8aa65b FS |
2017 | printk(KERN_WARNING "gadget driver register failed %d\n", |
2018 | retval); | |
b504882d LY |
2019 | return retval; |
2020 | } | |
b504882d LY |
2021 | |
2022 | /* Disconnect from gadget driver */ | |
0f91349b | 2023 | static int fsl_stop(struct usb_gadget_driver *driver) |
b504882d LY |
2024 | { |
2025 | struct fsl_ep *loop_ep; | |
2026 | unsigned long flags; | |
2027 | ||
2028 | if (!udc_controller) | |
2029 | return -ENODEV; | |
2030 | ||
2031 | if (!driver || driver != udc_controller->driver || !driver->unbind) | |
2032 | return -EINVAL; | |
2033 | ||
ded017ee | 2034 | if (!IS_ERR_OR_NULL(udc_controller->transceiver)) |
6e13c650 | 2035 | otg_set_peripheral(udc_controller->transceiver->otg, NULL); |
b504882d LY |
2036 | |
2037 | /* stop DR, disable intr */ | |
2038 | dr_controller_stop(udc_controller); | |
2039 | ||
2040 | /* in fact, no needed */ | |
2041 | udc_controller->usb_state = USB_STATE_ATTACHED; | |
2042 | udc_controller->ep0_state = WAIT_FOR_SETUP; | |
2043 | udc_controller->ep0_dir = 0; | |
2044 | ||
2045 | /* stand operation */ | |
2046 | spin_lock_irqsave(&udc_controller->lock, flags); | |
2047 | udc_controller->gadget.speed = USB_SPEED_UNKNOWN; | |
2048 | nuke(&udc_controller->eps[0], -ESHUTDOWN); | |
2049 | list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list, | |
2050 | ep.ep_list) | |
2051 | nuke(loop_ep, -ESHUTDOWN); | |
2052 | spin_unlock_irqrestore(&udc_controller->lock, flags); | |
2053 | ||
1f15a506 AV |
2054 | /* report disconnect; the controller is already quiesced */ |
2055 | driver->disconnect(&udc_controller->gadget); | |
2056 | ||
b504882d LY |
2057 | /* unbind gadget and unhook driver. */ |
2058 | driver->unbind(&udc_controller->gadget); | |
7483cff8 WN |
2059 | udc_controller->gadget.dev.driver = NULL; |
2060 | udc_controller->driver = NULL; | |
b504882d | 2061 | |
6f8aa65b FS |
2062 | printk(KERN_WARNING "unregistered gadget driver '%s'\n", |
2063 | driver->driver.name); | |
b504882d LY |
2064 | return 0; |
2065 | } | |
b504882d LY |
2066 | |
2067 | /*------------------------------------------------------------------------- | |
2068 | PROC File System Support | |
2069 | -------------------------------------------------------------------------*/ | |
2070 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
2071 | ||
2072 | #include <linux/seq_file.h> | |
2073 | ||
2074 | static const char proc_filename[] = "driver/fsl_usb2_udc"; | |
2075 | ||
2076 | static int fsl_proc_read(char *page, char **start, off_t off, int count, | |
2077 | int *eof, void *_dev) | |
2078 | { | |
2079 | char *buf = page; | |
2080 | char *next = buf; | |
2081 | unsigned size = count; | |
2082 | unsigned long flags; | |
2083 | int t, i; | |
2084 | u32 tmp_reg; | |
2085 | struct fsl_ep *ep = NULL; | |
2086 | struct fsl_req *req; | |
2087 | ||
2088 | struct fsl_udc *udc = udc_controller; | |
2089 | if (off != 0) | |
2090 | return 0; | |
2091 | ||
2092 | spin_lock_irqsave(&udc->lock, flags); | |
2093 | ||
dc0d5c1e | 2094 | /* ------basic driver information ---- */ |
b504882d LY |
2095 | t = scnprintf(next, size, |
2096 | DRIVER_DESC "\n" | |
2097 | "%s version: %s\n" | |
2098 | "Gadget driver: %s\n\n", | |
2099 | driver_name, DRIVER_VERSION, | |
2100 | udc->driver ? udc->driver->driver.name : "(none)"); | |
2101 | size -= t; | |
2102 | next += t; | |
2103 | ||
2104 | /* ------ DR Registers ----- */ | |
2105 | tmp_reg = fsl_readl(&dr_regs->usbcmd); | |
2106 | t = scnprintf(next, size, | |
2107 | "USBCMD reg:\n" | |
2108 | "SetupTW: %d\n" | |
2109 | "Run/Stop: %s\n\n", | |
2110 | (tmp_reg & USB_CMD_SUTW) ? 1 : 0, | |
2111 | (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop"); | |
2112 | size -= t; | |
2113 | next += t; | |
2114 | ||
2115 | tmp_reg = fsl_readl(&dr_regs->usbsts); | |
2116 | t = scnprintf(next, size, | |
2117 | "USB Status Reg:\n" | |
9d9d88c8 | 2118 | "Dr Suspend: %d Reset Received: %d System Error: %s " |
b504882d LY |
2119 | "USB Error Interrupt: %s\n\n", |
2120 | (tmp_reg & USB_STS_SUSPEND) ? 1 : 0, | |
2121 | (tmp_reg & USB_STS_RESET) ? 1 : 0, | |
2122 | (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal", | |
2123 | (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err"); | |
2124 | size -= t; | |
2125 | next += t; | |
2126 | ||
2127 | tmp_reg = fsl_readl(&dr_regs->usbintr); | |
2128 | t = scnprintf(next, size, | |
2129 | "USB Intrrupt Enable Reg:\n" | |
9d9d88c8 | 2130 | "Sleep Enable: %d SOF Received Enable: %d " |
b504882d | 2131 | "Reset Enable: %d\n" |
9d9d88c8 | 2132 | "System Error Enable: %d " |
b504882d | 2133 | "Port Change Dectected Enable: %d\n" |
9d9d88c8 | 2134 | "USB Error Intr Enable: %d USB Intr Enable: %d\n\n", |
b504882d LY |
2135 | (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0, |
2136 | (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0, | |
2137 | (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0, | |
2138 | (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0, | |
2139 | (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0, | |
2140 | (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0, | |
2141 | (tmp_reg & USB_INTR_INT_EN) ? 1 : 0); | |
2142 | size -= t; | |
2143 | next += t; | |
2144 | ||
2145 | tmp_reg = fsl_readl(&dr_regs->frindex); | |
2146 | t = scnprintf(next, size, | |
9d9d88c8 | 2147 | "USB Frame Index Reg: Frame Number is 0x%x\n\n", |
b504882d LY |
2148 | (tmp_reg & USB_FRINDEX_MASKS)); |
2149 | size -= t; | |
2150 | next += t; | |
2151 | ||
2152 | tmp_reg = fsl_readl(&dr_regs->deviceaddr); | |
2153 | t = scnprintf(next, size, | |
9d9d88c8 | 2154 | "USB Device Address Reg: Device Addr is 0x%x\n\n", |
b504882d LY |
2155 | (tmp_reg & USB_DEVICE_ADDRESS_MASK)); |
2156 | size -= t; | |
2157 | next += t; | |
2158 | ||
2159 | tmp_reg = fsl_readl(&dr_regs->endpointlistaddr); | |
2160 | t = scnprintf(next, size, | |
9d9d88c8 | 2161 | "USB Endpoint List Address Reg: " |
b504882d LY |
2162 | "Device Addr is 0x%x\n\n", |
2163 | (tmp_reg & USB_EP_LIST_ADDRESS_MASK)); | |
2164 | size -= t; | |
2165 | next += t; | |
2166 | ||
2167 | tmp_reg = fsl_readl(&dr_regs->portsc1); | |
2168 | t = scnprintf(next, size, | |
2169 | "USB Port Status&Control Reg:\n" | |
9d9d88c8 WN |
2170 | "Port Transceiver Type : %s Port Speed: %s\n" |
2171 | "PHY Low Power Suspend: %s Port Reset: %s " | |
2172 | "Port Suspend Mode: %s\n" | |
2173 | "Over-current Change: %s " | |
b504882d | 2174 | "Port Enable/Disable Change: %s\n" |
9d9d88c8 | 2175 | "Port Enabled/Disabled: %s " |
b504882d LY |
2176 | "Current Connect Status: %s\n\n", ( { |
2177 | char *s; | |
2178 | switch (tmp_reg & PORTSCX_PTS_FSLS) { | |
2179 | case PORTSCX_PTS_UTMI: | |
2180 | s = "UTMI"; break; | |
2181 | case PORTSCX_PTS_ULPI: | |
2182 | s = "ULPI "; break; | |
2183 | case PORTSCX_PTS_FSLS: | |
2184 | s = "FS/LS Serial"; break; | |
2185 | default: | |
2186 | s = "None"; break; | |
2187 | } | |
e538dfda MN |
2188 | s;} ), |
2189 | usb_speed_string(portscx_device_speed(tmp_reg)), | |
b504882d LY |
2190 | (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ? |
2191 | "Normal PHY mode" : "Low power mode", | |
2192 | (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" : | |
2193 | "Not in Reset", | |
2194 | (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in", | |
2195 | (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" : | |
2196 | "No", | |
2197 | (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" : | |
2198 | "Not change", | |
2199 | (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" : | |
2200 | "Not correct", | |
2201 | (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ? | |
2202 | "Attached" : "Not-Att"); | |
2203 | size -= t; | |
2204 | next += t; | |
2205 | ||
2206 | tmp_reg = fsl_readl(&dr_regs->usbmode); | |
2207 | t = scnprintf(next, size, | |
9d9d88c8 | 2208 | "USB Mode Reg: Controller Mode is: %s\n\n", ( { |
b504882d LY |
2209 | char *s; |
2210 | switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) { | |
2211 | case USB_MODE_CTRL_MODE_IDLE: | |
2212 | s = "Idle"; break; | |
2213 | case USB_MODE_CTRL_MODE_DEVICE: | |
2214 | s = "Device Controller"; break; | |
2215 | case USB_MODE_CTRL_MODE_HOST: | |
2216 | s = "Host Controller"; break; | |
2217 | default: | |
2218 | s = "None"; break; | |
2219 | } | |
2220 | s; | |
2221 | } )); | |
2222 | size -= t; | |
2223 | next += t; | |
2224 | ||
2225 | tmp_reg = fsl_readl(&dr_regs->endptsetupstat); | |
2226 | t = scnprintf(next, size, | |
9d9d88c8 | 2227 | "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n", |
b504882d LY |
2228 | (tmp_reg & EP_SETUP_STATUS_MASK)); |
2229 | size -= t; | |
2230 | next += t; | |
2231 | ||
2232 | for (i = 0; i < udc->max_ep / 2; i++) { | |
2233 | tmp_reg = fsl_readl(&dr_regs->endptctrl[i]); | |
2234 | t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n", | |
2235 | i, tmp_reg); | |
2236 | size -= t; | |
2237 | next += t; | |
2238 | } | |
2239 | tmp_reg = fsl_readl(&dr_regs->endpointprime); | |
9d9d88c8 | 2240 | t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg); |
b504882d LY |
2241 | size -= t; |
2242 | next += t; | |
2243 | ||
54e4026b | 2244 | #ifndef CONFIG_ARCH_MXC |
2ea6698d AG |
2245 | if (udc->pdata->have_sysif_regs) { |
2246 | tmp_reg = usb_sys_regs->snoop1; | |
2247 | t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg); | |
2248 | size -= t; | |
2249 | next += t; | |
b504882d | 2250 | |
2ea6698d AG |
2251 | tmp_reg = usb_sys_regs->control; |
2252 | t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n", | |
2253 | tmp_reg); | |
2254 | size -= t; | |
2255 | next += t; | |
2256 | } | |
54e4026b | 2257 | #endif |
b504882d LY |
2258 | |
2259 | /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */ | |
2260 | ep = &udc->eps[0]; | |
2261 | t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n", | |
2262 | ep->ep.name, ep_maxpacket(ep), ep_index(ep)); | |
2263 | size -= t; | |
2264 | next += t; | |
2265 | ||
2266 | if (list_empty(&ep->queue)) { | |
2267 | t = scnprintf(next, size, "its req queue is empty\n\n"); | |
2268 | size -= t; | |
2269 | next += t; | |
2270 | } else { | |
2271 | list_for_each_entry(req, &ep->queue, queue) { | |
2272 | t = scnprintf(next, size, | |
9d9d88c8 | 2273 | "req %p actual 0x%x length 0x%x buf %p\n", |
b504882d LY |
2274 | &req->req, req->req.actual, |
2275 | req->req.length, req->req.buf); | |
2276 | size -= t; | |
2277 | next += t; | |
2278 | } | |
2279 | } | |
2280 | /* other gadget->eplist ep */ | |
2281 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { | |
79149b8b | 2282 | if (ep->ep.desc) { |
b504882d LY |
2283 | t = scnprintf(next, size, |
2284 | "\nFor %s Maxpkt is 0x%x " | |
2285 | "index is 0x%x\n", | |
2286 | ep->ep.name, ep_maxpacket(ep), | |
2287 | ep_index(ep)); | |
2288 | size -= t; | |
2289 | next += t; | |
2290 | ||
2291 | if (list_empty(&ep->queue)) { | |
2292 | t = scnprintf(next, size, | |
2293 | "its req queue is empty\n\n"); | |
2294 | size -= t; | |
2295 | next += t; | |
2296 | } else { | |
2297 | list_for_each_entry(req, &ep->queue, queue) { | |
2298 | t = scnprintf(next, size, | |
9d9d88c8 | 2299 | "req %p actual 0x%x length " |
b504882d LY |
2300 | "0x%x buf %p\n", |
2301 | &req->req, req->req.actual, | |
2302 | req->req.length, req->req.buf); | |
2303 | size -= t; | |
2304 | next += t; | |
2305 | } /* end for each_entry of ep req */ | |
2306 | } /* end for else */ | |
2307 | } /* end for if(ep->queue) */ | |
2308 | } /* end (ep->desc) */ | |
2309 | ||
2310 | spin_unlock_irqrestore(&udc->lock, flags); | |
2311 | ||
2312 | *eof = 1; | |
2313 | return count - size; | |
2314 | } | |
2315 | ||
2316 | #define create_proc_file() create_proc_read_entry(proc_filename, \ | |
2317 | 0, NULL, fsl_proc_read, NULL) | |
2318 | ||
2319 | #define remove_proc_file() remove_proc_entry(proc_filename, NULL) | |
2320 | ||
2321 | #else /* !CONFIG_USB_GADGET_DEBUG_FILES */ | |
2322 | ||
2323 | #define create_proc_file() do {} while (0) | |
2324 | #define remove_proc_file() do {} while (0) | |
2325 | ||
2326 | #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ | |
2327 | ||
2328 | /*-------------------------------------------------------------------------*/ | |
2329 | ||
2330 | /* Release udc structures */ | |
2331 | static void fsl_udc_release(struct device *dev) | |
2332 | { | |
2333 | complete(udc_controller->done); | |
37c4fd8c | 2334 | dma_free_coherent(dev->parent, udc_controller->ep_qh_size, |
b504882d LY |
2335 | udc_controller->ep_qh, udc_controller->ep_qh_dma); |
2336 | kfree(udc_controller); | |
2337 | } | |
2338 | ||
2339 | /****************************************************************** | |
2340 | Internal structure setup functions | |
2341 | *******************************************************************/ | |
2342 | /*------------------------------------------------------------------ | |
2343 | * init resource for globle controller | |
2344 | * Return the udc handle on success or NULL on failure | |
2345 | ------------------------------------------------------------------*/ | |
4365831d LY |
2346 | static int __init struct_udc_setup(struct fsl_udc *udc, |
2347 | struct platform_device *pdev) | |
b504882d | 2348 | { |
b504882d LY |
2349 | struct fsl_usb2_platform_data *pdata; |
2350 | size_t size; | |
2351 | ||
b504882d LY |
2352 | pdata = pdev->dev.platform_data; |
2353 | udc->phy_mode = pdata->phy_mode; | |
b504882d LY |
2354 | |
2355 | udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL); | |
2356 | if (!udc->eps) { | |
2357 | ERR("malloc fsl_ep failed\n"); | |
4365831d | 2358 | return -1; |
b504882d LY |
2359 | } |
2360 | ||
2361 | /* initialized QHs, take care of alignment */ | |
2362 | size = udc->max_ep * sizeof(struct ep_queue_head); | |
2363 | if (size < QH_ALIGNMENT) | |
2364 | size = QH_ALIGNMENT; | |
2365 | else if ((size % QH_ALIGNMENT) != 0) { | |
2366 | size += QH_ALIGNMENT + 1; | |
2367 | size &= ~(QH_ALIGNMENT - 1); | |
2368 | } | |
2369 | udc->ep_qh = dma_alloc_coherent(&pdev->dev, size, | |
2370 | &udc->ep_qh_dma, GFP_KERNEL); | |
2371 | if (!udc->ep_qh) { | |
2372 | ERR("malloc QHs for udc failed\n"); | |
2373 | kfree(udc->eps); | |
4365831d | 2374 | return -1; |
b504882d LY |
2375 | } |
2376 | ||
2377 | udc->ep_qh_size = size; | |
2378 | ||
2379 | /* Initialize ep0 status request structure */ | |
2380 | /* FIXME: fsl_alloc_request() ignores ep argument */ | |
2381 | udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL), | |
2382 | struct fsl_req, req); | |
2383 | /* allocate a small amount of memory to get valid address */ | |
2384 | udc->status_req->req.buf = kmalloc(8, GFP_KERNEL); | |
b504882d LY |
2385 | |
2386 | udc->resume_state = USB_STATE_NOTATTACHED; | |
2387 | udc->usb_state = USB_STATE_POWERED; | |
2388 | udc->ep0_dir = 0; | |
2389 | udc->remote_wakeup = 0; /* default to 0 on reset */ | |
b504882d | 2390 | |
4365831d | 2391 | return 0; |
b504882d LY |
2392 | } |
2393 | ||
2394 | /*---------------------------------------------------------------- | |
2395 | * Setup the fsl_ep struct for eps | |
2396 | * Link fsl_ep->ep to gadget->ep_list | |
2397 | * ep0out is not used so do nothing here | |
2398 | * ep0in should be taken care | |
2399 | *--------------------------------------------------------------*/ | |
2400 | static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index, | |
2401 | char *name, int link) | |
2402 | { | |
2403 | struct fsl_ep *ep = &udc->eps[index]; | |
2404 | ||
2405 | ep->udc = udc; | |
2406 | strcpy(ep->name, name); | |
2407 | ep->ep.name = ep->name; | |
2408 | ||
2409 | ep->ep.ops = &fsl_ep_ops; | |
2410 | ep->stopped = 0; | |
2411 | ||
2412 | /* for ep0: maxP defined in desc | |
2413 | * for other eps, maxP is set by epautoconfig() called by gadget layer | |
2414 | */ | |
2415 | ep->ep.maxpacket = (unsigned short) ~0; | |
2416 | ||
2417 | /* the queue lists any req for this ep */ | |
2418 | INIT_LIST_HEAD(&ep->queue); | |
2419 | ||
2420 | /* gagdet.ep_list used for ep_autoconfig so no ep0 */ | |
2421 | if (link) | |
2422 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); | |
2423 | ep->gadget = &udc->gadget; | |
2424 | ep->qh = &udc->ep_qh[index]; | |
2425 | ||
2426 | return 0; | |
2427 | } | |
2428 | ||
2429 | /* Driver probe function | |
4365831d LY |
2430 | * all intialization operations implemented here except enabling usb_intr reg |
2431 | * board setup should have been done in the platform code | |
b504882d LY |
2432 | */ |
2433 | static int __init fsl_udc_probe(struct platform_device *pdev) | |
2434 | { | |
09ba0def | 2435 | struct fsl_usb2_platform_data *pdata; |
b504882d LY |
2436 | struct resource *res; |
2437 | int ret = -ENODEV; | |
2438 | unsigned int i; | |
4365831d | 2439 | u32 dccparams; |
b504882d LY |
2440 | |
2441 | if (strcmp(pdev->name, driver_name)) { | |
bf7409a2 | 2442 | VDBG("Wrong device"); |
b504882d LY |
2443 | return -ENODEV; |
2444 | } | |
2445 | ||
4365831d LY |
2446 | udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL); |
2447 | if (udc_controller == NULL) { | |
2448 | ERR("malloc udc failed\n"); | |
b504882d LY |
2449 | return -ENOMEM; |
2450 | } | |
2451 | ||
09ba0def AG |
2452 | pdata = pdev->dev.platform_data; |
2453 | udc_controller->pdata = pdata; | |
e06da9a8 WN |
2454 | spin_lock_init(&udc_controller->lock); |
2455 | udc_controller->stopped = 1; | |
2456 | ||
83722bc9 AG |
2457 | #ifdef CONFIG_USB_OTG |
2458 | if (pdata->operating_mode == FSL_USB2_DR_OTG) { | |
662dca54 | 2459 | udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 2460 | if (IS_ERR_OR_NULL(udc_controller->transceiver)) { |
83722bc9 AG |
2461 | ERR("Can't find OTG driver!\n"); |
2462 | ret = -ENODEV; | |
2463 | goto err_kfree; | |
2464 | } | |
2465 | } | |
2466 | #endif | |
2467 | ||
b504882d | 2468 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4365831d | 2469 | if (!res) { |
23d7cd04 WN |
2470 | ret = -ENXIO; |
2471 | goto err_kfree; | |
4365831d | 2472 | } |
b504882d | 2473 | |
83722bc9 | 2474 | if (pdata->operating_mode == FSL_USB2_DR_DEVICE) { |
28f65c11 | 2475 | if (!request_mem_region(res->start, resource_size(res), |
83722bc9 AG |
2476 | driver_name)) { |
2477 | ERR("request mem region for %s failed\n", pdev->name); | |
2478 | ret = -EBUSY; | |
2479 | goto err_kfree; | |
2480 | } | |
b504882d LY |
2481 | } |
2482 | ||
54e4026b | 2483 | dr_regs = ioremap(res->start, resource_size(res)); |
b504882d LY |
2484 | if (!dr_regs) { |
2485 | ret = -ENOMEM; | |
23d7cd04 | 2486 | goto err_release_mem_region; |
b504882d LY |
2487 | } |
2488 | ||
2ea6698d AG |
2489 | pdata->regs = (void *)dr_regs; |
2490 | ||
2491 | /* | |
2492 | * do platform specific init: check the clock, grab/config pins, etc. | |
2493 | */ | |
2494 | if (pdata->init && pdata->init(pdev)) { | |
2495 | ret = -ENODEV; | |
2496 | goto err_iounmap_noclk; | |
2497 | } | |
2498 | ||
2499 | /* Set accessors only after pdata->init() ! */ | |
3140d5b2 | 2500 | fsl_set_accessors(pdata); |
09ba0def | 2501 | |
54e4026b | 2502 | #ifndef CONFIG_ARCH_MXC |
2ea6698d | 2503 | if (pdata->have_sysif_regs) |
8981d76a | 2504 | usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET; |
54e4026b GL |
2505 | #endif |
2506 | ||
2507 | /* Initialize USB clocks */ | |
2508 | ret = fsl_udc_clk_init(pdev); | |
2509 | if (ret < 0) | |
2510 | goto err_iounmap_noclk; | |
b504882d | 2511 | |
4365831d LY |
2512 | /* Read Device Controller Capability Parameters register */ |
2513 | dccparams = fsl_readl(&dr_regs->dccparams); | |
2514 | if (!(dccparams & DCCPARAMS_DC)) { | |
2515 | ERR("This SOC doesn't support device role\n"); | |
2516 | ret = -ENODEV; | |
23d7cd04 | 2517 | goto err_iounmap; |
4365831d LY |
2518 | } |
2519 | /* Get max device endpoints */ | |
2520 | /* DEN is bidirectional ep number, max_ep doubles the number */ | |
2521 | udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2; | |
2522 | ||
b504882d LY |
2523 | udc_controller->irq = platform_get_irq(pdev, 0); |
2524 | if (!udc_controller->irq) { | |
2525 | ret = -ENODEV; | |
23d7cd04 | 2526 | goto err_iounmap; |
b504882d LY |
2527 | } |
2528 | ||
37b5453d | 2529 | ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED, |
b504882d LY |
2530 | driver_name, udc_controller); |
2531 | if (ret != 0) { | |
bf7409a2 | 2532 | ERR("cannot request irq %d err %d\n", |
b504882d | 2533 | udc_controller->irq, ret); |
23d7cd04 | 2534 | goto err_iounmap; |
b504882d LY |
2535 | } |
2536 | ||
4365831d LY |
2537 | /* Initialize the udc structure including QH member and other member */ |
2538 | if (struct_udc_setup(udc_controller, pdev)) { | |
2539 | ERR("Can't initialize udc data structure\n"); | |
2540 | ret = -ENOMEM; | |
23d7cd04 | 2541 | goto err_free_irq; |
4365831d LY |
2542 | } |
2543 | ||
ded017ee | 2544 | if (IS_ERR_OR_NULL(udc_controller->transceiver)) { |
83722bc9 AG |
2545 | /* initialize usb hw reg except for regs for EP, |
2546 | * leave usbintr reg untouched */ | |
2547 | dr_controller_setup(udc_controller); | |
2548 | } | |
b504882d | 2549 | |
54e4026b GL |
2550 | fsl_udc_clk_finalize(pdev); |
2551 | ||
b504882d LY |
2552 | /* Setup gadget structure */ |
2553 | udc_controller->gadget.ops = &fsl_gadget_ops; | |
d327ab5b | 2554 | udc_controller->gadget.max_speed = USB_SPEED_HIGH; |
b504882d LY |
2555 | udc_controller->gadget.ep0 = &udc_controller->eps[0].ep; |
2556 | INIT_LIST_HEAD(&udc_controller->gadget.ep_list); | |
2557 | udc_controller->gadget.speed = USB_SPEED_UNKNOWN; | |
2558 | udc_controller->gadget.name = driver_name; | |
2559 | ||
2560 | /* Setup gadget.dev and register with kernel */ | |
0031a06e | 2561 | dev_set_name(&udc_controller->gadget.dev, "gadget"); |
b504882d LY |
2562 | udc_controller->gadget.dev.release = fsl_udc_release; |
2563 | udc_controller->gadget.dev.parent = &pdev->dev; | |
cb4baf10 | 2564 | udc_controller->gadget.dev.of_node = pdev->dev.of_node; |
b504882d LY |
2565 | ret = device_register(&udc_controller->gadget.dev); |
2566 | if (ret < 0) | |
23d7cd04 | 2567 | goto err_free_irq; |
b504882d | 2568 | |
ded017ee | 2569 | if (!IS_ERR_OR_NULL(udc_controller->transceiver)) |
83722bc9 AG |
2570 | udc_controller->gadget.is_otg = 1; |
2571 | ||
b504882d LY |
2572 | /* setup QH and epctrl for ep0 */ |
2573 | ep0_setup(udc_controller); | |
2574 | ||
2575 | /* setup udc->eps[] for ep0 */ | |
2576 | struct_ep_setup(udc_controller, 0, "ep0", 0); | |
2577 | /* for ep0: the desc defined here; | |
2578 | * for other eps, gadget layer called ep_enable with defined desc | |
2579 | */ | |
80e91fd5 | 2580 | udc_controller->eps[0].ep.desc = &fsl_ep0_desc; |
b504882d LY |
2581 | udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD; |
2582 | ||
2583 | /* setup the udc->eps[] for non-control endpoints and link | |
2584 | * to gadget.ep_list */ | |
2585 | for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) { | |
2586 | char name[14]; | |
2587 | ||
2588 | sprintf(name, "ep%dout", i); | |
2589 | struct_ep_setup(udc_controller, i * 2, name, 1); | |
2590 | sprintf(name, "ep%din", i); | |
2591 | struct_ep_setup(udc_controller, i * 2 + 1, name, 1); | |
2592 | } | |
2593 | ||
2594 | /* use dma_pool for TD management */ | |
2595 | udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev, | |
2596 | sizeof(struct ep_td_struct), | |
2597 | DTD_ALIGNMENT, UDC_DMA_BOUNDARY); | |
2598 | if (udc_controller->td_pool == NULL) { | |
2599 | ret = -ENOMEM; | |
23d7cd04 | 2600 | goto err_unregister; |
b504882d | 2601 | } |
0f91349b SAS |
2602 | |
2603 | ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget); | |
2604 | if (ret) | |
2605 | goto err_del_udc; | |
2606 | ||
b504882d LY |
2607 | create_proc_file(); |
2608 | return 0; | |
2609 | ||
0f91349b SAS |
2610 | err_del_udc: |
2611 | dma_pool_destroy(udc_controller->td_pool); | |
23d7cd04 | 2612 | err_unregister: |
b504882d | 2613 | device_unregister(&udc_controller->gadget.dev); |
23d7cd04 | 2614 | err_free_irq: |
b504882d | 2615 | free_irq(udc_controller->irq, udc_controller); |
23d7cd04 | 2616 | err_iounmap: |
2ea6698d AG |
2617 | if (pdata->exit) |
2618 | pdata->exit(pdev); | |
54e4026b GL |
2619 | fsl_udc_clk_release(); |
2620 | err_iounmap_noclk: | |
b504882d | 2621 | iounmap(dr_regs); |
23d7cd04 | 2622 | err_release_mem_region: |
83722bc9 | 2623 | if (pdata->operating_mode == FSL_USB2_DR_DEVICE) |
28f65c11 | 2624 | release_mem_region(res->start, resource_size(res)); |
23d7cd04 | 2625 | err_kfree: |
4365831d | 2626 | kfree(udc_controller); |
23d7cd04 | 2627 | udc_controller = NULL; |
b504882d LY |
2628 | return ret; |
2629 | } | |
2630 | ||
2631 | /* Driver removal function | |
2632 | * Free resources and finish pending transactions | |
2633 | */ | |
2634 | static int __exit fsl_udc_remove(struct platform_device *pdev) | |
2635 | { | |
2636 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2ea6698d | 2637 | struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; |
b504882d LY |
2638 | |
2639 | DECLARE_COMPLETION(done); | |
2640 | ||
2641 | if (!udc_controller) | |
2642 | return -ENODEV; | |
0f91349b SAS |
2643 | |
2644 | usb_del_gadget_udc(&udc_controller->gadget); | |
b504882d LY |
2645 | udc_controller->done = &done; |
2646 | ||
54e4026b GL |
2647 | fsl_udc_clk_release(); |
2648 | ||
b504882d LY |
2649 | /* DR has been stopped in usb_gadget_unregister_driver() */ |
2650 | remove_proc_file(); | |
2651 | ||
2652 | /* Free allocated memory */ | |
2653 | kfree(udc_controller->status_req->req.buf); | |
2654 | kfree(udc_controller->status_req); | |
2655 | kfree(udc_controller->eps); | |
2656 | ||
2657 | dma_pool_destroy(udc_controller->td_pool); | |
2658 | free_irq(udc_controller->irq, udc_controller); | |
2659 | iounmap(dr_regs); | |
83722bc9 | 2660 | if (pdata->operating_mode == FSL_USB2_DR_DEVICE) |
28f65c11 | 2661 | release_mem_region(res->start, resource_size(res)); |
b504882d LY |
2662 | |
2663 | device_unregister(&udc_controller->gadget.dev); | |
2664 | /* free udc --wait for the release() finished */ | |
2665 | wait_for_completion(&done); | |
2666 | ||
2ea6698d AG |
2667 | /* |
2668 | * do platform specific un-initialization: | |
2669 | * release iomux pins, etc. | |
2670 | */ | |
2671 | if (pdata->exit) | |
2672 | pdata->exit(pdev); | |
2673 | ||
b504882d LY |
2674 | return 0; |
2675 | } | |
2676 | ||
2677 | /*----------------------------------------------------------------- | |
2678 | * Modify Power management attributes | |
2679 | * Used by OTG statemachine to disable gadget temporarily | |
2680 | -----------------------------------------------------------------*/ | |
2681 | static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state) | |
2682 | { | |
2683 | dr_controller_stop(udc_controller); | |
2684 | return 0; | |
2685 | } | |
2686 | ||
2687 | /*----------------------------------------------------------------- | |
2688 | * Invoked on USB resume. May be called in_interrupt. | |
2689 | * Here we start the DR controller and enable the irq | |
2690 | *-----------------------------------------------------------------*/ | |
2691 | static int fsl_udc_resume(struct platform_device *pdev) | |
2692 | { | |
2693 | /* Enable DR irq reg and set controller Run */ | |
2694 | if (udc_controller->stopped) { | |
2695 | dr_controller_setup(udc_controller); | |
2696 | dr_controller_run(udc_controller); | |
2697 | } | |
2698 | udc_controller->usb_state = USB_STATE_ATTACHED; | |
2699 | udc_controller->ep0_state = WAIT_FOR_SETUP; | |
2700 | udc_controller->ep0_dir = 0; | |
2701 | return 0; | |
2702 | } | |
2703 | ||
83722bc9 AG |
2704 | static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state) |
2705 | { | |
2706 | struct fsl_udc *udc = udc_controller; | |
2707 | u32 mode, usbcmd; | |
2708 | ||
2709 | mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK; | |
2710 | ||
2711 | pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped); | |
2712 | ||
2713 | /* | |
2714 | * If the controller is already stopped, then this must be a | |
2715 | * PM suspend. Remember this fact, so that we will leave the | |
2716 | * controller stopped at PM resume time. | |
2717 | */ | |
2718 | if (udc->stopped) { | |
2719 | pr_debug("gadget already stopped, leaving early\n"); | |
2720 | udc->already_stopped = 1; | |
2721 | return 0; | |
2722 | } | |
2723 | ||
2724 | if (mode != USB_MODE_CTRL_MODE_DEVICE) { | |
2725 | pr_debug("gadget not in device mode, leaving early\n"); | |
2726 | return 0; | |
2727 | } | |
2728 | ||
2729 | /* stop the controller */ | |
2730 | usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP; | |
2731 | fsl_writel(usbcmd, &dr_regs->usbcmd); | |
2732 | ||
2733 | udc->stopped = 1; | |
2734 | ||
2735 | pr_info("USB Gadget suspended\n"); | |
2736 | ||
2737 | return 0; | |
2738 | } | |
2739 | ||
2740 | static int fsl_udc_otg_resume(struct device *dev) | |
2741 | { | |
2742 | pr_debug("%s(): stopped %d already_stopped %d\n", __func__, | |
2743 | udc_controller->stopped, udc_controller->already_stopped); | |
2744 | ||
2745 | /* | |
2746 | * If the controller was stopped at suspend time, then | |
2747 | * don't resume it now. | |
2748 | */ | |
2749 | if (udc_controller->already_stopped) { | |
2750 | udc_controller->already_stopped = 0; | |
2751 | pr_debug("gadget was already stopped, leaving early\n"); | |
2752 | return 0; | |
2753 | } | |
2754 | ||
2755 | pr_info("USB Gadget resume\n"); | |
2756 | ||
2757 | return fsl_udc_resume(NULL); | |
2758 | } | |
2759 | ||
b504882d LY |
2760 | /*------------------------------------------------------------------------- |
2761 | Register entry point for the peripheral controller driver | |
2762 | --------------------------------------------------------------------------*/ | |
2763 | ||
2764 | static struct platform_driver udc_driver = { | |
2765 | .remove = __exit_p(fsl_udc_remove), | |
2766 | /* these suspend and resume are not usb suspend and resume */ | |
2767 | .suspend = fsl_udc_suspend, | |
2768 | .resume = fsl_udc_resume, | |
2769 | .driver = { | |
2770 | .name = (char *)driver_name, | |
2771 | .owner = THIS_MODULE, | |
83722bc9 AG |
2772 | /* udc suspend/resume called from OTG driver */ |
2773 | .suspend = fsl_udc_otg_suspend, | |
2774 | .resume = fsl_udc_otg_resume, | |
b504882d LY |
2775 | }, |
2776 | }; | |
2777 | ||
2778 | static int __init udc_init(void) | |
2779 | { | |
2780 | printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION); | |
2781 | return platform_driver_probe(&udc_driver, fsl_udc_probe); | |
2782 | } | |
2783 | ||
2784 | module_init(udc_init); | |
2785 | ||
2786 | static void __exit udc_exit(void) | |
2787 | { | |
2788 | platform_driver_unregister(&udc_driver); | |
6f8aa65b | 2789 | printk(KERN_WARNING "%s unregistered\n", driver_desc); |
b504882d LY |
2790 | } |
2791 | ||
2792 | module_exit(udc_exit); | |
2793 | ||
2794 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2795 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
2796 | MODULE_LICENSE("GPL"); | |
f34c32f1 | 2797 | MODULE_ALIAS("platform:fsl-usb2-udc"); |