projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b504882d | 1 | /* |
| 58c559e6 RM |
2 | * Copyright (C) 2004,2012 Freescale Semiconductor, Inc |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms of the GNU General Public License as published by the | |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 8 | * option) any later version. | |
| 9 | * | |
| b504882d LY |
10 | * Freescale USB device/endpoint management registers |
| 11 | */ | |
| 12 | #ifndef __FSL_USB2_UDC_H | |
| 13 | #define __FSL_USB2_UDC_H | |
| 14 | ||
| 15 | /* ### define USB registers here | |
| 16 | */ | |
| 17 | #define USB_MAX_CTRL_PAYLOAD 64 | |
| 18 | #define USB_DR_SYS_OFFSET 0x400 | |
| 19 | ||
| 20 | /* USB DR device mode registers (Little Endian) */ | |
| 21 | struct usb_dr_device { | |
| 22 | /* Capability register */ | |
| 23 | u8 res1[256]; | |
| 24 | u16 caplength; /* Capability Register Length */ | |
| 25 | u16 hciversion; /* Host Controller Interface Version */ | |
| 25985edc | 26 | u32 hcsparams; /* Host Controller Structural Parameters */ |
| b504882d LY |
27 | u32 hccparams; /* Host Controller Capability Parameters */ |
| 28 | u8 res2[20]; | |
| 29 | u32 dciversion; /* Device Controller Interface Version */ | |
| 30 | u32 dccparams; /* Device Controller Capability Parameters */ | |
| 31 | u8 res3[24]; | |
| 32 | /* Operation register */ | |
| 33 | u32 usbcmd; /* USB Command Register */ | |
| 34 | u32 usbsts; /* USB Status Register */ | |
| 35 | u32 usbintr; /* USB Interrupt Enable Register */ | |
| 36 | u32 frindex; /* Frame Index Register */ | |
| 37 | u8 res4[4]; | |
| 38 | u32 deviceaddr; /* Device Address */ | |
| 39 | u32 endpointlistaddr; /* Endpoint List Address Register */ | |
| 40 | u8 res5[4]; | |
| 41 | u32 burstsize; /* Master Interface Data Burst Size Register */ | |
| 42 | u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ | |
| 43 | u8 res6[24]; | |
| 44 | u32 configflag; /* Configure Flag Register */ | |
| 45 | u32 portsc1; /* Port 1 Status and Control Register */ | |
| 46 | u8 res7[28]; | |
| 47 | u32 otgsc; /* On-The-Go Status and Control */ | |
| 48 | u32 usbmode; /* USB Mode Register */ | |
| 49 | u32 endptsetupstat; /* Endpoint Setup Status Register */ | |
| 50 | u32 endpointprime; /* Endpoint Initialization Register */ | |
| 51 | u32 endptflush; /* Endpoint Flush Register */ | |
| 52 | u32 endptstatus; /* Endpoint Status Register */ | |
| 53 | u32 endptcomplete; /* Endpoint Complete Register */ | |
| 54 | u32 endptctrl[6]; /* Endpoint Control Registers */ | |
| 55 | }; | |
| 56 | ||
| 57 | /* USB DR host mode registers (Little Endian) */ | |
| 58 | struct usb_dr_host { | |
| 59 | /* Capability register */ | |
| 60 | u8 res1[256]; | |
| 61 | u16 caplength; /* Capability Register Length */ | |
| 62 | u16 hciversion; /* Host Controller Interface Version */ | |
| 25985edc | 63 | u32 hcsparams; /* Host Controller Structural Parameters */ |
| b504882d LY |
64 | u32 hccparams; /* Host Controller Capability Parameters */ |
| 65 | u8 res2[20]; | |
| 66 | u32 dciversion; /* Device Controller Interface Version */ | |
| 67 | u32 dccparams; /* Device Controller Capability Parameters */ | |
| 68 | u8 res3[24]; | |
| 69 | /* Operation register */ | |
| 70 | u32 usbcmd; /* USB Command Register */ | |
| 71 | u32 usbsts; /* USB Status Register */ | |
| 72 | u32 usbintr; /* USB Interrupt Enable Register */ | |
| 73 | u32 frindex; /* Frame Index Register */ | |
| 74 | u8 res4[4]; | |
| 75 | u32 periodiclistbase; /* Periodic Frame List Base Address Register */ | |
| 76 | u32 asynclistaddr; /* Current Asynchronous List Address Register */ | |
| 77 | u8 res5[4]; | |
| 78 | u32 burstsize; /* Master Interface Data Burst Size Register */ | |
| 79 | u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ | |
| 80 | u8 res6[24]; | |
| 81 | u32 configflag; /* Configure Flag Register */ | |
| 82 | u32 portsc1; /* Port 1 Status and Control Register */ | |
| 83 | u8 res7[28]; | |
| 84 | u32 otgsc; /* On-The-Go Status and Control */ | |
| 85 | u32 usbmode; /* USB Mode Register */ | |
| 86 | u32 endptsetupstat; /* Endpoint Setup Status Register */ | |
| 87 | u32 endpointprime; /* Endpoint Initialization Register */ | |
| 88 | u32 endptflush; /* Endpoint Flush Register */ | |
| 89 | u32 endptstatus; /* Endpoint Status Register */ | |
| 90 | u32 endptcomplete; /* Endpoint Complete Register */ | |
| 91 | u32 endptctrl[6]; /* Endpoint Control Registers */ | |
| 92 | }; | |
| 93 | ||
| 94 | /* non-EHCI USB system interface registers (Big Endian) */ | |
| 95 | struct usb_sys_interface { | |
| 96 | u32 snoop1; | |
| 97 | u32 snoop2; | |
| 98 | u32 age_cnt_thresh; /* Age Count Threshold Register */ | |
| 99 | u32 pri_ctrl; /* Priority Control Register */ | |
| 100 | u32 si_ctrl; /* System Interface Control Register */ | |
| 101 | u8 res[236]; | |
| 102 | u32 control; /* General Purpose Control Register */ | |
| 103 | }; | |
| 104 | ||
| 105 | /* ep0 transfer state */ | |
| 106 | #define WAIT_FOR_SETUP 0 | |
| 107 | #define DATA_STATE_XMIT 1 | |
| 108 | #define DATA_STATE_NEED_ZLP 2 | |
| 109 | #define WAIT_FOR_OUT_STATUS 3 | |
| 110 | #define DATA_STATE_RECV 4 | |
| 111 | ||
| 4365831d LY |
112 | /* Device Controller Capability Parameter register */ |
| 113 | #define DCCPARAMS_DC 0x00000080 | |
| 114 | #define DCCPARAMS_DEN_MASK 0x0000001f | |
| 115 | ||
| b504882d LY |
116 | /* Frame Index Register Bit Masks */ |
| 117 | #define USB_FRINDEX_MASKS 0x3fff | |
| 118 | /* USB CMD Register Bit Masks */ | |
| 119 | #define USB_CMD_RUN_STOP 0x00000001 | |
| 120 | #define USB_CMD_CTRL_RESET 0x00000002 | |
| 121 | #define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010 | |
| 122 | #define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020 | |
| 123 | #define USB_CMD_INT_AA_DOORBELL 0x00000040 | |
| 124 | #define USB_CMD_ASP 0x00000300 | |
| 125 | #define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800 | |
| 126 | #define USB_CMD_SUTW 0x00002000 | |
| 127 | #define USB_CMD_ATDTW 0x00004000 | |
| 128 | #define USB_CMD_ITC 0x00FF0000 | |
| 129 | ||
| 130 | /* bit 15,3,2 are frame list size */ | |
| 131 | #define USB_CMD_FRAME_SIZE_1024 0x00000000 | |
| 132 | #define USB_CMD_FRAME_SIZE_512 0x00000004 | |
| 133 | #define USB_CMD_FRAME_SIZE_256 0x00000008 | |
| 134 | #define USB_CMD_FRAME_SIZE_128 0x0000000C | |
| 135 | #define USB_CMD_FRAME_SIZE_64 0x00008000 | |
| 136 | #define USB_CMD_FRAME_SIZE_32 0x00008004 | |
| 137 | #define USB_CMD_FRAME_SIZE_16 0x00008008 | |
| 138 | #define USB_CMD_FRAME_SIZE_8 0x0000800C | |
| 139 | ||
| 140 | /* bit 9-8 are async schedule park mode count */ | |
| 141 | #define USB_CMD_ASP_00 0x00000000 | |
| 142 | #define USB_CMD_ASP_01 0x00000100 | |
| 143 | #define USB_CMD_ASP_10 0x00000200 | |
| 144 | #define USB_CMD_ASP_11 0x00000300 | |
| 145 | #define USB_CMD_ASP_BIT_POS 8 | |
| 146 | ||
| 147 | /* bit 23-16 are interrupt threshold control */ | |
| 148 | #define USB_CMD_ITC_NO_THRESHOLD 0x00000000 | |
| 149 | #define USB_CMD_ITC_1_MICRO_FRM 0x00010000 | |
| 150 | #define USB_CMD_ITC_2_MICRO_FRM 0x00020000 | |
| 151 | #define USB_CMD_ITC_4_MICRO_FRM 0x00040000 | |
| 152 | #define USB_CMD_ITC_8_MICRO_FRM 0x00080000 | |
| 153 | #define USB_CMD_ITC_16_MICRO_FRM 0x00100000 | |
| 154 | #define USB_CMD_ITC_32_MICRO_FRM 0x00200000 | |
| 155 | #define USB_CMD_ITC_64_MICRO_FRM 0x00400000 | |
| 156 | #define USB_CMD_ITC_BIT_POS 16 | |
| 157 | ||
| 158 | /* USB STS Register Bit Masks */ | |
| 159 | #define USB_STS_INT 0x00000001 | |
| 160 | #define USB_STS_ERR 0x00000002 | |
| 161 | #define USB_STS_PORT_CHANGE 0x00000004 | |
| 162 | #define USB_STS_FRM_LST_ROLL 0x00000008 | |
| 163 | #define USB_STS_SYS_ERR 0x00000010 | |
| 164 | #define USB_STS_IAA 0x00000020 | |
| 165 | #define USB_STS_RESET 0x00000040 | |
| 166 | #define USB_STS_SOF 0x00000080 | |
| 167 | #define USB_STS_SUSPEND 0x00000100 | |
| 168 | #define USB_STS_HC_HALTED 0x00001000 | |
| 169 | #define USB_STS_RCL 0x00002000 | |
| 170 | #define USB_STS_PERIODIC_SCHEDULE 0x00004000 | |
| 171 | #define USB_STS_ASYNC_SCHEDULE 0x00008000 | |
| 172 | ||
| 173 | /* USB INTR Register Bit Masks */ | |
| 174 | #define USB_INTR_INT_EN 0x00000001 | |
| 175 | #define USB_INTR_ERR_INT_EN 0x00000002 | |
| 176 | #define USB_INTR_PTC_DETECT_EN 0x00000004 | |
| 177 | #define USB_INTR_FRM_LST_ROLL_EN 0x00000008 | |
| 178 | #define USB_INTR_SYS_ERR_EN 0x00000010 | |
| 179 | #define USB_INTR_ASYN_ADV_EN 0x00000020 | |
| 180 | #define USB_INTR_RESET_EN 0x00000040 | |
| 181 | #define USB_INTR_SOF_EN 0x00000080 | |
| 182 | #define USB_INTR_DEVICE_SUSPEND 0x00000100 | |
| 183 | ||
| 184 | /* Device Address bit masks */ | |
| 185 | #define USB_DEVICE_ADDRESS_MASK 0xFE000000 | |
| 186 | #define USB_DEVICE_ADDRESS_BIT_POS 25 | |
| 187 | ||
| 188 | /* endpoint list address bit masks */ | |
| 189 | #define USB_EP_LIST_ADDRESS_MASK 0xfffff800 | |
| 190 | ||
| 191 | /* PORTSCX Register Bit Masks */ | |
| 192 | #define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001 | |
| 193 | #define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002 | |
| 194 | #define PORTSCX_PORT_ENABLE 0x00000004 | |
| 195 | #define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008 | |
| 196 | #define PORTSCX_OVER_CURRENT_ACT 0x00000010 | |
| 197 | #define PORTSCX_OVER_CURRENT_CHG 0x00000020 | |
| 198 | #define PORTSCX_PORT_FORCE_RESUME 0x00000040 | |
| 199 | #define PORTSCX_PORT_SUSPEND 0x00000080 | |
| 200 | #define PORTSCX_PORT_RESET 0x00000100 | |
| 201 | #define PORTSCX_LINE_STATUS_BITS 0x00000C00 | |
| 202 | #define PORTSCX_PORT_POWER 0x00001000 | |
| 203 | #define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000 | |
| 204 | #define PORTSCX_PORT_TEST_CTRL 0x000F0000 | |
| 205 | #define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000 | |
| 206 | #define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000 | |
| 207 | #define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000 | |
| 208 | #define PORTSCX_PHY_LOW_POWER_SPD 0x00800000 | |
| 209 | #define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000 | |
| 210 | #define PORTSCX_PORT_SPEED_MASK 0x0C000000 | |
| 211 | #define PORTSCX_PORT_WIDTH 0x10000000 | |
| 212 | #define PORTSCX_PHY_TYPE_SEL 0xC0000000 | |
| 213 | ||
| 214 | /* bit 11-10 are line status */ | |
| 215 | #define PORTSCX_LINE_STATUS_SE0 0x00000000 | |
| 216 | #define PORTSCX_LINE_STATUS_JSTATE 0x00000400 | |
| 217 | #define PORTSCX_LINE_STATUS_KSTATE 0x00000800 | |
| 218 | #define PORTSCX_LINE_STATUS_UNDEF 0x00000C00 | |
| 219 | #define PORTSCX_LINE_STATUS_BIT_POS 10 | |
| 220 | ||
| 221 | /* bit 15-14 are port indicator control */ | |
| 222 | #define PORTSCX_PIC_OFF 0x00000000 | |
| 223 | #define PORTSCX_PIC_AMBER 0x00004000 | |
| 224 | #define PORTSCX_PIC_GREEN 0x00008000 | |
| 225 | #define PORTSCX_PIC_UNDEF 0x0000C000 | |
| 226 | #define PORTSCX_PIC_BIT_POS 14 | |
| 227 | ||
| 228 | /* bit 19-16 are port test control */ | |
| 229 | #define PORTSCX_PTC_DISABLE 0x00000000 | |
| 230 | #define PORTSCX_PTC_JSTATE 0x00010000 | |
| 231 | #define PORTSCX_PTC_KSTATE 0x00020000 | |
| 232 | #define PORTSCX_PTC_SEQNAK 0x00030000 | |
| 233 | #define PORTSCX_PTC_PACKET 0x00040000 | |
| 234 | #define PORTSCX_PTC_FORCE_EN 0x00050000 | |
| 235 | #define PORTSCX_PTC_BIT_POS 16 | |
| 236 | ||
| 237 | /* bit 27-26 are port speed */ | |
| 238 | #define PORTSCX_PORT_SPEED_FULL 0x00000000 | |
| 239 | #define PORTSCX_PORT_SPEED_LOW 0x04000000 | |
| 240 | #define PORTSCX_PORT_SPEED_HIGH 0x08000000 | |
| 241 | #define PORTSCX_PORT_SPEED_UNDEF 0x0C000000 | |
| 242 | #define PORTSCX_SPEED_BIT_POS 26 | |
| 243 | ||
| 244 | /* bit 28 is parallel transceiver width for UTMI interface */ | |
| 245 | #define PORTSCX_PTW 0x10000000 | |
| 246 | #define PORTSCX_PTW_8BIT 0x00000000 | |
| 247 | #define PORTSCX_PTW_16BIT 0x10000000 | |
| 248 | ||
| 249 | /* bit 31-30 are port transceiver select */ | |
| 250 | #define PORTSCX_PTS_UTMI 0x00000000 | |
| 251 | #define PORTSCX_PTS_ULPI 0x80000000 | |
| 252 | #define PORTSCX_PTS_FSLS 0xC0000000 | |
| 253 | #define PORTSCX_PTS_BIT_POS 30 | |
| 254 | ||
| 255 | /* otgsc Register Bit Masks */ | |
| 256 | #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 | |
| 257 | #define OTGSC_CTRL_VUSB_CHARGE 0x00000002 | |
| 258 | #define OTGSC_CTRL_OTG_TERM 0x00000008 | |
| 259 | #define OTGSC_CTRL_DATA_PULSING 0x00000010 | |
| 260 | #define OTGSC_STS_USB_ID 0x00000100 | |
| 261 | #define OTGSC_STS_A_VBUS_VALID 0x00000200 | |
| 262 | #define OTGSC_STS_A_SESSION_VALID 0x00000400 | |
| 263 | #define OTGSC_STS_B_SESSION_VALID 0x00000800 | |
| 264 | #define OTGSC_STS_B_SESSION_END 0x00001000 | |
| 265 | #define OTGSC_STS_1MS_TOGGLE 0x00002000 | |
| 266 | #define OTGSC_STS_DATA_PULSING 0x00004000 | |
| 267 | #define OTGSC_INTSTS_USB_ID 0x00010000 | |
| 268 | #define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 | |
| 269 | #define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 | |
| 270 | #define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 | |
| 271 | #define OTGSC_INTSTS_B_SESSION_END 0x00100000 | |
| 272 | #define OTGSC_INTSTS_1MS 0x00200000 | |
| 273 | #define OTGSC_INTSTS_DATA_PULSING 0x00400000 | |
| 274 | #define OTGSC_INTR_USB_ID 0x01000000 | |
| 275 | #define OTGSC_INTR_A_VBUS_VALID 0x02000000 | |
| 276 | #define OTGSC_INTR_A_SESSION_VALID 0x04000000 | |
| 277 | #define OTGSC_INTR_B_SESSION_VALID 0x08000000 | |
| 278 | #define OTGSC_INTR_B_SESSION_END 0x10000000 | |
| 279 | #define OTGSC_INTR_1MS_TIMER 0x20000000 | |
| 280 | #define OTGSC_INTR_DATA_PULSING 0x40000000 | |
| 281 | ||
| 282 | /* USB MODE Register Bit Masks */ | |
| 283 | #define USB_MODE_CTRL_MODE_IDLE 0x00000000 | |
| 284 | #define USB_MODE_CTRL_MODE_DEVICE 0x00000002 | |
| 285 | #define USB_MODE_CTRL_MODE_HOST 0x00000003 | |
| 2ea6698d | 286 | #define USB_MODE_CTRL_MODE_MASK 0x00000003 |
| b504882d | 287 | #define USB_MODE_CTRL_MODE_RSV 0x00000001 |
| 2ea6698d | 288 | #define USB_MODE_ES 0x00000004 /* Endian Select */ |
| b504882d LY |
289 | #define USB_MODE_SETUP_LOCK_OFF 0x00000008 |
| 290 | #define USB_MODE_STREAM_DISABLE 0x00000010 | |
| 291 | /* Endpoint Flush Register */ | |
| 292 | #define EPFLUSH_TX_OFFSET 0x00010000 | |
| 293 | #define EPFLUSH_RX_OFFSET 0x00000000 | |
| 294 | ||
| 295 | /* Endpoint Setup Status bit masks */ | |
| 296 | #define EP_SETUP_STATUS_MASK 0x0000003F | |
| 297 | #define EP_SETUP_STATUS_EP0 0x00000001 | |
| 298 | ||
| 299 | /* ENDPOINTCTRLx Register Bit Masks */ | |
| 300 | #define EPCTRL_TX_ENABLE 0x00800000 | |
| 301 | #define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */ | |
| 302 | #define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */ | |
| 303 | #define EPCTRL_TX_TYPE 0x000C0000 | |
| 304 | #define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */ | |
| 305 | #define EPCTRL_TX_EP_STALL 0x00010000 | |
| 306 | #define EPCTRL_RX_ENABLE 0x00000080 | |
| 307 | #define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */ | |
| 308 | #define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */ | |
| 309 | #define EPCTRL_RX_TYPE 0x0000000C | |
| 310 | #define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */ | |
| 311 | #define EPCTRL_RX_EP_STALL 0x00000001 | |
| 312 | ||
| 313 | /* bit 19-18 and 3-2 are endpoint type */ | |
| 314 | #define EPCTRL_EP_TYPE_CONTROL 0 | |
| 315 | #define EPCTRL_EP_TYPE_ISO 1 | |
| 316 | #define EPCTRL_EP_TYPE_BULK 2 | |
| 317 | #define EPCTRL_EP_TYPE_INTERRUPT 3 | |
| 318 | #define EPCTRL_TX_EP_TYPE_SHIFT 18 | |
| 319 | #define EPCTRL_RX_EP_TYPE_SHIFT 2 | |
| 320 | ||
| 321 | /* SNOOPn Register Bit Masks */ | |
| 322 | #define SNOOP_ADDRESS_MASK 0xFFFFF000 | |
| 323 | #define SNOOP_SIZE_ZERO 0x00 /* snooping disable */ | |
| 324 | #define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */ | |
| 325 | #define SNOOP_SIZE_8KB 0x0C | |
| 326 | #define SNOOP_SIZE_16KB 0x0D | |
| 327 | #define SNOOP_SIZE_32KB 0x0E | |
| 328 | #define SNOOP_SIZE_64KB 0x0F | |
| 329 | #define SNOOP_SIZE_128KB 0x10 | |
| 330 | #define SNOOP_SIZE_256KB 0x11 | |
| 331 | #define SNOOP_SIZE_512KB 0x12 | |
| 332 | #define SNOOP_SIZE_1MB 0x13 | |
| 333 | #define SNOOP_SIZE_2MB 0x14 | |
| 334 | #define SNOOP_SIZE_4MB 0x15 | |
| 335 | #define SNOOP_SIZE_8MB 0x16 | |
| 336 | #define SNOOP_SIZE_16MB 0x17 | |
| 337 | #define SNOOP_SIZE_32MB 0x18 | |
| 338 | #define SNOOP_SIZE_64MB 0x19 | |
| 339 | #define SNOOP_SIZE_128MB 0x1A | |
| 340 | #define SNOOP_SIZE_256MB 0x1B | |
| 341 | #define SNOOP_SIZE_512MB 0x1C | |
| 342 | #define SNOOP_SIZE_1GB 0x1D | |
| 343 | #define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */ | |
| 344 | ||
| 345 | /* pri_ctrl Register Bit Masks */ | |
| 346 | #define PRI_CTRL_PRI_LVL1 0x0000000C | |
| 347 | #define PRI_CTRL_PRI_LVL0 0x00000003 | |
| 348 | ||
| 349 | /* si_ctrl Register Bit Masks */ | |
| 350 | #define SI_CTRL_ERR_DISABLE 0x00000010 | |
| 351 | #define SI_CTRL_IDRC_DISABLE 0x00000008 | |
| 352 | #define SI_CTRL_RD_SAFE_EN 0x00000004 | |
| 353 | #define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002 | |
| 354 | #define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001 | |
| 355 | ||
| 356 | /* control Register Bit Masks */ | |
| 357 | #define USB_CTRL_IOENB 0x00000004 | |
| 358 | #define USB_CTRL_ULPI_INT0EN 0x00000001 | |
| 58c559e6 RM |
359 | #define USB_CTRL_UTMI_PHY_EN 0x00000200 |
| 360 | #define USB_CTRL_USB_EN 0x00000004 | |
| 361 | #define USB_CTRL_ULPI_PHY_CLK_SEL 0x00000400 | |
| b504882d LY |
362 | |
| 363 | /* Endpoint Queue Head data struct | |
| 364 | * Rem: all the variables of qh are LittleEndian Mode | |
| 365 | * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr | |
| 366 | */ | |
| 367 | struct ep_queue_head { | |
| 368 | u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len | |
| 369 | and IOS(15) */ | |
| 370 | u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */ | |
| 371 | u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */ | |
| 372 | u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15), | |
| 373 | MultO(11-10), STS (7-0) */ | |
| 374 | u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */ | |
| 375 | u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */ | |
| 376 | u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */ | |
| 377 | u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */ | |
| 378 | u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */ | |
| 379 | u32 res1; | |
| 380 | u8 setup_buffer[8]; /* Setup data 8 bytes */ | |
| 381 | u32 res2[4]; | |
| 382 | }; | |
| 383 | ||
| 384 | /* Endpoint Queue Head Bit Masks */ | |
| 385 | #define EP_QUEUE_HEAD_MULT_POS 30 | |
| 386 | #define EP_QUEUE_HEAD_ZLT_SEL 0x20000000 | |
| 387 | #define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16 | |
| 388 | #define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) | |
| 389 | #define EP_QUEUE_HEAD_IOS 0x00008000 | |
| 390 | #define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001 | |
| 391 | #define EP_QUEUE_HEAD_IOC 0x00008000 | |
| 392 | #define EP_QUEUE_HEAD_MULTO 0x00000C00 | |
| 393 | #define EP_QUEUE_HEAD_STATUS_HALT 0x00000040 | |
| 394 | #define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080 | |
| 395 | #define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF | |
| 396 | #define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 | |
| 397 | #define EP_QUEUE_FRINDEX_MASK 0x000007FF | |
| 398 | #define EP_MAX_LENGTH_TRANSFER 0x4000 | |
| 399 | ||
| 400 | /* Endpoint Transfer Descriptor data struct */ | |
| 401 | /* Rem: all the variables of td are LittleEndian Mode */ | |
| 402 | struct ep_td_struct { | |
| 403 | u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set | |
| 404 | indicate invalid */ | |
| 405 | u32 size_ioc_sts; /* Total bytes (30-16), IOC (15), | |
| 406 | MultO(11-10), STS (7-0) */ | |
| 407 | u32 buff_ptr0; /* Buffer pointer Page 0 */ | |
| 408 | u32 buff_ptr1; /* Buffer pointer Page 1 */ | |
| 409 | u32 buff_ptr2; /* Buffer pointer Page 2 */ | |
| 410 | u32 buff_ptr3; /* Buffer pointer Page 3 */ | |
| 411 | u32 buff_ptr4; /* Buffer pointer Page 4 */ | |
| 412 | u32 res; | |
| 413 | /* 32 bytes */ | |
| 414 | dma_addr_t td_dma; /* dma address for this td */ | |
| 415 | /* virtual address of next td specified in next_td_ptr */ | |
| 416 | struct ep_td_struct *next_td_virt; | |
| 417 | }; | |
| 418 | ||
| 419 | /* Endpoint Transfer Descriptor bit Masks */ | |
| 420 | #define DTD_NEXT_TERMINATE 0x00000001 | |
| 421 | #define DTD_IOC 0x00008000 | |
| 422 | #define DTD_STATUS_ACTIVE 0x00000080 | |
| 423 | #define DTD_STATUS_HALTED 0x00000040 | |
| 424 | #define DTD_STATUS_DATA_BUFF_ERR 0x00000020 | |
| 425 | #define DTD_STATUS_TRANSACTION_ERR 0x00000008 | |
| 426 | #define DTD_RESERVED_FIELDS 0x80007300 | |
| 427 | #define DTD_ADDR_MASK 0xFFFFFFE0 | |
| 428 | #define DTD_PACKET_SIZE 0x7FFF0000 | |
| 429 | #define DTD_LENGTH_BIT_POS 16 | |
| 430 | #define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ | |
| 431 | DTD_STATUS_DATA_BUFF_ERR | \ | |
| 432 | DTD_STATUS_TRANSACTION_ERR) | |
| 433 | /* Alignment requirements; must be a power of two */ | |
| 434 | #define DTD_ALIGNMENT 0x20 | |
| 435 | #define QH_ALIGNMENT 2048 | |
| 436 | ||
| 437 | /* Controller dma boundary */ | |
| 438 | #define UDC_DMA_BOUNDARY 0x1000 | |
| 439 | ||
| b504882d LY |
440 | /*-------------------------------------------------------------------------*/ |
| 441 | ||
| 442 | /* ### driver private data | |
| 443 | */ | |
| 444 | struct fsl_req { | |
| 445 | struct usb_request req; | |
| 446 | struct list_head queue; | |
| 447 | /* ep_queue() func will add | |
| 448 | a request->queue into a udc_ep->queue 'd tail */ | |
| 449 | struct fsl_ep *ep; | |
| 450 | unsigned mapped:1; | |
| 451 | ||
| 452 | struct ep_td_struct *head, *tail; /* For dTD List | |
| 453 | cpu endian Virtual addr */ | |
| 454 | unsigned int dtd_count; | |
| 455 | }; | |
| 456 | ||
| 457 | #define REQ_UNCOMPLETE 1 | |
| 458 | ||
| 459 | struct fsl_ep { | |
| 460 | struct usb_ep ep; | |
| 461 | struct list_head queue; | |
| 462 | struct fsl_udc *udc; | |
| 463 | struct ep_queue_head *qh; | |
| b504882d LY |
464 | struct usb_gadget *gadget; |
| 465 | ||
| 466 | char name[14]; | |
| 467 | unsigned stopped:1; | |
| 468 | }; | |
| 469 | ||
| 470 | #define EP_DIR_IN 1 | |
| 471 | #define EP_DIR_OUT 0 | |
| 472 | ||
| 473 | struct fsl_udc { | |
| b504882d LY |
474 | struct usb_gadget gadget; |
| 475 | struct usb_gadget_driver *driver; | |
| 09ba0def | 476 | struct fsl_usb2_platform_data *pdata; |
| 7483cff8 | 477 | struct completion *done; /* to make sure release() is done */ |
| b504882d LY |
478 | struct fsl_ep *eps; |
| 479 | unsigned int max_ep; | |
| 480 | unsigned int irq; | |
| 481 | ||
| 482 | struct usb_ctrlrequest local_setup_buff; | |
| 483 | spinlock_t lock; | |
| 86753811 | 484 | struct usb_phy *transceiver; |
| b504882d LY |
485 | unsigned softconnect:1; |
| 486 | unsigned vbus_active:1; | |
| 487 | unsigned stopped:1; | |
| 488 | unsigned remote_wakeup:1; | |
| 83722bc9 | 489 | unsigned already_stopped:1; |
| 09ba0def | 490 | unsigned big_endian_desc:1; |
| b504882d LY |
491 | |
| 492 | struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ | |
| 493 | struct fsl_req *status_req; /* ep0 status request */ | |
| 494 | struct dma_pool *td_pool; /* dma pool for DTD */ | |
| 495 | enum fsl_usb2_phy_modes phy_mode; | |
| 496 | ||
| 497 | size_t ep_qh_size; /* size after alignment adjustment*/ | |
| 498 | dma_addr_t ep_qh_dma; /* dma address of QH */ | |
| 499 | ||
| 7483cff8 | 500 | u32 max_pipes; /* Device max pipes */ |
| 83722bc9 | 501 | u32 bus_reset; /* Device is bus resetting */ |
| b504882d LY |
502 | u32 resume_state; /* USB state to resume */ |
| 503 | u32 usb_state; /* USB current state */ | |
| b504882d LY |
504 | u32 ep0_state; /* Endpoint zero state */ |
| 505 | u32 ep0_dir; /* Endpoint zero direction: can be | |
| 506 | USB_DIR_IN or USB_DIR_OUT */ | |
| b504882d | 507 | u8 device_address; /* Device USB address */ |
| b504882d LY |
508 | }; |
| 509 | ||
| 510 | /*-------------------------------------------------------------------------*/ | |
| 511 | ||
| 512 | #ifdef DEBUG | |
| 513 | #define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \ | |
| 441b62c1 | 514 | __func__, ## args) |
| b504882d LY |
515 | #else |
| 516 | #define DBG(fmt, args...) do{}while(0) | |
| 517 | #endif | |
| 518 | ||
| 519 | #if 0 | |
| 520 | static void dump_msg(const char *label, const u8 * buf, unsigned int length) | |
| 521 | { | |
| 522 | unsigned int start, num, i; | |
| 523 | char line[52], *p; | |
| 524 | ||
| 525 | if (length >= 512) | |
| 526 | return; | |
| 527 | DBG("%s, length %u:\n", label, length); | |
| 528 | start = 0; | |
| 529 | while (length > 0) { | |
| 530 | num = min(length, 16u); | |
| 531 | p = line; | |
| 532 | for (i = 0; i < num; ++i) { | |
| 533 | if (i == 8) | |
| 534 | *p++ = ' '; | |
| 535 | sprintf(p, " %02x", buf[i]); | |
| 536 | p += 3; | |
| 537 | } | |
| 538 | *p = 0; | |
| 539 | printk(KERN_DEBUG "%6x: %s\n", start, line); | |
| 540 | buf += num; | |
| 541 | start += num; | |
| 542 | length -= num; | |
| 543 | } | |
| 544 | } | |
| 545 | #endif | |
| 546 | ||
| 547 | #ifdef VERBOSE | |
| 548 | #define VDBG DBG | |
| 549 | #else | |
| 550 | #define VDBG(stuff...) do{}while(0) | |
| 551 | #endif | |
| 552 | ||
| 00274921 | 553 | #define ERR(stuff...) pr_err("udc: " stuff) |
| b6c63937 | 554 | #define WARNING(stuff...) pr_warning("udc: " stuff) |
| 00274921 | 555 | #define INFO(stuff...) pr_info("udc: " stuff) |
| b504882d LY |
556 | |
| 557 | /*-------------------------------------------------------------------------*/ | |
| 558 | ||
| 559 | /* ### Add board specific defines here | |
| 560 | */ | |
| 561 | ||
| 562 | /* | |
| 563 | * ### pipe direction macro from device view | |
| 564 | */ | |
| 565 | #define USB_RECV 0 /* OUT EP */ | |
| 566 | #define USB_SEND 1 /* IN EP */ | |
| 567 | ||
| 568 | /* | |
| 569 | * ### internal used help routines. | |
| 570 | */ | |
| 80e91fd5 | 571 | #define ep_index(EP) ((EP)->ep.desc->bEndpointAddress&0xF) |
| b504882d LY |
572 | #define ep_maxpacket(EP) ((EP)->ep.maxpacket) |
| 573 | #define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ | |
| 80e91fd5 | 574 | USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \ |
| b504882d LY |
575 | & USB_DIR_IN)==USB_DIR_IN) |
| 576 | #define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \ | |
| 577 | &udc->eps[pipe]) | |
| 578 | #define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \ | |
| 579 | * 2 + ((windex & USB_DIR_IN) ? 1 : 0)) | |
| 580 | #define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP)) | |
| 581 | ||
| 6414e94c LY |
582 | static inline struct ep_queue_head *get_qh_by_ep(struct fsl_ep *ep) |
| 583 | { | |
| 584 | /* we only have one ep0 structure but two queue heads */ | |
| 585 | if (ep_index(ep) != 0) | |
| 586 | return ep->qh; | |
| 587 | else | |
| 588 | return &ep->udc->ep_qh[(ep->udc->ep0_dir == | |
| 589 | USB_DIR_IN) ? 1 : 0]; | |
| 590 | } | |
| 591 | ||
| 54e4026b GL |
592 | struct platform_device; |
| 593 | #ifdef CONFIG_ARCH_MXC | |
| 594 | int fsl_udc_clk_init(struct platform_device *pdev); | |
| c2c9caa9 | 595 | int fsl_udc_clk_finalize(struct platform_device *pdev); |
| 54e4026b GL |
596 | void fsl_udc_clk_release(void); |
| 597 | #else | |
| 598 | static inline int fsl_udc_clk_init(struct platform_device *pdev) | |
| 599 | { | |
| 600 | return 0; | |
| 601 | } | |
| c2c9caa9 | 602 | static inline int fsl_udc_clk_finalize(struct platform_device *pdev) |
| 54e4026b | 603 | { |
| c2c9caa9 | 604 | return 0; |
| 54e4026b GL |
605 | } |
| 606 | static inline void fsl_udc_clk_release(void) | |
| 607 | { | |
| 608 | } | |
| 609 | #endif | |
| 610 | ||
| b504882d | 611 | #endif |