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usb: gadget: net2280: Add support for PLX USB338X
[deliverable/linux.git] / drivers / usb / gadget / lpc32xx_udc.c
CommitLineData
24a28e42
RS		 1/*
2 * USB Gadget driver for LPC32xx
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Mike James
7 * Roland Stigge <stigge@antcom.de>
8 *
9 * Copyright (C) 2006 Philips Semiconductors
10 * Copyright (C) 2009 NXP Semiconductors
11 * Copyright (C) 2012 Roland Stigge
12 *
13 * Note: This driver is based on original work done by Mike James for
14 * the LPC3180.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/delay.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/list.h>
40#include <linux/interrupt.h>
41#include <linux/proc_fs.h>
42#include <linux/clk.h>
43#include <linux/usb/ch9.h>
44#include <linux/usb/gadget.h>
45#include <linux/i2c.h>
46#include <linux/kthread.h>
47#include <linux/freezer.h>
48#include <linux/dma-mapping.h>
49#include <linux/dmapool.h>
50#include <linux/workqueue.h>
51#include <linux/of.h>
52#include <linux/usb/isp1301.h>
53
54#include <asm/byteorder.h>
55#include <mach/hardware.h>
56#include <linux/io.h>
57#include <asm/irq.h>
24a28e42
RS		 58
59#include <mach/platform.h>
60#include <mach/irqs.h>
61#include <mach/board.h>
62#ifdef CONFIG_USB_GADGET_DEBUG_FILES
d7dbdb5e 63#include <linux/debugfs.h>
24a28e42
RS		 64#include <linux/seq_file.h>
65#endif
66
67/*
68 * USB device configuration structure
69 */
70typedef void (*usc_chg_event)(int);
71struct lpc32xx_usbd_cfg {
72 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
73 usc_chg_event conn_chgb; /* Connection change event (optional) */
74 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
75 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
76};
77
78/*
79 * controller driver data structures
80 */
81
82/* 16 endpoints (not to be confused with 32 hardware endpoints) */
83#define NUM_ENDPOINTS 16
84
85/*
86 * IRQ indices make reading the code a little easier
87 */
88#define IRQ_USB_LP 0
89#define IRQ_USB_HP 1
90#define IRQ_USB_DEVDMA 2
91#define IRQ_USB_ATX 3
92
93#define EP_OUT 0 /* RX (from host) */
94#define EP_IN 1 /* TX (to host) */
95
96/* Returns the interrupt mask for the selected hardware endpoint */
97#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
98
99#define EP_INT_TYPE 0
100#define EP_ISO_TYPE 1
101#define EP_BLK_TYPE 2
102#define EP_CTL_TYPE 3
103
104/* EP0 states */
105#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
106#define DATA_IN 1 /* Expect dev->host transfer */
107#define DATA_OUT 2 /* Expect host->dev transfer */
108
109/* DD (DMA Descriptor) structure, requires word alignment, this is already
110 * defined in the LPC32XX USB device header file, but this version is slightly
111 * modified to tag some work data with each DMA descriptor. */
112struct lpc32xx_usbd_dd_gad {
113 u32 dd_next_phy;
114 u32 dd_setup;
115 u32 dd_buffer_addr;
116 u32 dd_status;
117 u32 dd_iso_ps_mem_addr;
118 u32 this_dma;
119 u32 iso_status[6]; /* 5 spare */
120 u32 dd_next_v;
121};
122
123/*
124 * Logical endpoint structure
125 */
126struct lpc32xx_ep {
127 struct usb_ep ep;
128 struct list_head queue;
129 struct lpc32xx_udc *udc;
130
131 u32 hwep_num_base; /* Physical hardware EP */
132 u32 hwep_num; /* Maps to hardware endpoint */
133 u32 maxpacket;
134 u32 lep;
135
136 bool is_in;
137 bool req_pending;
138 u32 eptype;
139
140 u32 totalints;
141
142 bool wedge;
24a28e42
RS		 143};
144
145/*
146 * Common UDC structure
147 */
148struct lpc32xx_udc {
149 struct usb_gadget gadget;
150 struct usb_gadget_driver *driver;
151 struct platform_device *pdev;
152 struct device *dev;
153 struct dentry *pde;
154 spinlock_t lock;
155 struct i2c_client *isp1301_i2c_client;
156
157 /* Board and device specific */
158 struct lpc32xx_usbd_cfg *board;
159 u32 io_p_start;
160 u32 io_p_size;
161 void __iomem *udp_baseaddr;
162 int udp_irq[4];
163 struct clk *usb_pll_clk;
164 struct clk *usb_slv_clk;
50856699 165 struct clk *usb_otg_clk;
24a28e42
RS		 166
167 /* DMA support */
168 u32 *udca_v_base;
169 u32 udca_p_base;
170 struct dma_pool *dd_cache;
171
172 /* Common EP and control data */
173 u32 enabled_devints;
174 u32 enabled_hwepints;
175 u32 dev_status;
176 u32 realized_eps;
177
178 /* VBUS detection, pullup, and power flags */
179 u8 vbus;
180 u8 last_vbus;
181 int pullup;
182 int poweron;
183
184 /* Work queues related to I2C support */
185 struct work_struct pullup_job;
186 struct work_struct vbus_job;
187 struct work_struct power_job;
188
189 /* USB device peripheral - various */
190 struct lpc32xx_ep ep[NUM_ENDPOINTS];
191 bool enabled;
192 bool clocked;
193 bool suspended;
194 bool selfpowered;
195 int ep0state;
196 atomic_t enabled_ep_cnt;
197 wait_queue_head_t ep_disable_wait_queue;
198};
199
200/*
201 * Endpoint request
202 */
203struct lpc32xx_request {
204 struct usb_request req;
205 struct list_head queue;
206 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
207 bool mapped;
208 bool send_zlp;
209};
210
211static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
212{
213 return container_of(g, struct lpc32xx_udc, gadget);
214}
215
216#define ep_dbg(epp, fmt, arg...) \
217 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
218#define ep_err(epp, fmt, arg...) \
219 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
220#define ep_info(epp, fmt, arg...) \
221 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
222#define ep_warn(epp, fmt, arg...) \
223 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
224
225#define UDCA_BUFF_SIZE (128)
226
227/* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
50856699 228 * be replaced with an inremap()ed pointer
24a28e42
RS		 229 * */
230#define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
24a28e42
RS		 231
232/* USB_CTRL bit defines */
233#define USB_SLAVE_HCLK_EN (1 << 24)
234#define USB_HOST_NEED_CLK_EN (1 << 21)
235#define USB_DEV_NEED_CLK_EN (1 << 22)
236
24a28e42
RS		 237/**********************************************************************
238 * USB device controller register offsets
239 **********************************************************************/
240
241#define USBD_DEVINTST(x) ((x) + 0x200)
242#define USBD_DEVINTEN(x) ((x) + 0x204)
243#define USBD_DEVINTCLR(x) ((x) + 0x208)
244#define USBD_DEVINTSET(x) ((x) + 0x20C)
245#define USBD_CMDCODE(x) ((x) + 0x210)
246#define USBD_CMDDATA(x) ((x) + 0x214)
247#define USBD_RXDATA(x) ((x) + 0x218)
248#define USBD_TXDATA(x) ((x) + 0x21C)
249#define USBD_RXPLEN(x) ((x) + 0x220)
250#define USBD_TXPLEN(x) ((x) + 0x224)
251#define USBD_CTRL(x) ((x) + 0x228)
252#define USBD_DEVINTPRI(x) ((x) + 0x22C)
253#define USBD_EPINTST(x) ((x) + 0x230)
254#define USBD_EPINTEN(x) ((x) + 0x234)
255#define USBD_EPINTCLR(x) ((x) + 0x238)
256#define USBD_EPINTSET(x) ((x) + 0x23C)
257#define USBD_EPINTPRI(x) ((x) + 0x240)
258#define USBD_REEP(x) ((x) + 0x244)
259#define USBD_EPIND(x) ((x) + 0x248)
260#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
261/* DMA support registers only below */
262/* Set, clear, or get enabled state of the DMA request status. If
263 * enabled, an IN or OUT token will start a DMA transfer for the EP */
264#define USBD_DMARST(x) ((x) + 0x250)
265#define USBD_DMARCLR(x) ((x) + 0x254)
266#define USBD_DMARSET(x) ((x) + 0x258)
267/* DMA UDCA head pointer */
268#define USBD_UDCAH(x) ((x) + 0x280)
269/* EP DMA status, enable, and disable. This is used to specifically
270 * enabled or disable DMA for a specific EP */
271#define USBD_EPDMAST(x) ((x) + 0x284)
272#define USBD_EPDMAEN(x) ((x) + 0x288)
273#define USBD_EPDMADIS(x) ((x) + 0x28C)
274/* DMA master interrupts enable and pending interrupts */
275#define USBD_DMAINTST(x) ((x) + 0x290)
276#define USBD_DMAINTEN(x) ((x) + 0x294)
277/* DMA end of transfer interrupt enable, disable, status */
278#define USBD_EOTINTST(x) ((x) + 0x2A0)
279#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
280#define USBD_EOTINTSET(x) ((x) + 0x2A8)
281/* New DD request interrupt enable, disable, status */
282#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
283#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
284#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
285/* DMA error interrupt enable, disable, status */
286#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
287#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
288#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
289
290/**********************************************************************
291 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
292 * USBD_DEVINTPRI register definitions
293 **********************************************************************/
294#define USBD_ERR_INT (1 << 9)
295#define USBD_EP_RLZED (1 << 8)
296#define USBD_TXENDPKT (1 << 7)
297#define USBD_RXENDPKT (1 << 6)
298#define USBD_CDFULL (1 << 5)
299#define USBD_CCEMPTY (1 << 4)
300#define USBD_DEV_STAT (1 << 3)
301#define USBD_EP_SLOW (1 << 2)
302#define USBD_EP_FAST (1 << 1)
303#define USBD_FRAME (1 << 0)
304
305/**********************************************************************
306 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
307 * USBD_EPINTPRI register definitions
308 **********************************************************************/
309/* End point selection macro (RX) */
310#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
311
312/* End point selection macro (TX) */
313#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
314
315/**********************************************************************
316 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
317 * USBD_EPDMAEN/USBD_EPDMADIS/
318 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
319 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
320 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
321 * register definitions
322 **********************************************************************/
323/* Endpoint selection macro */
324#define USBD_EP_SEL(e) (1 << (e))
325
326/**********************************************************************
327 * SBD_DMAINTST/USBD_DMAINTEN
328 **********************************************************************/
329#define USBD_SYS_ERR_INT (1 << 2)
330#define USBD_NEW_DD_INT (1 << 1)
331#define USBD_EOT_INT (1 << 0)
332
333/**********************************************************************
334 * USBD_RXPLEN register definitions
335 **********************************************************************/
336#define USBD_PKT_RDY (1 << 11)
337#define USBD_DV (1 << 10)
338#define USBD_PK_LEN_MASK 0x3FF
339
340/**********************************************************************
341 * USBD_CTRL register definitions
342 **********************************************************************/
343#define USBD_LOG_ENDPOINT(e) ((e) << 2)
344#define USBD_WR_EN (1 << 1)
345#define USBD_RD_EN (1 << 0)
346
347/**********************************************************************
348 * USBD_CMDCODE register definitions
349 **********************************************************************/
350#define USBD_CMD_CODE(c) ((c) << 16)
351#define USBD_CMD_PHASE(p) ((p) << 8)
352
353/**********************************************************************
354 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
355 **********************************************************************/
356#define USBD_DMAEP(e) (1 << (e))
357
358/* DD (DMA Descriptor) structure, requires word alignment */
359struct lpc32xx_usbd_dd {
360 u32 *dd_next;
361 u32 dd_setup;
362 u32 dd_buffer_addr;
363 u32 dd_status;
364 u32 dd_iso_ps_mem_addr;
365};
366
367/* dd_setup bit defines */
368#define DD_SETUP_ATLE_DMA_MODE 0x01
369#define DD_SETUP_NEXT_DD_VALID 0x04
370#define DD_SETUP_ISO_EP 0x10
371#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
372#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
373
374/* dd_status bit defines */
375#define DD_STATUS_DD_RETIRED 0x01
376#define DD_STATUS_STS_MASK 0x1E
377#define DD_STATUS_STS_NS 0x00 /* Not serviced */
378#define DD_STATUS_STS_BS 0x02 /* Being serviced */
379#define DD_STATUS_STS_NC 0x04 /* Normal completion */
380#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
381#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
382#define DD_STATUS_STS_SE 0x12 /* System error */
383#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
384#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
385#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
386#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
387#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
388
389/*
390 *
391 * Protocol engine bits below
392 *
393 */
394/* Device Interrupt Bit Definitions */
395#define FRAME_INT 0x00000001
396#define EP_FAST_INT 0x00000002
397#define EP_SLOW_INT 0x00000004
398#define DEV_STAT_INT 0x00000008
399#define CCEMTY_INT 0x00000010
400#define CDFULL_INT 0x00000020
401#define RxENDPKT_INT 0x00000040
402#define TxENDPKT_INT 0x00000080
403#define EP_RLZED_INT 0x00000100
404#define ERR_INT 0x00000200
405
406/* Rx & Tx Packet Length Definitions */
407#define PKT_LNGTH_MASK 0x000003FF
408#define PKT_DV 0x00000400
409#define PKT_RDY 0x00000800
410
411/* USB Control Definitions */
412#define CTRL_RD_EN 0x00000001
413#define CTRL_WR_EN 0x00000002
414
415/* Command Codes */
416#define CMD_SET_ADDR 0x00D00500
417#define CMD_CFG_DEV 0x00D80500
418#define CMD_SET_MODE 0x00F30500
419#define CMD_RD_FRAME 0x00F50500
420#define DAT_RD_FRAME 0x00F50200
421#define CMD_RD_TEST 0x00FD0500
422#define DAT_RD_TEST 0x00FD0200
423#define CMD_SET_DEV_STAT 0x00FE0500
424#define CMD_GET_DEV_STAT 0x00FE0500
425#define DAT_GET_DEV_STAT 0x00FE0200
426#define CMD_GET_ERR_CODE 0x00FF0500
427#define DAT_GET_ERR_CODE 0x00FF0200
428#define CMD_RD_ERR_STAT 0x00FB0500
429#define DAT_RD_ERR_STAT 0x00FB0200
430#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
431#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
432#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
433#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
434#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
435#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
436#define CMD_CLR_BUF 0x00F20500
437#define DAT_CLR_BUF 0x00F20200
438#define CMD_VALID_BUF 0x00FA0500
439
440/* Device Address Register Definitions */
441#define DEV_ADDR_MASK 0x7F
442#define DEV_EN 0x80
443
444/* Device Configure Register Definitions */
445#define CONF_DVICE 0x01
446
447/* Device Mode Register Definitions */
448#define AP_CLK 0x01
449#define INAK_CI 0x02
450#define INAK_CO 0x04
451#define INAK_II 0x08
452#define INAK_IO 0x10
453#define INAK_BI 0x20
454#define INAK_BO 0x40
455
456/* Device Status Register Definitions */
457#define DEV_CON 0x01
458#define DEV_CON_CH 0x02
459#define DEV_SUS 0x04
460#define DEV_SUS_CH 0x08
461#define DEV_RST 0x10
462
463/* Error Code Register Definitions */
464#define ERR_EC_MASK 0x0F
465#define ERR_EA 0x10
466
467/* Error Status Register Definitions */
468#define ERR_PID 0x01
469#define ERR_UEPKT 0x02
470#define ERR_DCRC 0x04
471#define ERR_TIMOUT 0x08
472#define ERR_EOP 0x10
473#define ERR_B_OVRN 0x20
474#define ERR_BTSTF 0x40
475#define ERR_TGL 0x80
476
477/* Endpoint Select Register Definitions */
478#define EP_SEL_F 0x01
479#define EP_SEL_ST 0x02
480#define EP_SEL_STP 0x04
481#define EP_SEL_PO 0x08
482#define EP_SEL_EPN 0x10
483#define EP_SEL_B_1_FULL 0x20
484#define EP_SEL_B_2_FULL 0x40
485
486/* Endpoint Status Register Definitions */
487#define EP_STAT_ST 0x01
488#define EP_STAT_DA 0x20
489#define EP_STAT_RF_MO 0x40
490#define EP_STAT_CND_ST 0x80
491
492/* Clear Buffer Register Definitions */
493#define CLR_BUF_PO 0x01
494
495/* DMA Interrupt Bit Definitions */
496#define EOT_INT 0x01
497#define NDD_REQ_INT 0x02
498#define SYS_ERR_INT 0x04
499
500#define DRIVER_VERSION "1.03"
501static const char driver_name[] = "lpc32xx_udc";
502
503/*
504 *
505 * proc interface support
506 *
507 */
508#ifdef CONFIG_USB_GADGET_DEBUG_FILES
509static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
510static const char debug_filename[] = "driver/udc";
511
512static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
513{
514 struct lpc32xx_request *req;
515
516 seq_printf(s, "\n");
517 seq_printf(s, "%12s, maxpacket %4d %3s",
518 ep->ep.name, ep->ep.maxpacket,
519 ep->is_in ? "in" : "out");
520 seq_printf(s, " type %4s", epnames[ep->eptype]);
521 seq_printf(s, " ints: %12d", ep->totalints);
522
523 if (list_empty(&ep->queue))
524 seq_printf(s, "\t(queue empty)\n");
525 else {
526 list_for_each_entry(req, &ep->queue, queue) {
527 u32 length = req->req.actual;
528
529 seq_printf(s, "\treq %p len %d/%d buf %p\n",
530 &req->req, length,
531 req->req.length, req->req.buf);
532 }
533 }
534}
535
536static int proc_udc_show(struct seq_file *s, void *unused)
537{
538 struct lpc32xx_udc *udc = s->private;
539 struct lpc32xx_ep *ep;
540 unsigned long flags;
541
542 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
543
544 spin_lock_irqsave(&udc->lock, flags);
545
546 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
547 udc->vbus ? "present" : "off",
548 udc->enabled ? (udc->vbus ? "active" : "enabled") :
549 "disabled",
550 udc->selfpowered ? "self" : "VBUS",
551 udc->suspended ? ", suspended" : "",
552 udc->driver ? udc->driver->driver.name : "(none)");
553
554 if (udc->enabled && udc->vbus) {
555 proc_ep_show(s, &udc->ep[0]);
78ca9139
RS		 556 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
557 proc_ep_show(s, ep);
24a28e42
RS		 558 }
559
560 spin_unlock_irqrestore(&udc->lock, flags);
561
562 return 0;
563}
564
565static int proc_udc_open(struct inode *inode, struct file *file)
566{
d9dda78b 567 return single_open(file, proc_udc_show, PDE_DATA(inode));
24a28e42
RS		 568}
569
570static const struct file_operations proc_ops = {
571 .owner = THIS_MODULE,
572 .open = proc_udc_open,
573 .read = seq_read,
574 .llseek = seq_lseek,
575 .release = single_release,
576};
577
578static void create_debug_file(struct lpc32xx_udc *udc)
579{
580 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
581}
582
583static void remove_debug_file(struct lpc32xx_udc *udc)
584{
585 if (udc->pde)
586 debugfs_remove(udc->pde);
587}
588
589#else
590static inline void create_debug_file(struct lpc32xx_udc *udc) {}
591static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
592#endif
593
594/* Primary initialization sequence for the ISP1301 transceiver */
595static void isp1301_udc_configure(struct lpc32xx_udc *udc)
596{
597 /* LPC32XX only supports DAT_SE0 USB mode */
598 /* This sequence is important */
599
600 /* Disable transparent UART mode first */
601 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
602 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
603 MC1_UART_EN);
604
605 /* Set full speed and SE0 mode */
606 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
607 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
608 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
609 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
610
611 /*
612 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
613 */
614 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
615 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
616 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
617 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
618
619 /* Driver VBUS_DRV high or low depending on board setup */
620 if (udc->board->vbus_drv_pol != 0)
621 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
622 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
623 else
624 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
625 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
626 OTG1_VBUS_DRV);
627
628 /* Bi-directional mode with suspend control
629 * Enable both pulldowns for now - the pullup will be enable when VBUS
630 * is detected */
631 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
632 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
633 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
634 ISP1301_I2C_OTG_CONTROL_1,
635 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
636
637 /* Discharge VBUS (just in case) */
638 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
639 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
640 msleep(1);
641 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
642 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
643 OTG1_VBUS_DISCHRG);
644
645 /* Clear and enable VBUS high edge interrupt */
646 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
647 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
648 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
649 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
650 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
651 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
652 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
653 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
654 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
655 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
656
657 /* Enable usb_need_clk clock after transceiver is initialized */
50856699 658 writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL);
24a28e42
RS		 659
660 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
661 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
662 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
663 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
664 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
665 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
666}
667
668/* Enables or disables the USB device pullup via the ISP1301 transceiver */
669static void isp1301_pullup_set(struct lpc32xx_udc *udc)
670{
671 if (udc->pullup)
672 /* Enable pullup for bus signalling */
673 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
674 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
675 else
676 /* Enable pullup for bus signalling */
677 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
678 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
679 OTG1_DP_PULLUP);
680}
681
682static void pullup_work(struct work_struct *work)
683{
684 struct lpc32xx_udc *udc =
685 container_of(work, struct lpc32xx_udc, pullup_job);
686
687 isp1301_pullup_set(udc);
688}
689
690static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
691 int block)
692{
693 if (en_pullup == udc->pullup)
694 return;
695
696 udc->pullup = en_pullup;
697 if (block)
698 isp1301_pullup_set(udc);
699 else
700 /* defer slow i2c pull up setting */
701 schedule_work(&udc->pullup_job);
702}
703
704#ifdef CONFIG_PM
705/* Powers up or down the ISP1301 transceiver */
706static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
707{
708 if (enable != 0)
709 /* Power up ISP1301 - this ISP1301 will automatically wakeup
710 when VBUS is detected */
711 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
712 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
713 MC2_GLOBAL_PWR_DN);
714 else
715 /* Power down ISP1301 */
716 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
717 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
718}
719
720static void power_work(struct work_struct *work)
721{
722 struct lpc32xx_udc *udc =
723 container_of(work, struct lpc32xx_udc, power_job);
724
725 isp1301_set_powerstate(udc, udc->poweron);
726}
727#endif
728
729/*
730 *
731 * USB protocol engine command/data read/write helper functions
732 *
733 */
734/* Issues a single command to the USB device state machine */
735static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
736{
737 u32 pass = 0;
738 int to;
739
740 /* EP may lock on CLRI if this read isn't done */
741 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
742 (void) tmp;
743
744 while (pass == 0) {
745 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
746
747 /* Write command code */
748 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
749 to = 10000;
750 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
751 USBD_CCEMPTY) == 0) && (to > 0)) {
752 to--;
753 }
754
755 if (to > 0)
756 pass = 1;
757
758 cpu_relax();
759 }
760}
761
762/* Issues 2 commands (or command and data) to the USB device state machine */
763static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
764 u32 data)
765{
766 udc_protocol_cmd_w(udc, cmd);
767 udc_protocol_cmd_w(udc, data);
768}
769
770/* Issues a single command to the USB device state machine and reads
771 * response data */
772static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
773{
774 u32 tmp;
775 int to = 1000;
776
777 /* Write a command and read data from the protocol engine */
778 writel((USBD_CDFULL | USBD_CCEMPTY),
779 USBD_DEVINTCLR(udc->udp_baseaddr));
780
781 /* Write command code */
782 udc_protocol_cmd_w(udc, cmd);
783
784 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
785 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
786 && (to > 0))
787 to--;
788 if (!to)
789 dev_dbg(udc->dev,
790 "Protocol engine didn't receive response (CDFULL)\n");
791
792 return readl(USBD_CMDDATA(udc->udp_baseaddr));
793}
794
795/*
796 *
797 * USB device interrupt mask support functions
798 *
799 */
800/* Enable one or more USB device interrupts */
801static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
802{
803 udc->enabled_devints |= devmask;
804 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
805}
806
807/* Disable one or more USB device interrupts */
808static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
809{
810 udc->enabled_devints &= ~mask;
811 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
812}
813
814/* Clear one or more USB device interrupts */
815static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
816{
817 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
818}
819
820/*
821 *
822 * Endpoint interrupt disable/enable functions
823 *
824 */
825/* Enable one or more USB endpoint interrupts */
826static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
827{
828 udc->enabled_hwepints |= (1 << hwep);
829 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
830}
831
832/* Disable one or more USB endpoint interrupts */
833static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
834{
835 udc->enabled_hwepints &= ~(1 << hwep);
836 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
837}
838
839/* Clear one or more USB endpoint interrupts */
840static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
841{
842 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
843}
844
845/* Enable DMA for the HW channel */
846static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
847{
848 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
849}
850
851/* Disable DMA for the HW channel */
852static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
853{
854 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
855}
856
857/*
858 *
859 * Endpoint realize/unrealize functions
860 *
861 */
862/* Before an endpoint can be used, it needs to be realized
863 * in the USB protocol engine - this realizes the endpoint.
864 * The interrupt (FIFO or DMA) is not enabled with this function */
865static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
866 u32 maxpacket)
867{
868 int to = 1000;
869
870 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
871 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
872 udc->realized_eps |= (1 << hwep);
873 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
874 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
875
876 /* Wait until endpoint is realized in hardware */
877 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
878 USBD_EP_RLZED)) && (to > 0))
879 to--;
880 if (!to)
881 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
882
883 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
884}
885
886/* Unrealize an EP */
887static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
888{
889 udc->realized_eps &= ~(1 << hwep);
890 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
891}
892
893/*
894 *
895 * Endpoint support functions
896 *
897 */
898/* Select and clear endpoint interrupt */
899static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
900{
901 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
902 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
903}
904
905/* Disables the endpoint in the USB protocol engine */
906static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
907{
908 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
909 DAT_WR_BYTE(EP_STAT_DA));
910}
911
912/* Stalls the endpoint - endpoint will return STALL */
913static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
914{
915 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
916 DAT_WR_BYTE(EP_STAT_ST));
917}
918
919/* Clear stall or reset endpoint */
920static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
921{
922 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
923 DAT_WR_BYTE(0));
924}
925
926/* Select an endpoint for endpoint status, clear, validate */
927static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
928{
929 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
930}
931
932/*
933 *
934 * Endpoint buffer management functions
935 *
936 */
937/* Clear the current endpoint's buffer */
938static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
939{
940 udc_select_hwep(udc, hwep);
941 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
942}
943
944/* Validate the current endpoint's buffer */
945static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
946{
947 udc_select_hwep(udc, hwep);
948 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
949}
950
951static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
952{
953 /* Clear EP interrupt */
954 uda_clear_hwepint(udc, hwep);
955 return udc_selep_clrint(udc, hwep);
956}
957
958/*
959 *
960 * USB EP DMA support
961 *
962 */
963/* Allocate a DMA Descriptor */
964static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
965{
966 dma_addr_t dma;
967 struct lpc32xx_usbd_dd_gad *dd;
968
969 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
970 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
971 if (dd)
972 dd->this_dma = dma;
973
974 return dd;
975}
976
977/* Free a DMA Descriptor */
978static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
979{
980 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
981}
982
983/*
984 *
985 * USB setup and shutdown functions
986 *
987 */
988/* Enables or disables most of the USB system clocks when low power mode is
989 * needed. Clocks are typically started on a connection event, and disabled
990 * when a cable is disconnected */
24a28e42
RS		 991static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
992{
24a28e42
RS		 993 if (enable != 0) {
994 if (udc->clocked)
995 return;
996
997 udc->clocked = 1;
998
999 /* 48MHz PLL up */
1000 clk_enable(udc->usb_pll_clk);
1001
1002 /* Enable the USB device clock */
1003 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
1004 USB_CTRL);
1005
50856699 1006 clk_enable(udc->usb_otg_clk);
24a28e42
RS		 1007 } else {
1008 if (!udc->clocked)
1009 return;
1010
1011 udc->clocked = 0;
1012
1013 /* Never disable the USB_HCLK during normal operation */
1014
1015 /* 48MHz PLL dpwn */
1016 clk_disable(udc->usb_pll_clk);
1017
50856699 1018 /* Disable the USB device clock */
24a28e42
RS		 1019 writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
1020 USB_CTRL);
1021
50856699 1022 clk_disable(udc->usb_otg_clk);
24a28e42
RS		 1023 }
1024}
1025
1026/* Set/reset USB device address */
1027static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
1028{
1029 /* Address will be latched at the end of the status phase, or
1030 latched immediately if function is called twice */
1031 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
1032 DAT_WR_BYTE(DEV_EN | addr));
1033}
1034
1035/* Setup up a IN request for DMA transfer - this consists of determining the
1036 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1037 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1038static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1039{
1040 struct lpc32xx_request *req;
1041 u32 hwep = ep->hwep_num;
1042
1043 ep->req_pending = 1;
1044
1045 /* There will always be a request waiting here */
1046 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1047
1048 /* Place the DD Descriptor into the UDCA */
1049 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1050
1051 /* Enable DMA and interrupt for the HW EP */
1052 udc_ep_dma_enable(udc, hwep);
1053
1054 /* Clear ZLP if last packet is not of MAXP size */
1055 if (req->req.length % ep->ep.maxpacket)
1056 req->send_zlp = 0;
1057
1058 return 0;
1059}
1060
1061/* Setup up a OUT request for DMA transfer - this consists of determining the
1062 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1063 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1064static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1065{
1066 struct lpc32xx_request *req;
1067 u32 hwep = ep->hwep_num;
1068
1069 ep->req_pending = 1;
1070
1071 /* There will always be a request waiting here */
1072 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1073
1074 /* Place the DD Descriptor into the UDCA */
1075 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1076
1077 /* Enable DMA and interrupt for the HW EP */
1078 udc_ep_dma_enable(udc, hwep);
1079 return 0;
1080}
1081
1082static void udc_disable(struct lpc32xx_udc *udc)
1083{
1084 u32 i;
1085
1086 /* Disable device */
1087 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1088 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1089
1090 /* Disable all device interrupts (including EP0) */
1091 uda_disable_devint(udc, 0x3FF);
1092
1093 /* Disable and reset all endpoint interrupts */
1094 for (i = 0; i < 32; i++) {
1095 uda_disable_hwepint(udc, i);
1096 uda_clear_hwepint(udc, i);
1097 udc_disable_hwep(udc, i);
1098 udc_unrealize_hwep(udc, i);
1099 udc->udca_v_base[i] = 0;
1100
1101 /* Disable and clear all interrupts and DMA */
1102 udc_ep_dma_disable(udc, i);
1103 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1104 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1105 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1106 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1107 }
1108
1109 /* Disable DMA interrupts */
1110 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1111
1112 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1113}
1114
1115static void udc_enable(struct lpc32xx_udc *udc)
1116{
1117 u32 i;
1118 struct lpc32xx_ep *ep = &udc->ep[0];
1119
1120 /* Start with known state */
1121 udc_disable(udc);
1122
1123 /* Enable device */
1124 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1125
1126 /* EP interrupts on high priority, FRAME interrupt on low priority */
1127 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1128 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1129
1130 /* Clear any pending device interrupts */
1131 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1132
1133 /* Setup UDCA - not yet used (DMA) */
1134 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1135
1136 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1137 for (i = 0; i <= 1; i++) {
1138 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1139 uda_enable_hwepint(udc, i);
1140 udc_select_hwep(udc, i);
1141 udc_clrstall_hwep(udc, i);
1142 udc_clr_buffer_hwep(udc, i);
1143 }
1144
1145 /* Device interrupt setup */
1146 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1147 USBD_EP_FAST));
1148 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1149 USBD_EP_FAST));
1150
1151 /* Set device address to 0 - called twice to force a latch in the USB
1152 engine without the need of a setup packet status closure */
1153 udc_set_address(udc, 0);
1154 udc_set_address(udc, 0);
1155
1156 /* Enable master DMA interrupts */
1157 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1158 USBD_DMAINTEN(udc->udp_baseaddr));
1159
1160 udc->dev_status = 0;
1161}
1162
1163/*
1164 *
1165 * USB device board specific events handled via callbacks
1166 *
1167 */
1168/* Connection change event - notify board function of change */
1169static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1170{
1171 /* Just notify of a connection change event (optional) */
1172 if (udc->board->conn_chgb != NULL)
1173 udc->board->conn_chgb(conn);
1174}
1175
1176/* Suspend/resume event - notify board function of change */
1177static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1178{
1179 /* Just notify of a Suspend/resume change event (optional) */
1180 if (udc->board->susp_chgb != NULL)
1181 udc->board->susp_chgb(conn);
1182
1183 if (conn)
1184 udc->suspended = 0;
1185 else
1186 udc->suspended = 1;
1187}
1188
1189/* Remote wakeup enable/disable - notify board function of change */
1190static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1191{
1192 if (udc->board->rmwk_chgb != NULL)
1193 udc->board->rmwk_chgb(udc->dev_status &
1194 (1 << USB_DEVICE_REMOTE_WAKEUP));
1195}
1196
1197/* Reads data from FIFO, adjusts for alignment and data size */
1198static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1199{
1200 int n, i, bl;
1201 u16 *p16;
1202 u32 *p32, tmp, cbytes;
1203
1204 /* Use optimal data transfer method based on source address and size */
1205 switch (((u32) data) & 0x3) {
1206 case 0: /* 32-bit aligned */
1207 p32 = (u32 *) data;
1208 cbytes = (bytes & ~0x3);
1209
1210 /* Copy 32-bit aligned data first */
1211 for (n = 0; n < cbytes; n += 4)
1212 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1213
1214 /* Handle any remaining bytes */
1215 bl = bytes - cbytes;
1216 if (bl) {
1217 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1218 for (n = 0; n < bl; n++)
1219 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1220
1221 }
1222 break;
1223
1224 case 1: /* 8-bit aligned */
1225 case 3:
1226 /* Each byte has to be handled independently */
1227 for (n = 0; n < bytes; n += 4) {
1228 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1229
1230 bl = bytes - n;
1231 if (bl > 3)
1232 bl = 3;
1233
1234 for (i = 0; i < bl; i++)
1235 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
1236 }
1237 break;
1238
1239 case 2: /* 16-bit aligned */
1240 p16 = (u16 *) data;
1241 cbytes = (bytes & ~0x3);
1242
1243 /* Copy 32-bit sized objects first with 16-bit alignment */
1244 for (n = 0; n < cbytes; n += 4) {
1245 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1246 *p16++ = (u16)(tmp & 0xFFFF);
1247 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1248 }
1249
1250 /* Handle any remaining bytes */
1251 bl = bytes - cbytes;
1252 if (bl) {
1253 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1254 for (n = 0; n < bl; n++)
1255 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1256 }
1257 break;
1258 }
1259}
1260
1261/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1262 * as EP0) that don't use DMA. This function should only be called if a packet
1263 * is known to be ready to read for the endpoint. Note that the endpoint must
1264 * be selected in the protocol engine prior to this call. */
1265static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1266 u32 bytes)
1267{
1268 u32 tmpv;
1269 int to = 1000;
1270 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1271
1272 /* Setup read of endpoint */
1273 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1274
1275 /* Wait until packet is ready */
1276 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1277 PKT_RDY) == 0) && (to > 0))
1278 to--;
1279 if (!to)
1280 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1281
1282 /* Mask out count */
1283 tmp = tmpv & PKT_LNGTH_MASK;
1284 if (bytes < tmp)
1285 tmp = bytes;
1286
1287 if ((tmp > 0) && (data != NULL))
1288 udc_pop_fifo(udc, (u8 *) data, tmp);
1289
1290 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1291
1292 /* Clear the buffer */
1293 udc_clr_buffer_hwep(udc, hwep);
1294
1295 return tmp;
1296}
1297
1298/* Stuffs data into the FIFO, adjusts for alignment and data size */
1299static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1300{
1301 int n, i, bl;
1302 u16 *p16;
1303 u32 *p32, tmp, cbytes;
1304
1305 /* Use optimal data transfer method based on source address and size */
1306 switch (((u32) data) & 0x3) {
1307 case 0: /* 32-bit aligned */
1308 p32 = (u32 *) data;
1309 cbytes = (bytes & ~0x3);
1310
1311 /* Copy 32-bit aligned data first */
1312 for (n = 0; n < cbytes; n += 4)
1313 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1314
1315 /* Handle any remaining bytes */
1316 bl = bytes - cbytes;
1317 if (bl) {
1318 tmp = 0;
1319 for (n = 0; n < bl; n++)
1320 tmp |= data[cbytes + n] << (n * 8);
1321
1322 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1323 }
1324 break;
1325
1326 case 1: /* 8-bit aligned */
1327 case 3:
1328 /* Each byte has to be handled independently */
1329 for (n = 0; n < bytes; n += 4) {
1330 bl = bytes - n;
1331 if (bl > 4)
1332 bl = 4;
1333
1334 tmp = 0;
1335 for (i = 0; i < bl; i++)
1336 tmp |= data[n + i] << (i * 8);
1337
1338 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1339 }
1340 break;
1341
1342 case 2: /* 16-bit aligned */
1343 p16 = (u16 *) data;
1344 cbytes = (bytes & ~0x3);
1345
1346 /* Copy 32-bit aligned data first */
1347 for (n = 0; n < cbytes; n += 4) {
1348 tmp = *p16++ & 0xFFFF;
1349 tmp |= (*p16++ & 0xFFFF) << 16;
1350 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1351 }
1352
1353 /* Handle any remaining bytes */
1354 bl = bytes - cbytes;
1355 if (bl) {
1356 tmp = 0;
1357 for (n = 0; n < bl; n++)
1358 tmp |= data[cbytes + n] << (n * 8);
1359
1360 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1361 }
1362 break;
1363 }
1364}
1365
1366/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1367 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1368 * protocol engine prior to this call. */
1369static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1370 u32 bytes)
1371{
1372 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1373
1374 if ((bytes > 0) && (data == NULL))
1375 return;
1376
1377 /* Setup write of endpoint */
1378 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1379
1380 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1381
1382 /* Need at least 1 byte to trigger TX */
1383 if (bytes == 0)
1384 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1385 else
1386 udc_stuff_fifo(udc, (u8 *) data, bytes);
1387
1388 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1389
1390 udc_val_buffer_hwep(udc, hwep);
1391}
1392
1393/* USB device reset - resets USB to a default state with just EP0
1394 enabled */
1395static void uda_usb_reset(struct lpc32xx_udc *udc)
1396{
1397 u32 i = 0;
1398 /* Re-init device controller and EP0 */
1399 udc_enable(udc);
1400 udc->gadget.speed = USB_SPEED_FULL;
1401
1402 for (i = 1; i < NUM_ENDPOINTS; i++) {
1403 struct lpc32xx_ep *ep = &udc->ep[i];
1404 ep->req_pending = 0;
1405 }
1406}
1407
1408/* Send a ZLP on EP0 */
1409static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1410{
1411 udc_write_hwep(udc, EP_IN, NULL, 0);
1412}
1413
1414/* Get current frame number */
1415static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1416{
1417 u16 flo, fhi;
1418
1419 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1420 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1421 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1422
1423 return (fhi << 8) | flo;
1424}
1425
1426/* Set the device as configured - enables all endpoints */
1427static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1428{
1429 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1430}
1431
1432/* Set the device as unconfigured - disables all endpoints */
1433static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1434{
1435 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1436}
1437
1438/* reinit == restore initial software state */
1439static void udc_reinit(struct lpc32xx_udc *udc)
1440{
1441 u32 i;
1442
1443 INIT_LIST_HEAD(&udc->gadget.ep_list);
1444 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1445
1446 for (i = 0; i < NUM_ENDPOINTS; i++) {
1447 struct lpc32xx_ep *ep = &udc->ep[i];
1448
1449 if (i != 0)
1450 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
e117e742 1451 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
24a28e42
RS		 1452 INIT_LIST_HEAD(&ep->queue);
1453 ep->req_pending = 0;
1454 }
1455
1456 udc->ep0state = WAIT_FOR_SETUP;
1457}
1458
1459/* Must be called with lock */
1460static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1461{
1462 struct lpc32xx_udc *udc = ep->udc;
1463
1464 list_del_init(&req->queue);
1465 if (req->req.status == -EINPROGRESS)
1466 req->req.status = status;
1467 else
1468 status = req->req.status;
1469
1470 if (ep->lep) {
369ac9cb 1471 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
24a28e42
RS		 1472
1473 /* Free DDs */
1474 udc_dd_free(udc, req->dd_desc_ptr);
1475 }
1476
1477 if (status && status != -ESHUTDOWN)
1478 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1479
1480 ep->req_pending = 0;
1481 spin_unlock(&udc->lock);
1482 req->req.complete(&ep->ep, &req->req);
1483 spin_lock(&udc->lock);
1484}
1485
1486/* Must be called with lock */
1487static void nuke(struct lpc32xx_ep *ep, int status)
1488{
1489 struct lpc32xx_request *req;
1490
1491 while (!list_empty(&ep->queue)) {
1492 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1493 done(ep, req, status);
1494 }
1495
78ca9139 1496 if (status == -ESHUTDOWN) {
24a28e42
RS		 1497 uda_disable_hwepint(ep->udc, ep->hwep_num);
1498 udc_disable_hwep(ep->udc, ep->hwep_num);
1499 }
1500}
1501
1502/* IN endpoint 0 transfer */
1503static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1504{
1505 struct lpc32xx_request *req;
1506 struct lpc32xx_ep *ep0 = &udc->ep[0];
1507 u32 tsend, ts = 0;
1508
1509 if (list_empty(&ep0->queue))
1510 /* Nothing to send */
1511 return 0;
1512 else
1513 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1514 queue);
1515
1516 tsend = ts = req->req.length - req->req.actual;
1517 if (ts == 0) {
1518 /* Send a ZLP */
1519 udc_ep0_send_zlp(udc);
1520 done(ep0, req, 0);
1521 return 1;
1522 } else if (ts > ep0->ep.maxpacket)
1523 ts = ep0->ep.maxpacket; /* Just send what we can */
1524
1525 /* Write data to the EP0 FIFO and start transfer */
1526 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1527
1528 /* Increment data pointer */
1529 req->req.actual += ts;
1530
1531 if (tsend >= ep0->ep.maxpacket)
1532 return 0; /* Stay in data transfer state */
1533
1534 /* Transfer request is complete */
1535 udc->ep0state = WAIT_FOR_SETUP;
1536 done(ep0, req, 0);
1537 return 1;
1538}
1539
1540/* OUT endpoint 0 transfer */
1541static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1542{
1543 struct lpc32xx_request *req;
1544 struct lpc32xx_ep *ep0 = &udc->ep[0];
1545 u32 tr, bufferspace;
1546
1547 if (list_empty(&ep0->queue))
1548 return 0;
1549 else
1550 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1551 queue);
1552
1553 if (req) {
1554 if (req->req.length == 0) {
1555 /* Just dequeue request */
1556 done(ep0, req, 0);
1557 udc->ep0state = WAIT_FOR_SETUP;
1558 return 1;
1559 }
1560
1561 /* Get data from FIFO */
1562 bufferspace = req->req.length - req->req.actual;
1563 if (bufferspace > ep0->ep.maxpacket)
1564 bufferspace = ep0->ep.maxpacket;
1565
1566 /* Copy data to buffer */
1567 prefetchw(req->req.buf + req->req.actual);
1568 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1569 bufferspace);
1570 req->req.actual += bufferspace;
1571
1572 if (tr < ep0->ep.maxpacket) {
1573 /* This is the last packet */
1574 done(ep0, req, 0);
1575 udc->ep0state = WAIT_FOR_SETUP;
1576 return 1;
1577 }
1578 }
1579
1580 return 0;
1581}
1582
1583/* Must be called with lock */
1584static void stop_activity(struct lpc32xx_udc *udc)
1585{
1586 struct usb_gadget_driver *driver = udc->driver;
1587 int i;
1588
1589 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1590 driver = NULL;
1591
1592 udc->gadget.speed = USB_SPEED_UNKNOWN;
1593 udc->suspended = 0;
1594
1595 for (i = 0; i < NUM_ENDPOINTS; i++) {
1596 struct lpc32xx_ep *ep = &udc->ep[i];
1597 nuke(ep, -ESHUTDOWN);
1598 }
1599 if (driver) {
1600 spin_unlock(&udc->lock);
1601 driver->disconnect(&udc->gadget);
1602 spin_lock(&udc->lock);
1603 }
1604
1605 isp1301_pullup_enable(udc, 0, 0);
1606 udc_disable(udc);
1607 udc_reinit(udc);
1608}
1609
1610/*
1611 * Activate or kill host pullup
1612 * Can be called with or without lock
1613 */
1614static void pullup(struct lpc32xx_udc *udc, int is_on)
1615{
1616 if (!udc->clocked)
1617 return;
1618
1619 if (!udc->enabled || !udc->vbus)
1620 is_on = 0;
1621
1622 if (is_on != udc->pullup)
1623 isp1301_pullup_enable(udc, is_on, 0);
1624}
1625
1626/* Must be called without lock */
1627static int lpc32xx_ep_disable(struct usb_ep *_ep)
1628{
1629 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1630 struct lpc32xx_udc *udc = ep->udc;
1631 unsigned long flags;
1632
1633 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1634 return -EINVAL;
1635 spin_lock_irqsave(&udc->lock, flags);
1636
1637 nuke(ep, -ESHUTDOWN);
1638
24a28e42
RS		 1639 /* Clear all DMA statuses for this EP */
1640 udc_ep_dma_disable(udc, ep->hwep_num);
1641 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1642 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1643 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1644 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1645
1646 /* Remove the DD pointer in the UDCA */
1647 udc->udca_v_base[ep->hwep_num] = 0;
1648
1649 /* Disable and reset endpoint and interrupt */
1650 uda_clear_hwepint(udc, ep->hwep_num);
1651 udc_unrealize_hwep(udc, ep->hwep_num);
1652
1653 ep->hwep_num = 0;
1654
1655 spin_unlock_irqrestore(&udc->lock, flags);
1656
1657 atomic_dec(&udc->enabled_ep_cnt);
1658 wake_up(&udc->ep_disable_wait_queue);
1659
1660 return 0;
1661}
1662
1663/* Must be called without lock */
1664static int lpc32xx_ep_enable(struct usb_ep *_ep,
1665 const struct usb_endpoint_descriptor *desc)
1666{
1667 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1668 struct lpc32xx_udc *udc = ep->udc;
1669 u16 maxpacket;
1670 u32 tmp;
1671 unsigned long flags;
1672
1673 /* Verify EP data */
78ca9139 1674 if ((!_ep) || (!ep) || (!desc) ||
24a28e42
RS		 1675 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1676 dev_dbg(udc->dev, "bad ep or descriptor\n");
1677 return -EINVAL;
1678 }
1679 maxpacket = usb_endpoint_maxp(desc);
1680 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1681 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1682 return -EINVAL;
1683 }
1684
1685 /* Don't touch EP0 */
1686 if (ep->hwep_num_base == 0) {
1687 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1688 return -EINVAL;
1689 }
1690
1691 /* Is driver ready? */
1692 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1693 dev_dbg(udc->dev, "bogus device state\n");
1694 return -ESHUTDOWN;
1695 }
1696
1697 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1698 switch (tmp) {
1699 case USB_ENDPOINT_XFER_CONTROL:
1700 return -EINVAL;
1701
1702 case USB_ENDPOINT_XFER_INT:
1703 if (maxpacket > ep->maxpacket) {
1704 dev_dbg(udc->dev,
1705 "Bad INT endpoint maxpacket %d\n", maxpacket);
1706 return -EINVAL;
1707 }
1708 break;
1709
1710 case USB_ENDPOINT_XFER_BULK:
1711 switch (maxpacket) {
1712 case 8:
1713 case 16:
1714 case 32:
1715 case 64:
1716 break;
1717
1718 default:
1719 dev_dbg(udc->dev,
1720 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1721 return -EINVAL;
1722 }
1723 break;
1724
1725 case USB_ENDPOINT_XFER_ISOC:
1726 break;
1727 }
1728 spin_lock_irqsave(&udc->lock, flags);
1729
1730 /* Initialize endpoint to match the selected descriptor */
1731 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
24a28e42
RS		 1732 ep->ep.maxpacket = maxpacket;
1733
1734 /* Map hardware endpoint from base and direction */
1735 if (ep->is_in)
1736 /* IN endpoints are offset 1 from the OUT endpoint */
1737 ep->hwep_num = ep->hwep_num_base + EP_IN;
1738 else
1739 ep->hwep_num = ep->hwep_num_base;
1740
1741 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1742 ep->hwep_num, maxpacket, (ep->is_in == 1));
1743
1744 /* Realize the endpoint, interrupt is enabled later when
1745 * buffers are queued, IN EPs will NAK until buffers are ready */
1746 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1747 udc_clr_buffer_hwep(udc, ep->hwep_num);
1748 uda_disable_hwepint(udc, ep->hwep_num);
1749 udc_clrstall_hwep(udc, ep->hwep_num);
1750
1751 /* Clear all DMA statuses for this EP */
1752 udc_ep_dma_disable(udc, ep->hwep_num);
1753 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1754 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1755 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1756 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1757
1758 spin_unlock_irqrestore(&udc->lock, flags);
1759
1760 atomic_inc(&udc->enabled_ep_cnt);
1761 return 0;
1762}
1763
1764/*
1765 * Allocate a USB request list
1766 * Can be called with or without lock
1767 */
1768static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1769 gfp_t gfp_flags)
1770{
1771 struct lpc32xx_request *req;
1772
1773 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1774 if (!req)
1775 return NULL;
1776
1777 INIT_LIST_HEAD(&req->queue);
1778 return &req->req;
1779}
1780
1781/*
1782 * De-allocate a USB request list
1783 * Can be called with or without lock
1784 */
1785static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1786 struct usb_request *_req)
1787{
1788 struct lpc32xx_request *req;
1789
1790 req = container_of(_req, struct lpc32xx_request, req);
1791 BUG_ON(!list_empty(&req->queue));
1792 kfree(req);
1793}
1794
1795/* Must be called without lock */
1796static int lpc32xx_ep_queue(struct usb_ep *_ep,
1797 struct usb_request *_req, gfp_t gfp_flags)
1798{
1799 struct lpc32xx_request *req;
1800 struct lpc32xx_ep *ep;
1801 struct lpc32xx_udc *udc;
1802 unsigned long flags;
1803 int status = 0;
1804
1805 req = container_of(_req, struct lpc32xx_request, req);
1806 ep = container_of(_ep, struct lpc32xx_ep, ep);
1807
1808 if (!_req || !_req->complete || !_req->buf ||
1809 !list_empty(&req->queue))
1810 return -EINVAL;
1811
1812 udc = ep->udc;
1813
78ca9139 1814 if (!_ep) {
24a28e42
RS		 1815 dev_dbg(udc->dev, "invalid ep\n");
1816 return -EINVAL;
1817 }
1818
1819
1820 if ((!udc) || (!udc->driver) ||
1821 (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1822 dev_dbg(udc->dev, "invalid device\n");
1823 return -EINVAL;
1824 }
1825
1826 if (ep->lep) {
24a28e42
RS		 1827 struct lpc32xx_usbd_dd_gad *dd;
1828
369ac9cb
FB		 1829 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1830 if (status)
1831 return status;
24a28e42
RS		 1832
1833 /* For the request, build a list of DDs */
1834 dd = udc_dd_alloc(udc);
1835 if (!dd) {
1836 /* Error allocating DD */
1837 return -ENOMEM;
1838 }
1839 req->dd_desc_ptr = dd;
1840
1841 /* Setup the DMA descriptor */
1842 dd->dd_next_phy = dd->dd_next_v = 0;
1843 dd->dd_buffer_addr = req->req.dma;
1844 dd->dd_status = 0;
1845
1846 /* Special handling for ISO EPs */
1847 if (ep->eptype == EP_ISO_TYPE) {
1848 dd->dd_setup = DD_SETUP_ISO_EP |
1849 DD_SETUP_PACKETLEN(0) |
1850 DD_SETUP_DMALENBYTES(1);
1851 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1852 if (ep->is_in)
1853 dd->iso_status[0] = req->req.length;
1854 else
1855 dd->iso_status[0] = 0;
1856 } else
1857 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1858 DD_SETUP_DMALENBYTES(req->req.length);
1859 }
1860
1861 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1862 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1863
1864 spin_lock_irqsave(&udc->lock, flags);
1865
1866 _req->status = -EINPROGRESS;
1867 _req->actual = 0;
1868 req->send_zlp = _req->zero;
1869
1870 /* Kickstart empty queues */
1871 if (list_empty(&ep->queue)) {
1872 list_add_tail(&req->queue, &ep->queue);
1873
1874 if (ep->hwep_num_base == 0) {
1875 /* Handle expected data direction */
1876 if (ep->is_in) {
1877 /* IN packet to host */
1878 udc->ep0state = DATA_IN;
1879 status = udc_ep0_in_req(udc);
1880 } else {
1881 /* OUT packet from host */
1882 udc->ep0state = DATA_OUT;
1883 status = udc_ep0_out_req(udc);
1884 }
1885 } else if (ep->is_in) {
1886 /* IN packet to host and kick off transfer */
1887 if (!ep->req_pending)
1888 udc_ep_in_req_dma(udc, ep);
1889 } else
1890 /* OUT packet from host and kick off list */
1891 if (!ep->req_pending)
1892 udc_ep_out_req_dma(udc, ep);
1893 } else
1894 list_add_tail(&req->queue, &ep->queue);
1895
1896 spin_unlock_irqrestore(&udc->lock, flags);
1897
1898 return (status < 0) ? status : 0;
1899}
1900
1901/* Must be called without lock */
1902static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1903{
1904 struct lpc32xx_ep *ep;
1905 struct lpc32xx_request *req;
1906 unsigned long flags;
1907
1908 ep = container_of(_ep, struct lpc32xx_ep, ep);
1909 if (!_ep || ep->hwep_num_base == 0)
1910 return -EINVAL;
1911
1912 spin_lock_irqsave(&ep->udc->lock, flags);
1913
1914 /* make sure it's actually queued on this endpoint */
1915 list_for_each_entry(req, &ep->queue, queue) {
1916 if (&req->req == _req)
1917 break;
1918 }
1919 if (&req->req != _req) {
1920 spin_unlock_irqrestore(&ep->udc->lock, flags);
1921 return -EINVAL;
1922 }
1923
1924 done(ep, req, -ECONNRESET);
1925
1926 spin_unlock_irqrestore(&ep->udc->lock, flags);
1927
1928 return 0;
1929}
1930
1931/* Must be called without lock */
1932static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1933{
1934 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1935 struct lpc32xx_udc *udc = ep->udc;
1936 unsigned long flags;
1937
78ca9139 1938 if ((!ep) || (ep->hwep_num <= 1))
24a28e42
RS		 1939 return -EINVAL;
1940
1941 /* Don't halt an IN EP */
1942 if (ep->is_in)
1943 return -EAGAIN;
1944
1945 spin_lock_irqsave(&udc->lock, flags);
1946
1947 if (value == 1) {
1948 /* stall */
1949 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1950 DAT_WR_BYTE(EP_STAT_ST));
1951 } else {
1952 /* End stall */
1953 ep->wedge = 0;
1954 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1955 DAT_WR_BYTE(0));
1956 }
1957
1958 spin_unlock_irqrestore(&udc->lock, flags);
1959
1960 return 0;
1961}
1962
1963/* set the halt feature and ignores clear requests */
1964static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1965{
1966 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1967
1968 if (!_ep || !ep->udc)
1969 return -EINVAL;
1970
1971 ep->wedge = 1;
1972
1973 return usb_ep_set_halt(_ep);
1974}
1975
1976static const struct usb_ep_ops lpc32xx_ep_ops = {
1977 .enable = lpc32xx_ep_enable,
1978 .disable = lpc32xx_ep_disable,
1979 .alloc_request = lpc32xx_ep_alloc_request,
1980 .free_request = lpc32xx_ep_free_request,
1981 .queue = lpc32xx_ep_queue,
1982 .dequeue = lpc32xx_ep_dequeue,
1983 .set_halt = lpc32xx_ep_set_halt,
1984 .set_wedge = lpc32xx_ep_set_wedge,
1985};
1986
1987/* Send a ZLP on a non-0 IN EP */
1988void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1989{
1990 /* Clear EP status */
1991 udc_clearep_getsts(udc, ep->hwep_num);
1992
1993 /* Send ZLP via FIFO mechanism */
1994 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1995}
1996
1997/*
1998 * Handle EP completion for ZLP
1999 * This function will only be called when a delayed ZLP needs to be sent out
2000 * after a DMA transfer has filled both buffers.
2001 */
2002void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2003{
2004 u32 epstatus;
2005 struct lpc32xx_request *req;
2006
2007 if (ep->hwep_num <= 0)
2008 return;
2009
2010 uda_clear_hwepint(udc, ep->hwep_num);
2011
2012 /* If this interrupt isn't enabled, return now */
2013 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
2014 return;
2015
2016 /* Get endpoint status */
2017 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2018
2019 /*
2020 * This should never happen, but protect against writing to the
2021 * buffer when full.
2022 */
2023 if (epstatus & EP_SEL_F)
2024 return;
2025
2026 if (ep->is_in) {
2027 udc_send_in_zlp(udc, ep);
2028 uda_disable_hwepint(udc, ep->hwep_num);
2029 } else
2030 return;
2031
2032 /* If there isn't a request waiting, something went wrong */
2033 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2034 if (req) {
2035 done(ep, req, 0);
2036
2037 /* Start another request if ready */
2038 if (!list_empty(&ep->queue)) {
2039 if (ep->is_in)
2040 udc_ep_in_req_dma(udc, ep);
2041 else
2042 udc_ep_out_req_dma(udc, ep);
2043 } else
2044 ep->req_pending = 0;
2045 }
2046}
2047
2048
2049/* DMA end of transfer completion */
2050static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2051{
2052 u32 status, epstatus;
2053 struct lpc32xx_request *req;
2054 struct lpc32xx_usbd_dd_gad *dd;
2055
2056#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2057 ep->totalints++;
2058#endif
2059
2060 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2061 if (!req) {
2062 ep_err(ep, "DMA interrupt on no req!\n");
2063 return;
2064 }
2065 dd = req->dd_desc_ptr;
2066
2067 /* DMA descriptor should always be retired for this call */
2068 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2069 ep_warn(ep, "DMA descriptor did not retire\n");
2070
2071 /* Disable DMA */
2072 udc_ep_dma_disable(udc, ep->hwep_num);
2073 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2074 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2075
2076 /* System error? */
2077 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2078 (1 << ep->hwep_num)) {
2079 writel((1 << ep->hwep_num),
2080 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2081 ep_err(ep, "AHB critical error!\n");
2082 ep->req_pending = 0;
2083
2084 /* The error could have occurred on a packet of a multipacket
2085 * transfer, so recovering the transfer is not possible. Close
2086 * the request with an error */
2087 done(ep, req, -ECONNABORTED);
2088 return;
2089 }
2090
2091 /* Handle the current DD's status */
2092 status = dd->dd_status;
2093 switch (status & DD_STATUS_STS_MASK) {
2094 case DD_STATUS_STS_NS:
2095 /* DD not serviced? This shouldn't happen! */
2096 ep->req_pending = 0;
2097 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2098 status);
2099
2100 done(ep, req, -ECONNABORTED);
2101 return;
2102
2103 case DD_STATUS_STS_BS:
2104 /* Interrupt only fires on EOT - This shouldn't happen! */
2105 ep->req_pending = 0;
2106 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2107 status);
2108 done(ep, req, -ECONNABORTED);
2109 return;
2110
2111 case DD_STATUS_STS_NC:
2112 case DD_STATUS_STS_DUR:
2113 /* Really just a short packet, not an underrun */
2114 /* This is a good status and what we expect */
2115 break;
2116
2117 default:
2118 /* Data overrun, system error, or unknown */
2119 ep->req_pending = 0;
2120 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2121 status);
2122 done(ep, req, -ECONNABORTED);
2123 return;
2124 }
2125
2126 /* ISO endpoints are handled differently */
2127 if (ep->eptype == EP_ISO_TYPE) {
2128 if (ep->is_in)
2129 req->req.actual = req->req.length;
2130 else
2131 req->req.actual = dd->iso_status[0] & 0xFFFF;
2132 } else
2133 req->req.actual += DD_STATUS_CURDMACNT(status);
2134
2135 /* Send a ZLP if necessary. This will be done for non-int
2136 * packets which have a size that is a divisor of MAXP */
2137 if (req->send_zlp) {
2138 /*
2139 * If at least 1 buffer is available, send the ZLP now.
2140 * Otherwise, the ZLP send needs to be deferred until a
2141 * buffer is available.
2142 */
2143 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2144 udc_clearep_getsts(udc, ep->hwep_num);
2145 uda_enable_hwepint(udc, ep->hwep_num);
2146 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2147
2148 /* Let the EP interrupt handle the ZLP */
2149 return;
2150 } else
2151 udc_send_in_zlp(udc, ep);
2152 }
2153
2154 /* Transfer request is complete */
2155 done(ep, req, 0);
2156
2157 /* Start another request if ready */
2158 udc_clearep_getsts(udc, ep->hwep_num);
2159 if (!list_empty((&ep->queue))) {
2160 if (ep->is_in)
2161 udc_ep_in_req_dma(udc, ep);
2162 else
2163 udc_ep_out_req_dma(udc, ep);
2164 } else
2165 ep->req_pending = 0;
2166
2167}
2168
2169/*
2170 *
2171 * Endpoint 0 functions
2172 *
2173 */
2174static void udc_handle_dev(struct lpc32xx_udc *udc)
2175{
2176 u32 tmp;
2177
2178 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2179 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2180
2181 if (tmp & DEV_RST)
2182 uda_usb_reset(udc);
2183 else if (tmp & DEV_CON_CH)
2184 uda_power_event(udc, (tmp & DEV_CON));
2185 else if (tmp & DEV_SUS_CH) {
2186 if (tmp & DEV_SUS) {
2187 if (udc->vbus == 0)
2188 stop_activity(udc);
2189 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2190 udc->driver) {
2191 /* Power down transceiver */
2192 udc->poweron = 0;
2193 schedule_work(&udc->pullup_job);
2194 uda_resm_susp_event(udc, 1);
2195 }
2196 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2197 udc->driver && udc->vbus) {
2198 uda_resm_susp_event(udc, 0);
2199 /* Power up transceiver */
2200 udc->poweron = 1;
2201 schedule_work(&udc->pullup_job);
2202 }
2203 }
2204}
2205
2206static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2207{
2208 struct lpc32xx_ep *ep;
2209 u32 ep0buff = 0, tmp;
2210
2211 switch (reqtype & USB_RECIP_MASK) {
2212 case USB_RECIP_INTERFACE:
2213 break; /* Not supported */
2214
2215 case USB_RECIP_DEVICE:
2216 ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
2217 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2218 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2219 break;
2220
2221 case USB_RECIP_ENDPOINT:
2222 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2223 ep = &udc->ep[tmp];
78ca9139 2224 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
24a28e42
RS		 2225 return -EOPNOTSUPP;
2226
2227 if (wIndex & USB_DIR_IN) {
2228 if (!ep->is_in)
2229 return -EOPNOTSUPP; /* Something's wrong */
2230 } else if (ep->is_in)
2231 return -EOPNOTSUPP; /* Not an IN endpoint */
2232
2233 /* Get status of the endpoint */
2234 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2235 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2236
2237 if (tmp & EP_SEL_ST)
2238 ep0buff = (1 << USB_ENDPOINT_HALT);
2239 else
2240 ep0buff = 0;
2241 break;
2242
2243 default:
2244 break;
2245 }
2246
2247 /* Return data */
2248 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2249
2250 return 0;
2251}
2252
2253static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2254{
2255 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2256 struct usb_ctrlrequest ctrlpkt;
2257 int i, bytes;
2258 u16 wIndex, wValue, wLength, reqtype, req, tmp;
2259
2260 /* Nuke previous transfers */
2261 nuke(ep0, -EPROTO);
2262
2263 /* Get setup packet */
2264 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2265 if (bytes != 8) {
2266 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2267 bytes);
2268 return;
2269 }
2270
2271 /* Native endianness */
2272 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2273 wValue = le16_to_cpu(ctrlpkt.wValue);
2274 wLength = le16_to_cpu(ctrlpkt.wLength);
2275 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2276
2277 /* Set direction of EP0 */
2278 if (likely(reqtype & USB_DIR_IN))
2279 ep0->is_in = 1;
2280 else
2281 ep0->is_in = 0;
2282
2283 /* Handle SETUP packet */
2284 req = le16_to_cpu(ctrlpkt.bRequest);
2285 switch (req) {
2286 case USB_REQ_CLEAR_FEATURE:
2287 case USB_REQ_SET_FEATURE:
2288 switch (reqtype) {
2289 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2290 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2291 goto stall; /* Nothing else handled */
2292
2293 /* Tell board about event */
2294 if (req == USB_REQ_CLEAR_FEATURE)
2295 udc->dev_status &=
2296 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2297 else
2298 udc->dev_status |=
2299 (1 << USB_DEVICE_REMOTE_WAKEUP);
2300 uda_remwkp_cgh(udc);
2301 goto zlp_send;
2302
2303 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2304 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2305 if ((wValue != USB_ENDPOINT_HALT) ||
2306 (tmp >= NUM_ENDPOINTS))
2307 break;
2308
2309 /* Find hardware endpoint from logical endpoint */
2310 ep = &udc->ep[tmp];
2311 tmp = ep->hwep_num;
2312 if (tmp == 0)
2313 break;
2314
2315 if (req == USB_REQ_SET_FEATURE)
2316 udc_stall_hwep(udc, tmp);
2317 else if (!ep->wedge)
2318 udc_clrstall_hwep(udc, tmp);
2319
2320 goto zlp_send;
2321
2322 default:
2323 break;
2324 }
2325
2326
2327 case USB_REQ_SET_ADDRESS:
2328 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2329 udc_set_address(udc, wValue);
2330 goto zlp_send;
2331 }
2332 break;
2333
2334 case USB_REQ_GET_STATUS:
2335 udc_get_status(udc, reqtype, wIndex);
2336 return;
2337
2338 default:
2339 break; /* Let GadgetFS handle the descriptor instead */
2340 }
2341
2342 if (likely(udc->driver)) {
2343 /* device-2-host (IN) or no data setup command, process
2344 * immediately */
2345 spin_unlock(&udc->lock);
2346 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2347
2348 spin_lock(&udc->lock);
2349 if (req == USB_REQ_SET_CONFIGURATION) {
2350 /* Configuration is set after endpoints are realized */
2351 if (wValue) {
2352 /* Set configuration */
2353 udc_set_device_configured(udc);
2354
2355 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2356 DAT_WR_BYTE(AP_CLK |
2357 INAK_BI | INAK_II));
2358 } else {
2359 /* Clear configuration */
2360 udc_set_device_unconfigured(udc);
2361
2362 /* Disable NAK interrupts */
2363 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2364 DAT_WR_BYTE(AP_CLK));
2365 }
2366 }
2367
2368 if (i < 0) {
2369 /* setup processing failed, force stall */
0696f929 2370 dev_dbg(udc->dev,
24a28e42
RS		 2371 "req %02x.%02x protocol STALL; stat %d\n",
2372 reqtype, req, i);
2373 udc->ep0state = WAIT_FOR_SETUP;
2374 goto stall;
2375 }
2376 }
2377
2378 if (!ep0->is_in)
2379 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2380
2381 return;
2382
2383stall:
2384 udc_stall_hwep(udc, EP_IN);
2385 return;
2386
2387zlp_send:
2388 udc_ep0_send_zlp(udc);
2389 return;
2390}
2391
2392/* IN endpoint 0 transfer */
2393static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2394{
2395 struct lpc32xx_ep *ep0 = &udc->ep[0];
2396 u32 epstatus;
2397
2398 /* Clear EP interrupt */
2399 epstatus = udc_clearep_getsts(udc, EP_IN);
2400
2401#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2402 ep0->totalints++;
2403#endif
2404
2405 /* Stalled? Clear stall and reset buffers */
2406 if (epstatus & EP_SEL_ST) {
2407 udc_clrstall_hwep(udc, EP_IN);
2408 nuke(ep0, -ECONNABORTED);
2409 udc->ep0state = WAIT_FOR_SETUP;
2410 return;
2411 }
2412
2413 /* Is a buffer available? */
2414 if (!(epstatus & EP_SEL_F)) {
2415 /* Handle based on current state */
2416 if (udc->ep0state == DATA_IN)
2417 udc_ep0_in_req(udc);
2418 else {
2419 /* Unknown state for EP0 oe end of DATA IN phase */
2420 nuke(ep0, -ECONNABORTED);
2421 udc->ep0state = WAIT_FOR_SETUP;
2422 }
2423 }
2424}
2425
2426/* OUT endpoint 0 transfer */
2427static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2428{
2429 struct lpc32xx_ep *ep0 = &udc->ep[0];
2430 u32 epstatus;
2431
2432 /* Clear EP interrupt */
2433 epstatus = udc_clearep_getsts(udc, EP_OUT);
2434
2435
2436#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2437 ep0->totalints++;
2438#endif
2439
2440 /* Stalled? */
2441 if (epstatus & EP_SEL_ST) {
2442 udc_clrstall_hwep(udc, EP_OUT);
2443 nuke(ep0, -ECONNABORTED);
2444 udc->ep0state = WAIT_FOR_SETUP;
2445 return;
2446 }
2447
2448 /* A NAK may occur if a packet couldn't be received yet */
2449 if (epstatus & EP_SEL_EPN)
2450 return;
2451 /* Setup packet incoming? */
2452 if (epstatus & EP_SEL_STP) {
2453 nuke(ep0, 0);
2454 udc->ep0state = WAIT_FOR_SETUP;
2455 }
2456
2457 /* Data available? */
2458 if (epstatus & EP_SEL_F)
2459 /* Handle based on current state */
2460 switch (udc->ep0state) {
2461 case WAIT_FOR_SETUP:
2462 udc_handle_ep0_setup(udc);
2463 break;
2464
2465 case DATA_OUT:
2466 udc_ep0_out_req(udc);
2467 break;
2468
2469 default:
2470 /* Unknown state for EP0 */
2471 nuke(ep0, -ECONNABORTED);
2472 udc->ep0state = WAIT_FOR_SETUP;
2473 }
2474}
2475
2476/* Must be called without lock */
2477static int lpc32xx_get_frame(struct usb_gadget *gadget)
2478{
2479 int frame;
2480 unsigned long flags;
2481 struct lpc32xx_udc *udc = to_udc(gadget);
2482
2483 if (!udc->clocked)
2484 return -EINVAL;
2485
2486 spin_lock_irqsave(&udc->lock, flags);
2487
2488 frame = (int) udc_get_current_frame(udc);
2489
2490 spin_unlock_irqrestore(&udc->lock, flags);
2491
2492 return frame;
2493}
2494
2495static int lpc32xx_wakeup(struct usb_gadget *gadget)
2496{
2497 return -ENOTSUPP;
2498}
2499
2500static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2501{
2502 struct lpc32xx_udc *udc = to_udc(gadget);
2503
2504 /* Always self-powered */
2505 udc->selfpowered = (is_on != 0);
2506
2507 return 0;
2508}
2509
2510/*
2511 * vbus is here! turn everything on that's ready
2512 * Must be called without lock
2513 */
2514static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2515{
2516 unsigned long flags;
2517 struct lpc32xx_udc *udc = to_udc(gadget);
2518
2519 spin_lock_irqsave(&udc->lock, flags);
2520
2521 /* Doesn't need lock */
2522 if (udc->driver) {
2523 udc_clk_set(udc, 1);
2524 udc_enable(udc);
2525 pullup(udc, is_active);
2526 } else {
2527 stop_activity(udc);
2528 pullup(udc, 0);
2529
2530 spin_unlock_irqrestore(&udc->lock, flags);
2531 /*
2532 * Wait for all the endpoints to disable,
2533 * before disabling clocks. Don't wait if
2534 * endpoints are not enabled.
2535 */
2536 if (atomic_read(&udc->enabled_ep_cnt))
2537 wait_event_interruptible(udc->ep_disable_wait_queue,
2538 (atomic_read(&udc->enabled_ep_cnt) == 0));
2539
2540 spin_lock_irqsave(&udc->lock, flags);
2541
2542 udc_clk_set(udc, 0);
2543 }
2544
2545 spin_unlock_irqrestore(&udc->lock, flags);
2546
2547 return 0;
2548}
2549
2550/* Can be called with or without lock */
2551static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2552{
2553 struct lpc32xx_udc *udc = to_udc(gadget);
2554
2555 /* Doesn't need lock */
2556 pullup(udc, is_on);
2557
2558 return 0;
2559}
2560
252d8cec
RS		 2561static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2562static int lpc32xx_stop(struct usb_gadget *, struct usb_gadget_driver *);
24a28e42
RS		 2563
2564static const struct usb_gadget_ops lpc32xx_udc_ops = {
2565 .get_frame = lpc32xx_get_frame,
2566 .wakeup = lpc32xx_wakeup,
2567 .set_selfpowered = lpc32xx_set_selfpowered,
2568 .vbus_session = lpc32xx_vbus_session,
2569 .pullup = lpc32xx_pullup,
252d8cec
RS		 2570 .udc_start = lpc32xx_start,
2571 .udc_stop = lpc32xx_stop,
24a28e42
RS		 2572};
2573
2574static void nop_release(struct device *dev)
2575{
2576 /* nothing to free */
2577}
2578
c4846a18 2579static const struct lpc32xx_udc controller_template = {
24a28e42
RS		 2580 .gadget = {
2581 .ops = &lpc32xx_udc_ops,
24a28e42
RS		 2582 .name = driver_name,
2583 .dev = {
2584 .init_name = "gadget",
2585 .release = nop_release,
2586 }
2587 },
2588 .ep[0] = {
2589 .ep = {
2590 .name = "ep0",
2591 .ops = &lpc32xx_ep_ops,
2592 },
24a28e42
RS		 2593 .maxpacket = 64,
2594 .hwep_num_base = 0,
2595 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2596 .lep = 0,
2597 .eptype = EP_CTL_TYPE,
2598 },
2599 .ep[1] = {
2600 .ep = {
2601 .name = "ep1-int",
2602 .ops = &lpc32xx_ep_ops,
2603 },
24a28e42
RS		 2604 .maxpacket = 64,
2605 .hwep_num_base = 2,
2606 .hwep_num = 0, /* 2 or 3, will be set later */
2607 .lep = 1,
2608 .eptype = EP_INT_TYPE,
2609 },
2610 .ep[2] = {
2611 .ep = {
2612 .name = "ep2-bulk",
2613 .ops = &lpc32xx_ep_ops,
2614 },
24a28e42
RS		 2615 .maxpacket = 64,
2616 .hwep_num_base = 4,
2617 .hwep_num = 0, /* 4 or 5, will be set later */
2618 .lep = 2,
2619 .eptype = EP_BLK_TYPE,
2620 },
2621 .ep[3] = {
2622 .ep = {
2623 .name = "ep3-iso",
2624 .ops = &lpc32xx_ep_ops,
2625 },
24a28e42
RS		 2626 .maxpacket = 1023,
2627 .hwep_num_base = 6,
2628 .hwep_num = 0, /* 6 or 7, will be set later */
2629 .lep = 3,
2630 .eptype = EP_ISO_TYPE,
2631 },
2632 .ep[4] = {
2633 .ep = {
2634 .name = "ep4-int",
2635 .ops = &lpc32xx_ep_ops,
2636 },
24a28e42
RS		 2637 .maxpacket = 64,
2638 .hwep_num_base = 8,
2639 .hwep_num = 0, /* 8 or 9, will be set later */
2640 .lep = 4,
2641 .eptype = EP_INT_TYPE,
2642 },
2643 .ep[5] = {
2644 .ep = {
2645 .name = "ep5-bulk",
2646 .ops = &lpc32xx_ep_ops,
2647 },
24a28e42
RS		 2648 .maxpacket = 64,
2649 .hwep_num_base = 10,
2650 .hwep_num = 0, /* 10 or 11, will be set later */
2651 .lep = 5,
2652 .eptype = EP_BLK_TYPE,
2653 },
2654 .ep[6] = {
2655 .ep = {
2656 .name = "ep6-iso",
2657 .ops = &lpc32xx_ep_ops,
2658 },
24a28e42
RS		 2659 .maxpacket = 1023,
2660 .hwep_num_base = 12,
2661 .hwep_num = 0, /* 12 or 13, will be set later */
2662 .lep = 6,
2663 .eptype = EP_ISO_TYPE,
2664 },
2665 .ep[7] = {
2666 .ep = {
2667 .name = "ep7-int",
2668 .ops = &lpc32xx_ep_ops,
2669 },
24a28e42
RS		 2670 .maxpacket = 64,
2671 .hwep_num_base = 14,
2672 .hwep_num = 0,
2673 .lep = 7,
2674 .eptype = EP_INT_TYPE,
2675 },
2676 .ep[8] = {
2677 .ep = {
2678 .name = "ep8-bulk",
2679 .ops = &lpc32xx_ep_ops,
2680 },
24a28e42
RS		 2681 .maxpacket = 64,
2682 .hwep_num_base = 16,
2683 .hwep_num = 0,
2684 .lep = 8,
2685 .eptype = EP_BLK_TYPE,
2686 },
2687 .ep[9] = {
2688 .ep = {
2689 .name = "ep9-iso",
2690 .ops = &lpc32xx_ep_ops,
2691 },
24a28e42
RS		 2692 .maxpacket = 1023,
2693 .hwep_num_base = 18,
2694 .hwep_num = 0,
2695 .lep = 9,
2696 .eptype = EP_ISO_TYPE,
2697 },
2698 .ep[10] = {
2699 .ep = {
2700 .name = "ep10-int",
2701 .ops = &lpc32xx_ep_ops,
2702 },
24a28e42
RS		 2703 .maxpacket = 64,
2704 .hwep_num_base = 20,
2705 .hwep_num = 0,
2706 .lep = 10,
2707 .eptype = EP_INT_TYPE,
2708 },
2709 .ep[11] = {
2710 .ep = {
2711 .name = "ep11-bulk",
2712 .ops = &lpc32xx_ep_ops,
2713 },
24a28e42
RS		 2714 .maxpacket = 64,
2715 .hwep_num_base = 22,
2716 .hwep_num = 0,
2717 .lep = 11,
2718 .eptype = EP_BLK_TYPE,
2719 },
2720 .ep[12] = {
2721 .ep = {
2722 .name = "ep12-iso",
2723 .ops = &lpc32xx_ep_ops,
2724 },
24a28e42
RS		 2725 .maxpacket = 1023,
2726 .hwep_num_base = 24,
2727 .hwep_num = 0,
2728 .lep = 12,
2729 .eptype = EP_ISO_TYPE,
2730 },
2731 .ep[13] = {
2732 .ep = {
2733 .name = "ep13-int",
2734 .ops = &lpc32xx_ep_ops,
2735 },
24a28e42
RS		 2736 .maxpacket = 64,
2737 .hwep_num_base = 26,
2738 .hwep_num = 0,
2739 .lep = 13,
2740 .eptype = EP_INT_TYPE,
2741 },
2742 .ep[14] = {
2743 .ep = {
2744 .name = "ep14-bulk",
2745 .ops = &lpc32xx_ep_ops,
2746 },
24a28e42
RS		 2747 .maxpacket = 64,
2748 .hwep_num_base = 28,
2749 .hwep_num = 0,
2750 .lep = 14,
2751 .eptype = EP_BLK_TYPE,
2752 },
2753 .ep[15] = {
2754 .ep = {
2755 .name = "ep15-bulk",
2756 .ops = &lpc32xx_ep_ops,
2757 },
24a28e42
RS		 2758 .maxpacket = 1023,
2759 .hwep_num_base = 30,
2760 .hwep_num = 0,
2761 .lep = 15,
2762 .eptype = EP_BLK_TYPE,
2763 },
2764};
2765
2766/* ISO and status interrupts */
2767static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2768{
2769 u32 tmp, devstat;
2770 struct lpc32xx_udc *udc = _udc;
2771
2772 spin_lock(&udc->lock);
2773
2774 /* Read the device status register */
2775 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2776
2777 devstat &= ~USBD_EP_FAST;
2778 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2779 devstat = devstat & udc->enabled_devints;
2780
2781 /* Device specific handling needed? */
2782 if (devstat & USBD_DEV_STAT)
2783 udc_handle_dev(udc);
2784
2785 /* Start of frame? (devstat & FRAME_INT):
2786 * The frame interrupt isn't really needed for ISO support,
2787 * as the driver will queue the necessary packets */
2788
2789 /* Error? */
2790 if (devstat & ERR_INT) {
2791 /* All types of errors, from cable removal during transfer to
2792 * misc protocol and bit errors. These are mostly for just info,
2793 * as the USB hardware will work around these. If these errors
2794 * happen alot, something is wrong. */
2795 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2796 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2797 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2798 }
2799
2800 spin_unlock(&udc->lock);
2801
2802 return IRQ_HANDLED;
2803}
2804
2805/* EP interrupts */
2806static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2807{
2808 u32 tmp;
2809 struct lpc32xx_udc *udc = _udc;
2810
2811 spin_lock(&udc->lock);
2812
2813 /* Read the device status register */
2814 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2815
2816 /* Endpoints */
2817 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2818
2819 /* Special handling for EP0 */
2820 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2821 /* Handle EP0 IN */
2822 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2823 udc_handle_ep0_in(udc);
2824
2825 /* Handle EP0 OUT */
2826 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2827 udc_handle_ep0_out(udc);
2828 }
2829
2830 /* All other EPs */
2831 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2832 int i;
2833
2834 /* Handle other EP interrupts */
2835 for (i = 1; i < NUM_ENDPOINTS; i++) {
2836 if (tmp & (1 << udc->ep[i].hwep_num))
2837 udc_handle_eps(udc, &udc->ep[i]);
2838 }
2839 }
2840
2841 spin_unlock(&udc->lock);
2842
2843 return IRQ_HANDLED;
2844}
2845
2846static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2847{
2848 struct lpc32xx_udc *udc = _udc;
2849
2850 int i;
2851 u32 tmp;
2852
2853 spin_lock(&udc->lock);
2854
2855 /* Handle EP DMA EOT interrupts */
2856 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2857 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2858 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2859 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2860 for (i = 1; i < NUM_ENDPOINTS; i++) {
2861 if (tmp & (1 << udc->ep[i].hwep_num))
2862 udc_handle_dma_ep(udc, &udc->ep[i]);
2863 }
2864
2865 spin_unlock(&udc->lock);
2866
2867 return IRQ_HANDLED;
2868}
2869
2870/*
2871 *
2872 * VBUS detection, pullup handler, and Gadget cable state notification
2873 *
2874 */
2875static void vbus_work(struct work_struct *work)
2876{
2877 u8 value;
2878 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
2879 vbus_job);
2880
2881 if (udc->enabled != 0) {
2882 /* Discharge VBUS real quick */
2883 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2884 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2885
2886 /* Give VBUS some time (100mS) to discharge */
2887 msleep(100);
2888
2889 /* Disable VBUS discharge resistor */
2890 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2891 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2892 OTG1_VBUS_DISCHRG);
2893
2894 /* Clear interrupt */
2895 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2896 ISP1301_I2C_INTERRUPT_LATCH |
2897 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2898
2899 /* Get the VBUS status from the transceiver */
2900 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
69da85ed 2901 ISP1301_I2C_INTERRUPT_SOURCE);
24a28e42
RS		 2902
2903 /* VBUS on or off? */
69da85ed 2904 if (value & INT_SESS_VLD)
24a28e42
RS		 2905 udc->vbus = 1;
2906 else
2907 udc->vbus = 0;
2908
2909 /* VBUS changed? */
2910 if (udc->last_vbus != udc->vbus) {
2911 udc->last_vbus = udc->vbus;
2912 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2913 }
2914 }
2915
2916 /* Re-enable after completion */
2917 enable_irq(udc->udp_irq[IRQ_USB_ATX]);
2918}
2919
2920static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2921{
2922 struct lpc32xx_udc *udc = _udc;
2923
2924 /* Defer handling of VBUS IRQ to work queue */
2925 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
2926 schedule_work(&udc->vbus_job);
2927
2928 return IRQ_HANDLED;
2929}
2930
252d8cec
RS		 2931static int lpc32xx_start(struct usb_gadget *gadget,
2932 struct usb_gadget_driver *driver)
24a28e42 2933{
252d8cec
RS		 2934 struct lpc32xx_udc *udc = to_udc(gadget);
2935 int i;
24a28e42 2936
252d8cec 2937 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
24a28e42
RS		 2938 dev_err(udc->dev, "bad parameter.\n");
2939 return -EINVAL;
2940 }
2941
2942 if (udc->driver) {
2943 dev_err(udc->dev, "UDC already has a gadget driver\n");
2944 return -EBUSY;
2945 }
2946
2947 udc->driver = driver;
eebc0d36 2948 udc->gadget.dev.of_node = udc->dev->of_node;
24a28e42
RS		 2949 udc->enabled = 1;
2950 udc->selfpowered = 1;
2951 udc->vbus = 0;
2952
24a28e42
RS		 2953 /* Force VBUS process once to check for cable insertion */
2954 udc->last_vbus = udc->vbus = 0;
2955 schedule_work(&udc->vbus_job);
2956
2957 /* Do not re-enable ATX IRQ (3) */
2958 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
2959 enable_irq(udc->udp_irq[i]);
2960
2961 return 0;
2962}
2963
252d8cec
RS		 2964static int lpc32xx_stop(struct usb_gadget *gadget,
2965 struct usb_gadget_driver *driver)
24a28e42
RS		 2966{
2967 int i;
252d8cec 2968 struct lpc32xx_udc *udc = to_udc(gadget);
24a28e42 2969
252d8cec 2970 if (!driver || driver != udc->driver)
24a28e42
RS		 2971 return -EINVAL;
2972
24a28e42
RS		 2973 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
2974 disable_irq(udc->udp_irq[i]);
2975
2976 if (udc->clocked) {
24a28e42
RS		 2977 spin_lock(&udc->lock);
2978 stop_activity(udc);
2979 spin_unlock(&udc->lock);
2980
2981 /*
2982 * Wait for all the endpoints to disable,
2983 * before disabling clocks. Don't wait if
2984 * endpoints are not enabled.
2985 */
2986 if (atomic_read(&udc->enabled_ep_cnt))
2987 wait_event_interruptible(udc->ep_disable_wait_queue,
2988 (atomic_read(&udc->enabled_ep_cnt) == 0));
2989
2990 spin_lock(&udc->lock);
2991 udc_clk_set(udc, 0);
2992 spin_unlock(&udc->lock);
2993 }
2994
2995 udc->enabled = 0;
24a28e42
RS		 2996 udc->driver = NULL;
2997
24a28e42
RS		 2998 return 0;
2999}
3000
3001static void lpc32xx_udc_shutdown(struct platform_device *dev)
3002{
3003 /* Force disconnect on reboot */
252d8cec 3004 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
24a28e42
RS		 3005
3006 pullup(udc, 0);
3007}
3008
3009/*
3010 * Callbacks to be overridden by options passed via OF (TODO)
3011 */
3012
3013static void lpc32xx_usbd_conn_chg(int conn)
3014{
3015 /* Do nothing, it might be nice to enable an LED
3016 * based on conn state being !0 */
3017}
3018
3019static void lpc32xx_usbd_susp_chg(int susp)
3020{
3021 /* Device suspend if susp != 0 */
3022}
3023
3024static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
3025{
3026 /* Enable or disable USB remote wakeup */
3027}
3028
3029struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
3030 .vbus_drv_pol = 0,
3031 .conn_chgb = &lpc32xx_usbd_conn_chg,
3032 .susp_chgb = &lpc32xx_usbd_susp_chg,
3033 .rmwk_chgb = &lpc32xx_rmwkup_chg,
3034};
3035
3036
3037static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3038
3039static int __init lpc32xx_udc_probe(struct platform_device *pdev)
3040{
3041 struct device *dev = &pdev->dev;
c4846a18 3042 struct lpc32xx_udc *udc;
24a28e42
RS		 3043 int retval, i;
3044 struct resource *res;
3045 dma_addr_t dma_handle;
3046 struct device_node *isp1301_node;
3047
c4846a18
RS		 3048 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
3049 if (!udc)
3050 return -ENOMEM;
3051
3052 memcpy(udc, &controller_template, sizeof(*udc));
3053 for (i = 0; i <= 15; i++)
3054 udc->ep[i].udc = udc;
3055 udc->gadget.ep0 = &udc->ep[0].ep;
3056
24a28e42
RS		 3057 /* init software state */
3058 udc->gadget.dev.parent = dev;
3059 udc->pdev = pdev;
3060 udc->dev = &pdev->dev;
3061 udc->enabled = 0;
3062
3063 if (pdev->dev.of_node) {
3064 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3065 "transceiver", 0);
3066 } else {
3067 isp1301_node = NULL;
3068 }
3069
3070 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
c4846a18
RS		 3071 if (!udc->isp1301_i2c_client) {
3072 retval = -EPROBE_DEFER;
3073 goto phy_fail;
3074 }
24a28e42
RS		 3075
3076 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3077 udc->isp1301_i2c_client->addr);
3078
3079 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
22d9d8e8
RK		 3080 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3081 if (retval)
3082 goto resource_fail;
24a28e42
RS		 3083
3084 udc->board = &lpc32xx_usbddata;
3085
3086 /*
3087 * Resources are mapped as follows:
3088 * IORESOURCE_MEM, base address and size of USB space
3089 * IORESOURCE_IRQ, USB device low priority interrupt number
3090 * IORESOURCE_IRQ, USB device high priority interrupt number
3091 * IORESOURCE_IRQ, USB device interrupt number
3092 * IORESOURCE_IRQ, USB transceiver interrupt number
3093 */
3094 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c4846a18
RS		 3095 if (!res) {
3096 retval = -ENXIO;
3097 goto resource_fail;
3098 }
24a28e42
RS		 3099
3100 spin_lock_init(&udc->lock);
3101
3102 /* Get IRQs */
3103 for (i = 0; i < 4; i++) {
3104 udc->udp_irq[i] = platform_get_irq(pdev, i);
3105 if (udc->udp_irq[i] < 0) {
3106 dev_err(udc->dev,
3107 "irq resource %d not available!\n", i);
c4846a18
RS		 3108 retval = udc->udp_irq[i];
3109 goto irq_fail;
24a28e42
RS		 3110 }
3111 }
3112
3113 udc->io_p_start = res->start;
3114 udc->io_p_size = resource_size(res);
3115 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
3116 dev_err(udc->dev, "someone's using UDC memory\n");
c4846a18
RS		 3117 retval = -EBUSY;
3118 goto request_mem_region_fail;
24a28e42
RS		 3119 }
3120
3121 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
3122 if (!udc->udp_baseaddr) {
3123 retval = -ENOMEM;
3124 dev_err(udc->dev, "IO map failure\n");
3125 goto io_map_fail;
3126 }
3127
3128 /* Enable AHB slave USB clock, needed for further USB clock control */
3129 writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
3130
3131 /* Get required clocks */
3132 udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
3133 if (IS_ERR(udc->usb_pll_clk)) {
3134 dev_err(udc->dev, "failed to acquire USB PLL\n");
3135 retval = PTR_ERR(udc->usb_pll_clk);
3136 goto pll_get_fail;
3137 }
3138 udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
3139 if (IS_ERR(udc->usb_slv_clk)) {
3140 dev_err(udc->dev, "failed to acquire USB device clock\n");
3141 retval = PTR_ERR(udc->usb_slv_clk);
3142 goto usb_clk_get_fail;
3143 }
50856699
APS		 3144 udc->usb_otg_clk = clk_get(&pdev->dev, "ck_usb_otg");
3145 if (IS_ERR(udc->usb_otg_clk)) {
3146 dev_err(udc->dev, "failed to acquire USB otg clock\n");
44fd6c02 3147 retval = PTR_ERR(udc->usb_otg_clk);
50856699
APS		 3148 goto usb_otg_clk_get_fail;
3149 }
24a28e42
RS		 3150
3151 /* Setup PLL clock to 48MHz */
3152 retval = clk_enable(udc->usb_pll_clk);
3153 if (retval < 0) {
3154 dev_err(udc->dev, "failed to start USB PLL\n");
3155 goto pll_enable_fail;
3156 }
3157
3158 retval = clk_set_rate(udc->usb_pll_clk, 48000);
3159 if (retval < 0) {
3160 dev_err(udc->dev, "failed to set USB clock rate\n");
3161 goto pll_set_fail;
3162 }
3163
3164 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
3165
3166 /* Enable USB device clock */
3167 retval = clk_enable(udc->usb_slv_clk);
3168 if (retval < 0) {
3169 dev_err(udc->dev, "failed to start USB device clock\n");
3170 goto usb_clk_enable_fail;
3171 }
3172
50856699
APS		 3173 /* Enable USB OTG clock */
3174 retval = clk_enable(udc->usb_otg_clk);
3175 if (retval < 0) {
3176 dev_err(udc->dev, "failed to start USB otg clock\n");
3177 goto usb_otg_clk_enable_fail;
3178 }
24a28e42
RS		 3179
3180 /* Setup deferred workqueue data */
3181 udc->poweron = udc->pullup = 0;
3182 INIT_WORK(&udc->pullup_job, pullup_work);
3183 INIT_WORK(&udc->vbus_job, vbus_work);
3184#ifdef CONFIG_PM
3185 INIT_WORK(&udc->power_job, power_work);
3186#endif
3187
3188 /* All clocks are now on */
3189 udc->clocked = 1;
3190
3191 isp1301_udc_configure(udc);
3192 /* Allocate memory for the UDCA */
3193 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3194 &dma_handle,
3195 (GFP_KERNEL | GFP_DMA));
3196 if (!udc->udca_v_base) {
3197 dev_err(udc->dev, "error getting UDCA region\n");
3198 retval = -ENOMEM;
3199 goto i2c_fail;
3200 }
3201 udc->udca_p_base = dma_handle;
3202 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3203 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3204
3205 /* Setup the DD DMA memory pool */
3206 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3207 sizeof(struct lpc32xx_usbd_dd_gad),
3208 sizeof(u32), 0);
3209 if (!udc->dd_cache) {
3210 dev_err(udc->dev, "error getting DD DMA region\n");
3211 retval = -ENOMEM;
3212 goto dma_alloc_fail;
3213 }
3214
3215 /* Clear USB peripheral and initialize gadget endpoints */
3216 udc_disable(udc);
3217 udc_reinit(udc);
3218
24a28e42
RS		 3219 /* Request IRQs - low and high priority USB device IRQs are routed to
3220 * the same handler, while the DMA interrupt is routed elsewhere */
3221 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
3222 0, "udc_lp", udc);
3223 if (retval < 0) {
3224 dev_err(udc->dev, "LP request irq %d failed\n",
3225 udc->udp_irq[IRQ_USB_LP]);
3226 goto irq_lp_fail;
3227 }
3228 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
3229 0, "udc_hp", udc);
3230 if (retval < 0) {
3231 dev_err(udc->dev, "HP request irq %d failed\n",
3232 udc->udp_irq[IRQ_USB_HP]);
3233 goto irq_hp_fail;
3234 }
3235
3236 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
3237 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3238 if (retval < 0) {
3239 dev_err(udc->dev, "DEV request irq %d failed\n",
3240 udc->udp_irq[IRQ_USB_DEVDMA]);
3241 goto irq_dev_fail;
3242 }
3243
3244 /* The transceiver interrupt is used for VBUS detection and will
3245 kick off the VBUS handler function */
3246 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
3247 0, "udc_otg", udc);
3248 if (retval < 0) {
3249 dev_err(udc->dev, "VBUS request irq %d failed\n",
3250 udc->udp_irq[IRQ_USB_ATX]);
3251 goto irq_xcvr_fail;
3252 }
3253
3254 /* Initialize wait queue */
3255 init_waitqueue_head(&udc->ep_disable_wait_queue);
3256 atomic_set(&udc->enabled_ep_cnt, 0);
3257
3258 /* Keep all IRQs disabled until GadgetFS starts up */
3259 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3260 disable_irq(udc->udp_irq[i]);
3261
3262 retval = usb_add_gadget_udc(dev, &udc->gadget);
3263 if (retval < 0)
3264 goto add_gadget_fail;
3265
3266 dev_set_drvdata(dev, udc);
3267 device_init_wakeup(dev, 1);
3268 create_debug_file(udc);
3269
3270 /* Disable clocks for now */
3271 udc_clk_set(udc, 0);
3272
3273 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3274 return 0;
3275
3276add_gadget_fail:
3277 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3278irq_xcvr_fail:
3279 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3280irq_dev_fail:
3281 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3282irq_hp_fail:
3283 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3284irq_lp_fail:
24a28e42
RS		 3285 dma_pool_destroy(udc->dd_cache);
3286dma_alloc_fail:
3287 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3288 udc->udca_v_base, udc->udca_p_base);
3289i2c_fail:
50856699
APS		 3290 clk_disable(udc->usb_otg_clk);
3291usb_otg_clk_enable_fail:
24a28e42
RS		 3292 clk_disable(udc->usb_slv_clk);
3293usb_clk_enable_fail:
3294pll_set_fail:
3295 clk_disable(udc->usb_pll_clk);
3296pll_enable_fail:
50856699 3297 clk_put(udc->usb_otg_clk);
ade79d13
FB		 3298usb_otg_clk_get_fail:
3299 clk_put(udc->usb_slv_clk);
24a28e42
RS		 3300usb_clk_get_fail:
3301 clk_put(udc->usb_pll_clk);
3302pll_get_fail:
3303 iounmap(udc->udp_baseaddr);
3304io_map_fail:
3305 release_mem_region(udc->io_p_start, udc->io_p_size);
3306 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
c4846a18
RS		 3307request_mem_region_fail:
3308irq_fail:
3309resource_fail:
3310phy_fail:
3311 kfree(udc);
24a28e42
RS		 3312 return retval;
3313}
3314
fb4e98ab 3315static int lpc32xx_udc_remove(struct platform_device *pdev)
24a28e42
RS		 3316{
3317 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3318
3319 usb_del_gadget_udc(&udc->gadget);
3320 if (udc->driver)
3321 return -EBUSY;
3322
3323 udc_clk_set(udc, 1);
3324 udc_disable(udc);
3325 pullup(udc, 0);
3326
3327 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3328
3329 device_init_wakeup(&pdev->dev, 0);
3330 remove_debug_file(udc);
3331
3332 dma_pool_destroy(udc->dd_cache);
3333 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3334 udc->udca_v_base, udc->udca_p_base);
3335 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3336 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3337 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3338
50856699
APS		 3339 clk_disable(udc->usb_otg_clk);
3340 clk_put(udc->usb_otg_clk);
24a28e42
RS		 3341 clk_disable(udc->usb_slv_clk);
3342 clk_put(udc->usb_slv_clk);
3343 clk_disable(udc->usb_pll_clk);
3344 clk_put(udc->usb_pll_clk);
3345 iounmap(udc->udp_baseaddr);
3346 release_mem_region(udc->io_p_start, udc->io_p_size);
c4846a18 3347 kfree(udc);
24a28e42
RS		 3348
3349 return 0;
3350}
3351
3352#ifdef CONFIG_PM
3353static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3354{
24a28e42
RS		 3355 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3356
3357 if (udc->clocked) {
3358 /* Power down ISP */
3359 udc->poweron = 0;
3360 isp1301_set_powerstate(udc, 0);
3361
3362 /* Disable clocking */
3363 udc_clk_set(udc, 0);
3364
3365 /* Keep clock flag on, so we know to re-enable clocks
3366 on resume */
3367 udc->clocked = 1;
3368
24a28e42
RS		 3369 /* Kill global USB clock */
3370 clk_disable(udc->usb_slv_clk);
3371 }
3372
3373 return 0;
3374}
3375
3376static int lpc32xx_udc_resume(struct platform_device *pdev)
3377{
3378 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3379
3380 if (udc->clocked) {
3381 /* Enable global USB clock */
3382 clk_enable(udc->usb_slv_clk);
3383
3384 /* Enable clocking */
3385 udc_clk_set(udc, 1);
3386
3387 /* ISP back to normal power mode */
3388 udc->poweron = 1;
3389 isp1301_set_powerstate(udc, 1);
3390 }
3391
3392 return 0;
3393}
3394#else
3395#define lpc32xx_udc_suspend NULL
3396#define lpc32xx_udc_resume NULL
3397#endif
3398
3399#ifdef CONFIG_OF
3400static struct of_device_id lpc32xx_udc_of_match[] = {
3401 { .compatible = "nxp,lpc3220-udc", },
3402 { },
3403};
3404MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3405#endif
3406
3407static struct platform_driver lpc32xx_udc_driver = {
7690417d 3408 .remove = lpc32xx_udc_remove,
24a28e42
RS		 3409 .shutdown = lpc32xx_udc_shutdown,
3410 .suspend = lpc32xx_udc_suspend,
3411 .resume = lpc32xx_udc_resume,
3412 .driver = {
3413 .name = (char *) driver_name,
3414 .owner = THIS_MODULE,
3415 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3416 },
3417};
3418
52f7a82b 3419module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
24a28e42
RS		 3420
3421MODULE_DESCRIPTION("LPC32XX udc driver");
3422MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3423MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3424MODULE_LICENSE("GPL");
3425MODULE_ALIAS("platform:lpc32xx_udc");
Linux kernel - Deliverables
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