Commit | Line | Data |
---|---|---|
4cf2503c YS |
1 | /* |
2 | * M66592 UDC (USB gadget) | |
3 | * | |
4 | * Copyright (C) 2006-2007 Renesas Solutions Corp. | |
5 | * | |
5db05c09 | 6 | * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
4cf2503c YS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
4cf2503c | 24 | #include <linux/interrupt.h> |
598f22e1 YS |
25 | #include <linux/delay.h> |
26 | #include <linux/io.h> | |
4cf2503c | 27 | #include <linux/platform_device.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
56fd1260 | 29 | #include <linux/err.h> |
4cf2503c | 30 | #include <linux/usb/ch9.h> |
9454a57a | 31 | #include <linux/usb/gadget.h> |
4cf2503c | 32 | |
4cf2503c YS |
33 | #include "m66592-udc.h" |
34 | ||
598f22e1 | 35 | MODULE_DESCRIPTION("M66592 USB gadget driver"); |
4cf2503c YS |
36 | MODULE_LICENSE("GPL"); |
37 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
f34c32f1 | 38 | MODULE_ALIAS("platform:m66592_udc"); |
4cf2503c | 39 | |
2c59b0b7 | 40 | #define DRIVER_VERSION "21 July 2009" |
4cf2503c YS |
41 | |
42 | static const char udc_name[] = "m66592_udc"; | |
43 | static const char *m66592_ep_name[] = { | |
44 | "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7" | |
45 | }; | |
46 | ||
47 | static void disable_controller(struct m66592 *m66592); | |
48 | static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req); | |
49 | static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req); | |
50 | static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req, | |
51 | gfp_t gfp_flags); | |
52 | ||
53 | static void transfer_complete(struct m66592_ep *ep, | |
598f22e1 YS |
54 | struct m66592_request *req, int status); |
55 | ||
4cf2503c YS |
56 | /*-------------------------------------------------------------------------*/ |
57 | static inline u16 get_usb_speed(struct m66592 *m66592) | |
58 | { | |
59 | return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST); | |
60 | } | |
61 | ||
62 | static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum, | |
598f22e1 | 63 | unsigned long reg) |
4cf2503c YS |
64 | { |
65 | u16 tmp; | |
66 | ||
67 | tmp = m66592_read(m66592, M66592_INTENB0); | |
68 | m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE, | |
598f22e1 | 69 | M66592_INTENB0); |
4cf2503c YS |
70 | m66592_bset(m66592, (1 << pipenum), reg); |
71 | m66592_write(m66592, tmp, M66592_INTENB0); | |
72 | } | |
73 | ||
74 | static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum, | |
598f22e1 | 75 | unsigned long reg) |
4cf2503c YS |
76 | { |
77 | u16 tmp; | |
78 | ||
79 | tmp = m66592_read(m66592, M66592_INTENB0); | |
80 | m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE, | |
598f22e1 | 81 | M66592_INTENB0); |
4cf2503c YS |
82 | m66592_bclr(m66592, (1 << pipenum), reg); |
83 | m66592_write(m66592, tmp, M66592_INTENB0); | |
84 | } | |
85 | ||
86 | static void m66592_usb_connect(struct m66592 *m66592) | |
87 | { | |
88 | m66592_bset(m66592, M66592_CTRE, M66592_INTENB0); | |
89 | m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL, | |
598f22e1 | 90 | M66592_INTENB0); |
4cf2503c YS |
91 | m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0); |
92 | ||
93 | m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG); | |
94 | } | |
95 | ||
96 | static void m66592_usb_disconnect(struct m66592 *m66592) | |
598f22e1 YS |
97 | __releases(m66592->lock) |
98 | __acquires(m66592->lock) | |
4cf2503c YS |
99 | { |
100 | m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0); | |
101 | m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL, | |
598f22e1 | 102 | M66592_INTENB0); |
4cf2503c YS |
103 | m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0); |
104 | m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG); | |
105 | ||
106 | m66592->gadget.speed = USB_SPEED_UNKNOWN; | |
107 | spin_unlock(&m66592->lock); | |
108 | m66592->driver->disconnect(&m66592->gadget); | |
109 | spin_lock(&m66592->lock); | |
110 | ||
111 | disable_controller(m66592); | |
112 | INIT_LIST_HEAD(&m66592->ep[0].queue); | |
113 | } | |
114 | ||
115 | static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum) | |
116 | { | |
117 | u16 pid = 0; | |
118 | unsigned long offset; | |
119 | ||
120 | if (pipenum == 0) | |
121 | pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID; | |
122 | else if (pipenum < M66592_MAX_NUM_PIPE) { | |
123 | offset = get_pipectr_addr(pipenum); | |
124 | pid = m66592_read(m66592, offset) & M66592_PID; | |
125 | } else | |
00274921 | 126 | pr_err("unexpect pipe num (%d)\n", pipenum); |
4cf2503c YS |
127 | |
128 | return pid; | |
129 | } | |
130 | ||
131 | static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum, | |
598f22e1 | 132 | u16 pid) |
4cf2503c YS |
133 | { |
134 | unsigned long offset; | |
135 | ||
136 | if (pipenum == 0) | |
137 | m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR); | |
138 | else if (pipenum < M66592_MAX_NUM_PIPE) { | |
139 | offset = get_pipectr_addr(pipenum); | |
140 | m66592_mdfy(m66592, pid, M66592_PID, offset); | |
141 | } else | |
00274921 | 142 | pr_err("unexpect pipe num (%d)\n", pipenum); |
4cf2503c YS |
143 | } |
144 | ||
145 | static inline void pipe_start(struct m66592 *m66592, u16 pipenum) | |
146 | { | |
147 | control_reg_set_pid(m66592, pipenum, M66592_PID_BUF); | |
148 | } | |
149 | ||
150 | static inline void pipe_stop(struct m66592 *m66592, u16 pipenum) | |
151 | { | |
152 | control_reg_set_pid(m66592, pipenum, M66592_PID_NAK); | |
153 | } | |
154 | ||
155 | static inline void pipe_stall(struct m66592 *m66592, u16 pipenum) | |
156 | { | |
157 | control_reg_set_pid(m66592, pipenum, M66592_PID_STALL); | |
158 | } | |
159 | ||
160 | static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum) | |
161 | { | |
162 | u16 ret = 0; | |
163 | unsigned long offset; | |
164 | ||
165 | if (pipenum == 0) | |
166 | ret = m66592_read(m66592, M66592_DCPCTR); | |
167 | else if (pipenum < M66592_MAX_NUM_PIPE) { | |
168 | offset = get_pipectr_addr(pipenum); | |
169 | ret = m66592_read(m66592, offset); | |
170 | } else | |
00274921 | 171 | pr_err("unexpect pipe num (%d)\n", pipenum); |
4cf2503c YS |
172 | |
173 | return ret; | |
174 | } | |
175 | ||
176 | static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum) | |
177 | { | |
178 | unsigned long offset; | |
179 | ||
180 | pipe_stop(m66592, pipenum); | |
181 | ||
182 | if (pipenum == 0) | |
183 | m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR); | |
184 | else if (pipenum < M66592_MAX_NUM_PIPE) { | |
185 | offset = get_pipectr_addr(pipenum); | |
186 | m66592_bset(m66592, M66592_SQCLR, offset); | |
187 | } else | |
00274921 | 188 | pr_err("unexpect pipe num(%d)\n", pipenum); |
4cf2503c YS |
189 | } |
190 | ||
191 | static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum) | |
192 | { | |
193 | u16 tmp; | |
194 | int size; | |
195 | ||
196 | if (pipenum == 0) { | |
197 | tmp = m66592_read(m66592, M66592_DCPCFG); | |
198 | if ((tmp & M66592_CNTMD) != 0) | |
199 | size = 256; | |
200 | else { | |
201 | tmp = m66592_read(m66592, M66592_DCPMAXP); | |
202 | size = tmp & M66592_MAXP; | |
203 | } | |
204 | } else { | |
205 | m66592_write(m66592, pipenum, M66592_PIPESEL); | |
206 | tmp = m66592_read(m66592, M66592_PIPECFG); | |
207 | if ((tmp & M66592_CNTMD) != 0) { | |
208 | tmp = m66592_read(m66592, M66592_PIPEBUF); | |
209 | size = ((tmp >> 10) + 1) * 64; | |
210 | } else { | |
211 | tmp = m66592_read(m66592, M66592_PIPEMAXP); | |
212 | size = tmp & M66592_MXPS; | |
213 | } | |
214 | } | |
215 | ||
216 | return size; | |
217 | } | |
218 | ||
219 | static inline void pipe_change(struct m66592 *m66592, u16 pipenum) | |
220 | { | |
221 | struct m66592_ep *ep = m66592->pipenum2ep[pipenum]; | |
2c59b0b7 | 222 | unsigned short mbw; |
4cf2503c YS |
223 | |
224 | if (ep->use_dma) | |
225 | return; | |
226 | ||
227 | m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel); | |
228 | ||
229 | ndelay(450); | |
230 | ||
2c59b0b7 MD |
231 | if (m66592->pdata->on_chip) |
232 | mbw = M66592_MBW_32; | |
233 | else | |
234 | mbw = M66592_MBW_16; | |
235 | ||
236 | m66592_bset(m66592, mbw, ep->fifosel); | |
4cf2503c YS |
237 | } |
238 | ||
239 | static int pipe_buffer_setting(struct m66592 *m66592, | |
598f22e1 | 240 | struct m66592_pipe_info *info) |
4cf2503c YS |
241 | { |
242 | u16 bufnum = 0, buf_bsize = 0; | |
243 | u16 pipecfg = 0; | |
244 | ||
245 | if (info->pipe == 0) | |
246 | return -EINVAL; | |
247 | ||
248 | m66592_write(m66592, info->pipe, M66592_PIPESEL); | |
249 | ||
250 | if (info->dir_in) | |
251 | pipecfg |= M66592_DIR; | |
252 | pipecfg |= info->type; | |
253 | pipecfg |= info->epnum; | |
254 | switch (info->type) { | |
255 | case M66592_INT: | |
256 | bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT); | |
257 | buf_bsize = 0; | |
258 | break; | |
259 | case M66592_BULK: | |
4048e5ca | 260 | /* isochronous pipes may be used as bulk pipes */ |
108be95f | 261 | if (info->pipe >= M66592_BASE_PIPENUM_BULK) |
4048e5ca MD |
262 | bufnum = info->pipe - M66592_BASE_PIPENUM_BULK; |
263 | else | |
264 | bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC; | |
265 | ||
266 | bufnum = M66592_BASE_BUFNUM + (bufnum * 16); | |
4cf2503c YS |
267 | buf_bsize = 7; |
268 | pipecfg |= M66592_DBLB; | |
269 | if (!info->dir_in) | |
270 | pipecfg |= M66592_SHTNAK; | |
271 | break; | |
272 | case M66592_ISO: | |
4048e5ca | 273 | bufnum = M66592_BASE_BUFNUM + |
4cf2503c | 274 | (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16; |
4cf2503c YS |
275 | buf_bsize = 7; |
276 | break; | |
277 | } | |
4048e5ca MD |
278 | |
279 | if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) { | |
280 | pr_err("m66592 pipe memory is insufficient\n"); | |
4cf2503c YS |
281 | return -ENOMEM; |
282 | } | |
283 | ||
284 | m66592_write(m66592, pipecfg, M66592_PIPECFG); | |
285 | m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF); | |
286 | m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP); | |
287 | if (info->interval) | |
288 | info->interval--; | |
289 | m66592_write(m66592, info->interval, M66592_PIPEPERI); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static void pipe_buffer_release(struct m66592 *m66592, | |
295 | struct m66592_pipe_info *info) | |
296 | { | |
297 | if (info->pipe == 0) | |
298 | return; | |
299 | ||
4cf2503c YS |
300 | if (is_bulk_pipe(info->pipe)) { |
301 | m66592->bulk--; | |
302 | } else if (is_interrupt_pipe(info->pipe)) | |
303 | m66592->interrupt--; | |
304 | else if (is_isoc_pipe(info->pipe)) { | |
305 | m66592->isochronous--; | |
306 | if (info->type == M66592_BULK) | |
307 | m66592->bulk--; | |
308 | } else | |
00274921 | 309 | pr_err("ep_release: unexpect pipenum (%d)\n", |
598f22e1 | 310 | info->pipe); |
4cf2503c YS |
311 | } |
312 | ||
313 | static void pipe_initialize(struct m66592_ep *ep) | |
314 | { | |
315 | struct m66592 *m66592 = ep->m66592; | |
2c59b0b7 | 316 | unsigned short mbw; |
4cf2503c YS |
317 | |
318 | m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel); | |
319 | ||
320 | m66592_write(m66592, M66592_ACLRM, ep->pipectr); | |
321 | m66592_write(m66592, 0, ep->pipectr); | |
322 | m66592_write(m66592, M66592_SQCLR, ep->pipectr); | |
323 | if (ep->use_dma) { | |
324 | m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel); | |
325 | ||
326 | ndelay(450); | |
327 | ||
2c59b0b7 MD |
328 | if (m66592->pdata->on_chip) |
329 | mbw = M66592_MBW_32; | |
330 | else | |
331 | mbw = M66592_MBW_16; | |
332 | ||
333 | m66592_bset(m66592, mbw, ep->fifosel); | |
4cf2503c YS |
334 | } |
335 | } | |
336 | ||
337 | static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep, | |
598f22e1 YS |
338 | const struct usb_endpoint_descriptor *desc, |
339 | u16 pipenum, int dma) | |
4cf2503c YS |
340 | { |
341 | if ((pipenum != 0) && dma) { | |
342 | if (m66592->num_dma == 0) { | |
343 | m66592->num_dma++; | |
344 | ep->use_dma = 1; | |
345 | ep->fifoaddr = M66592_D0FIFO; | |
346 | ep->fifosel = M66592_D0FIFOSEL; | |
347 | ep->fifoctr = M66592_D0FIFOCTR; | |
348 | ep->fifotrn = M66592_D0FIFOTRN; | |
2c59b0b7 | 349 | } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) { |
4cf2503c YS |
350 | m66592->num_dma++; |
351 | ep->use_dma = 1; | |
352 | ep->fifoaddr = M66592_D1FIFO; | |
353 | ep->fifosel = M66592_D1FIFOSEL; | |
354 | ep->fifoctr = M66592_D1FIFOCTR; | |
355 | ep->fifotrn = M66592_D1FIFOTRN; | |
356 | } else { | |
357 | ep->use_dma = 0; | |
358 | ep->fifoaddr = M66592_CFIFO; | |
359 | ep->fifosel = M66592_CFIFOSEL; | |
360 | ep->fifoctr = M66592_CFIFOCTR; | |
361 | ep->fifotrn = 0; | |
362 | } | |
363 | } else { | |
364 | ep->use_dma = 0; | |
365 | ep->fifoaddr = M66592_CFIFO; | |
366 | ep->fifosel = M66592_CFIFOSEL; | |
367 | ep->fifoctr = M66592_CFIFOCTR; | |
368 | ep->fifotrn = 0; | |
369 | } | |
370 | ||
371 | ep->pipectr = get_pipectr_addr(pipenum); | |
372 | ep->pipenum = pipenum; | |
598f22e1 | 373 | ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); |
4cf2503c YS |
374 | m66592->pipenum2ep[pipenum] = ep; |
375 | m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep; | |
376 | INIT_LIST_HEAD(&ep->queue); | |
377 | } | |
378 | ||
379 | static void m66592_ep_release(struct m66592_ep *ep) | |
380 | { | |
381 | struct m66592 *m66592 = ep->m66592; | |
382 | u16 pipenum = ep->pipenum; | |
383 | ||
384 | if (pipenum == 0) | |
385 | return; | |
386 | ||
387 | if (ep->use_dma) | |
388 | m66592->num_dma--; | |
389 | ep->pipenum = 0; | |
390 | ep->busy = 0; | |
391 | ep->use_dma = 0; | |
392 | } | |
393 | ||
394 | static int alloc_pipe_config(struct m66592_ep *ep, | |
598f22e1 | 395 | const struct usb_endpoint_descriptor *desc) |
4cf2503c YS |
396 | { |
397 | struct m66592 *m66592 = ep->m66592; | |
398 | struct m66592_pipe_info info; | |
399 | int dma = 0; | |
400 | int *counter; | |
401 | int ret; | |
402 | ||
403 | ep->desc = desc; | |
404 | ||
405 | BUG_ON(ep->pipenum); | |
406 | ||
598f22e1 | 407 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
4cf2503c YS |
408 | case USB_ENDPOINT_XFER_BULK: |
409 | if (m66592->bulk >= M66592_MAX_NUM_BULK) { | |
410 | if (m66592->isochronous >= M66592_MAX_NUM_ISOC) { | |
00274921 | 411 | pr_err("bulk pipe is insufficient\n"); |
4cf2503c YS |
412 | return -ENODEV; |
413 | } else { | |
598f22e1 YS |
414 | info.pipe = M66592_BASE_PIPENUM_ISOC |
415 | + m66592->isochronous; | |
4cf2503c YS |
416 | counter = &m66592->isochronous; |
417 | } | |
418 | } else { | |
419 | info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk; | |
420 | counter = &m66592->bulk; | |
421 | } | |
422 | info.type = M66592_BULK; | |
423 | dma = 1; | |
424 | break; | |
425 | case USB_ENDPOINT_XFER_INT: | |
426 | if (m66592->interrupt >= M66592_MAX_NUM_INT) { | |
00274921 | 427 | pr_err("interrupt pipe is insufficient\n"); |
4cf2503c YS |
428 | return -ENODEV; |
429 | } | |
430 | info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt; | |
431 | info.type = M66592_INT; | |
432 | counter = &m66592->interrupt; | |
433 | break; | |
434 | case USB_ENDPOINT_XFER_ISOC: | |
435 | if (m66592->isochronous >= M66592_MAX_NUM_ISOC) { | |
00274921 | 436 | pr_err("isochronous pipe is insufficient\n"); |
4cf2503c YS |
437 | return -ENODEV; |
438 | } | |
439 | info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous; | |
440 | info.type = M66592_ISO; | |
441 | counter = &m66592->isochronous; | |
442 | break; | |
443 | default: | |
00274921 | 444 | pr_err("unexpect xfer type\n"); |
4cf2503c YS |
445 | return -EINVAL; |
446 | } | |
447 | ep->type = info.type; | |
448 | ||
449 | info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; | |
598f22e1 | 450 | info.maxpacket = le16_to_cpu(desc->wMaxPacketSize); |
4cf2503c YS |
451 | info.interval = desc->bInterval; |
452 | if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) | |
453 | info.dir_in = 1; | |
454 | else | |
455 | info.dir_in = 0; | |
456 | ||
457 | ret = pipe_buffer_setting(m66592, &info); | |
458 | if (ret < 0) { | |
00274921 | 459 | pr_err("pipe_buffer_setting fail\n"); |
4cf2503c YS |
460 | return ret; |
461 | } | |
462 | ||
463 | (*counter)++; | |
464 | if ((counter == &m66592->isochronous) && info.type == M66592_BULK) | |
465 | m66592->bulk++; | |
466 | ||
467 | m66592_ep_setting(m66592, ep, desc, info.pipe, dma); | |
468 | pipe_initialize(ep); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | static int free_pipe_config(struct m66592_ep *ep) | |
474 | { | |
475 | struct m66592 *m66592 = ep->m66592; | |
476 | struct m66592_pipe_info info; | |
477 | ||
478 | info.pipe = ep->pipenum; | |
479 | info.type = ep->type; | |
480 | pipe_buffer_release(m66592, &info); | |
481 | m66592_ep_release(ep); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | /*-------------------------------------------------------------------------*/ | |
487 | static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum) | |
488 | { | |
489 | enable_irq_ready(m66592, pipenum); | |
490 | enable_irq_nrdy(m66592, pipenum); | |
491 | } | |
492 | ||
493 | static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum) | |
494 | { | |
495 | disable_irq_ready(m66592, pipenum); | |
496 | disable_irq_nrdy(m66592, pipenum); | |
497 | } | |
498 | ||
499 | /* if complete is true, gadget driver complete function is not call */ | |
500 | static void control_end(struct m66592 *m66592, unsigned ccpl) | |
501 | { | |
502 | m66592->ep[0].internal_ccpl = ccpl; | |
503 | pipe_start(m66592, 0); | |
504 | m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR); | |
505 | } | |
506 | ||
507 | static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req) | |
508 | { | |
509 | struct m66592 *m66592 = ep->m66592; | |
510 | ||
511 | pipe_change(m66592, ep->pipenum); | |
512 | m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0, | |
598f22e1 YS |
513 | (M66592_ISEL | M66592_CURPIPE), |
514 | M66592_CFIFOSEL); | |
4cf2503c YS |
515 | m66592_write(m66592, M66592_BCLR, ep->fifoctr); |
516 | if (req->req.length == 0) { | |
517 | m66592_bset(m66592, M66592_BVAL, ep->fifoctr); | |
518 | pipe_start(m66592, 0); | |
519 | transfer_complete(ep, req, 0); | |
520 | } else { | |
521 | m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS); | |
522 | irq_ep0_write(ep, req); | |
523 | } | |
524 | } | |
525 | ||
526 | static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req) | |
527 | { | |
528 | struct m66592 *m66592 = ep->m66592; | |
529 | u16 tmp; | |
530 | ||
531 | pipe_change(m66592, ep->pipenum); | |
532 | disable_irq_empty(m66592, ep->pipenum); | |
533 | pipe_start(m66592, ep->pipenum); | |
534 | ||
535 | tmp = m66592_read(m66592, ep->fifoctr); | |
536 | if (unlikely((tmp & M66592_FRDY) == 0)) | |
537 | pipe_irq_enable(m66592, ep->pipenum); | |
538 | else | |
539 | irq_packet_write(ep, req); | |
540 | } | |
541 | ||
542 | static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req) | |
543 | { | |
544 | struct m66592 *m66592 = ep->m66592; | |
545 | u16 pipenum = ep->pipenum; | |
546 | ||
547 | if (ep->pipenum == 0) { | |
548 | m66592_mdfy(m66592, M66592_PIPE0, | |
598f22e1 YS |
549 | (M66592_ISEL | M66592_CURPIPE), |
550 | M66592_CFIFOSEL); | |
4cf2503c YS |
551 | m66592_write(m66592, M66592_BCLR, ep->fifoctr); |
552 | pipe_start(m66592, pipenum); | |
553 | pipe_irq_enable(m66592, pipenum); | |
554 | } else { | |
555 | if (ep->use_dma) { | |
556 | m66592_bset(m66592, M66592_TRCLR, ep->fifosel); | |
557 | pipe_change(m66592, pipenum); | |
558 | m66592_bset(m66592, M66592_TRENB, ep->fifosel); | |
559 | m66592_write(m66592, | |
598f22e1 YS |
560 | (req->req.length + ep->ep.maxpacket - 1) |
561 | / ep->ep.maxpacket, | |
562 | ep->fifotrn); | |
4cf2503c YS |
563 | } |
564 | pipe_start(m66592, pipenum); /* trigger once */ | |
565 | pipe_irq_enable(m66592, pipenum); | |
566 | } | |
567 | } | |
568 | ||
569 | static void start_packet(struct m66592_ep *ep, struct m66592_request *req) | |
570 | { | |
571 | if (ep->desc->bEndpointAddress & USB_DIR_IN) | |
572 | start_packet_write(ep, req); | |
573 | else | |
574 | start_packet_read(ep, req); | |
575 | } | |
576 | ||
577 | static void start_ep0(struct m66592_ep *ep, struct m66592_request *req) | |
578 | { | |
579 | u16 ctsq; | |
580 | ||
581 | ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ; | |
582 | ||
583 | switch (ctsq) { | |
584 | case M66592_CS_RDDS: | |
585 | start_ep0_write(ep, req); | |
586 | break; | |
587 | case M66592_CS_WRDS: | |
588 | start_packet_read(ep, req); | |
589 | break; | |
590 | ||
591 | case M66592_CS_WRND: | |
592 | control_end(ep->m66592, 0); | |
593 | break; | |
594 | default: | |
00274921 | 595 | pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq); |
4cf2503c YS |
596 | break; |
597 | } | |
598 | } | |
599 | ||
8c73aff6 YS |
600 | static void init_controller(struct m66592 *m66592) |
601 | { | |
2c59b0b7 | 602 | unsigned int endian; |
8c73aff6 | 603 | |
2c59b0b7 MD |
604 | if (m66592->pdata->on_chip) { |
605 | if (m66592->pdata->endian) | |
606 | endian = 0; /* big endian */ | |
607 | else | |
608 | endian = M66592_LITTLE; /* little endian */ | |
8c73aff6 | 609 | |
2c59b0b7 MD |
610 | m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */ |
611 | m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG); | |
612 | m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG); | |
613 | m66592_bset(m66592, M66592_USBE, M66592_SYSCFG); | |
8c73aff6 | 614 | |
2c59b0b7 MD |
615 | /* This is a workaound for SH7722 2nd cut */ |
616 | m66592_bset(m66592, 0x8000, M66592_DVSTCTR); | |
617 | m66592_bset(m66592, 0x1000, M66592_TESTMODE); | |
618 | m66592_bclr(m66592, 0x8000, M66592_DVSTCTR); | |
4cf2503c | 619 | |
2c59b0b7 MD |
620 | m66592_bset(m66592, M66592_INTL, M66592_INTENB1); |
621 | ||
622 | m66592_write(m66592, 0, M66592_CFBCFG); | |
623 | m66592_write(m66592, 0, M66592_D0FBCFG); | |
624 | m66592_bset(m66592, endian, M66592_CFBCFG); | |
625 | m66592_bset(m66592, endian, M66592_D0FBCFG); | |
626 | } else { | |
627 | unsigned int clock, vif, irq_sense; | |
628 | ||
629 | if (m66592->pdata->endian) | |
630 | endian = M66592_BIGEND; /* big endian */ | |
631 | else | |
632 | endian = 0; /* little endian */ | |
633 | ||
634 | if (m66592->pdata->vif) | |
635 | vif = M66592_LDRV; /* 3.3v */ | |
636 | else | |
637 | vif = 0; /* 1.5v */ | |
638 | ||
639 | switch (m66592->pdata->xtal) { | |
640 | case M66592_PLATDATA_XTAL_12MHZ: | |
641 | clock = M66592_XTAL12; | |
642 | break; | |
643 | case M66592_PLATDATA_XTAL_24MHZ: | |
644 | clock = M66592_XTAL24; | |
645 | break; | |
646 | case M66592_PLATDATA_XTAL_48MHZ: | |
647 | clock = M66592_XTAL48; | |
648 | break; | |
649 | default: | |
650 | pr_warning("m66592-udc: xtal configuration error\n"); | |
651 | clock = 0; | |
652 | } | |
4cf2503c | 653 | |
2c59b0b7 MD |
654 | switch (m66592->irq_trigger) { |
655 | case IRQF_TRIGGER_LOW: | |
656 | irq_sense = M66592_INTL; | |
657 | break; | |
658 | case IRQF_TRIGGER_FALLING: | |
659 | irq_sense = 0; | |
660 | break; | |
661 | default: | |
662 | pr_warning("m66592-udc: irq trigger config error\n"); | |
663 | irq_sense = 0; | |
664 | } | |
4cf2503c | 665 | |
2c59b0b7 MD |
666 | m66592_bset(m66592, |
667 | (vif & M66592_LDRV) | (endian & M66592_BIGEND), | |
668 | M66592_PINCFG); | |
669 | m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */ | |
670 | m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, | |
671 | M66592_SYSCFG); | |
672 | m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG); | |
673 | m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG); | |
674 | m66592_bset(m66592, M66592_USBE, M66592_SYSCFG); | |
4cf2503c | 675 | |
2c59b0b7 MD |
676 | m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG); |
677 | ||
678 | msleep(3); | |
4cf2503c | 679 | |
2c59b0b7 | 680 | m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG); |
4cf2503c | 681 | |
2c59b0b7 | 682 | msleep(1); |
4cf2503c | 683 | |
2c59b0b7 MD |
684 | m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG); |
685 | ||
686 | m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1); | |
687 | m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR, | |
688 | M66592_DMA0CFG); | |
689 | } | |
4cf2503c YS |
690 | } |
691 | ||
692 | static void disable_controller(struct m66592 *m66592) | |
693 | { | |
ceaa0a6e | 694 | m66592_bclr(m66592, M66592_UTST, M66592_TESTMODE); |
2c59b0b7 MD |
695 | if (!m66592->pdata->on_chip) { |
696 | m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG); | |
697 | udelay(1); | |
698 | m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG); | |
699 | udelay(1); | |
700 | m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG); | |
701 | udelay(1); | |
702 | m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG); | |
703 | } | |
4cf2503c YS |
704 | } |
705 | ||
706 | static void m66592_start_xclock(struct m66592 *m66592) | |
707 | { | |
708 | u16 tmp; | |
709 | ||
2c59b0b7 MD |
710 | if (!m66592->pdata->on_chip) { |
711 | tmp = m66592_read(m66592, M66592_SYSCFG); | |
712 | if (!(tmp & M66592_XCKE)) | |
713 | m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG); | |
714 | } | |
4cf2503c YS |
715 | } |
716 | ||
717 | /*-------------------------------------------------------------------------*/ | |
718 | static void transfer_complete(struct m66592_ep *ep, | |
598f22e1 YS |
719 | struct m66592_request *req, int status) |
720 | __releases(m66592->lock) | |
721 | __acquires(m66592->lock) | |
4cf2503c YS |
722 | { |
723 | int restart = 0; | |
724 | ||
725 | if (unlikely(ep->pipenum == 0)) { | |
726 | if (ep->internal_ccpl) { | |
727 | ep->internal_ccpl = 0; | |
728 | return; | |
729 | } | |
730 | } | |
731 | ||
732 | list_del_init(&req->queue); | |
733 | if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN) | |
734 | req->req.status = -ESHUTDOWN; | |
735 | else | |
736 | req->req.status = status; | |
737 | ||
738 | if (!list_empty(&ep->queue)) | |
739 | restart = 1; | |
740 | ||
598f22e1 YS |
741 | spin_unlock(&ep->m66592->lock); |
742 | req->req.complete(&ep->ep, &req->req); | |
743 | spin_lock(&ep->m66592->lock); | |
4cf2503c YS |
744 | |
745 | if (restart) { | |
746 | req = list_entry(ep->queue.next, struct m66592_request, queue); | |
747 | if (ep->desc) | |
748 | start_packet(ep, req); | |
749 | } | |
750 | } | |
751 | ||
752 | static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req) | |
753 | { | |
754 | int i; | |
598f22e1 | 755 | u16 tmp; |
4cf2503c YS |
756 | unsigned bufsize; |
757 | size_t size; | |
758 | void *buf; | |
759 | u16 pipenum = ep->pipenum; | |
760 | struct m66592 *m66592 = ep->m66592; | |
761 | ||
762 | pipe_change(m66592, pipenum); | |
763 | m66592_bset(m66592, M66592_ISEL, ep->fifosel); | |
764 | ||
765 | i = 0; | |
766 | do { | |
767 | tmp = m66592_read(m66592, ep->fifoctr); | |
768 | if (i++ > 100000) { | |
00274921 | 769 | pr_err("pipe0 is busy. maybe cpu i/o bus " |
4cf2503c YS |
770 | "conflict. please power off this controller."); |
771 | return; | |
772 | } | |
773 | ndelay(1); | |
774 | } while ((tmp & M66592_FRDY) == 0); | |
775 | ||
776 | /* prepare parameters */ | |
777 | bufsize = get_buffer_size(m66592, pipenum); | |
778 | buf = req->req.buf + req->req.actual; | |
779 | size = min(bufsize, req->req.length - req->req.actual); | |
780 | ||
781 | /* write fifo */ | |
782 | if (req->req.buf) { | |
783 | if (size > 0) | |
784 | m66592_write_fifo(m66592, ep->fifoaddr, buf, size); | |
785 | if ((size == 0) || ((size % ep->ep.maxpacket) != 0)) | |
786 | m66592_bset(m66592, M66592_BVAL, ep->fifoctr); | |
787 | } | |
788 | ||
789 | /* update parameters */ | |
790 | req->req.actual += size; | |
791 | ||
792 | /* check transfer finish */ | |
598f22e1 YS |
793 | if ((!req->req.zero && (req->req.actual == req->req.length)) |
794 | || (size % ep->ep.maxpacket) | |
795 | || (size == 0)) { | |
4cf2503c YS |
796 | disable_irq_ready(m66592, pipenum); |
797 | disable_irq_empty(m66592, pipenum); | |
798 | } else { | |
799 | disable_irq_ready(m66592, pipenum); | |
800 | enable_irq_empty(m66592, pipenum); | |
801 | } | |
802 | pipe_start(m66592, pipenum); | |
803 | } | |
804 | ||
805 | static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req) | |
806 | { | |
807 | u16 tmp; | |
808 | unsigned bufsize; | |
809 | size_t size; | |
810 | void *buf; | |
811 | u16 pipenum = ep->pipenum; | |
812 | struct m66592 *m66592 = ep->m66592; | |
813 | ||
814 | pipe_change(m66592, pipenum); | |
815 | tmp = m66592_read(m66592, ep->fifoctr); | |
816 | if (unlikely((tmp & M66592_FRDY) == 0)) { | |
817 | pipe_stop(m66592, pipenum); | |
818 | pipe_irq_disable(m66592, pipenum); | |
00274921 | 819 | pr_err("write fifo not ready. pipnum=%d\n", pipenum); |
4cf2503c YS |
820 | return; |
821 | } | |
822 | ||
823 | /* prepare parameters */ | |
824 | bufsize = get_buffer_size(m66592, pipenum); | |
825 | buf = req->req.buf + req->req.actual; | |
826 | size = min(bufsize, req->req.length - req->req.actual); | |
827 | ||
828 | /* write fifo */ | |
829 | if (req->req.buf) { | |
830 | m66592_write_fifo(m66592, ep->fifoaddr, buf, size); | |
598f22e1 YS |
831 | if ((size == 0) |
832 | || ((size % ep->ep.maxpacket) != 0) | |
833 | || ((bufsize != ep->ep.maxpacket) | |
834 | && (bufsize > size))) | |
4cf2503c YS |
835 | m66592_bset(m66592, M66592_BVAL, ep->fifoctr); |
836 | } | |
837 | ||
838 | /* update parameters */ | |
839 | req->req.actual += size; | |
840 | /* check transfer finish */ | |
598f22e1 YS |
841 | if ((!req->req.zero && (req->req.actual == req->req.length)) |
842 | || (size % ep->ep.maxpacket) | |
843 | || (size == 0)) { | |
4cf2503c YS |
844 | disable_irq_ready(m66592, pipenum); |
845 | enable_irq_empty(m66592, pipenum); | |
846 | } else { | |
847 | disable_irq_empty(m66592, pipenum); | |
848 | pipe_irq_enable(m66592, pipenum); | |
849 | } | |
850 | } | |
851 | ||
852 | static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req) | |
853 | { | |
854 | u16 tmp; | |
855 | int rcv_len, bufsize, req_len; | |
856 | int size; | |
857 | void *buf; | |
858 | u16 pipenum = ep->pipenum; | |
859 | struct m66592 *m66592 = ep->m66592; | |
860 | int finish = 0; | |
861 | ||
862 | pipe_change(m66592, pipenum); | |
863 | tmp = m66592_read(m66592, ep->fifoctr); | |
864 | if (unlikely((tmp & M66592_FRDY) == 0)) { | |
865 | req->req.status = -EPIPE; | |
866 | pipe_stop(m66592, pipenum); | |
867 | pipe_irq_disable(m66592, pipenum); | |
00274921 | 868 | pr_err("read fifo not ready"); |
4cf2503c YS |
869 | return; |
870 | } | |
871 | ||
872 | /* prepare parameters */ | |
873 | rcv_len = tmp & M66592_DTLN; | |
874 | bufsize = get_buffer_size(m66592, pipenum); | |
875 | ||
876 | buf = req->req.buf + req->req.actual; | |
877 | req_len = req->req.length - req->req.actual; | |
878 | if (rcv_len < bufsize) | |
879 | size = min(rcv_len, req_len); | |
880 | else | |
881 | size = min(bufsize, req_len); | |
882 | ||
883 | /* update parameters */ | |
884 | req->req.actual += size; | |
885 | ||
886 | /* check transfer finish */ | |
598f22e1 YS |
887 | if ((!req->req.zero && (req->req.actual == req->req.length)) |
888 | || (size % ep->ep.maxpacket) | |
889 | || (size == 0)) { | |
4cf2503c YS |
890 | pipe_stop(m66592, pipenum); |
891 | pipe_irq_disable(m66592, pipenum); | |
892 | finish = 1; | |
893 | } | |
894 | ||
895 | /* read fifo */ | |
896 | if (req->req.buf) { | |
897 | if (size == 0) | |
898 | m66592_write(m66592, M66592_BCLR, ep->fifoctr); | |
899 | else | |
900 | m66592_read_fifo(m66592, ep->fifoaddr, buf, size); | |
901 | } | |
902 | ||
903 | if ((ep->pipenum != 0) && finish) | |
904 | transfer_complete(ep, req, 0); | |
905 | } | |
906 | ||
907 | static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb) | |
908 | { | |
909 | u16 check; | |
910 | u16 pipenum; | |
911 | struct m66592_ep *ep; | |
912 | struct m66592_request *req; | |
913 | ||
914 | if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) { | |
915 | m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS); | |
916 | m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE, | |
598f22e1 | 917 | M66592_CFIFOSEL); |
4cf2503c YS |
918 | |
919 | ep = &m66592->ep[0]; | |
920 | req = list_entry(ep->queue.next, struct m66592_request, queue); | |
921 | irq_packet_read(ep, req); | |
922 | } else { | |
923 | for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) { | |
924 | check = 1 << pipenum; | |
925 | if ((status & check) && (enb & check)) { | |
926 | m66592_write(m66592, ~check, M66592_BRDYSTS); | |
927 | ep = m66592->pipenum2ep[pipenum]; | |
928 | req = list_entry(ep->queue.next, | |
929 | struct m66592_request, queue); | |
930 | if (ep->desc->bEndpointAddress & USB_DIR_IN) | |
931 | irq_packet_write(ep, req); | |
932 | else | |
933 | irq_packet_read(ep, req); | |
934 | } | |
935 | } | |
936 | } | |
937 | } | |
938 | ||
939 | static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb) | |
940 | { | |
941 | u16 tmp; | |
942 | u16 check; | |
943 | u16 pipenum; | |
944 | struct m66592_ep *ep; | |
945 | struct m66592_request *req; | |
946 | ||
947 | if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) { | |
948 | m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS); | |
949 | ||
950 | ep = &m66592->ep[0]; | |
951 | req = list_entry(ep->queue.next, struct m66592_request, queue); | |
952 | irq_ep0_write(ep, req); | |
953 | } else { | |
954 | for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) { | |
955 | check = 1 << pipenum; | |
956 | if ((status & check) && (enb & check)) { | |
957 | m66592_write(m66592, ~check, M66592_BEMPSTS); | |
958 | tmp = control_reg_get(m66592, pipenum); | |
959 | if ((tmp & M66592_INBUFM) == 0) { | |
960 | disable_irq_empty(m66592, pipenum); | |
961 | pipe_irq_disable(m66592, pipenum); | |
962 | pipe_stop(m66592, pipenum); | |
963 | ep = m66592->pipenum2ep[pipenum]; | |
964 | req = list_entry(ep->queue.next, | |
965 | struct m66592_request, | |
966 | queue); | |
967 | if (!list_empty(&ep->queue)) | |
968 | transfer_complete(ep, req, 0); | |
969 | } | |
970 | } | |
971 | } | |
972 | } | |
973 | } | |
974 | ||
975 | static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) | |
598f22e1 YS |
976 | __releases(m66592->lock) |
977 | __acquires(m66592->lock) | |
4cf2503c YS |
978 | { |
979 | struct m66592_ep *ep; | |
980 | u16 pid; | |
981 | u16 status = 0; | |
598f22e1 | 982 | u16 w_index = le16_to_cpu(ctrl->wIndex); |
4cf2503c YS |
983 | |
984 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
985 | case USB_RECIP_DEVICE: | |
598f22e1 | 986 | status = 1 << USB_DEVICE_SELF_POWERED; |
4cf2503c YS |
987 | break; |
988 | case USB_RECIP_INTERFACE: | |
989 | status = 0; | |
990 | break; | |
991 | case USB_RECIP_ENDPOINT: | |
598f22e1 | 992 | ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK]; |
4cf2503c YS |
993 | pid = control_reg_get_pid(m66592, ep->pipenum); |
994 | if (pid == M66592_PID_STALL) | |
598f22e1 | 995 | status = 1 << USB_ENDPOINT_HALT; |
4cf2503c YS |
996 | else |
997 | status = 0; | |
998 | break; | |
999 | default: | |
1000 | pipe_stall(m66592, 0); | |
1001 | return; /* exit */ | |
1002 | } | |
1003 | ||
598f22e1 YS |
1004 | m66592->ep0_data = cpu_to_le16(status); |
1005 | m66592->ep0_req->buf = &m66592->ep0_data; | |
4cf2503c | 1006 | m66592->ep0_req->length = 2; |
53b67950 | 1007 | /* AV: what happens if we get called again before that gets through? */ |
598f22e1 | 1008 | spin_unlock(&m66592->lock); |
4cf2503c | 1009 | m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL); |
598f22e1 | 1010 | spin_lock(&m66592->lock); |
4cf2503c YS |
1011 | } |
1012 | ||
1013 | static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) | |
1014 | { | |
1015 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1016 | case USB_RECIP_DEVICE: | |
1017 | control_end(m66592, 1); | |
1018 | break; | |
1019 | case USB_RECIP_INTERFACE: | |
1020 | control_end(m66592, 1); | |
1021 | break; | |
1022 | case USB_RECIP_ENDPOINT: { | |
1023 | struct m66592_ep *ep; | |
1024 | struct m66592_request *req; | |
598f22e1 | 1025 | u16 w_index = le16_to_cpu(ctrl->wIndex); |
4cf2503c | 1026 | |
598f22e1 | 1027 | ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK]; |
4cf2503c YS |
1028 | pipe_stop(m66592, ep->pipenum); |
1029 | control_reg_sqclr(m66592, ep->pipenum); | |
1030 | ||
1031 | control_end(m66592, 1); | |
1032 | ||
1033 | req = list_entry(ep->queue.next, | |
1034 | struct m66592_request, queue); | |
1035 | if (ep->busy) { | |
1036 | ep->busy = 0; | |
1037 | if (list_empty(&ep->queue)) | |
1038 | break; | |
1039 | start_packet(ep, req); | |
1040 | } else if (!list_empty(&ep->queue)) | |
1041 | pipe_start(m66592, ep->pipenum); | |
1042 | } | |
1043 | break; | |
1044 | default: | |
1045 | pipe_stall(m66592, 0); | |
1046 | break; | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) | |
1051 | { | |
ceaa0a6e YS |
1052 | u16 tmp; |
1053 | int timeout = 3000; | |
4cf2503c YS |
1054 | |
1055 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1056 | case USB_RECIP_DEVICE: | |
ceaa0a6e YS |
1057 | switch (le16_to_cpu(ctrl->wValue)) { |
1058 | case USB_DEVICE_TEST_MODE: | |
1059 | control_end(m66592, 1); | |
1060 | /* Wait for the completion of status stage */ | |
1061 | do { | |
1062 | tmp = m66592_read(m66592, M66592_INTSTS0) & | |
1063 | M66592_CTSQ; | |
1064 | udelay(1); | |
1065 | } while (tmp != M66592_CS_IDST || timeout-- > 0); | |
1066 | ||
1067 | if (tmp == M66592_CS_IDST) | |
1068 | m66592_bset(m66592, | |
1069 | le16_to_cpu(ctrl->wIndex >> 8), | |
1070 | M66592_TESTMODE); | |
1071 | break; | |
1072 | default: | |
1073 | pipe_stall(m66592, 0); | |
1074 | break; | |
1075 | } | |
4cf2503c YS |
1076 | break; |
1077 | case USB_RECIP_INTERFACE: | |
1078 | control_end(m66592, 1); | |
1079 | break; | |
1080 | case USB_RECIP_ENDPOINT: { | |
1081 | struct m66592_ep *ep; | |
598f22e1 | 1082 | u16 w_index = le16_to_cpu(ctrl->wIndex); |
4cf2503c | 1083 | |
598f22e1 | 1084 | ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK]; |
4cf2503c YS |
1085 | pipe_stall(m66592, ep->pipenum); |
1086 | ||
1087 | control_end(m66592, 1); | |
1088 | } | |
1089 | break; | |
1090 | default: | |
1091 | pipe_stall(m66592, 0); | |
1092 | break; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | /* if return value is true, call class driver's setup() */ | |
1097 | static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) | |
1098 | { | |
1099 | u16 *p = (u16 *)ctrl; | |
1100 | unsigned long offset = M66592_USBREQ; | |
1101 | int i, ret = 0; | |
1102 | ||
1103 | /* read fifo */ | |
1104 | m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0); | |
1105 | ||
1106 | for (i = 0; i < 4; i++) | |
1107 | p[i] = m66592_read(m66592, offset + i*2); | |
1108 | ||
1109 | /* check request */ | |
1110 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1111 | switch (ctrl->bRequest) { | |
1112 | case USB_REQ_GET_STATUS: | |
1113 | get_status(m66592, ctrl); | |
1114 | break; | |
1115 | case USB_REQ_CLEAR_FEATURE: | |
1116 | clear_feature(m66592, ctrl); | |
1117 | break; | |
1118 | case USB_REQ_SET_FEATURE: | |
1119 | set_feature(m66592, ctrl); | |
1120 | break; | |
1121 | default: | |
1122 | ret = 1; | |
1123 | break; | |
1124 | } | |
1125 | } else | |
1126 | ret = 1; | |
1127 | return ret; | |
1128 | } | |
1129 | ||
1130 | static void m66592_update_usb_speed(struct m66592 *m66592) | |
1131 | { | |
1132 | u16 speed = get_usb_speed(m66592); | |
1133 | ||
1134 | switch (speed) { | |
1135 | case M66592_HSMODE: | |
1136 | m66592->gadget.speed = USB_SPEED_HIGH; | |
1137 | break; | |
1138 | case M66592_FSMODE: | |
1139 | m66592->gadget.speed = USB_SPEED_FULL; | |
1140 | break; | |
1141 | default: | |
1142 | m66592->gadget.speed = USB_SPEED_UNKNOWN; | |
00274921 | 1143 | pr_err("USB speed unknown\n"); |
4cf2503c YS |
1144 | } |
1145 | } | |
1146 | ||
1147 | static void irq_device_state(struct m66592 *m66592) | |
1148 | { | |
1149 | u16 dvsq; | |
1150 | ||
1151 | dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ; | |
1152 | m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0); | |
1153 | ||
1154 | if (dvsq == M66592_DS_DFLT) { /* bus reset */ | |
1155 | m66592->driver->disconnect(&m66592->gadget); | |
1156 | m66592_update_usb_speed(m66592); | |
1157 | } | |
1158 | if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG) | |
1159 | m66592_update_usb_speed(m66592); | |
598f22e1 YS |
1160 | if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS) |
1161 | && m66592->gadget.speed == USB_SPEED_UNKNOWN) | |
4cf2503c YS |
1162 | m66592_update_usb_speed(m66592); |
1163 | ||
1164 | m66592->old_dvsq = dvsq; | |
1165 | } | |
1166 | ||
1167 | static void irq_control_stage(struct m66592 *m66592) | |
598f22e1 YS |
1168 | __releases(m66592->lock) |
1169 | __acquires(m66592->lock) | |
4cf2503c YS |
1170 | { |
1171 | struct usb_ctrlrequest ctrl; | |
1172 | u16 ctsq; | |
1173 | ||
1174 | ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ; | |
1175 | m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0); | |
1176 | ||
1177 | switch (ctsq) { | |
1178 | case M66592_CS_IDST: { | |
1179 | struct m66592_ep *ep; | |
1180 | struct m66592_request *req; | |
1181 | ep = &m66592->ep[0]; | |
1182 | req = list_entry(ep->queue.next, struct m66592_request, queue); | |
1183 | transfer_complete(ep, req, 0); | |
1184 | } | |
1185 | break; | |
1186 | ||
1187 | case M66592_CS_RDDS: | |
1188 | case M66592_CS_WRDS: | |
1189 | case M66592_CS_WRND: | |
1190 | if (setup_packet(m66592, &ctrl)) { | |
598f22e1 | 1191 | spin_unlock(&m66592->lock); |
4cf2503c YS |
1192 | if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0) |
1193 | pipe_stall(m66592, 0); | |
598f22e1 | 1194 | spin_lock(&m66592->lock); |
4cf2503c YS |
1195 | } |
1196 | break; | |
1197 | case M66592_CS_RDSS: | |
1198 | case M66592_CS_WRSS: | |
1199 | control_end(m66592, 0); | |
1200 | break; | |
1201 | default: | |
00274921 | 1202 | pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq); |
4cf2503c YS |
1203 | break; |
1204 | } | |
1205 | } | |
1206 | ||
1207 | static irqreturn_t m66592_irq(int irq, void *_m66592) | |
1208 | { | |
1209 | struct m66592 *m66592 = _m66592; | |
1210 | u16 intsts0; | |
1211 | u16 intenb0; | |
1212 | u16 brdysts, nrdysts, bempsts; | |
1213 | u16 brdyenb, nrdyenb, bempenb; | |
1214 | u16 savepipe; | |
1215 | u16 mask0; | |
1216 | ||
598f22e1 YS |
1217 | spin_lock(&m66592->lock); |
1218 | ||
4cf2503c YS |
1219 | intsts0 = m66592_read(m66592, M66592_INTSTS0); |
1220 | intenb0 = m66592_read(m66592, M66592_INTENB0); | |
1221 | ||
2c59b0b7 | 1222 | if (m66592->pdata->on_chip && !intsts0 && !intenb0) { |
8c73aff6 YS |
1223 | /* |
1224 | * When USB clock stops, it cannot read register. Even if a | |
1225 | * clock stops, the interrupt occurs. So this driver turn on | |
1226 | * a clock by this timing and do re-reading of register. | |
1227 | */ | |
1228 | m66592_start_xclock(m66592); | |
1229 | intsts0 = m66592_read(m66592, M66592_INTSTS0); | |
1230 | intenb0 = m66592_read(m66592, M66592_INTENB0); | |
1231 | } | |
8c73aff6 | 1232 | |
4cf2503c YS |
1233 | savepipe = m66592_read(m66592, M66592_CFIFOSEL); |
1234 | ||
1235 | mask0 = intsts0 & intenb0; | |
1236 | if (mask0) { | |
1237 | brdysts = m66592_read(m66592, M66592_BRDYSTS); | |
1238 | nrdysts = m66592_read(m66592, M66592_NRDYSTS); | |
1239 | bempsts = m66592_read(m66592, M66592_BEMPSTS); | |
1240 | brdyenb = m66592_read(m66592, M66592_BRDYENB); | |
1241 | nrdyenb = m66592_read(m66592, M66592_NRDYENB); | |
1242 | bempenb = m66592_read(m66592, M66592_BEMPENB); | |
1243 | ||
1244 | if (mask0 & M66592_VBINT) { | |
598f22e1 YS |
1245 | m66592_write(m66592, 0xffff & ~M66592_VBINT, |
1246 | M66592_INTSTS0); | |
4cf2503c YS |
1247 | m66592_start_xclock(m66592); |
1248 | ||
1249 | /* start vbus sampling */ | |
1250 | m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0) | |
598f22e1 | 1251 | & M66592_VBSTS; |
4cf2503c YS |
1252 | m66592->scount = M66592_MAX_SAMPLING; |
1253 | ||
1254 | mod_timer(&m66592->timer, | |
598f22e1 | 1255 | jiffies + msecs_to_jiffies(50)); |
4cf2503c YS |
1256 | } |
1257 | if (intsts0 & M66592_DVSQ) | |
1258 | irq_device_state(m66592); | |
1259 | ||
598f22e1 YS |
1260 | if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE) |
1261 | && (brdysts & brdyenb)) { | |
4cf2503c YS |
1262 | irq_pipe_ready(m66592, brdysts, brdyenb); |
1263 | } | |
598f22e1 YS |
1264 | if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE) |
1265 | && (bempsts & bempenb)) { | |
4cf2503c YS |
1266 | irq_pipe_empty(m66592, bempsts, bempenb); |
1267 | } | |
1268 | ||
1269 | if (intsts0 & M66592_CTRT) | |
1270 | irq_control_stage(m66592); | |
1271 | } | |
1272 | ||
1273 | m66592_write(m66592, savepipe, M66592_CFIFOSEL); | |
1274 | ||
598f22e1 | 1275 | spin_unlock(&m66592->lock); |
4cf2503c YS |
1276 | return IRQ_HANDLED; |
1277 | } | |
1278 | ||
1279 | static void m66592_timer(unsigned long _m66592) | |
1280 | { | |
1281 | struct m66592 *m66592 = (struct m66592 *)_m66592; | |
1282 | unsigned long flags; | |
1283 | u16 tmp; | |
1284 | ||
1285 | spin_lock_irqsave(&m66592->lock, flags); | |
1286 | tmp = m66592_read(m66592, M66592_SYSCFG); | |
1287 | if (!(tmp & M66592_RCKE)) { | |
1288 | m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG); | |
1289 | udelay(10); | |
1290 | m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG); | |
1291 | } | |
1292 | if (m66592->scount > 0) { | |
1293 | tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS; | |
1294 | if (tmp == m66592->old_vbus) { | |
1295 | m66592->scount--; | |
1296 | if (m66592->scount == 0) { | |
1297 | if (tmp == M66592_VBSTS) | |
1298 | m66592_usb_connect(m66592); | |
1299 | else | |
1300 | m66592_usb_disconnect(m66592); | |
1301 | } else { | |
1302 | mod_timer(&m66592->timer, | |
598f22e1 | 1303 | jiffies + msecs_to_jiffies(50)); |
4cf2503c YS |
1304 | } |
1305 | } else { | |
1306 | m66592->scount = M66592_MAX_SAMPLING; | |
1307 | m66592->old_vbus = tmp; | |
1308 | mod_timer(&m66592->timer, | |
598f22e1 | 1309 | jiffies + msecs_to_jiffies(50)); |
4cf2503c YS |
1310 | } |
1311 | } | |
1312 | spin_unlock_irqrestore(&m66592->lock, flags); | |
1313 | } | |
1314 | ||
1315 | /*-------------------------------------------------------------------------*/ | |
1316 | static int m66592_enable(struct usb_ep *_ep, | |
1317 | const struct usb_endpoint_descriptor *desc) | |
1318 | { | |
1319 | struct m66592_ep *ep; | |
1320 | ||
1321 | ep = container_of(_ep, struct m66592_ep, ep); | |
1322 | return alloc_pipe_config(ep, desc); | |
1323 | } | |
1324 | ||
1325 | static int m66592_disable(struct usb_ep *_ep) | |
1326 | { | |
1327 | struct m66592_ep *ep; | |
1328 | struct m66592_request *req; | |
1329 | unsigned long flags; | |
1330 | ||
1331 | ep = container_of(_ep, struct m66592_ep, ep); | |
1332 | BUG_ON(!ep); | |
1333 | ||
1334 | while (!list_empty(&ep->queue)) { | |
1335 | req = list_entry(ep->queue.next, struct m66592_request, queue); | |
1336 | spin_lock_irqsave(&ep->m66592->lock, flags); | |
1337 | transfer_complete(ep, req, -ECONNRESET); | |
1338 | spin_unlock_irqrestore(&ep->m66592->lock, flags); | |
1339 | } | |
1340 | ||
1341 | pipe_irq_disable(ep->m66592, ep->pipenum); | |
1342 | return free_pipe_config(ep); | |
1343 | } | |
1344 | ||
1345 | static struct usb_request *m66592_alloc_request(struct usb_ep *_ep, | |
1346 | gfp_t gfp_flags) | |
1347 | { | |
1348 | struct m66592_request *req; | |
1349 | ||
1350 | req = kzalloc(sizeof(struct m66592_request), gfp_flags); | |
1351 | if (!req) | |
1352 | return NULL; | |
1353 | ||
1354 | INIT_LIST_HEAD(&req->queue); | |
1355 | ||
1356 | return &req->req; | |
1357 | } | |
1358 | ||
1359 | static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
1360 | { | |
1361 | struct m66592_request *req; | |
1362 | ||
1363 | req = container_of(_req, struct m66592_request, req); | |
1364 | kfree(req); | |
1365 | } | |
1366 | ||
4cf2503c YS |
1367 | static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req, |
1368 | gfp_t gfp_flags) | |
1369 | { | |
1370 | struct m66592_ep *ep; | |
1371 | struct m66592_request *req; | |
1372 | unsigned long flags; | |
1373 | int request = 0; | |
1374 | ||
1375 | ep = container_of(_ep, struct m66592_ep, ep); | |
1376 | req = container_of(_req, struct m66592_request, req); | |
1377 | ||
1378 | if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN) | |
1379 | return -ESHUTDOWN; | |
1380 | ||
1381 | spin_lock_irqsave(&ep->m66592->lock, flags); | |
1382 | ||
1383 | if (list_empty(&ep->queue)) | |
1384 | request = 1; | |
1385 | ||
1386 | list_add_tail(&req->queue, &ep->queue); | |
1387 | req->req.actual = 0; | |
1388 | req->req.status = -EINPROGRESS; | |
1389 | ||
a9475226 | 1390 | if (ep->desc == NULL) /* control */ |
4cf2503c YS |
1391 | start_ep0(ep, req); |
1392 | else { | |
1393 | if (request && !ep->busy) | |
1394 | start_packet(ep, req); | |
1395 | } | |
1396 | ||
1397 | spin_unlock_irqrestore(&ep->m66592->lock, flags); | |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
1403 | { | |
1404 | struct m66592_ep *ep; | |
1405 | struct m66592_request *req; | |
1406 | unsigned long flags; | |
1407 | ||
1408 | ep = container_of(_ep, struct m66592_ep, ep); | |
1409 | req = container_of(_req, struct m66592_request, req); | |
1410 | ||
1411 | spin_lock_irqsave(&ep->m66592->lock, flags); | |
1412 | if (!list_empty(&ep->queue)) | |
1413 | transfer_complete(ep, req, -ECONNRESET); | |
1414 | spin_unlock_irqrestore(&ep->m66592->lock, flags); | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static int m66592_set_halt(struct usb_ep *_ep, int value) | |
1420 | { | |
1421 | struct m66592_ep *ep; | |
1422 | struct m66592_request *req; | |
1423 | unsigned long flags; | |
1424 | int ret = 0; | |
1425 | ||
1426 | ep = container_of(_ep, struct m66592_ep, ep); | |
1427 | req = list_entry(ep->queue.next, struct m66592_request, queue); | |
1428 | ||
1429 | spin_lock_irqsave(&ep->m66592->lock, flags); | |
1430 | if (!list_empty(&ep->queue)) { | |
1431 | ret = -EAGAIN; | |
1432 | goto out; | |
1433 | } | |
1434 | if (value) { | |
1435 | ep->busy = 1; | |
1436 | pipe_stall(ep->m66592, ep->pipenum); | |
1437 | } else { | |
1438 | ep->busy = 0; | |
1439 | pipe_stop(ep->m66592, ep->pipenum); | |
1440 | } | |
1441 | ||
1442 | out: | |
1443 | spin_unlock_irqrestore(&ep->m66592->lock, flags); | |
1444 | return ret; | |
1445 | } | |
1446 | ||
4cf2503c YS |
1447 | static void m66592_fifo_flush(struct usb_ep *_ep) |
1448 | { | |
1449 | struct m66592_ep *ep; | |
1450 | unsigned long flags; | |
1451 | ||
1452 | ep = container_of(_ep, struct m66592_ep, ep); | |
1453 | spin_lock_irqsave(&ep->m66592->lock, flags); | |
1454 | if (list_empty(&ep->queue) && !ep->busy) { | |
1455 | pipe_stop(ep->m66592, ep->pipenum); | |
1456 | m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr); | |
1457 | } | |
1458 | spin_unlock_irqrestore(&ep->m66592->lock, flags); | |
1459 | } | |
1460 | ||
1461 | static struct usb_ep_ops m66592_ep_ops = { | |
1462 | .enable = m66592_enable, | |
1463 | .disable = m66592_disable, | |
1464 | ||
1465 | .alloc_request = m66592_alloc_request, | |
1466 | .free_request = m66592_free_request, | |
1467 | ||
4cf2503c YS |
1468 | .queue = m66592_queue, |
1469 | .dequeue = m66592_dequeue, | |
1470 | ||
1471 | .set_halt = m66592_set_halt, | |
4cf2503c YS |
1472 | .fifo_flush = m66592_fifo_flush, |
1473 | }; | |
1474 | ||
1475 | /*-------------------------------------------------------------------------*/ | |
1476 | static struct m66592 *the_controller; | |
1477 | ||
0f91349b | 1478 | static int m66592_start(struct usb_gadget_driver *driver, |
b0fca50f | 1479 | int (*bind)(struct usb_gadget *)) |
4cf2503c YS |
1480 | { |
1481 | struct m66592 *m66592 = the_controller; | |
1482 | int retval; | |
1483 | ||
598f22e1 YS |
1484 | if (!driver |
1485 | || driver->speed != USB_SPEED_HIGH | |
b0fca50f | 1486 | || !bind |
598f22e1 | 1487 | || !driver->setup) |
4cf2503c YS |
1488 | return -EINVAL; |
1489 | if (!m66592) | |
1490 | return -ENODEV; | |
1491 | if (m66592->driver) | |
1492 | return -EBUSY; | |
1493 | ||
1494 | /* hook up the driver */ | |
1495 | driver->driver.bus = NULL; | |
1496 | m66592->driver = driver; | |
1497 | m66592->gadget.dev.driver = &driver->driver; | |
1498 | ||
1499 | retval = device_add(&m66592->gadget.dev); | |
1500 | if (retval) { | |
00274921 | 1501 | pr_err("device_add error (%d)\n", retval); |
4cf2503c YS |
1502 | goto error; |
1503 | } | |
1504 | ||
b0fca50f | 1505 | retval = bind(&m66592->gadget); |
4cf2503c | 1506 | if (retval) { |
00274921 | 1507 | pr_err("bind to driver error (%d)\n", retval); |
4cf2503c YS |
1508 | device_del(&m66592->gadget.dev); |
1509 | goto error; | |
1510 | } | |
1511 | ||
1512 | m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0); | |
1513 | if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) { | |
1514 | m66592_start_xclock(m66592); | |
1515 | /* start vbus sampling */ | |
1516 | m66592->old_vbus = m66592_read(m66592, | |
1517 | M66592_INTSTS0) & M66592_VBSTS; | |
1518 | m66592->scount = M66592_MAX_SAMPLING; | |
598f22e1 | 1519 | mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50)); |
4cf2503c YS |
1520 | } |
1521 | ||
1522 | return 0; | |
1523 | ||
1524 | error: | |
1525 | m66592->driver = NULL; | |
1526 | m66592->gadget.dev.driver = NULL; | |
1527 | ||
1528 | return retval; | |
1529 | } | |
4cf2503c | 1530 | |
0f91349b | 1531 | static int m66592_stop(struct usb_gadget_driver *driver) |
4cf2503c YS |
1532 | { |
1533 | struct m66592 *m66592 = the_controller; | |
1534 | unsigned long flags; | |
1535 | ||
598f22e1 YS |
1536 | if (driver != m66592->driver || !driver->unbind) |
1537 | return -EINVAL; | |
1538 | ||
4cf2503c YS |
1539 | spin_lock_irqsave(&m66592->lock, flags); |
1540 | if (m66592->gadget.speed != USB_SPEED_UNKNOWN) | |
1541 | m66592_usb_disconnect(m66592); | |
1542 | spin_unlock_irqrestore(&m66592->lock, flags); | |
1543 | ||
1544 | m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0); | |
1545 | ||
1546 | driver->unbind(&m66592->gadget); | |
eb0be47d | 1547 | m66592->gadget.dev.driver = NULL; |
4cf2503c YS |
1548 | |
1549 | init_controller(m66592); | |
1550 | disable_controller(m66592); | |
1551 | ||
1552 | device_del(&m66592->gadget.dev); | |
1553 | m66592->driver = NULL; | |
1554 | return 0; | |
1555 | } | |
4cf2503c YS |
1556 | |
1557 | /*-------------------------------------------------------------------------*/ | |
1558 | static int m66592_get_frame(struct usb_gadget *_gadget) | |
1559 | { | |
1560 | struct m66592 *m66592 = gadget_to_m66592(_gadget); | |
1561 | return m66592_read(m66592, M66592_FRMNUM) & 0x03FF; | |
1562 | } | |
1563 | ||
1564 | static struct usb_gadget_ops m66592_gadget_ops = { | |
1565 | .get_frame = m66592_get_frame, | |
0f91349b SAS |
1566 | .start = m66592_start, |
1567 | .stop = m66592_stop, | |
4cf2503c YS |
1568 | }; |
1569 | ||
598f22e1 | 1570 | static int __exit m66592_remove(struct platform_device *pdev) |
4cf2503c YS |
1571 | { |
1572 | struct m66592 *m66592 = dev_get_drvdata(&pdev->dev); | |
1573 | ||
0f91349b SAS |
1574 | usb_del_gadget_udc(&m66592->gadget); |
1575 | ||
4cf2503c YS |
1576 | del_timer_sync(&m66592->timer); |
1577 | iounmap(m66592->reg); | |
1578 | free_irq(platform_get_irq(pdev, 0), m66592); | |
598f22e1 | 1579 | m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req); |
2c59b0b7 MD |
1580 | #ifdef CONFIG_HAVE_CLK |
1581 | if (m66592->pdata->on_chip) { | |
1582 | clk_disable(m66592->clk); | |
1583 | clk_put(m66592->clk); | |
1584 | } | |
af5be79a | 1585 | #endif |
4cf2503c YS |
1586 | kfree(m66592); |
1587 | return 0; | |
1588 | } | |
1589 | ||
598f22e1 YS |
1590 | static void nop_completion(struct usb_ep *ep, struct usb_request *r) |
1591 | { | |
1592 | } | |
1593 | ||
4cf2503c YS |
1594 | static int __init m66592_probe(struct platform_device *pdev) |
1595 | { | |
2c59b0b7 | 1596 | struct resource *res, *ires; |
4cf2503c YS |
1597 | void __iomem *reg = NULL; |
1598 | struct m66592 *m66592 = NULL; | |
2c59b0b7 | 1599 | #ifdef CONFIG_HAVE_CLK |
af5be79a MD |
1600 | char clk_name[8]; |
1601 | #endif | |
4cf2503c YS |
1602 | int ret = 0; |
1603 | int i; | |
1604 | ||
0a2e5b9b | 1605 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4cf2503c YS |
1606 | if (!res) { |
1607 | ret = -ENODEV; | |
0a2e5b9b | 1608 | pr_err("platform_get_resource error.\n"); |
4cf2503c YS |
1609 | goto clean_up; |
1610 | } | |
1611 | ||
2c59b0b7 MD |
1612 | ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1613 | if (!ires) { | |
4cf2503c | 1614 | ret = -ENODEV; |
2c59b0b7 MD |
1615 | dev_err(&pdev->dev, |
1616 | "platform_get_resource IORESOURCE_IRQ error.\n"); | |
4cf2503c YS |
1617 | goto clean_up; |
1618 | } | |
1619 | ||
0a2e5b9b | 1620 | reg = ioremap(res->start, resource_size(res)); |
4cf2503c YS |
1621 | if (reg == NULL) { |
1622 | ret = -ENOMEM; | |
00274921 | 1623 | pr_err("ioremap error.\n"); |
4cf2503c YS |
1624 | goto clean_up; |
1625 | } | |
1626 | ||
2c59b0b7 MD |
1627 | if (pdev->dev.platform_data == NULL) { |
1628 | dev_err(&pdev->dev, "no platform data\n"); | |
1629 | ret = -ENODEV; | |
1630 | goto clean_up; | |
1631 | } | |
1632 | ||
4cf2503c YS |
1633 | /* initialize ucd */ |
1634 | m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL); | |
1635 | if (m66592 == NULL) { | |
7c81aafa | 1636 | ret = -ENOMEM; |
00274921 | 1637 | pr_err("kzalloc error\n"); |
4cf2503c YS |
1638 | goto clean_up; |
1639 | } | |
1640 | ||
2c59b0b7 MD |
1641 | m66592->pdata = pdev->dev.platform_data; |
1642 | m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK; | |
1643 | ||
4cf2503c YS |
1644 | spin_lock_init(&m66592->lock); |
1645 | dev_set_drvdata(&pdev->dev, m66592); | |
1646 | ||
1647 | m66592->gadget.ops = &m66592_gadget_ops; | |
1648 | device_initialize(&m66592->gadget.dev); | |
836e4b14 | 1649 | dev_set_name(&m66592->gadget.dev, "gadget"); |
4cf2503c YS |
1650 | m66592->gadget.is_dualspeed = 1; |
1651 | m66592->gadget.dev.parent = &pdev->dev; | |
1652 | m66592->gadget.dev.dma_mask = pdev->dev.dma_mask; | |
1653 | m66592->gadget.dev.release = pdev->dev.release; | |
1654 | m66592->gadget.name = udc_name; | |
1655 | ||
1656 | init_timer(&m66592->timer); | |
1657 | m66592->timer.function = m66592_timer; | |
1658 | m66592->timer.data = (unsigned long)m66592; | |
1659 | m66592->reg = reg; | |
1660 | ||
2c59b0b7 | 1661 | ret = request_irq(ires->start, m66592_irq, IRQF_DISABLED | IRQF_SHARED, |
598f22e1 | 1662 | udc_name, m66592); |
4cf2503c | 1663 | if (ret < 0) { |
00274921 | 1664 | pr_err("request_irq error (%d)\n", ret); |
4cf2503c YS |
1665 | goto clean_up; |
1666 | } | |
1667 | ||
2c59b0b7 MD |
1668 | #ifdef CONFIG_HAVE_CLK |
1669 | if (m66592->pdata->on_chip) { | |
1670 | snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id); | |
1671 | m66592->clk = clk_get(&pdev->dev, clk_name); | |
1672 | if (IS_ERR(m66592->clk)) { | |
1673 | dev_err(&pdev->dev, "cannot get clock \"%s\"\n", | |
1674 | clk_name); | |
1675 | ret = PTR_ERR(m66592->clk); | |
1676 | goto clean_up2; | |
1677 | } | |
1678 | clk_enable(m66592->clk); | |
af5be79a | 1679 | } |
af5be79a | 1680 | #endif |
4cf2503c YS |
1681 | INIT_LIST_HEAD(&m66592->gadget.ep_list); |
1682 | m66592->gadget.ep0 = &m66592->ep[0].ep; | |
1683 | INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list); | |
1684 | for (i = 0; i < M66592_MAX_NUM_PIPE; i++) { | |
1685 | struct m66592_ep *ep = &m66592->ep[i]; | |
1686 | ||
1687 | if (i != 0) { | |
1688 | INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list); | |
1689 | list_add_tail(&m66592->ep[i].ep.ep_list, | |
598f22e1 | 1690 | &m66592->gadget.ep_list); |
4cf2503c YS |
1691 | } |
1692 | ep->m66592 = m66592; | |
1693 | INIT_LIST_HEAD(&ep->queue); | |
1694 | ep->ep.name = m66592_ep_name[i]; | |
1695 | ep->ep.ops = &m66592_ep_ops; | |
1696 | ep->ep.maxpacket = 512; | |
1697 | } | |
1698 | m66592->ep[0].ep.maxpacket = 64; | |
1699 | m66592->ep[0].pipenum = 0; | |
1700 | m66592->ep[0].fifoaddr = M66592_CFIFO; | |
1701 | m66592->ep[0].fifosel = M66592_CFIFOSEL; | |
1702 | m66592->ep[0].fifoctr = M66592_CFIFOCTR; | |
1703 | m66592->ep[0].fifotrn = 0; | |
1704 | m66592->ep[0].pipectr = get_pipectr_addr(0); | |
1705 | m66592->pipenum2ep[0] = &m66592->ep[0]; | |
1706 | m66592->epaddr2ep[0] = &m66592->ep[0]; | |
1707 | ||
1708 | the_controller = m66592; | |
1709 | ||
1710 | m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL); | |
1711 | if (m66592->ep0_req == NULL) | |
af5be79a | 1712 | goto clean_up3; |
598f22e1 | 1713 | m66592->ep0_req->complete = nop_completion; |
4cf2503c YS |
1714 | |
1715 | init_controller(m66592); | |
1716 | ||
0f91349b SAS |
1717 | ret = usb_add_gadget_udc(&pdev->dev, &m66592->gadget); |
1718 | if (ret) | |
1719 | goto err_add_udc; | |
1720 | ||
598f22e1 | 1721 | dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION); |
4cf2503c YS |
1722 | return 0; |
1723 | ||
0f91349b SAS |
1724 | err_add_udc: |
1725 | m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req); | |
1726 | ||
af5be79a | 1727 | clean_up3: |
2c59b0b7 MD |
1728 | #ifdef CONFIG_HAVE_CLK |
1729 | if (m66592->pdata->on_chip) { | |
1730 | clk_disable(m66592->clk); | |
1731 | clk_put(m66592->clk); | |
1732 | } | |
598f22e1 | 1733 | clean_up2: |
d6435102 | 1734 | #endif |
2c59b0b7 | 1735 | free_irq(ires->start, m66592); |
4cf2503c YS |
1736 | clean_up: |
1737 | if (m66592) { | |
1738 | if (m66592->ep0_req) | |
1739 | m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req); | |
1740 | kfree(m66592); | |
1741 | } | |
1742 | if (reg) | |
1743 | iounmap(reg); | |
1744 | ||
1745 | return ret; | |
1746 | } | |
1747 | ||
1748 | /*-------------------------------------------------------------------------*/ | |
1749 | static struct platform_driver m66592_driver = { | |
598f22e1 | 1750 | .remove = __exit_p(m66592_remove), |
4cf2503c YS |
1751 | .driver = { |
1752 | .name = (char *) udc_name, | |
f34c32f1 | 1753 | .owner = THIS_MODULE, |
4cf2503c YS |
1754 | }, |
1755 | }; | |
1756 | ||
1757 | static int __init m66592_udc_init(void) | |
1758 | { | |
598f22e1 | 1759 | return platform_driver_probe(&m66592_driver, m66592_probe); |
4cf2503c YS |
1760 | } |
1761 | module_init(m66592_udc_init); | |
1762 | ||
1763 | static void __exit m66592_udc_cleanup(void) | |
1764 | { | |
1765 | platform_driver_unregister(&m66592_driver); | |
1766 | } | |
1767 | module_exit(m66592_udc_cleanup); |