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usb: gadget: completely remove ->start/->stop
[deliverable/linux.git] / drivers / usb / gadget / mv_udc_core.c
CommitLineData
dde34cc5
NZ		 1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
e7cddda4 12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/dmapool.h>
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/ioport.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/errno.h>
ded017ee 22#include <linux/err.h>
e7cddda4 23#include <linux/init.h>
24#include <linux/timer.h>
25#include <linux/list.h>
26#include <linux/interrupt.h>
27#include <linux/moduleparam.h>
28#include <linux/device.h>
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31#include <linux/usb/otg.h>
32#include <linux/pm.h>
33#include <linux/io.h>
34#include <linux/irq.h>
35#include <linux/platform_device.h>
36#include <linux/clk.h>
dde34cc5 37#include <linux/platform_data/mv_usb.h>
e7cddda4 38#include <asm/unaligned.h>
39
40#include "mv_udc.h"
41
42#define DRIVER_DESC "Marvell PXA USB Device Controller driver"
43#define DRIVER_VERSION "8 Nov 2010"
44
45#define ep_dir(ep) (((ep)->ep_num == 0) ? \
46 ((ep)->udc->ep0_dir) : ((ep)->direction))
47
48/* timeout value -- usec */
49#define RESET_TIMEOUT 10000
50#define FLUSH_TIMEOUT 10000
51#define EPSTATUS_TIMEOUT 10000
52#define PRIME_TIMEOUT 10000
53#define READSAFE_TIMEOUT 1000
e7cddda4 54
9b2035a0 55#define LOOPS_USEC_SHIFT 1
e7cddda4 56#define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
57#define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
58
dde34cc5
NZ		 59static DECLARE_COMPLETION(release_done);
60
e7cddda4 61static const char driver_name[] = "mv_udc";
62static const char driver_desc[] = DRIVER_DESC;
63
e7cddda4 64static void nuke(struct mv_ep *ep, int status);
1aec033b 65static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
e7cddda4 66
67/* for endpoint 0 operations */
68static const struct usb_endpoint_descriptor mv_ep0_desc = {
69 .bLength = USB_DT_ENDPOINT_SIZE,
70 .bDescriptorType = USB_DT_ENDPOINT,
71 .bEndpointAddress = 0,
72 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
73 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
74};
75
76static void ep0_reset(struct mv_udc *udc)
77{
78 struct mv_ep *ep;
79 u32 epctrlx;
80 int i = 0;
81
82 /* ep0 in and out */
83 for (i = 0; i < 2; i++) {
84 ep = &udc->eps[i];
85 ep->udc = udc;
86
87 /* ep0 dQH */
88 ep->dqh = &udc->ep_dqh[i];
89
90 /* configure ep0 endpoint capabilities in dQH */
91 ep->dqh->max_packet_length =
92 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
93 | EP_QUEUE_HEAD_IOS;
94
fbebe1f0
NZ		 95 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
96
e7cddda4 97 epctrlx = readl(&udc->op_regs->epctrlx[0]);
98 if (i) { /* TX */
43ad9f3f 99 epctrlx |= EPCTRL_TX_ENABLE
e7cddda4 100 | (USB_ENDPOINT_XFER_CONTROL
101 << EPCTRL_TX_EP_TYPE_SHIFT);
102
103 } else { /* RX */
43ad9f3f 104 epctrlx |= EPCTRL_RX_ENABLE
e7cddda4 105 | (USB_ENDPOINT_XFER_CONTROL
106 << EPCTRL_RX_EP_TYPE_SHIFT);
107 }
108
109 writel(epctrlx, &udc->op_regs->epctrlx[0]);
110 }
111}
112
113/* protocol ep0 stall, will automatically be cleared on new transaction */
114static void ep0_stall(struct mv_udc *udc)
115{
116 u32 epctrlx;
117
118 /* set TX and RX to stall */
119 epctrlx = readl(&udc->op_regs->epctrlx[0]);
120 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
121 writel(epctrlx, &udc->op_regs->epctrlx[0]);
122
123 /* update ep0 state */
124 udc->ep0_state = WAIT_FOR_SETUP;
125 udc->ep0_dir = EP_DIR_OUT;
126}
127
128static int process_ep_req(struct mv_udc *udc, int index,
129 struct mv_req *curr_req)
130{
131 struct mv_dtd *curr_dtd;
132 struct mv_dqh *curr_dqh;
133 int td_complete, actual, remaining_length;
134 int i, direction;
135 int retval = 0;
136 u32 errors;
daec765d 137 u32 bit_pos;
e7cddda4 138
139 curr_dqh = &udc->ep_dqh[index];
140 direction = index % 2;
141
142 curr_dtd = curr_req->head;
143 td_complete = 0;
144 actual = curr_req->req.length;
145
146 for (i = 0; i < curr_req->dtd_count; i++) {
147 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
148 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
149 udc->eps[index].name);
150 return 1;
151 }
152
153 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
154 if (!errors) {
daec765d 155 remaining_length =
e7cddda4 156 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
157 >> DTD_LENGTH_BIT_POS;
158 actual -= remaining_length;
daec765d
NZ		 159
160 if (remaining_length) {
161 if (direction) {
162 dev_dbg(&udc->dev->dev,
163 "TX dTD remains data\n");
164 retval = -EPROTO;
165 break;
166 } else
167 break;
168 }
e7cddda4 169 } else {
170 dev_info(&udc->dev->dev,
171 "complete_tr error: ep=%d %s: error = 0x%x\n",
172 index >> 1, direction ? "SEND" : "RECV",
173 errors);
174 if (errors & DTD_STATUS_HALTED) {
175 /* Clear the errors and Halt condition */
176 curr_dqh->size_ioc_int_sts &= ~errors;
177 retval = -EPIPE;
178 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
179 retval = -EPROTO;
180 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
181 retval = -EILSEQ;
182 }
183 }
184 if (i != curr_req->dtd_count - 1)
185 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
186 }
187 if (retval)
188 return retval;
189
daec765d
NZ		 190 if (direction == EP_DIR_OUT)
191 bit_pos = 1 << curr_req->ep->ep_num;
192 else
193 bit_pos = 1 << (16 + curr_req->ep->ep_num);
194
195 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
196 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
197 while (readl(&udc->op_regs->epstatus) & bit_pos)
198 udelay(1);
199 break;
200 }
201 udelay(1);
202 }
203
e7cddda4 204 curr_req->req.actual = actual;
205
206 return 0;
207}
208
209/*
210 * done() - retire a request; caller blocked irqs
211 * @status : request status to be set, only works when
212 * request is still in progress.
213 */
214static void done(struct mv_ep *ep, struct mv_req *req, int status)
215{
216 struct mv_udc *udc = NULL;
217 unsigned char stopped = ep->stopped;
218 struct mv_dtd *curr_td, *next_td;
219 int j;
220
221 udc = (struct mv_udc *)ep->udc;
222 /* Removed the req from fsl_ep->queue */
223 list_del_init(&req->queue);
224
225 /* req.status should be set as -EINPROGRESS in ep_queue() */
226 if (req->req.status == -EINPROGRESS)
227 req->req.status = status;
228 else
229 status = req->req.status;
230
231 /* Free dtd for the request */
232 next_td = req->head;
233 for (j = 0; j < req->dtd_count; j++) {
234 curr_td = next_td;
235 if (j != req->dtd_count - 1)
236 next_td = curr_td->next_dtd_virt;
237 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
238 }
239
240 if (req->mapped) {
241 dma_unmap_single(ep->udc->gadget.dev.parent,
242 req->req.dma, req->req.length,
243 ((ep_dir(ep) == EP_DIR_IN) ?
244 DMA_TO_DEVICE : DMA_FROM_DEVICE));
245 req->req.dma = DMA_ADDR_INVALID;
246 req->mapped = 0;
247 } else
248 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
249 req->req.dma, req->req.length,
250 ((ep_dir(ep) == EP_DIR_IN) ?
251 DMA_TO_DEVICE : DMA_FROM_DEVICE));
252
253 if (status && (status != -ESHUTDOWN))
254 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
255 ep->ep.name, &req->req, status,
256 req->req.actual, req->req.length);
257
258 ep->stopped = 1;
259
260 spin_unlock(&ep->udc->lock);
261 /*
262 * complete() is from gadget layer,
263 * eg fsg->bulk_in_complete()
264 */
265 if (req->req.complete)
266 req->req.complete(&ep->ep, &req->req);
267
268 spin_lock(&ep->udc->lock);
269 ep->stopped = stopped;
270}
271
272static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
273{
e7cddda4 274 struct mv_udc *udc;
275 struct mv_dqh *dqh;
91d959d8
NZ		 276 u32 bit_pos, direction;
277 u32 usbcmd, epstatus;
e7cddda4 278 unsigned int loops;
91d959d8 279 int retval = 0;
e7cddda4 280
281 udc = ep->udc;
282 direction = ep_dir(ep);
283 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
284 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
285
286 /* check if the pipe is empty */
287 if (!(list_empty(&ep->queue))) {
288 struct mv_req *lastreq;
289 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
290 lastreq->tail->dtd_next =
291 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
91d959d8
NZ		 292
293 wmb();
294
295 if (readl(&udc->op_regs->epprime) & bit_pos)
296 goto done;
297
e7cddda4 298 loops = LOOPS(READSAFE_TIMEOUT);
91d959d8 299 while (1) {
e7cddda4 300 /* start with setting the semaphores */
91d959d8
NZ		 301 usbcmd = readl(&udc->op_regs->usbcmd);
302 usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
303 writel(usbcmd, &udc->op_regs->usbcmd);
e7cddda4 304
305 /* read the endpoint status */
306 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
307
308 /*
309 * Reread the ATDTW semaphore bit to check if it is
310 * cleared. When hardware see a hazard, it will clear
311 * the bit or else we remain set to 1 and we can
312 * proceed with priming of endpoint if not already
313 * primed.
314 */
315 if (readl(&udc->op_regs->usbcmd)
91d959d8
NZ		 316 & USBCMD_ATDTW_TRIPWIRE_SET)
317 break;
318
e7cddda4 319 loops--;
91d959d8
NZ		 320 if (loops == 0) {
321 dev_err(&udc->dev->dev,
322 "Timeout for ATDTW_TRIPWIRE...\n");
323 retval = -ETIME;
324 goto done;
325 }
e7cddda4 326 udelay(LOOPS_USEC);
327 }
328
329 /* Clear the semaphore */
91d959d8
NZ		 330 usbcmd = readl(&udc->op_regs->usbcmd);
331 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
332 writel(usbcmd, &udc->op_regs->usbcmd);
e7cddda4 333
91d959d8
NZ		 334 if (epstatus)
335 goto done;
336 }
e7cddda4 337
91d959d8
NZ		 338 /* Write dQH next pointer and terminate bit to 0 */
339 dqh->next_dtd_ptr = req->head->td_dma
e7cddda4 340 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
e7cddda4 341
91d959d8
NZ		 342 /* clear active and halt bit, in case set from a previous error */
343 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
e7cddda4 344
91d959d8
NZ		 345 /* Ensure that updates to the QH will occure before priming. */
346 wmb();
e7cddda4 347
91d959d8
NZ		 348 /* Prime the Endpoint */
349 writel(bit_pos, &udc->op_regs->epprime);
e7cddda4 350
e7cddda4 351done:
69932487 352 return retval;
e7cddda4 353}
354
355static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
356 dma_addr_t *dma, int *is_last)
357{
e7cddda4 358 struct mv_dtd *dtd;
359 struct mv_udc *udc;
60326ce3
CX		 360 struct mv_dqh *dqh;
361 u32 temp, mult = 0;
e7cddda4 362
363 /* how big will this transfer be? */
60326ce3
CX		 364 if (usb_endpoint_xfer_isoc(req->ep->ep.desc)) {
365 dqh = req->ep->dqh;
366 mult = (dqh->max_packet_length >> EP_QUEUE_HEAD_MULT_POS)
367 & 0x3;
368 *length = min(req->req.length - req->req.actual,
369 (unsigned)(mult * req->ep->ep.maxpacket));
370 } else
371 *length = min(req->req.length - req->req.actual,
372 (unsigned)EP_MAX_LENGTH_TRANSFER);
e7cddda4 373
374 udc = req->ep->udc;
375
376 /*
377 * Be careful that no _GFP_HIGHMEM is set,
378 * or we can not use dma_to_virt
379 */
0344606b 380 dtd = dma_pool_alloc(udc->dtd_pool, GFP_ATOMIC, dma);
e7cddda4 381 if (dtd == NULL)
382 return dtd;
383
384 dtd->td_dma = *dma;
385 /* initialize buffer page pointers */
386 temp = (u32)(req->req.dma + req->req.actual);
387 dtd->buff_ptr0 = cpu_to_le32(temp);
388 temp &= ~0xFFF;
389 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
390 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
391 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
392 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
393
394 req->req.actual += *length;
395
396 /* zlp is needed if req->req.zero is set */
397 if (req->req.zero) {
398 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
399 *is_last = 1;
400 else
401 *is_last = 0;
402 } else if (req->req.length == req->req.actual)
403 *is_last = 1;
404 else
405 *is_last = 0;
406
407 /* Fill in the transfer size; set active bit */
408 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
409
410 /* Enable interrupt for the last dtd of a request */
411 if (*is_last && !req->req.no_interrupt)
412 temp |= DTD_IOC;
413
60326ce3
CX		 414 temp |= mult << 10;
415
e7cddda4 416 dtd->size_ioc_sts = temp;
417
418 mb();
419
420 return dtd;
421}
422
423/* generate dTD linked list for a request */
424static int req_to_dtd(struct mv_req *req)
425{
426 unsigned count;
427 int is_last, is_first = 1;
428 struct mv_dtd *dtd, *last_dtd = NULL;
429 struct mv_udc *udc;
430 dma_addr_t dma;
431
432 udc = req->ep->udc;
433
434 do {
435 dtd = build_dtd(req, &count, &dma, &is_last);
436 if (dtd == NULL)
437 return -ENOMEM;
438
439 if (is_first) {
440 is_first = 0;
441 req->head = dtd;
442 } else {
443 last_dtd->dtd_next = dma;
444 last_dtd->next_dtd_virt = dtd;
445 }
446 last_dtd = dtd;
447 req->dtd_count++;
448 } while (!is_last);
449
450 /* set terminate bit to 1 for the last dTD */
451 dtd->dtd_next = DTD_NEXT_TERMINATE;
452
453 req->tail = dtd;
454
455 return 0;
456}
457
458static int mv_ep_enable(struct usb_ep *_ep,
459 const struct usb_endpoint_descriptor *desc)
460{
461 struct mv_udc *udc;
462 struct mv_ep *ep;
463 struct mv_dqh *dqh;
464 u16 max = 0;
465 u32 bit_pos, epctrlx, direction;
466 unsigned char zlt = 0, ios = 0, mult = 0;
27cec2b2 467 unsigned long flags;
e7cddda4 468
469 ep = container_of(_ep, struct mv_ep, ep);
470 udc = ep->udc;
471
e0f4f9d4 472 if (!_ep || !desc
e7cddda4 473 || desc->bDescriptorType != USB_DT_ENDPOINT)
474 return -EINVAL;
475
476 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
477 return -ESHUTDOWN;
478
479 direction = ep_dir(ep);
29cc8897 480 max = usb_endpoint_maxp(desc);
e7cddda4 481
482 /*
483 * disable HW zero length termination select
484 * driver handles zero length packet through req->req.zero
485 */
486 zlt = 1;
487
e7cddda4 488 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
489
490 /* Check if the Endpoint is Primed */
491 if ((readl(&udc->op_regs->epprime) & bit_pos)
492 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
493 dev_info(&udc->dev->dev,
494 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
495 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
496 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
497 (unsigned)readl(&udc->op_regs->epprime),
498 (unsigned)readl(&udc->op_regs->epstatus),
499 (unsigned)bit_pos);
500 goto en_done;
501 }
502 /* Set the max packet length, interrupt on Setup and Mult fields */
503 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
504 case USB_ENDPOINT_XFER_BULK:
505 zlt = 1;
506 mult = 0;
507 break;
508 case USB_ENDPOINT_XFER_CONTROL:
509 ios = 1;
510 case USB_ENDPOINT_XFER_INT:
511 mult = 0;
512 break;
513 case USB_ENDPOINT_XFER_ISOC:
514 /* Calculate transactions needed for high bandwidth iso */
515 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
bedcff97 516 max = max & 0x7ff; /* bit 0~10 */
e7cddda4 517 /* 3 transactions at most */
518 if (mult > 3)
519 goto en_done;
520 break;
521 default:
522 goto en_done;
523 }
27cec2b2
NZ		 524
525 spin_lock_irqsave(&udc->lock, flags);
526 /* Get the endpoint queue head address */
527 dqh = ep->dqh;
e7cddda4 528 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
529 | (mult << EP_QUEUE_HEAD_MULT_POS)
530 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
531 | (ios ? EP_QUEUE_HEAD_IOS : 0);
532 dqh->next_dtd_ptr = 1;
533 dqh->size_ioc_int_sts = 0;
534
535 ep->ep.maxpacket = max;
b1371d16 536 ep->ep.desc = desc;
e7cddda4 537 ep->stopped = 0;
538
539 /* Enable the endpoint for Rx or Tx and set the endpoint type */
540 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
541 if (direction == EP_DIR_IN) {
542 epctrlx &= ~EPCTRL_TX_ALL_MASK;
543 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
544 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
545 << EPCTRL_TX_EP_TYPE_SHIFT);
546 } else {
547 epctrlx &= ~EPCTRL_RX_ALL_MASK;
548 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
549 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
550 << EPCTRL_RX_EP_TYPE_SHIFT);
551 }
552 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
553
554 /*
555 * Implement Guideline (GL# USB-7) The unused endpoint type must
556 * be programmed to bulk.
557 */
558 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
559 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
615268b0 560 epctrlx |= (USB_ENDPOINT_XFER_BULK
e7cddda4 561 << EPCTRL_RX_EP_TYPE_SHIFT);
562 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
563 }
564
565 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
566 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
615268b0 567 epctrlx |= (USB_ENDPOINT_XFER_BULK
e7cddda4 568 << EPCTRL_TX_EP_TYPE_SHIFT);
569 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
570 }
571
27cec2b2
NZ		 572 spin_unlock_irqrestore(&udc->lock, flags);
573
e7cddda4 574 return 0;
575en_done:
576 return -EINVAL;
577}
578
579static int mv_ep_disable(struct usb_ep *_ep)
580{
581 struct mv_udc *udc;
582 struct mv_ep *ep;
583 struct mv_dqh *dqh;
584 u32 bit_pos, epctrlx, direction;
27cec2b2 585 unsigned long flags;
e7cddda4 586
587 ep = container_of(_ep, struct mv_ep, ep);
b1371d16 588 if ((_ep == NULL) || !ep->ep.desc)
e7cddda4 589 return -EINVAL;
590
591 udc = ep->udc;
592
593 /* Get the endpoint queue head address */
594 dqh = ep->dqh;
595
27cec2b2
NZ		 596 spin_lock_irqsave(&udc->lock, flags);
597
e7cddda4 598 direction = ep_dir(ep);
599 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
600
601 /* Reset the max packet length and the interrupt on Setup */
602 dqh->max_packet_length = 0;
603
604 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
605 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
606 epctrlx &= ~((direction == EP_DIR_IN)
607 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
608 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
609 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
610
611 /* nuke all pending requests (does flush) */
612 nuke(ep, -ESHUTDOWN);
613
f9c56cdd 614 ep->ep.desc = NULL;
e7cddda4 615 ep->stopped = 1;
27cec2b2
NZ		 616
617 spin_unlock_irqrestore(&udc->lock, flags);
618
e7cddda4 619 return 0;
620}
621
622static struct usb_request *
623mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
624{
625 struct mv_req *req = NULL;
626
627 req = kzalloc(sizeof *req, gfp_flags);
628 if (!req)
629 return NULL;
630
631 req->req.dma = DMA_ADDR_INVALID;
632 INIT_LIST_HEAD(&req->queue);
633
634 return &req->req;
635}
636
637static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
638{
639 struct mv_req *req = NULL;
640
641 req = container_of(_req, struct mv_req, req);
642
643 if (_req)
644 kfree(req);
645}
646
647static void mv_ep_fifo_flush(struct usb_ep *_ep)
648{
649 struct mv_udc *udc;
650 u32 bit_pos, direction;
0c70840b 651 struct mv_ep *ep;
e7cddda4 652 unsigned int loops;
653
0c70840b
NZ		 654 if (!_ep)
655 return;
656
657 ep = container_of(_ep, struct mv_ep, ep);
b1371d16 658 if (!ep->ep.desc)
0c70840b
NZ		 659 return;
660
e7cddda4 661 udc = ep->udc;
662 direction = ep_dir(ep);
e7cddda4 663
0c70840b
NZ		 664 if (ep->ep_num == 0)
665 bit_pos = (1 << 16) | 1;
666 else if (direction == EP_DIR_OUT)
667 bit_pos = 1 << ep->ep_num;
668 else
669 bit_pos = 1 << (16 + ep->ep_num);
670
e7cddda4 671 loops = LOOPS(EPSTATUS_TIMEOUT);
0c70840b 672 do {
e7cddda4 673 unsigned int inter_loops;
674
675 if (loops == 0) {
676 dev_err(&udc->dev->dev,
677 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
678 (unsigned)readl(&udc->op_regs->epstatus),
679 (unsigned)bit_pos);
680 return;
681 }
682 /* Write 1 to the Flush register */
683 writel(bit_pos, &udc->op_regs->epflush);
684
685 /* Wait until flushing completed */
686 inter_loops = LOOPS(FLUSH_TIMEOUT);
0c70840b 687 while (readl(&udc->op_regs->epflush)) {
e7cddda4 688 /*
689 * ENDPTFLUSH bit should be cleared to indicate this
690 * operation is complete
691 */
692 if (inter_loops == 0) {
693 dev_err(&udc->dev->dev,
694 "TIMEOUT for ENDPTFLUSH=0x%x,"
695 "bit_pos=0x%x\n",
696 (unsigned)readl(&udc->op_regs->epflush),
697 (unsigned)bit_pos);
698 return;
699 }
700 inter_loops--;
701 udelay(LOOPS_USEC);
702 }
703 loops--;
0c70840b 704 } while (readl(&udc->op_regs->epstatus) & bit_pos);
e7cddda4 705}
706
707/* queues (submits) an I/O request to an endpoint */
708static int
709mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
710{
711 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
712 struct mv_req *req = container_of(_req, struct mv_req, req);
713 struct mv_udc *udc = ep->udc;
714 unsigned long flags;
0344606b 715 int retval;
e7cddda4 716
717 /* catch various bogus parameters */
718 if (!_req || !req->req.complete || !req->req.buf
719 || !list_empty(&req->queue)) {
720 dev_err(&udc->dev->dev, "%s, bad params", __func__);
721 return -EINVAL;
722 }
b1371d16 723 if (unlikely(!_ep || !ep->ep.desc)) {
e7cddda4 724 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
725 return -EINVAL;
726 }
e7cddda4 727
728 udc = ep->udc;
729 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
730 return -ESHUTDOWN;
731
732 req->ep = ep;
733
734 /* map virtual address to hardware */
735 if (req->req.dma == DMA_ADDR_INVALID) {
736 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
737 req->req.buf,
738 req->req.length, ep_dir(ep)
739 ? DMA_TO_DEVICE
740 : DMA_FROM_DEVICE);
741 req->mapped = 1;
742 } else {
743 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
744 req->req.dma, req->req.length,
745 ep_dir(ep)
746 ? DMA_TO_DEVICE
747 : DMA_FROM_DEVICE);
748 req->mapped = 0;
749 }
750
751 req->req.status = -EINPROGRESS;
752 req->req.actual = 0;
753 req->dtd_count = 0;
754
755 spin_lock_irqsave(&udc->lock, flags);
756
757 /* build dtds and push them to device queue */
758 if (!req_to_dtd(req)) {
e7cddda4 759 retval = queue_dtd(ep, req);
760 if (retval) {
761 spin_unlock_irqrestore(&udc->lock, flags);
0344606b
NZ		 762 dev_err(&udc->dev->dev, "Failed to queue dtd\n");
763 goto err_unmap_dma;
e7cddda4 764 }
765 } else {
766 spin_unlock_irqrestore(&udc->lock, flags);
0344606b
NZ		 767 dev_err(&udc->dev->dev, "Failed to dma_pool_alloc\n");
768 retval = -ENOMEM;
769 goto err_unmap_dma;
e7cddda4 770 }
771
772 /* Update ep0 state */
773 if (ep->ep_num == 0)
774 udc->ep0_state = DATA_STATE_XMIT;
775
776 /* irq handler advances the queue */
10800f2c 777 list_add_tail(&req->queue, &ep->queue);
e7cddda4 778 spin_unlock_irqrestore(&udc->lock, flags);
779
780 return 0;
0344606b
NZ		 781
782err_unmap_dma:
783 if (req->mapped) {
784 dma_unmap_single(ep->udc->gadget.dev.parent,
785 req->req.dma, req->req.length,
786 ((ep_dir(ep) == EP_DIR_IN) ?
787 DMA_TO_DEVICE : DMA_FROM_DEVICE));
788 req->req.dma = DMA_ADDR_INVALID;
789 req->mapped = 0;
790 } else
791 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
792 req->req.dma, req->req.length,
793 ((ep_dir(ep) == EP_DIR_IN) ?
794 DMA_TO_DEVICE : DMA_FROM_DEVICE));
795
796 return retval;
e7cddda4 797}
798
c2bbd16b
NZ		 799static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
800{
801 struct mv_dqh *dqh = ep->dqh;
802 u32 bit_pos;
803
804 /* Write dQH next pointer and terminate bit to 0 */
805 dqh->next_dtd_ptr = req->head->td_dma
806 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
807
808 /* clear active and halt bit, in case set from a previous error */
809 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
810
811 /* Ensure that updates to the QH will occure before priming. */
812 wmb();
813
814 bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
815
816 /* Prime the Endpoint */
817 writel(bit_pos, &ep->udc->op_regs->epprime);
818}
819
e7cddda4 820/* dequeues (cancels, unlinks) an I/O request from an endpoint */
821static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
822{
823 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
824 struct mv_req *req;
825 struct mv_udc *udc = ep->udc;
826 unsigned long flags;
827 int stopped, ret = 0;
828 u32 epctrlx;
829
830 if (!_ep || !_req)
831 return -EINVAL;
832
833 spin_lock_irqsave(&ep->udc->lock, flags);
834 stopped = ep->stopped;
835
836 /* Stop the ep before we deal with the queue */
837 ep->stopped = 1;
838 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
839 if (ep_dir(ep) == EP_DIR_IN)
840 epctrlx &= ~EPCTRL_TX_ENABLE;
841 else
842 epctrlx &= ~EPCTRL_RX_ENABLE;
843 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
844
845 /* make sure it's actually queued on this endpoint */
846 list_for_each_entry(req, &ep->queue, queue) {
847 if (&req->req == _req)
848 break;
849 }
850 if (&req->req != _req) {
851 ret = -EINVAL;
852 goto out;
853 }
854
855 /* The request is in progress, or completed but not dequeued */
856 if (ep->queue.next == &req->queue) {
857 _req->status = -ECONNRESET;
858 mv_ep_fifo_flush(_ep); /* flush current transfer */
859
860 /* The request isn't the last request in this ep queue */
861 if (req->queue.next != &ep->queue) {
e7cddda4 862 struct mv_req *next_req;
863
c2bbd16b
NZ		 864 next_req = list_entry(req->queue.next,
865 struct mv_req, queue);
e7cddda4 866
867 /* Point the QH to the first TD of next request */
c2bbd16b 868 mv_prime_ep(ep, next_req);
e7cddda4 869 } else {
870 struct mv_dqh *qh;
871
872 qh = ep->dqh;
873 qh->next_dtd_ptr = 1;
874 qh->size_ioc_int_sts = 0;
875 }
876
877 /* The request hasn't been processed, patch up the TD chain */
878 } else {
879 struct mv_req *prev_req;
880
881 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
882 writel(readl(&req->tail->dtd_next),
883 &prev_req->tail->dtd_next);
884
885 }
886
887 done(ep, req, -ECONNRESET);
888
889 /* Enable EP */
890out:
891 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
892 if (ep_dir(ep) == EP_DIR_IN)
893 epctrlx |= EPCTRL_TX_ENABLE;
894 else
895 epctrlx |= EPCTRL_RX_ENABLE;
896 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
897 ep->stopped = stopped;
898
899 spin_unlock_irqrestore(&ep->udc->lock, flags);
900 return ret;
901}
902
903static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
904{
905 u32 epctrlx;
906
907 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
908
909 if (stall) {
910 if (direction == EP_DIR_IN)
911 epctrlx |= EPCTRL_TX_EP_STALL;
912 else
913 epctrlx |= EPCTRL_RX_EP_STALL;
914 } else {
915 if (direction == EP_DIR_IN) {
916 epctrlx &= ~EPCTRL_TX_EP_STALL;
917 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
918 } else {
919 epctrlx &= ~EPCTRL_RX_EP_STALL;
920 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
921 }
922 }
923 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
924}
925
926static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
927{
928 u32 epctrlx;
929
930 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
931
932 if (direction == EP_DIR_OUT)
933 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
934 else
935 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
936}
937
938static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
939{
940 struct mv_ep *ep;
941 unsigned long flags = 0;
942 int status = 0;
943 struct mv_udc *udc;
944
945 ep = container_of(_ep, struct mv_ep, ep);
946 udc = ep->udc;
b1371d16 947 if (!_ep || !ep->ep.desc) {
e7cddda4 948 status = -EINVAL;
949 goto out;
950 }
951
b1371d16 952 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
e7cddda4 953 status = -EOPNOTSUPP;
954 goto out;
955 }
956
957 /*
958 * Attempt to halt IN ep will fail if any transfer requests
959 * are still queue
960 */
961 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
962 status = -EAGAIN;
963 goto out;
964 }
965
966 spin_lock_irqsave(&ep->udc->lock, flags);
967 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
968 if (halt && wedge)
969 ep->wedge = 1;
970 else if (!halt)
971 ep->wedge = 0;
972 spin_unlock_irqrestore(&ep->udc->lock, flags);
973
974 if (ep->ep_num == 0) {
975 udc->ep0_state = WAIT_FOR_SETUP;
976 udc->ep0_dir = EP_DIR_OUT;
977 }
978out:
979 return status;
980}
981
982static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
983{
984 return mv_ep_set_halt_wedge(_ep, halt, 0);
985}
986
987static int mv_ep_set_wedge(struct usb_ep *_ep)
988{
989 return mv_ep_set_halt_wedge(_ep, 1, 1);
990}
991
992static struct usb_ep_ops mv_ep_ops = {
993 .enable = mv_ep_enable,
994 .disable = mv_ep_disable,
995
996 .alloc_request = mv_alloc_request,
997 .free_request = mv_free_request,
998
999 .queue = mv_ep_queue,
1000 .dequeue = mv_ep_dequeue,
1001
1002 .set_wedge = mv_ep_set_wedge,
1003 .set_halt = mv_ep_set_halt,
1004 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
1005};
1006
dde34cc5
NZ		 1007static void udc_clock_enable(struct mv_udc *udc)
1008{
1009 unsigned int i;
1010
1011 for (i = 0; i < udc->clknum; i++)
1012 clk_enable(udc->clk[i]);
1013}
1014
1015static void udc_clock_disable(struct mv_udc *udc)
1016{
1017 unsigned int i;
1018
1019 for (i = 0; i < udc->clknum; i++)
1020 clk_disable(udc->clk[i]);
1021}
1022
e7cddda4 1023static void udc_stop(struct mv_udc *udc)
1024{
1025 u32 tmp;
1026
1027 /* Disable interrupts */
1028 tmp = readl(&udc->op_regs->usbintr);
1029 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
1030 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
1031 writel(tmp, &udc->op_regs->usbintr);
1032
309d6d2b
NZ		 1033 udc->stopped = 1;
1034
e7cddda4 1035 /* Reset the Run the bit in the command register to stop VUSB */
1036 tmp = readl(&udc->op_regs->usbcmd);
1037 tmp &= ~USBCMD_RUN_STOP;
1038 writel(tmp, &udc->op_regs->usbcmd);
1039}
1040
1041static void udc_start(struct mv_udc *udc)
1042{
1043 u32 usbintr;
1044
1045 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1046 | USBINTR_PORT_CHANGE_DETECT_EN
1047 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1048 /* Enable interrupts */
1049 writel(usbintr, &udc->op_regs->usbintr);
1050
309d6d2b
NZ		 1051 udc->stopped = 0;
1052
e7cddda4 1053 /* Set the Run bit in the command register */
1054 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1055}
1056
1057static int udc_reset(struct mv_udc *udc)
1058{
1059 unsigned int loops;
1060 u32 tmp, portsc;
1061
1062 /* Stop the controller */
1063 tmp = readl(&udc->op_regs->usbcmd);
1064 tmp &= ~USBCMD_RUN_STOP;
1065 writel(tmp, &udc->op_regs->usbcmd);
1066
1067 /* Reset the controller to get default values */
1068 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1069
1070 /* wait for reset to complete */
1071 loops = LOOPS(RESET_TIMEOUT);
1072 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1073 if (loops == 0) {
1074 dev_err(&udc->dev->dev,
1075 "Wait for RESET completed TIMEOUT\n");
1076 return -ETIMEDOUT;
1077 }
1078 loops--;
1079 udelay(LOOPS_USEC);
1080 }
1081
1082 /* set controller to device mode */
1083 tmp = readl(&udc->op_regs->usbmode);
1084 tmp |= USBMODE_CTRL_MODE_DEVICE;
1085
1086 /* turn setup lockout off, require setup tripwire in usbcmd */
583a7263 1087 tmp |= USBMODE_SETUP_LOCK_OFF;
e7cddda4 1088
1089 writel(tmp, &udc->op_regs->usbmode);
1090
1091 writel(0x0, &udc->op_regs->epsetupstat);
1092
1093 /* Configure the Endpoint List Address */
1094 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1095 &udc->op_regs->eplistaddr);
1096
1097 portsc = readl(&udc->op_regs->portsc[0]);
1098 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1099 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1100
1101 if (udc->force_fs)
1102 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1103 else
1104 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1105
1106 writel(portsc, &udc->op_regs->portsc[0]);
1107
1108 tmp = readl(&udc->op_regs->epctrlx[0]);
1109 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1110 writel(tmp, &udc->op_regs->epctrlx[0]);
1111
1112 return 0;
1113}
1114
85ff7bfb 1115static int mv_udc_enable_internal(struct mv_udc *udc)
1aec033b
NZ		 1116{
1117 int retval;
1118
85ff7bfb 1119 if (udc->active)
1aec033b
NZ		 1120 return 0;
1121
1122 dev_dbg(&udc->dev->dev, "enable udc\n");
1123 udc_clock_enable(udc);
1124 if (udc->pdata->phy_init) {
1125 retval = udc->pdata->phy_init(udc->phy_regs);
1126 if (retval) {
1127 dev_err(&udc->dev->dev,
1128 "init phy error %d\n", retval);
1129 udc_clock_disable(udc);
1130 return retval;
1131 }
1132 }
1133 udc->active = 1;
1134
1135 return 0;
1136}
1137
85ff7bfb 1138static int mv_udc_enable(struct mv_udc *udc)
1aec033b 1139{
85ff7bfb
NZ		 1140 if (udc->clock_gating)
1141 return mv_udc_enable_internal(udc);
1142
1143 return 0;
1144}
1145
1146static void mv_udc_disable_internal(struct mv_udc *udc)
1147{
1148 if (udc->active) {
1aec033b
NZ		 1149 dev_dbg(&udc->dev->dev, "disable udc\n");
1150 if (udc->pdata->phy_deinit)
1151 udc->pdata->phy_deinit(udc->phy_regs);
1152 udc_clock_disable(udc);
1153 udc->active = 0;
1154 }
1155}
1156
85ff7bfb
NZ		 1157static void mv_udc_disable(struct mv_udc *udc)
1158{
1159 if (udc->clock_gating)
1160 mv_udc_disable_internal(udc);
1161}
1162
e7cddda4 1163static int mv_udc_get_frame(struct usb_gadget *gadget)
1164{
1165 struct mv_udc *udc;
1166 u16 retval;
1167
1168 if (!gadget)
1169 return -ENODEV;
1170
1171 udc = container_of(gadget, struct mv_udc, gadget);
1172
86bb7028 1173 retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
e7cddda4 1174
1175 return retval;
1176}
1177
1178/* Tries to wake up the host connected to this gadget */
1179static int mv_udc_wakeup(struct usb_gadget *gadget)
1180{
1181 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1182 u32 portsc;
1183
1184 /* Remote wakeup feature not enabled by host */
1185 if (!udc->remote_wakeup)
1186 return -ENOTSUPP;
1187
1188 portsc = readl(&udc->op_regs->portsc);
1189 /* not suspended? */
1190 if (!(portsc & PORTSCX_PORT_SUSPEND))
1191 return 0;
1192 /* trigger force resume */
1193 portsc |= PORTSCX_PORT_FORCE_RESUME;
1194 writel(portsc, &udc->op_regs->portsc[0]);
1195 return 0;
1196}
1197
1aec033b
NZ		 1198static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1199{
1200 struct mv_udc *udc;
1201 unsigned long flags;
1202 int retval = 0;
1203
1204 udc = container_of(gadget, struct mv_udc, gadget);
1205 spin_lock_irqsave(&udc->lock, flags);
1206
2bcb7514
NZ		 1207 udc->vbus_active = (is_active != 0);
1208
1aec033b
NZ		 1209 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1210 __func__, udc->softconnect, udc->vbus_active);
1211
1aec033b
NZ		 1212 if (udc->driver && udc->softconnect && udc->vbus_active) {
1213 retval = mv_udc_enable(udc);
1214 if (retval == 0) {
1215 /* Clock is disabled, need re-init registers */
1216 udc_reset(udc);
1217 ep0_reset(udc);
1218 udc_start(udc);
1219 }
1220 } else if (udc->driver && udc->softconnect) {
11c37c8b
NZ		 1221 if (!udc->active)
1222 goto out;
1223
1aec033b
NZ		 1224 /* stop all the transfer in queue*/
1225 stop_activity(udc, udc->driver);
1226 udc_stop(udc);
1227 mv_udc_disable(udc);
1228 }
1229
11c37c8b 1230out:
1aec033b
NZ		 1231 spin_unlock_irqrestore(&udc->lock, flags);
1232 return retval;
1233}
1234
e7cddda4 1235static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1236{
1237 struct mv_udc *udc;
1238 unsigned long flags;
1aec033b 1239 int retval = 0;
e7cddda4 1240
1241 udc = container_of(gadget, struct mv_udc, gadget);
1242 spin_lock_irqsave(&udc->lock, flags);
1243
2bcb7514
NZ		 1244 udc->softconnect = (is_on != 0);
1245
1aec033b
NZ		 1246 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1247 __func__, udc->softconnect, udc->vbus_active);
1248
1aec033b
NZ		 1249 if (udc->driver && udc->softconnect && udc->vbus_active) {
1250 retval = mv_udc_enable(udc);
1251 if (retval == 0) {
1252 /* Clock is disabled, need re-init registers */
1253 udc_reset(udc);
1254 ep0_reset(udc);
1255 udc_start(udc);
1256 }
1257 } else if (udc->driver && udc->vbus_active) {
1258 /* stop all the transfer in queue*/
1259 stop_activity(udc, udc->driver);
e7cddda4 1260 udc_stop(udc);
1aec033b
NZ		 1261 mv_udc_disable(udc);
1262 }
e7cddda4 1263
1264 spin_unlock_irqrestore(&udc->lock, flags);
1aec033b 1265 return retval;
e7cddda4 1266}
1267
aac16b63
CX		 1268static int mv_udc_start(struct usb_gadget *, struct usb_gadget_driver *);
1269static int mv_udc_stop(struct usb_gadget *, struct usb_gadget_driver *);
e7cddda4 1270/* device controller usb_gadget_ops structure */
1271static const struct usb_gadget_ops mv_ops = {
1272
1273 /* returns the current frame number */
1274 .get_frame = mv_udc_get_frame,
1275
1276 /* tries to wake up the host connected to this gadget */
1277 .wakeup = mv_udc_wakeup,
1278
1aec033b
NZ		 1279 /* notify controller that VBUS is powered or not */
1280 .vbus_session = mv_udc_vbus_session,
1281
e7cddda4 1282 /* D+ pullup, software-controlled connect/disconnect to USB host */
1283 .pullup = mv_udc_pullup,
aac16b63
CX		 1284 .udc_start = mv_udc_start,
1285 .udc_stop = mv_udc_stop,
e7cddda4 1286};
1287
e7cddda4 1288static int eps_init(struct mv_udc *udc)
1289{
1290 struct mv_ep *ep;
1291 char name[14];
1292 int i;
1293
1294 /* initialize ep0 */
1295 ep = &udc->eps[0];
1296 ep->udc = udc;
1297 strncpy(ep->name, "ep0", sizeof(ep->name));
1298 ep->ep.name = ep->name;
1299 ep->ep.ops = &mv_ep_ops;
1300 ep->wedge = 0;
1301 ep->stopped = 0;
1302 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1303 ep->ep_num = 0;
b1371d16 1304 ep->ep.desc = &mv_ep0_desc;
e7cddda4 1305 INIT_LIST_HEAD(&ep->queue);
1306
1307 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1308
1309 /* initialize other endpoints */
1310 for (i = 2; i < udc->max_eps * 2; i++) {
1311 ep = &udc->eps[i];
1312 if (i % 2) {
1313 snprintf(name, sizeof(name), "ep%din", i / 2);
1314 ep->direction = EP_DIR_IN;
1315 } else {
1316 snprintf(name, sizeof(name), "ep%dout", i / 2);
1317 ep->direction = EP_DIR_OUT;
1318 }
1319 ep->udc = udc;
1320 strncpy(ep->name, name, sizeof(ep->name));
1321 ep->ep.name = ep->name;
1322
1323 ep->ep.ops = &mv_ep_ops;
1324 ep->stopped = 0;
1325 ep->ep.maxpacket = (unsigned short) ~0;
1326 ep->ep_num = i / 2;
1327
1328 INIT_LIST_HEAD(&ep->queue);
1329 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1330
1331 ep->dqh = &udc->ep_dqh[i];
1332 }
1333
1334 return 0;
1335}
1336
1337/* delete all endpoint requests, called with spinlock held */
1338static void nuke(struct mv_ep *ep, int status)
1339{
1340 /* called with spinlock held */
1341 ep->stopped = 1;
1342
1343 /* endpoint fifo flush */
1344 mv_ep_fifo_flush(&ep->ep);
1345
1346 while (!list_empty(&ep->queue)) {
1347 struct mv_req *req = NULL;
1348 req = list_entry(ep->queue.next, struct mv_req, queue);
1349 done(ep, req, status);
1350 }
1351}
1352
1353/* stop all USB activities */
1354static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1355{
1356 struct mv_ep *ep;
1357
1358 nuke(&udc->eps[0], -ESHUTDOWN);
1359
1360 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1361 nuke(ep, -ESHUTDOWN);
1362 }
1363
1364 /* report disconnect; the driver is already quiesced */
1365 if (driver) {
1366 spin_unlock(&udc->lock);
1367 driver->disconnect(&udc->gadget);
1368 spin_lock(&udc->lock);
1369 }
1370}
1371
aac16b63
CX		 1372static int mv_udc_start(struct usb_gadget *gadget,
1373 struct usb_gadget_driver *driver)
e7cddda4 1374{
aac16b63 1375 struct mv_udc *udc;
e7cddda4 1376 int retval = 0;
1377 unsigned long flags;
1378
aac16b63 1379 udc = container_of(gadget, struct mv_udc, gadget);
e7cddda4 1380
1381 if (udc->driver)
1382 return -EBUSY;
1383
1384 spin_lock_irqsave(&udc->lock, flags);
1385
1386 /* hook up the driver ... */
1387 driver->driver.bus = NULL;
1388 udc->driver = driver;
1389 udc->gadget.dev.driver = &driver->driver;
1390
1391 udc->usb_state = USB_STATE_ATTACHED;
1392 udc->ep0_state = WAIT_FOR_SETUP;
1aec033b 1393 udc->ep0_dir = EP_DIR_OUT;
e7cddda4 1394
1395 spin_unlock_irqrestore(&udc->lock, flags);
1396
ded017ee 1397 if (!IS_ERR_OR_NULL(udc->transceiver)) {
6e13c650
HK		 1398 retval = otg_set_peripheral(udc->transceiver->otg,
1399 &udc->gadget);
487d54d1
NZ		 1400 if (retval) {
1401 dev_err(&udc->dev->dev,
1402 "unable to register peripheral to otg\n");
aac16b63
CX		 1403 udc->driver = NULL;
1404 udc->gadget.dev.driver = NULL;
487d54d1
NZ		 1405 return retval;
1406 }
1407 }
1408
1aec033b
NZ		 1409 /* pullup is always on */
1410 mv_udc_pullup(&udc->gadget, 1);
1411
1412 /* When boot with cable attached, there will be no vbus irq occurred */
1413 if (udc->qwork)
1414 queue_work(udc->qwork, &udc->vbus_work);
e7cddda4 1415
1416 return 0;
1417}
e7cddda4 1418
aac16b63
CX		 1419static int mv_udc_stop(struct usb_gadget *gadget,
1420 struct usb_gadget_driver *driver)
e7cddda4 1421{
aac16b63 1422 struct mv_udc *udc;
e7cddda4 1423 unsigned long flags;
1424
aac16b63 1425 udc = container_of(gadget, struct mv_udc, gadget);
e7cddda4 1426
e7cddda4 1427 spin_lock_irqsave(&udc->lock, flags);
1428
1aec033b
NZ		 1429 mv_udc_enable(udc);
1430 udc_stop(udc);
1431
e7cddda4 1432 /* stop all usb activities */
1433 udc->gadget.speed = USB_SPEED_UNKNOWN;
1434 stop_activity(udc, driver);
1aec033b
NZ		 1435 mv_udc_disable(udc);
1436
e7cddda4 1437 spin_unlock_irqrestore(&udc->lock, flags);
1438
1439 /* unbind gadget driver */
e7cddda4 1440 udc->gadget.dev.driver = NULL;
1441 udc->driver = NULL;
1442
1443 return 0;
1444}
e7cddda4 1445
fb22cbac
NZ		 1446static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1447{
1448 u32 portsc;
1449
1450 portsc = readl(&udc->op_regs->portsc[0]);
1451 portsc |= mode << 16;
1452 writel(portsc, &udc->op_regs->portsc[0]);
1453}
1454
1455static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1456{
aac16b63 1457 struct mv_ep *mvep = container_of(ep, struct mv_ep, ep);
fb22cbac 1458 struct mv_req *req = container_of(_req, struct mv_req, req);
aac16b63 1459 struct mv_udc *udc;
fb22cbac
NZ		 1460 unsigned long flags;
1461
aac16b63
CX		 1462 udc = mvep->udc;
1463
fb22cbac
NZ		 1464 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1465
1466 spin_lock_irqsave(&udc->lock, flags);
1467 if (req->test_mode) {
1468 mv_set_ptc(udc, req->test_mode);
1469 req->test_mode = 0;
1470 }
1471 spin_unlock_irqrestore(&udc->lock, flags);
1472}
1473
e7cddda4 1474static int
1475udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1476{
1477 int retval = 0;
1478 struct mv_req *req;
1479 struct mv_ep *ep;
1480
1481 ep = &udc->eps[0];
1482 udc->ep0_dir = direction;
36616224 1483 udc->ep0_state = WAIT_FOR_OUT_STATUS;
e7cddda4 1484
1485 req = udc->status_req;
1486
1487 /* fill in the reqest structure */
1488 if (empty == false) {
1489 *((u16 *) req->req.buf) = cpu_to_le16(status);
1490 req->req.length = 2;
1491 } else
1492 req->req.length = 0;
1493
1494 req->ep = ep;
1495 req->req.status = -EINPROGRESS;
1496 req->req.actual = 0;
fb22cbac
NZ		 1497 if (udc->test_mode) {
1498 req->req.complete = prime_status_complete;
1499 req->test_mode = udc->test_mode;
1500 udc->test_mode = 0;
1501 } else
1502 req->req.complete = NULL;
e7cddda4 1503 req->dtd_count = 0;
1504
46e172df
NZ		 1505 if (req->req.dma == DMA_ADDR_INVALID) {
1506 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1507 req->req.buf, req->req.length,
1508 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1509 req->mapped = 1;
1510 }
1511
e7cddda4 1512 /* prime the data phase */
0344606b 1513 if (!req_to_dtd(req)) {
e7cddda4 1514 retval = queue_dtd(ep, req);
0344606b
NZ		 1515 if (retval) {
1516 dev_err(&udc->dev->dev,
1517 "Failed to queue dtd when prime status\n");
1518 goto out;
1519 }
1520 } else{ /* no mem */
e7cddda4 1521 retval = -ENOMEM;
0344606b
NZ		 1522 dev_err(&udc->dev->dev,
1523 "Failed to dma_pool_alloc when prime status\n");
e7cddda4 1524 goto out;
1525 }
1526
1527 list_add_tail(&req->queue, &ep->queue);
1528
1529 return 0;
1530out:
0344606b
NZ		 1531 if (req->mapped) {
1532 dma_unmap_single(ep->udc->gadget.dev.parent,
1533 req->req.dma, req->req.length,
1534 ((ep_dir(ep) == EP_DIR_IN) ?
1535 DMA_TO_DEVICE : DMA_FROM_DEVICE));
1536 req->req.dma = DMA_ADDR_INVALID;
1537 req->mapped = 0;
1538 }
1539
e7cddda4 1540 return retval;
1541}
1542
fb22cbac
NZ		 1543static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1544{
1545 if (index <= TEST_FORCE_EN) {
1546 udc->test_mode = index;
1547 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1548 ep0_stall(udc);
1549 } else
1550 dev_err(&udc->dev->dev,
1551 "This test mode(%d) is not supported\n", index);
1552}
1553
e7cddda4 1554static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1555{
1556 udc->dev_addr = (u8)setup->wValue;
1557
1558 /* update usb state */
1559 udc->usb_state = USB_STATE_ADDRESS;
1560
1561 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1562 ep0_stall(udc);
1563}
1564
1565static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1566 struct usb_ctrlrequest *setup)
1567{
431879a7 1568 u16 status = 0;
e7cddda4 1569 int retval;
1570
1571 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1572 != (USB_DIR_IN | USB_TYPE_STANDARD))
1573 return;
1574
1575 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1576 status = 1 << USB_DEVICE_SELF_POWERED;
1577 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1578 } else if ((setup->bRequestType & USB_RECIP_MASK)
1579 == USB_RECIP_INTERFACE) {
1580 /* get interface status */
1581 status = 0;
1582 } else if ((setup->bRequestType & USB_RECIP_MASK)
1583 == USB_RECIP_ENDPOINT) {
1584 u8 ep_num, direction;
1585
1586 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1587 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1588 ? EP_DIR_IN : EP_DIR_OUT;
1589 status = ep_is_stall(udc, ep_num, direction)
1590 << USB_ENDPOINT_HALT;
1591 }
1592
1593 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1594 if (retval)
1595 ep0_stall(udc);
36616224
NZ		 1596 else
1597 udc->ep0_state = DATA_STATE_XMIT;
e7cddda4 1598}
1599
1600static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1601{
1602 u8 ep_num;
1603 u8 direction;
1604 struct mv_ep *ep;
1605
1606 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1607 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1608 switch (setup->wValue) {
1609 case USB_DEVICE_REMOTE_WAKEUP:
1610 udc->remote_wakeup = 0;
1611 break;
e7cddda4 1612 default:
1613 goto out;
1614 }
1615 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1616 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1617 switch (setup->wValue) {
1618 case USB_ENDPOINT_HALT:
1619 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1620 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1621 ? EP_DIR_IN : EP_DIR_OUT;
1622 if (setup->wValue != 0 || setup->wLength != 0
1623 || ep_num > udc->max_eps)
1624 goto out;
1625 ep = &udc->eps[ep_num * 2 + direction];
1626 if (ep->wedge == 1)
1627 break;
1628 spin_unlock(&udc->lock);
1629 ep_set_stall(udc, ep_num, direction, 0);
1630 spin_lock(&udc->lock);
1631 break;
1632 default:
1633 goto out;
1634 }
1635 } else
1636 goto out;
1637
1638 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1639 ep0_stall(udc);
e7cddda4 1640out:
1641 return;
1642}
1643
1644static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1645{
1646 u8 ep_num;
1647 u8 direction;
1648
1649 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1650 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1651 switch (setup->wValue) {
1652 case USB_DEVICE_REMOTE_WAKEUP:
1653 udc->remote_wakeup = 1;
1654 break;
1655 case USB_DEVICE_TEST_MODE:
1656 if (setup->wIndex & 0xFF
fb22cbac
NZ		 1657 || udc->gadget.speed != USB_SPEED_HIGH)
1658 ep0_stall(udc);
1659
1660 if (udc->usb_state != USB_STATE_CONFIGURED
1661 && udc->usb_state != USB_STATE_ADDRESS
1662 && udc->usb_state != USB_STATE_DEFAULT)
1663 ep0_stall(udc);
1664
1665 mv_udc_testmode(udc, (setup->wIndex >> 8));
1666 goto out;
e7cddda4 1667 default:
1668 goto out;
1669 }
1670 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1671 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1672 switch (setup->wValue) {
1673 case USB_ENDPOINT_HALT:
1674 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1675 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1676 ? EP_DIR_IN : EP_DIR_OUT;
1677 if (setup->wValue != 0 || setup->wLength != 0
1678 || ep_num > udc->max_eps)
1679 goto out;
1680 spin_unlock(&udc->lock);
1681 ep_set_stall(udc, ep_num, direction, 1);
1682 spin_lock(&udc->lock);
1683 break;
1684 default:
1685 goto out;
1686 }
1687 } else
1688 goto out;
1689
1690 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1691 ep0_stall(udc);
1692out:
1693 return;
1694}
1695
1696static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1697 struct usb_ctrlrequest *setup)
1698{
1699 bool delegate = false;
1700
1701 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1702
1703 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1704 setup->bRequestType, setup->bRequest,
1705 setup->wValue, setup->wIndex, setup->wLength);
1706 /* We process some stardard setup requests here */
1707 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1708 switch (setup->bRequest) {
1709 case USB_REQ_GET_STATUS:
1710 ch9getstatus(udc, ep_num, setup);
1711 break;
1712
1713 case USB_REQ_SET_ADDRESS:
1714 ch9setaddress(udc, setup);
1715 break;
1716
1717 case USB_REQ_CLEAR_FEATURE:
1718 ch9clearfeature(udc, setup);
1719 break;
1720
1721 case USB_REQ_SET_FEATURE:
1722 ch9setfeature(udc, setup);
1723 break;
1724
1725 default:
1726 delegate = true;
1727 }
1728 } else
1729 delegate = true;
1730
1731 /* delegate USB standard requests to the gadget driver */
1732 if (delegate == true) {
1733 /* USB requests handled by gadget */
1734 if (setup->wLength) {
1735 /* DATA phase from gadget, STATUS phase from udc */
1736 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1737 ? EP_DIR_IN : EP_DIR_OUT;
1738 spin_unlock(&udc->lock);
1739 if (udc->driver->setup(&udc->gadget,
1740 &udc->local_setup_buff) < 0)
1741 ep0_stall(udc);
1742 spin_lock(&udc->lock);
1743 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1744 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1745 } else {
1746 /* no DATA phase, IN STATUS phase from gadget */
1747 udc->ep0_dir = EP_DIR_IN;
1748 spin_unlock(&udc->lock);
1749 if (udc->driver->setup(&udc->gadget,
1750 &udc->local_setup_buff) < 0)
1751 ep0_stall(udc);
1752 spin_lock(&udc->lock);
1753 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1754 }
1755 }
1756}
1757
1758/* complete DATA or STATUS phase of ep0 prime status phase if needed */
1759static void ep0_req_complete(struct mv_udc *udc,
1760 struct mv_ep *ep0, struct mv_req *req)
1761{
1762 u32 new_addr;
1763
1764 if (udc->usb_state == USB_STATE_ADDRESS) {
1765 /* set the new address */
1766 new_addr = (u32)udc->dev_addr;
1767 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1768 &udc->op_regs->deviceaddr);
1769 }
1770
1771 done(ep0, req, 0);
1772
1773 switch (udc->ep0_state) {
1774 case DATA_STATE_XMIT:
1775 /* receive status phase */
1776 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1777 ep0_stall(udc);
1778 break;
1779 case DATA_STATE_RECV:
1780 /* send status phase */
1781 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1782 ep0_stall(udc);
1783 break;
1784 case WAIT_FOR_OUT_STATUS:
1785 udc->ep0_state = WAIT_FOR_SETUP;
1786 break;
1787 case WAIT_FOR_SETUP:
1788 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1789 break;
1790 default:
1791 ep0_stall(udc);
1792 break;
1793 }
1794}
1795
1796static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1797{
1798 u32 temp;
1799 struct mv_dqh *dqh;
1800
1801 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1802
1803 /* Clear bit in ENDPTSETUPSTAT */
96c2bbb0 1804 writel((1 << ep_num), &udc->op_regs->epsetupstat);
e7cddda4 1805
1806 /* while a hazard exists when setup package arrives */
1807 do {
1808 /* Set Setup Tripwire */
1809 temp = readl(&udc->op_regs->usbcmd);
1810 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1811
1812 /* Copy the setup packet to local buffer */
1813 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1814 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1815
1816 /* Clear Setup Tripwire */
1817 temp = readl(&udc->op_regs->usbcmd);
1818 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1819}
1820
1821static void irq_process_tr_complete(struct mv_udc *udc)
1822{
1823 u32 tmp, bit_pos;
1824 int i, ep_num = 0, direction = 0;
1825 struct mv_ep *curr_ep;
1826 struct mv_req *curr_req, *temp_req;
1827 int status;
1828
1829 /*
1830 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1831 * because the setup packets are to be read ASAP
1832 */
1833
1834 /* Process all Setup packet received interrupts */
1835 tmp = readl(&udc->op_regs->epsetupstat);
1836
1837 if (tmp) {
1838 for (i = 0; i < udc->max_eps; i++) {
1839 if (tmp & (1 << i)) {
1840 get_setup_data(udc, i,
1841 (u8 *)(&udc->local_setup_buff));
1842 handle_setup_packet(udc, i,
1843 &udc->local_setup_buff);
1844 }
1845 }
1846 }
1847
1848 /* Don't clear the endpoint setup status register here.
1849 * It is cleared as a setup packet is read out of the buffer
1850 */
1851
1852 /* Process non-setup transaction complete interrupts */
1853 tmp = readl(&udc->op_regs->epcomplete);
1854
1855 if (!tmp)
1856 return;
1857
1858 writel(tmp, &udc->op_regs->epcomplete);
1859
1860 for (i = 0; i < udc->max_eps * 2; i++) {
1861 ep_num = i >> 1;
1862 direction = i % 2;
1863
1864 bit_pos = 1 << (ep_num + 16 * direction);
1865
1866 if (!(bit_pos & tmp))
1867 continue;
1868
1869 if (i == 1)
1870 curr_ep = &udc->eps[0];
1871 else
1872 curr_ep = &udc->eps[i];
1873 /* process the req queue until an uncomplete request */
1874 list_for_each_entry_safe(curr_req, temp_req,
1875 &curr_ep->queue, queue) {
1876 status = process_ep_req(udc, i, curr_req);
1877 if (status)
1878 break;
1879
1880 /* write back status to req */
1881 curr_req->req.status = status;
1882
1883 /* ep0 request completion */
1884 if (ep_num == 0) {
1885 ep0_req_complete(udc, curr_ep, curr_req);
1886 break;
1887 } else {
1888 done(curr_ep, curr_req, status);
1889 }
1890 }
1891 }
1892}
1893
1894void irq_process_reset(struct mv_udc *udc)
1895{
1896 u32 tmp;
1897 unsigned int loops;
1898
1899 udc->ep0_dir = EP_DIR_OUT;
1900 udc->ep0_state = WAIT_FOR_SETUP;
1901 udc->remote_wakeup = 0; /* default to 0 on reset */
1902
1903 /* The address bits are past bit 25-31. Set the address */
1904 tmp = readl(&udc->op_regs->deviceaddr);
1905 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1906 writel(tmp, &udc->op_regs->deviceaddr);
1907
1908 /* Clear all the setup token semaphores */
1909 tmp = readl(&udc->op_regs->epsetupstat);
1910 writel(tmp, &udc->op_regs->epsetupstat);
1911
1912 /* Clear all the endpoint complete status bits */
1913 tmp = readl(&udc->op_regs->epcomplete);
1914 writel(tmp, &udc->op_regs->epcomplete);
1915
1916 /* wait until all endptprime bits cleared */
1917 loops = LOOPS(PRIME_TIMEOUT);
1918 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1919 if (loops == 0) {
1920 dev_err(&udc->dev->dev,
1921 "Timeout for ENDPTPRIME = 0x%x\n",
1922 readl(&udc->op_regs->epprime));
1923 break;
1924 }
1925 loops--;
1926 udelay(LOOPS_USEC);
1927 }
1928
1929 /* Write 1s to the Flush register */
1930 writel((u32)~0, &udc->op_regs->epflush);
1931
1932 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1933 dev_info(&udc->dev->dev, "usb bus reset\n");
1934 udc->usb_state = USB_STATE_DEFAULT;
1935 /* reset all the queues, stop all USB activities */
1936 stop_activity(udc, udc->driver);
1937 } else {
1938 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1939 readl(&udc->op_regs->portsc));
1940
1941 /*
1942 * re-initialize
1943 * controller reset
1944 */
1945 udc_reset(udc);
1946
1947 /* reset all the queues, stop all USB activities */
1948 stop_activity(udc, udc->driver);
1949
1950 /* reset ep0 dQH and endptctrl */
1951 ep0_reset(udc);
1952
1953 /* enable interrupt and set controller to run state */
1954 udc_start(udc);
1955
1956 udc->usb_state = USB_STATE_ATTACHED;
1957 }
1958}
1959
1960static void handle_bus_resume(struct mv_udc *udc)
1961{
1962 udc->usb_state = udc->resume_state;
1963 udc->resume_state = 0;
1964
1965 /* report resume to the driver */
1966 if (udc->driver) {
1967 if (udc->driver->resume) {
1968 spin_unlock(&udc->lock);
1969 udc->driver->resume(&udc->gadget);
1970 spin_lock(&udc->lock);
1971 }
1972 }
1973}
1974
1975static void irq_process_suspend(struct mv_udc *udc)
1976{
1977 udc->resume_state = udc->usb_state;
1978 udc->usb_state = USB_STATE_SUSPENDED;
1979
1980 if (udc->driver->suspend) {
1981 spin_unlock(&udc->lock);
1982 udc->driver->suspend(&udc->gadget);
1983 spin_lock(&udc->lock);
1984 }
1985}
1986
1987static void irq_process_port_change(struct mv_udc *udc)
1988{
1989 u32 portsc;
1990
1991 portsc = readl(&udc->op_regs->portsc[0]);
1992 if (!(portsc & PORTSCX_PORT_RESET)) {
1993 /* Get the speed */
1994 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1995 switch (speed) {
1996 case PORTSCX_PORT_SPEED_HIGH:
1997 udc->gadget.speed = USB_SPEED_HIGH;
1998 break;
1999 case PORTSCX_PORT_SPEED_FULL:
2000 udc->gadget.speed = USB_SPEED_FULL;
2001 break;
2002 case PORTSCX_PORT_SPEED_LOW:
2003 udc->gadget.speed = USB_SPEED_LOW;
2004 break;
2005 default:
2006 udc->gadget.speed = USB_SPEED_UNKNOWN;
2007 break;
2008 }
2009 }
2010
2011 if (portsc & PORTSCX_PORT_SUSPEND) {
2012 udc->resume_state = udc->usb_state;
2013 udc->usb_state = USB_STATE_SUSPENDED;
2014 if (udc->driver->suspend) {
2015 spin_unlock(&udc->lock);
2016 udc->driver->suspend(&udc->gadget);
2017 spin_lock(&udc->lock);
2018 }
2019 }
2020
2021 if (!(portsc & PORTSCX_PORT_SUSPEND)
2022 && udc->usb_state == USB_STATE_SUSPENDED) {
2023 handle_bus_resume(udc);
2024 }
2025
2026 if (!udc->resume_state)
2027 udc->usb_state = USB_STATE_DEFAULT;
2028}
2029
2030static void irq_process_error(struct mv_udc *udc)
2031{
2032 /* Increment the error count */
2033 udc->errors++;
2034}
2035
2036static irqreturn_t mv_udc_irq(int irq, void *dev)
2037{
2038 struct mv_udc *udc = (struct mv_udc *)dev;
2039 u32 status, intr;
2040
309d6d2b
NZ		 2041 /* Disable ISR when stopped bit is set */
2042 if (udc->stopped)
2043 return IRQ_NONE;
2044
e7cddda4 2045 spin_lock(&udc->lock);
2046
2047 status = readl(&udc->op_regs->usbsts);
2048 intr = readl(&udc->op_regs->usbintr);
2049 status &= intr;
2050
2051 if (status == 0) {
2052 spin_unlock(&udc->lock);
2053 return IRQ_NONE;
2054 }
2055
25985edc 2056 /* Clear all the interrupts occurred */
e7cddda4 2057 writel(status, &udc->op_regs->usbsts);
2058
2059 if (status & USBSTS_ERR)
2060 irq_process_error(udc);
2061
2062 if (status & USBSTS_RESET)
2063 irq_process_reset(udc);
2064
2065 if (status & USBSTS_PORT_CHANGE)
2066 irq_process_port_change(udc);
2067
2068 if (status & USBSTS_INT)
2069 irq_process_tr_complete(udc);
2070
2071 if (status & USBSTS_SUSPEND)
2072 irq_process_suspend(udc);
2073
2074 spin_unlock(&udc->lock);
2075
2076 return IRQ_HANDLED;
2077}
2078
1aec033b
NZ		 2079static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2080{
2081 struct mv_udc *udc = (struct mv_udc *)dev;
2082
2083 /* polling VBUS and init phy may cause too much time*/
2084 if (udc->qwork)
2085 queue_work(udc->qwork, &udc->vbus_work);
2086
2087 return IRQ_HANDLED;
2088}
2089
2090static void mv_udc_vbus_work(struct work_struct *work)
2091{
2092 struct mv_udc *udc;
2093 unsigned int vbus;
2094
2095 udc = container_of(work, struct mv_udc, vbus_work);
2096 if (!udc->pdata->vbus)
2097 return;
2098
2099 vbus = udc->pdata->vbus->poll();
2100 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2101
2102 if (vbus == VBUS_HIGH)
2103 mv_udc_vbus_session(&udc->gadget, 1);
2104 else if (vbus == VBUS_LOW)
2105 mv_udc_vbus_session(&udc->gadget, 0);
2106}
2107
e7cddda4 2108/* release device structure */
2109static void gadget_release(struct device *_dev)
2110{
aac16b63
CX		 2111 struct mv_udc *udc;
2112
2113 udc = dev_get_drvdata(_dev);
e7cddda4 2114
2115 complete(udc->done);
e7cddda4 2116}
2117
fb4e98ab 2118static int mv_udc_remove(struct platform_device *dev)
e7cddda4 2119{
aac16b63 2120 struct mv_udc *udc;
dde34cc5 2121 int clk_i;
e7cddda4 2122
aac16b63
CX		 2123 udc = platform_get_drvdata(dev);
2124
0f91349b
SAS		 2125 usb_del_gadget_udc(&udc->gadget);
2126
1aec033b
NZ		 2127 if (udc->qwork) {
2128 flush_workqueue(udc->qwork);
2129 destroy_workqueue(udc->qwork);
2130 }
2131
487d54d1
NZ		 2132 /*
2133 * If we have transceiver inited,
2134 * then vbus irq will not be requested in udc driver.
2135 */
2136 if (udc->pdata && udc->pdata->vbus
ded017ee 2137 && udc->clock_gating && IS_ERR_OR_NULL(udc->transceiver))
1aec033b 2138 free_irq(udc->pdata->vbus->irq, &dev->dev);
e7cddda4 2139
2140 /* free memory allocated in probe */
2141 if (udc->dtd_pool)
2142 dma_pool_destroy(udc->dtd_pool);
2143
2144 if (udc->ep_dqh)
2145 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2146 udc->ep_dqh, udc->ep_dqh_dma);
2147
2148 kfree(udc->eps);
2149
2150 if (udc->irq)
2151 free_irq(udc->irq, &dev->dev);
2152
1aec033b
NZ		 2153 mv_udc_disable(udc);
2154
e7cddda4 2155 if (udc->cap_regs)
2156 iounmap(udc->cap_regs);
e7cddda4 2157
2158 if (udc->phy_regs)
5e6c86b0 2159 iounmap(udc->phy_regs);
e7cddda4 2160
2161 if (udc->status_req) {
2162 kfree(udc->status_req->req.buf);
2163 kfree(udc->status_req);
2164 }
2165
dde34cc5
NZ		 2166 for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
2167 clk_put(udc->clk[clk_i]);
2168
e7cddda4 2169 device_unregister(&udc->gadget.dev);
2170
2171 /* free dev, wait for the release() finished */
dde34cc5
NZ		 2172 wait_for_completion(udc->done);
2173 kfree(udc);
e7cddda4 2174
e7cddda4 2175 return 0;
2176}
2177
41ac7b3a 2178static int mv_udc_probe(struct platform_device *dev)
e7cddda4 2179{
dde34cc5 2180 struct mv_usb_platform_data *pdata = dev->dev.platform_data;
e7cddda4 2181 struct mv_udc *udc;
2182 int retval = 0;
dde34cc5 2183 int clk_i = 0;
e7cddda4 2184 struct resource *r;
2185 size_t size;
2186
dde34cc5
NZ		 2187 if (pdata == NULL) {
2188 dev_err(&dev->dev, "missing platform_data\n");
2189 return -ENODEV;
2190 }
2191
2192 size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2193 udc = kzalloc(size, GFP_KERNEL);
e7cddda4 2194 if (udc == NULL) {
2195 dev_err(&dev->dev, "failed to allocate memory for udc\n");
dde34cc5 2196 return -ENOMEM;
e7cddda4 2197 }
2198
dde34cc5
NZ		 2199 udc->done = &release_done;
2200 udc->pdata = dev->dev.platform_data;
e7cddda4 2201 spin_lock_init(&udc->lock);
2202
2203 udc->dev = dev;
2204
487d54d1
NZ		 2205#ifdef CONFIG_USB_OTG_UTILS
2206 if (pdata->mode == MV_USB_MODE_OTG)
662dca54 2207 udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
487d54d1
NZ		 2208#endif
2209
dde34cc5
NZ		 2210 udc->clknum = pdata->clknum;
2211 for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2212 udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
2213 if (IS_ERR(udc->clk[clk_i])) {
2214 retval = PTR_ERR(udc->clk[clk_i]);
2215 goto err_put_clk;
2216 }
e7cddda4 2217 }
2218
dde34cc5 2219 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
e7cddda4 2220 if (r == NULL) {
2221 dev_err(&dev->dev, "no I/O memory resource defined\n");
2222 retval = -ENODEV;
dde34cc5 2223 goto err_put_clk;
e7cddda4 2224 }
2225
2226 udc->cap_regs = (struct mv_cap_regs __iomem *)
2227 ioremap(r->start, resource_size(r));
2228 if (udc->cap_regs == NULL) {
2229 dev_err(&dev->dev, "failed to map I/O memory\n");
2230 retval = -EBUSY;
dde34cc5 2231 goto err_put_clk;
e7cddda4 2232 }
2233
dde34cc5 2234 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
e7cddda4 2235 if (r == NULL) {
2236 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
2237 retval = -ENODEV;
dde34cc5 2238 goto err_iounmap_capreg;
e7cddda4 2239 }
2240
5e6c86b0
NZ		 2241 udc->phy_regs = ioremap(r->start, resource_size(r));
2242 if (udc->phy_regs == NULL) {
e7cddda4 2243 dev_err(&dev->dev, "failed to map phy I/O memory\n");
2244 retval = -EBUSY;
dde34cc5 2245 goto err_iounmap_capreg;
e7cddda4 2246 }
2247
2248 /* we will acces controller register, so enable the clk */
85ff7bfb
NZ		 2249 retval = mv_udc_enable_internal(udc);
2250 if (retval)
2251 goto err_iounmap_phyreg;
e7cddda4 2252
5e6c86b0
NZ		 2253 udc->op_regs =
2254 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
e7cddda4 2255 + (readl(&udc->cap_regs->caplength_hciversion)
2256 & CAPLENGTH_MASK));
2257 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2258
4540a9ab
NZ		 2259 /*
2260 * some platform will use usb to download image, it may not disconnect
2261 * usb gadget before loading kernel. So first stop udc here.
2262 */
2263 udc_stop(udc);
2264 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2265
e7cddda4 2266 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2267 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2268 udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
2269 &udc->ep_dqh_dma, GFP_KERNEL);
2270
2271 if (udc->ep_dqh == NULL) {
2272 dev_err(&dev->dev, "allocate dQH memory failed\n");
2273 retval = -ENOMEM;
dde34cc5 2274 goto err_disable_clock;
e7cddda4 2275 }
2276 udc->ep_dqh_size = size;
2277
2278 /* create dTD dma_pool resource */
2279 udc->dtd_pool = dma_pool_create("mv_dtd",
2280 &dev->dev,
2281 sizeof(struct mv_dtd),
2282 DTD_ALIGNMENT,
2283 DMA_BOUNDARY);
2284
2285 if (!udc->dtd_pool) {
2286 retval = -ENOMEM;
dde34cc5 2287 goto err_free_dma;
e7cddda4 2288 }
2289
2290 size = udc->max_eps * sizeof(struct mv_ep) *2;
2291 udc->eps = kzalloc(size, GFP_KERNEL);
2292 if (udc->eps == NULL) {
2293 dev_err(&dev->dev, "allocate ep memory failed\n");
2294 retval = -ENOMEM;
dde34cc5 2295 goto err_destroy_dma;
e7cddda4 2296 }
2297
2298 /* initialize ep0 status request structure */
2299 udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2300 if (!udc->status_req) {
2301 dev_err(&dev->dev, "allocate status_req memory failed\n");
2302 retval = -ENOMEM;
dde34cc5 2303 goto err_free_eps;
e7cddda4 2304 }
2305 INIT_LIST_HEAD(&udc->status_req->queue);
2306
2307 /* allocate a small amount of memory to get valid address */
2308 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
46e172df 2309 udc->status_req->req.dma = DMA_ADDR_INVALID;
e7cddda4 2310
2311 udc->resume_state = USB_STATE_NOTATTACHED;
2312 udc->usb_state = USB_STATE_POWERED;
2313 udc->ep0_dir = EP_DIR_OUT;
2314 udc->remote_wakeup = 0;
2315
2316 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2317 if (r == NULL) {
2318 dev_err(&dev->dev, "no IRQ resource defined\n");
2319 retval = -ENODEV;
dde34cc5 2320 goto err_free_status_req;
e7cddda4 2321 }
2322 udc->irq = r->start;
2323 if (request_irq(udc->irq, mv_udc_irq,
b5dd18d8 2324 IRQF_SHARED, driver_name, udc)) {
e7cddda4 2325 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2326 udc->irq);
2327 retval = -ENODEV;
dde34cc5 2328 goto err_free_status_req;
e7cddda4 2329 }
2330
2331 /* initialize gadget structure */
2332 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2333 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2334 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2335 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
d327ab5b 2336 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
e7cddda4 2337
2338 /* the "gadget" abstracts/virtualizes the controller */
2339 dev_set_name(&udc->gadget.dev, "gadget");
2340 udc->gadget.dev.parent = &dev->dev;
2341 udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2342 udc->gadget.dev.release = gadget_release;
2343 udc->gadget.name = driver_name; /* gadget name */
2344
2345 retval = device_register(&udc->gadget.dev);
2346 if (retval)
dde34cc5 2347 goto err_free_irq;
e7cddda4 2348
2349 eps_init(udc);
2350
1aec033b 2351 /* VBUS detect: we can disable/enable clock on demand.*/
ded017ee 2352 if (!IS_ERR_OR_NULL(udc->transceiver))
487d54d1
NZ		 2353 udc->clock_gating = 1;
2354 else if (pdata->vbus) {
1aec033b
NZ		 2355 udc->clock_gating = 1;
2356 retval = request_threaded_irq(pdata->vbus->irq, NULL,
2357 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2358 if (retval) {
2359 dev_info(&dev->dev,
2360 "Can not request irq for VBUS, "
2361 "disable clock gating\n");
2362 udc->clock_gating = 0;
2363 }
2364
2365 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2366 if (!udc->qwork) {
2367 dev_err(&dev->dev, "cannot create workqueue\n");
2368 retval = -ENOMEM;
2369 goto err_unregister;
2370 }
2371
2372 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2373 }
2374
2375 /*
2376 * When clock gating is supported, we can disable clk and phy.
2377 * If not, it means that VBUS detection is not supported, we
2378 * have to enable vbus active all the time to let controller work.
2379 */
85ff7bfb
NZ		 2380 if (udc->clock_gating)
2381 mv_udc_disable_internal(udc);
2382 else
1aec033b 2383 udc->vbus_active = 1;
e7cddda4 2384
0f91349b 2385 retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
dde34cc5
NZ		 2386 if (retval)
2387 goto err_unregister;
2388
aac16b63 2389 platform_set_drvdata(dev, udc);
1aec033b
NZ		 2390 dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n",
2391 udc->clock_gating ? "with" : "without");
2392
dde34cc5
NZ		 2393 return 0;
2394
2395err_unregister:
487d54d1 2396 if (udc->pdata && udc->pdata->vbus
ded017ee 2397 && udc->clock_gating && IS_ERR_OR_NULL(udc->transceiver))
1aec033b 2398 free_irq(pdata->vbus->irq, &dev->dev);
dde34cc5
NZ		 2399 device_unregister(&udc->gadget.dev);
2400err_free_irq:
2401 free_irq(udc->irq, &dev->dev);
2402err_free_status_req:
2403 kfree(udc->status_req->req.buf);
2404 kfree(udc->status_req);
2405err_free_eps:
2406 kfree(udc->eps);
2407err_destroy_dma:
2408 dma_pool_destroy(udc->dtd_pool);
2409err_free_dma:
2410 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2411 udc->ep_dqh, udc->ep_dqh_dma);
2412err_disable_clock:
85ff7bfb 2413 mv_udc_disable_internal(udc);
dde34cc5 2414err_iounmap_phyreg:
5e6c86b0 2415 iounmap(udc->phy_regs);
dde34cc5
NZ		 2416err_iounmap_capreg:
2417 iounmap(udc->cap_regs);
2418err_put_clk:
2419 for (clk_i--; clk_i >= 0; clk_i--)
2420 clk_put(udc->clk[clk_i]);
dde34cc5 2421 kfree(udc);
e7cddda4 2422 return retval;
2423}
2424
2425#ifdef CONFIG_PM
aac16b63 2426static int mv_udc_suspend(struct device *dev)
e7cddda4 2427{
aac16b63
CX		 2428 struct mv_udc *udc;
2429
2430 udc = dev_get_drvdata(dev);
e7cddda4 2431
5076ae55 2432 /* if OTG is enabled, the following will be done in OTG driver*/
ded017ee 2433 if (!IS_ERR_OR_NULL(udc->transceiver))
5076ae55
NZ		 2434 return 0;
2435
2436 if (udc->pdata->vbus && udc->pdata->vbus->poll)
2437 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2438 dev_info(&udc->dev->dev, "USB cable is connected!\n");
2439 return -EAGAIN;
2440 }
2441
2442 /*
2443 * only cable is unplugged, udc can suspend.
2444 * So do not care about clock_gating == 1.
2445 */
2446 if (!udc->clock_gating) {
2447 udc_stop(udc);
2448
2449 spin_lock_irq(&udc->lock);
2450 /* stop all usb activities */
2451 stop_activity(udc, udc->driver);
2452 spin_unlock_irq(&udc->lock);
2453
2454 mv_udc_disable_internal(udc);
2455 }
e7cddda4 2456
2457 return 0;
2458}
2459
aac16b63 2460static int mv_udc_resume(struct device *dev)
e7cddda4 2461{
aac16b63 2462 struct mv_udc *udc;
e7cddda4 2463 int retval;
2464
aac16b63
CX		 2465 udc = dev_get_drvdata(dev);
2466
5076ae55 2467 /* if OTG is enabled, the following will be done in OTG driver*/
ded017ee 2468 if (!IS_ERR_OR_NULL(udc->transceiver))
5076ae55
NZ		 2469 return 0;
2470
2471 if (!udc->clock_gating) {
2472 retval = mv_udc_enable_internal(udc);
2473 if (retval)
dde34cc5 2474 return retval;
5076ae55
NZ		 2475
2476 if (udc->driver && udc->softconnect) {
2477 udc_reset(udc);
2478 ep0_reset(udc);
2479 udc_start(udc);
dde34cc5 2480 }
e7cddda4 2481 }
dde34cc5 2482
e7cddda4 2483 return 0;
2484}
2485
2486static const struct dev_pm_ops mv_udc_pm_ops = {
2487 .suspend = mv_udc_suspend,
2488 .resume = mv_udc_resume,
2489};
2490#endif
2491
046b07ac
NZ		 2492static void mv_udc_shutdown(struct platform_device *dev)
2493{
aac16b63 2494 struct mv_udc *udc;
046b07ac
NZ		 2495 u32 mode;
2496
aac16b63 2497 udc = platform_get_drvdata(dev);
046b07ac 2498 /* reset controller mode to IDLE */
1dcaa252 2499 mv_udc_enable(udc);
046b07ac
NZ		 2500 mode = readl(&udc->op_regs->usbmode);
2501 mode &= ~3;
2502 writel(mode, &udc->op_regs->usbmode);
1dcaa252 2503 mv_udc_disable(udc);
046b07ac
NZ		 2504}
2505
e7cddda4 2506static struct platform_driver udc_driver = {
2507 .probe = mv_udc_probe,
2508 .remove = __exit_p(mv_udc_remove),
046b07ac 2509 .shutdown = mv_udc_shutdown,
e7cddda4 2510 .driver = {
2511 .owner = THIS_MODULE,
5e6c86b0 2512 .name = "mv-udc",
e7cddda4 2513#ifdef CONFIG_PM
cb424473 2514 .pm = &mv_udc_pm_ops,
e7cddda4 2515#endif
2516 },
2517};
cc27c96c
AL		 2518
2519module_platform_driver(udc_driver);
ee0db58a 2520MODULE_ALIAS("platform:mv-udc");
e7cddda4 2521MODULE_DESCRIPTION(DRIVER_DESC);
2522MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2523MODULE_VERSION(DRIVER_VERSION);
2524MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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