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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/config.h> | |
20 | ||
21 | #ifdef CONFIG_USB_DEBUG | |
22 | #define DEBUG | |
23 | #else | |
24 | #undef DEBUG | |
25 | #endif | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/dmapool.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/smp_lock.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/list.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/reboot.h> | |
42 | #include <linux/usb.h> | |
43 | #include <linux/moduleparam.h> | |
44 | #include <linux/dma-mapping.h> | |
45 | ||
46 | #include "../core/hcd.h" | |
47 | ||
48 | #include <asm/byteorder.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/irq.h> | |
51 | #include <asm/system.h> | |
52 | #include <asm/unaligned.h> | |
53 | ||
54 | ||
55 | /*-------------------------------------------------------------------------*/ | |
56 | ||
57 | /* | |
58 | * EHCI hc_driver implementation ... experimental, incomplete. | |
59 | * Based on the final 1.0 register interface specification. | |
60 | * | |
61 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
62 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
63 | * Next comes "CardBay", using USB 2.0 signals. | |
64 | * | |
65 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
66 | * Special thanks to Intel and VIA for providing host controllers to | |
67 | * test this driver on, and Cypress (including In-System Design) for | |
68 | * providing early devices for those host controllers to talk to! | |
69 | * | |
70 | * HISTORY: | |
71 | * | |
72 | * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db) | |
73 | * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net) | |
74 | * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka, | |
75 | * <sojkam@centrum.cz>, updates by DB). | |
76 | * | |
77 | * 2002-11-29 Correct handling for hw async_next register. | |
78 | * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared; | |
79 | * only scheduling is different, no arbitrary limitations. | |
80 | * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support, | |
81 | * clean up HC run state handshaking. | |
82 | * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts | |
83 | * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other | |
84 | * missing pieces: enabling 64bit dma, handoff from BIOS/SMM. | |
85 | * 2002-05-07 Some error path cleanups to report better errors; wmb(); | |
86 | * use non-CVS version id; better iso bandwidth claim. | |
87 | * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on | |
88 | * errors in submit path. Bugfixes to interrupt scheduling/processing. | |
89 | * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift | |
90 | * more checking to generic hcd framework (db). Make it work with | |
91 | * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt). | |
92 | * 2002-01-14 Minor cleanup; version synch. | |
93 | * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers. | |
94 | * 2002-01-04 Control/Bulk queuing behaves. | |
95 | * | |
96 | * 2001-12-12 Initial patch version for Linux 2.5.1 kernel. | |
97 | * 2001-June Works with usb-storage and NEC EHCI on 2.4 | |
98 | */ | |
99 | ||
100 | #define DRIVER_VERSION "10 Dec 2004" | |
101 | #define DRIVER_AUTHOR "David Brownell" | |
102 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
103 | ||
104 | static const char hcd_name [] = "ehci_hcd"; | |
105 | ||
106 | ||
107 | #undef EHCI_VERBOSE_DEBUG | |
108 | #undef EHCI_URB_TRACE | |
109 | ||
110 | #ifdef DEBUG | |
111 | #define EHCI_STATS | |
112 | #endif | |
113 | ||
114 | /* magic numbers that can affect system performance */ | |
115 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
116 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
117 | #define EHCI_TUNE_RL_TT 0 | |
118 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
119 | #define EHCI_TUNE_MULT_TT 1 | |
120 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
121 | ||
122 | #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */ | |
123 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ | |
124 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
125 | #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ | |
126 | ||
127 | /* Initial IRQ latency: faster than hw default */ | |
128 | static int log2_irq_thresh = 0; // 0 to 6 | |
129 | module_param (log2_irq_thresh, int, S_IRUGO); | |
130 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
131 | ||
132 | /* initial park setting: slower than hw default */ | |
133 | static unsigned park = 0; | |
134 | module_param (park, uint, S_IRUGO); | |
135 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
136 | ||
137 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) | |
138 | ||
139 | /*-------------------------------------------------------------------------*/ | |
140 | ||
141 | #include "ehci.h" | |
142 | #include "ehci-dbg.c" | |
143 | ||
144 | /*-------------------------------------------------------------------------*/ | |
145 | ||
146 | /* | |
147 | * handshake - spin reading hc until handshake completes or fails | |
148 | * @ptr: address of hc register to be read | |
149 | * @mask: bits to look at in result of read | |
150 | * @done: value of those bits when handshake succeeds | |
151 | * @usec: timeout in microseconds | |
152 | * | |
153 | * Returns negative errno, or zero on success | |
154 | * | |
155 | * Success happens when the "mask" bits have the specified value (hardware | |
156 | * handshake done). There are two failure modes: "usec" have passed (major | |
157 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
158 | * | |
159 | * That last failure should_only happen in cases like physical cardbus eject | |
160 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
161 | * bridge shutdown: shutting down the bridge before the devices using it. | |
162 | */ | |
163 | static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec) | |
164 | { | |
165 | u32 result; | |
166 | ||
167 | do { | |
168 | result = readl (ptr); | |
169 | if (result == ~(u32)0) /* card removed */ | |
170 | return -ENODEV; | |
171 | result &= mask; | |
172 | if (result == done) | |
173 | return 0; | |
174 | udelay (1); | |
175 | usec--; | |
176 | } while (usec > 0); | |
177 | return -ETIMEDOUT; | |
178 | } | |
179 | ||
180 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ | |
181 | static int ehci_halt (struct ehci_hcd *ehci) | |
182 | { | |
183 | u32 temp = readl (&ehci->regs->status); | |
184 | ||
185 | if ((temp & STS_HALT) != 0) | |
186 | return 0; | |
187 | ||
188 | temp = readl (&ehci->regs->command); | |
189 | temp &= ~CMD_RUN; | |
190 | writel (temp, &ehci->regs->command); | |
191 | return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125); | |
192 | } | |
193 | ||
194 | /* put TDI/ARC silicon into EHCI mode */ | |
195 | static void tdi_reset (struct ehci_hcd *ehci) | |
196 | { | |
197 | u32 __iomem *reg_ptr; | |
198 | u32 tmp; | |
199 | ||
200 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68); | |
201 | tmp = readl (reg_ptr); | |
202 | tmp |= 0x3; | |
203 | writel (tmp, reg_ptr); | |
204 | } | |
205 | ||
206 | /* reset a non-running (STS_HALT == 1) controller */ | |
207 | static int ehci_reset (struct ehci_hcd *ehci) | |
208 | { | |
209 | int retval; | |
210 | u32 command = readl (&ehci->regs->command); | |
211 | ||
212 | command |= CMD_RESET; | |
213 | dbg_cmd (ehci, "reset", command); | |
214 | writel (command, &ehci->regs->command); | |
215 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
216 | ehci->next_statechange = jiffies; | |
217 | retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000); | |
218 | ||
219 | if (retval) | |
220 | return retval; | |
221 | ||
222 | if (ehci_is_TDI(ehci)) | |
223 | tdi_reset (ehci); | |
224 | ||
225 | return retval; | |
226 | } | |
227 | ||
228 | /* idle the controller (from running) */ | |
229 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
230 | { | |
231 | u32 temp; | |
232 | ||
233 | #ifdef DEBUG | |
234 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
235 | BUG (); | |
236 | #endif | |
237 | ||
238 | /* wait for any schedule enables/disables to take effect */ | |
239 | temp = readl (&ehci->regs->command) << 10; | |
240 | temp &= STS_ASS | STS_PSS; | |
241 | if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, | |
242 | temp, 16 * 125) != 0) { | |
243 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
244 | return; | |
245 | } | |
246 | ||
247 | /* then disable anything that's still active */ | |
248 | temp = readl (&ehci->regs->command); | |
249 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); | |
250 | writel (temp, &ehci->regs->command); | |
251 | ||
252 | /* hardware can take 16 microframes to turn off ... */ | |
253 | if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, | |
254 | 0, 16 * 125) != 0) { | |
255 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
256 | return; | |
257 | } | |
258 | } | |
259 | ||
260 | /*-------------------------------------------------------------------------*/ | |
261 | ||
262 | static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs); | |
263 | ||
264 | #include "ehci-hub.c" | |
265 | #include "ehci-mem.c" | |
266 | #include "ehci-q.c" | |
267 | #include "ehci-sched.c" | |
268 | ||
269 | /*-------------------------------------------------------------------------*/ | |
270 | ||
271 | static void ehci_watchdog (unsigned long param) | |
272 | { | |
273 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
274 | unsigned long flags; | |
275 | ||
276 | spin_lock_irqsave (&ehci->lock, flags); | |
277 | ||
278 | /* lost IAA irqs wedge things badly; seen with a vt8235 */ | |
279 | if (ehci->reclaim) { | |
280 | u32 status = readl (&ehci->regs->status); | |
281 | ||
282 | if (status & STS_IAA) { | |
283 | ehci_vdbg (ehci, "lost IAA\n"); | |
284 | COUNT (ehci->stats.lost_iaa); | |
285 | writel (STS_IAA, &ehci->regs->status); | |
286 | ehci->reclaim_ready = 1; | |
287 | } | |
288 | } | |
289 | ||
290 | /* stop async processing after it's idled a bit */ | |
291 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) | |
292 | start_unlink_async (ehci, ehci->async); | |
293 | ||
294 | /* ehci could run by timer, without IRQs ... */ | |
295 | ehci_work (ehci, NULL); | |
296 | ||
297 | spin_unlock_irqrestore (&ehci->lock, flags); | |
298 | } | |
299 | ||
300 | #ifdef CONFIG_PCI | |
301 | ||
302 | /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/... | |
303 | * off the controller (maybe it can boot from highspeed USB disks). | |
304 | */ | |
305 | static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap) | |
306 | { | |
d49d4317 DB |
307 | struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller); |
308 | ||
309 | /* always say Linux will own the hardware */ | |
310 | pci_write_config_byte(pdev, where + 3, 1); | |
311 | ||
312 | /* maybe wait a while for BIOS to respond */ | |
1da177e4 LT |
313 | if (cap & (1 << 16)) { |
314 | int msec = 5000; | |
1da177e4 | 315 | |
1da177e4 LT |
316 | do { |
317 | msleep(10); | |
318 | msec -= 10; | |
319 | pci_read_config_dword(pdev, where, &cap); | |
320 | } while ((cap & (1 << 16)) && msec); | |
321 | if (cap & (1 << 16)) { | |
d49d4317 | 322 | ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n", |
1da177e4 LT |
323 | where, cap); |
324 | // some BIOS versions seem buggy... | |
325 | // return 1; | |
326 | ehci_warn (ehci, "continuing after BIOS bug...\n"); | |
d49d4317 DB |
327 | /* disable all SMIs, and clear "BIOS owns" flag */ |
328 | pci_write_config_dword(pdev, where + 4, 0); | |
329 | pci_write_config_byte(pdev, where + 2, 0); | |
330 | } else | |
331 | ehci_dbg(ehci, "BIOS handoff succeeded\n"); | |
1da177e4 LT |
332 | } |
333 | return 0; | |
334 | } | |
335 | ||
336 | #endif | |
337 | ||
338 | static int | |
339 | ehci_reboot (struct notifier_block *self, unsigned long code, void *null) | |
340 | { | |
341 | struct ehci_hcd *ehci; | |
342 | ||
343 | ehci = container_of (self, struct ehci_hcd, reboot_notifier); | |
344 | ||
345 | /* make BIOS/etc use companion controller during reboot */ | |
346 | writel (0, &ehci->regs->configured_flag); | |
347 | return 0; | |
348 | } | |
349 | ||
56c1e26d DB |
350 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
351 | { | |
352 | unsigned port; | |
353 | ||
354 | if (!HCS_PPC (ehci->hcs_params)) | |
355 | return; | |
356 | ||
357 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
358 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
359 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
360 | is_on ? SetPortFeature : ClearPortFeature, | |
361 | USB_PORT_FEAT_POWER, | |
362 | port--, NULL, 0); | |
363 | msleep(20); | |
364 | } | |
365 | ||
1da177e4 LT |
366 | |
367 | /* called by khubd or root hub init threads */ | |
368 | ||
369 | static int ehci_hc_reset (struct usb_hcd *hcd) | |
370 | { | |
371 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
372 | u32 temp; | |
373 | unsigned count = 256/4; | |
374 | ||
375 | spin_lock_init (&ehci->lock); | |
376 | ||
377 | ehci->caps = hcd->regs; | |
378 | ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase)); | |
379 | dbg_hcs_params (ehci, "reset"); | |
380 | dbg_hcc_params (ehci, "reset"); | |
381 | ||
56c1e26d DB |
382 | /* cache this readonly data; minimize chip reads */ |
383 | ehci->hcs_params = readl (&ehci->caps->hcs_params); | |
384 | ||
1da177e4 | 385 | #ifdef CONFIG_PCI |
1da177e4 LT |
386 | if (hcd->self.controller->bus == &pci_bus_type) { |
387 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
388 | ||
389 | switch (pdev->vendor) { | |
390 | case PCI_VENDOR_ID_TDI: | |
391 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | |
392 | ehci->is_tdi_rh_tt = 1; | |
393 | tdi_reset (ehci); | |
394 | } | |
395 | break; | |
396 | case PCI_VENDOR_ID_AMD: | |
397 | /* AMD8111 EHCI doesn't work, according to AMD errata */ | |
398 | if (pdev->device == 0x7463) { | |
399 | ehci_info (ehci, "ignoring AMD8111 (errata)\n"); | |
400 | return -EIO; | |
401 | } | |
402 | break; | |
f7201c3d DB |
403 | case PCI_VENDOR_ID_NVIDIA: |
404 | /* NVidia reports that certain chips don't handle | |
405 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
406 | * data buffer, and periodic schedule are normal.) | |
407 | */ | |
408 | switch (pdev->device) { | |
409 | case 0x003c: /* MCP04 */ | |
410 | case 0x005b: /* CK804 */ | |
411 | case 0x00d8: /* CK8 */ | |
412 | case 0x00e8: /* CK8S */ | |
413 | if (pci_set_consistent_dma_mask(pdev, | |
414 | DMA_31BIT_MASK) < 0) | |
415 | ehci_warn (ehci, "can't enable NVidia " | |
416 | "workaround for >2GB RAM\n"); | |
417 | break; | |
418 | } | |
419 | break; | |
1da177e4 LT |
420 | } |
421 | ||
56c1e26d DB |
422 | /* optional debug port, normally in the first BAR */ |
423 | temp = pci_find_capability (pdev, 0x0a); | |
424 | if (temp) { | |
425 | pci_read_config_dword(pdev, temp, &temp); | |
426 | temp >>= 16; | |
427 | if ((temp & (3 << 13)) == (1 << 13)) { | |
428 | temp &= 0x1fff; | |
429 | ehci->debug = hcd->regs + temp; | |
430 | temp = readl (&ehci->debug->control); | |
431 | ehci_info (ehci, "debug port %d%s\n", | |
432 | HCS_DEBUG_PORT(ehci->hcs_params), | |
433 | (temp & DBGP_ENABLED) | |
434 | ? " IN USE" | |
435 | : ""); | |
436 | if (!(temp & DBGP_ENABLED)) | |
437 | ehci->debug = NULL; | |
438 | } | |
439 | } | |
440 | ||
1da177e4 LT |
441 | temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params)); |
442 | } else | |
443 | temp = 0; | |
56c1e26d DB |
444 | |
445 | /* EHCI 0.96 and later may have "extended capabilities" */ | |
1da177e4 LT |
446 | while (temp && count--) { |
447 | u32 cap; | |
448 | ||
449 | pci_read_config_dword (to_pci_dev(hcd->self.controller), | |
450 | temp, &cap); | |
451 | ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp); | |
452 | switch (cap & 0xff) { | |
453 | case 1: /* BIOS/SMM/... handoff */ | |
454 | if (bios_handoff (ehci, temp, cap) != 0) | |
455 | return -EOPNOTSUPP; | |
456 | break; | |
457 | case 0: /* illegal reserved capability */ | |
458 | ehci_warn (ehci, "illegal capability!\n"); | |
459 | cap = 0; | |
460 | /* FALLTHROUGH */ | |
461 | default: /* unknown */ | |
462 | break; | |
463 | } | |
464 | temp = (cap >> 8) & 0xff; | |
465 | } | |
466 | if (!count) { | |
467 | ehci_err (ehci, "bogus capabilities ... PCI problems!\n"); | |
468 | return -EIO; | |
469 | } | |
470 | if (ehci_is_TDI(ehci)) | |
471 | ehci_reset (ehci); | |
472 | #endif | |
473 | ||
56c1e26d | 474 | ehci_port_power (ehci, 0); |
1da177e4 LT |
475 | |
476 | /* at least the Genesys GL880S needs fixup here */ | |
477 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
478 | temp &= 0x0f; | |
479 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
480 | ehci_dbg (ehci, "bogus port configuration: " | |
481 | "cc=%d x pcc=%d < ports=%d\n", | |
482 | HCS_N_CC(ehci->hcs_params), | |
483 | HCS_N_PCC(ehci->hcs_params), | |
484 | HCS_N_PORTS(ehci->hcs_params)); | |
485 | ||
486 | #ifdef CONFIG_PCI | |
487 | if (hcd->self.controller->bus == &pci_bus_type) { | |
488 | struct pci_dev *pdev; | |
489 | ||
490 | pdev = to_pci_dev(hcd->self.controller); | |
491 | switch (pdev->vendor) { | |
492 | case 0x17a0: /* GENESYS */ | |
493 | /* GL880S: should be PORTS=2 */ | |
494 | temp |= (ehci->hcs_params & ~0xf); | |
495 | ehci->hcs_params = temp; | |
496 | break; | |
497 | case PCI_VENDOR_ID_NVIDIA: | |
498 | /* NF4: should be PCC=10 */ | |
499 | break; | |
500 | } | |
501 | } | |
502 | #endif | |
503 | } | |
504 | ||
505 | /* force HC to halt state */ | |
506 | return ehci_halt (ehci); | |
507 | } | |
508 | ||
509 | static int ehci_start (struct usb_hcd *hcd) | |
510 | { | |
511 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
512 | u32 temp; | |
1da177e4 LT |
513 | int retval; |
514 | u32 hcc_params; | |
515 | u8 sbrn = 0; | |
516 | int first; | |
517 | ||
518 | /* skip some things on restart paths */ | |
519 | first = (ehci->watchdog.data == 0); | |
520 | if (first) { | |
521 | init_timer (&ehci->watchdog); | |
522 | ehci->watchdog.function = ehci_watchdog; | |
523 | ehci->watchdog.data = (unsigned long) ehci; | |
524 | } | |
525 | ||
526 | /* | |
527 | * hw default: 1K periodic list heads, one per frame. | |
528 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
529 | */ | |
530 | ehci->periodic_size = DEFAULT_I_TDPS; | |
531 | if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0) | |
532 | return retval; | |
533 | ||
534 | /* controllers may cache some of the periodic schedule ... */ | |
535 | hcc_params = readl (&ehci->caps->hcc_params); | |
536 | if (HCC_ISOC_CACHE (hcc_params)) // full frame cache | |
537 | ehci->i_thresh = 8; | |
538 | else // N microframes cached | |
539 | ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params); | |
540 | ||
541 | ehci->reclaim = NULL; | |
542 | ehci->reclaim_ready = 0; | |
543 | ehci->next_uframe = -1; | |
544 | ||
545 | /* controller state: unknown --> reset */ | |
546 | ||
547 | /* EHCI spec section 4.1 */ | |
548 | if ((retval = ehci_reset (ehci)) != 0) { | |
549 | ehci_mem_cleanup (ehci); | |
550 | return retval; | |
551 | } | |
552 | writel (ehci->periodic_dma, &ehci->regs->frame_list); | |
553 | ||
554 | #ifdef CONFIG_PCI | |
555 | if (hcd->self.controller->bus == &pci_bus_type) { | |
556 | struct pci_dev *pdev; | |
557 | u16 port_wake; | |
558 | ||
559 | pdev = to_pci_dev(hcd->self.controller); | |
560 | ||
561 | /* Serial Bus Release Number is at PCI 0x60 offset */ | |
562 | pci_read_config_byte(pdev, 0x60, &sbrn); | |
563 | ||
564 | /* port wake capability, reported by boot firmware */ | |
565 | pci_read_config_word(pdev, 0x62, &port_wake); | |
566 | hcd->can_wakeup = (port_wake & 1) != 0; | |
567 | ||
568 | /* help hc dma work well with cachelines */ | |
95a62965 GKH |
569 | retval = pci_set_mwi(pdev); |
570 | if (retval) | |
571 | ehci_dbg(ehci, "unable to enable MWI - not fatal.\n"); | |
1da177e4 LT |
572 | } |
573 | #endif | |
574 | ||
575 | /* | |
576 | * dedicate a qh for the async ring head, since we couldn't unlink | |
577 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
578 | * as the 'reclamation list head' too. | |
579 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
580 | * from automatically advancing to the next td after short reads. | |
581 | */ | |
582 | if (first) { | |
583 | ehci->async->qh_next.qh = NULL; | |
584 | ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma); | |
585 | ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD); | |
586 | ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT); | |
587 | ehci->async->hw_qtd_next = EHCI_LIST_END; | |
588 | ehci->async->qh_state = QH_STATE_LINKED; | |
589 | ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma); | |
590 | } | |
591 | writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
592 | ||
593 | /* | |
594 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
595 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
596 | * pci_pool consistent memory always uses segment zero. | |
597 | * streaming mappings for I/O buffers, like pci_map_single(), | |
598 | * can return segments above 4GB, if the device allows. | |
599 | * | |
600 | * NOTE: the dma mask is visible through dma_supported(), so | |
601 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
602 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
603 | * host side drivers though. | |
604 | */ | |
605 | if (HCC_64BIT_ADDR (hcc_params)) { | |
606 | writel (0, &ehci->regs->segment); | |
607 | #if 0 | |
608 | // this is deeply broken on almost all architectures | |
d49d4317 DB |
609 | if (!dma_set_mask (hcd->self.controller, DMA_64BIT_MASK)) |
610 | ehci_info (ehci, "enabled 64bit DMA\n"); | |
1da177e4 LT |
611 | #endif |
612 | } | |
613 | ||
614 | /* clear interrupt enables, set irq latency */ | |
615 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
616 | log2_irq_thresh = 0; | |
617 | temp = 1 << (16 + log2_irq_thresh); | |
618 | if (HCC_CANPARK(hcc_params)) { | |
619 | /* HW default park == 3, on hardware that supports it (like | |
620 | * NVidia and ALI silicon), maximizes throughput on the async | |
621 | * schedule by avoiding QH fetches between transfers. | |
622 | * | |
623 | * With fast usb storage devices and NForce2, "park" seems to | |
624 | * make problems: throughput reduction (!), data errors... | |
625 | */ | |
626 | if (park) { | |
627 | park = min (park, (unsigned) 3); | |
628 | temp |= CMD_PARK; | |
629 | temp |= park << 8; | |
630 | } | |
631 | ehci_info (ehci, "park %d\n", park); | |
632 | } | |
633 | if (HCC_PGM_FRAMELISTLEN (hcc_params)) { | |
634 | /* periodic schedule size can be smaller than default */ | |
635 | temp &= ~(3 << 2); | |
636 | temp |= (EHCI_TUNE_FLS << 2); | |
637 | switch (EHCI_TUNE_FLS) { | |
638 | case 0: ehci->periodic_size = 1024; break; | |
639 | case 1: ehci->periodic_size = 512; break; | |
640 | case 2: ehci->periodic_size = 256; break; | |
641 | default: BUG (); | |
642 | } | |
643 | } | |
644 | // Philips, Intel, and maybe others need CMD_RUN before the | |
645 | // root hub will detect new devices (why?); NEC doesn't | |
646 | temp |= CMD_RUN; | |
647 | writel (temp, &ehci->regs->command); | |
648 | dbg_cmd (ehci, "init", temp); | |
649 | ||
650 | /* set async sleep time = 10 us ... ? */ | |
651 | ||
1da177e4 LT |
652 | /* |
653 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
654 | * are explicitly handed to companion controller(s), so no TT is | |
655 | * involved with the root hub. (Except where one is integrated, | |
656 | * and there's no companion controller unless maybe for USB OTG.) | |
657 | */ | |
658 | if (first) { | |
659 | ehci->reboot_notifier.notifier_call = ehci_reboot; | |
660 | register_reboot_notifier (&ehci->reboot_notifier); | |
661 | } | |
662 | ||
663 | hcd->state = HC_STATE_RUNNING; | |
664 | writel (FLAG_CF, &ehci->regs->configured_flag); | |
665 | readl (&ehci->regs->command); /* unblock posted write */ | |
666 | ||
667 | temp = HC_VERSION(readl (&ehci->caps->hc_capbase)); | |
668 | ehci_info (ehci, | |
669 | "USB %x.%x %s, EHCI %x.%02x, driver %s\n", | |
670 | ((sbrn & 0xf0)>>4), (sbrn & 0x0f), | |
671 | first ? "initialized" : "restarted", | |
672 | temp >> 8, temp & 0xff, DRIVER_VERSION); | |
673 | ||
1da177e4 LT |
674 | writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */ |
675 | ||
676 | if (first) | |
677 | create_debug_files (ehci); | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
682 | /* always called by thread; normally rmmod */ | |
683 | ||
684 | static void ehci_stop (struct usb_hcd *hcd) | |
685 | { | |
686 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 LT |
687 | |
688 | ehci_dbg (ehci, "stop\n"); | |
689 | ||
690 | /* Turn off port power on all root hub ports. */ | |
56c1e26d | 691 | ehci_port_power (ehci, 0); |
1da177e4 LT |
692 | |
693 | /* no more interrupts ... */ | |
694 | del_timer_sync (&ehci->watchdog); | |
695 | ||
696 | spin_lock_irq(&ehci->lock); | |
697 | if (HC_IS_RUNNING (hcd->state)) | |
698 | ehci_quiesce (ehci); | |
699 | ||
700 | ehci_reset (ehci); | |
701 | writel (0, &ehci->regs->intr_enable); | |
702 | spin_unlock_irq(&ehci->lock); | |
703 | ||
704 | /* let companion controllers work when we aren't */ | |
705 | writel (0, &ehci->regs->configured_flag); | |
706 | unregister_reboot_notifier (&ehci->reboot_notifier); | |
707 | ||
708 | remove_debug_files (ehci); | |
709 | ||
710 | /* root hub is shut down separately (first, when possible) */ | |
711 | spin_lock_irq (&ehci->lock); | |
712 | if (ehci->async) | |
713 | ehci_work (ehci, NULL); | |
714 | spin_unlock_irq (&ehci->lock); | |
715 | ehci_mem_cleanup (ehci); | |
716 | ||
717 | #ifdef EHCI_STATS | |
718 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
719 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
720 | ehci->stats.lost_iaa); | |
721 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
722 | ehci->stats.complete, ehci->stats.unlink); | |
723 | #endif | |
724 | ||
725 | dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status)); | |
726 | } | |
727 | ||
728 | static int ehci_get_frame (struct usb_hcd *hcd) | |
729 | { | |
730 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
731 | return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size; | |
732 | } | |
733 | ||
734 | /*-------------------------------------------------------------------------*/ | |
735 | ||
736 | #ifdef CONFIG_PM | |
737 | ||
738 | /* suspend/resume, section 4.3 */ | |
739 | ||
740 | /* These routines rely on the bus (pci, platform, etc) | |
741 | * to handle powerdown and wakeup, and currently also on | |
742 | * transceivers that don't need any software attention to set up | |
743 | * the right sort of wakeup. | |
744 | */ | |
745 | ||
9a5d3e98 | 746 | static int ehci_suspend (struct usb_hcd *hcd, pm_message_t message) |
1da177e4 LT |
747 | { |
748 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
749 | ||
750 | if (time_before (jiffies, ehci->next_statechange)) | |
751 | msleep (100); | |
752 | ||
753 | #ifdef CONFIG_USB_SUSPEND | |
9a5d3e98 | 754 | (void) usb_suspend_device (hcd->self.root_hub, message); |
1da177e4 LT |
755 | #else |
756 | usb_lock_device (hcd->self.root_hub); | |
757 | (void) ehci_hub_suspend (hcd); | |
758 | usb_unlock_device (hcd->self.root_hub); | |
759 | #endif | |
760 | ||
761 | // save (PCI) FLADJ in case of Vaux power loss | |
762 | // ... we'd only use it to handle clock skew | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
767 | static int ehci_resume (struct usb_hcd *hcd) | |
768 | { | |
769 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
770 | unsigned port; | |
771 | struct usb_device *root = hcd->self.root_hub; | |
772 | int retval = -EINVAL; | |
1da177e4 LT |
773 | |
774 | // maybe restore (PCI) FLADJ | |
775 | ||
776 | if (time_before (jiffies, ehci->next_statechange)) | |
777 | msleep (100); | |
778 | ||
10f6524a DB |
779 | /* If any port is suspended (or owned by the companion), |
780 | * we know we can/must resume the HC (and mustn't reset it). | |
781 | */ | |
1da177e4 LT |
782 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) { |
783 | u32 status; | |
784 | port--; | |
785 | status = readl (&ehci->regs->port_status [port]); | |
10f6524a DB |
786 | if (!(status & PORT_POWER)) |
787 | continue; | |
788 | if (status & (PORT_SUSPEND | PORT_OWNER)) { | |
1da177e4 LT |
789 | down (&hcd->self.root_hub->serialize); |
790 | retval = ehci_hub_resume (hcd); | |
791 | up (&hcd->self.root_hub->serialize); | |
792 | break; | |
793 | } | |
1da177e4 LT |
794 | if (!root->children [port]) |
795 | continue; | |
796 | dbg_port (ehci, __FUNCTION__, port + 1, status); | |
797 | usb_set_device_state (root->children[port], | |
798 | USB_STATE_NOTATTACHED); | |
799 | } | |
800 | ||
801 | /* Else reset, to cope with power loss or flush-to-storage | |
802 | * style "resume" having activated BIOS during reboot. | |
803 | */ | |
804 | if (port == 0) { | |
805 | (void) ehci_halt (ehci); | |
806 | (void) ehci_reset (ehci); | |
807 | (void) ehci_hc_reset (hcd); | |
808 | ||
809 | /* emptying the schedule aborts any urbs */ | |
810 | spin_lock_irq (&ehci->lock); | |
811 | if (ehci->reclaim) | |
812 | ehci->reclaim_ready = 1; | |
813 | ehci_work (ehci, NULL); | |
814 | spin_unlock_irq (&ehci->lock); | |
815 | ||
816 | /* restart; khubd will disconnect devices */ | |
817 | retval = ehci_start (hcd); | |
818 | ||
819 | /* here we "know" root ports should always stay powered; | |
56c1e26d | 820 | * but some controllers may lose all power. |
1da177e4 | 821 | */ |
56c1e26d | 822 | ehci_port_power (ehci, 1); |
1da177e4 LT |
823 | } |
824 | ||
825 | return retval; | |
826 | } | |
827 | ||
828 | #endif | |
829 | ||
830 | /*-------------------------------------------------------------------------*/ | |
831 | ||
832 | /* | |
833 | * ehci_work is called from some interrupts, timers, and so on. | |
834 | * it calls driver completion functions, after dropping ehci->lock. | |
835 | */ | |
836 | static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs) | |
837 | { | |
838 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
839 | if (ehci->reclaim_ready) | |
840 | end_unlink_async (ehci, regs); | |
841 | ||
842 | /* another CPU may drop ehci->lock during a schedule scan while | |
843 | * it reports urb completions. this flag guards against bogus | |
844 | * attempts at re-entrant schedule scanning. | |
845 | */ | |
846 | if (ehci->scanning) | |
847 | return; | |
848 | ehci->scanning = 1; | |
849 | scan_async (ehci, regs); | |
850 | if (ehci->next_uframe != -1) | |
851 | scan_periodic (ehci, regs); | |
852 | ehci->scanning = 0; | |
853 | ||
854 | /* the IO watchdog guards against hardware or driver bugs that | |
855 | * misplace IRQs, and should let us run completely without IRQs. | |
856 | * such lossage has been observed on both VT6202 and VT8235. | |
857 | */ | |
858 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
859 | (ehci->async->qh_next.ptr != NULL || | |
860 | ehci->periodic_sched != 0)) | |
861 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
862 | } | |
863 | ||
864 | /*-------------------------------------------------------------------------*/ | |
865 | ||
866 | static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs) | |
867 | { | |
868 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
869 | u32 status; | |
870 | int bh; | |
871 | ||
872 | spin_lock (&ehci->lock); | |
873 | ||
874 | status = readl (&ehci->regs->status); | |
875 | ||
876 | /* e.g. cardbus physical eject */ | |
877 | if (status == ~(u32) 0) { | |
878 | ehci_dbg (ehci, "device removed\n"); | |
879 | goto dead; | |
880 | } | |
881 | ||
882 | status &= INTR_MASK; | |
883 | if (!status) { /* irq sharing? */ | |
884 | spin_unlock(&ehci->lock); | |
885 | return IRQ_NONE; | |
886 | } | |
887 | ||
888 | /* clear (just) interrupts */ | |
889 | writel (status, &ehci->regs->status); | |
890 | readl (&ehci->regs->command); /* unblock posted write */ | |
891 | bh = 0; | |
892 | ||
893 | #ifdef EHCI_VERBOSE_DEBUG | |
894 | /* unrequested/ignored: Frame List Rollover */ | |
895 | dbg_status (ehci, "irq", status); | |
896 | #endif | |
897 | ||
898 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
899 | ||
900 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
901 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
902 | if (likely ((status & STS_ERR) == 0)) | |
903 | COUNT (ehci->stats.normal); | |
904 | else | |
905 | COUNT (ehci->stats.error); | |
906 | bh = 1; | |
907 | } | |
908 | ||
909 | /* complete the unlinking of some qh [4.15.2.3] */ | |
910 | if (status & STS_IAA) { | |
911 | COUNT (ehci->stats.reclaim); | |
912 | ehci->reclaim_ready = 1; | |
913 | bh = 1; | |
914 | } | |
915 | ||
916 | /* remote wakeup [4.3.1] */ | |
917 | if ((status & STS_PCD) && hcd->remote_wakeup) { | |
918 | unsigned i = HCS_N_PORTS (ehci->hcs_params); | |
919 | ||
920 | /* resume root hub? */ | |
921 | status = readl (&ehci->regs->command); | |
922 | if (!(status & CMD_RUN)) | |
923 | writel (status | CMD_RUN, &ehci->regs->command); | |
924 | ||
925 | while (i--) { | |
926 | status = readl (&ehci->regs->port_status [i]); | |
927 | if (status & PORT_OWNER) | |
928 | continue; | |
929 | if (!(status & PORT_RESUME) | |
930 | || ehci->reset_done [i] != 0) | |
931 | continue; | |
932 | ||
933 | /* start 20 msec resume signaling from this port, | |
934 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
935 | * stop that signaling. | |
936 | */ | |
937 | ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); | |
938 | mod_timer (&hcd->rh_timer, | |
939 | ehci->reset_done [i] + 1); | |
940 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); | |
941 | } | |
942 | } | |
943 | ||
944 | /* PCI errors [4.15.2.4] */ | |
945 | if (unlikely ((status & STS_FATAL) != 0)) { | |
946 | /* bogus "fatal" IRQs appear on some chips... why? */ | |
947 | status = readl (&ehci->regs->status); | |
948 | dbg_cmd (ehci, "fatal", readl (&ehci->regs->command)); | |
949 | dbg_status (ehci, "fatal", status); | |
950 | if (status & STS_HALT) { | |
951 | ehci_err (ehci, "fatal error\n"); | |
952 | dead: | |
953 | ehci_reset (ehci); | |
954 | writel (0, &ehci->regs->configured_flag); | |
955 | /* generic layer kills/unlinks all urbs, then | |
956 | * uses ehci_stop to clean up the rest | |
957 | */ | |
958 | bh = 1; | |
959 | } | |
960 | } | |
961 | ||
962 | if (bh) | |
963 | ehci_work (ehci, regs); | |
964 | spin_unlock (&ehci->lock); | |
965 | return IRQ_HANDLED; | |
966 | } | |
967 | ||
968 | /*-------------------------------------------------------------------------*/ | |
969 | ||
970 | /* | |
971 | * non-error returns are a promise to giveback() the urb later | |
972 | * we drop ownership so next owner (or urb unlink) can get it | |
973 | * | |
974 | * urb + dev is in hcd.self.controller.urb_list | |
975 | * we're queueing TDs onto software and hardware lists | |
976 | * | |
977 | * hcd-specific init for hcpriv hasn't been done yet | |
978 | * | |
979 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
980 | * to a (possibly active) QH, and the same QH scanning code. | |
981 | */ | |
982 | static int ehci_urb_enqueue ( | |
983 | struct usb_hcd *hcd, | |
984 | struct usb_host_endpoint *ep, | |
985 | struct urb *urb, | |
55016f10 | 986 | gfp_t mem_flags |
1da177e4 LT |
987 | ) { |
988 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
989 | struct list_head qtd_list; | |
990 | ||
991 | INIT_LIST_HEAD (&qtd_list); | |
992 | ||
993 | switch (usb_pipetype (urb->pipe)) { | |
994 | // case PIPE_CONTROL: | |
995 | // case PIPE_BULK: | |
996 | default: | |
997 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
998 | return -ENOMEM; | |
999 | return submit_async (ehci, ep, urb, &qtd_list, mem_flags); | |
1000 | ||
1001 | case PIPE_INTERRUPT: | |
1002 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
1003 | return -ENOMEM; | |
1004 | return intr_submit (ehci, ep, urb, &qtd_list, mem_flags); | |
1005 | ||
1006 | case PIPE_ISOCHRONOUS: | |
1007 | if (urb->dev->speed == USB_SPEED_HIGH) | |
1008 | return itd_submit (ehci, urb, mem_flags); | |
1009 | else | |
1010 | return sitd_submit (ehci, urb, mem_flags); | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
1015 | { | |
1016 | /* if we need to use IAA and it's busy, defer */ | |
1017 | if (qh->qh_state == QH_STATE_LINKED | |
1018 | && ehci->reclaim | |
1019 | && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) { | |
1020 | struct ehci_qh *last; | |
1021 | ||
1022 | for (last = ehci->reclaim; | |
1023 | last->reclaim; | |
1024 | last = last->reclaim) | |
1025 | continue; | |
1026 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
1027 | last->reclaim = qh; | |
1028 | ||
1029 | /* bypass IAA if the hc can't care */ | |
1030 | } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim) | |
1031 | end_unlink_async (ehci, NULL); | |
1032 | ||
1033 | /* something else might have unlinked the qh by now */ | |
1034 | if (qh->qh_state == QH_STATE_LINKED) | |
1035 | start_unlink_async (ehci, qh); | |
1036 | } | |
1037 | ||
1038 | /* remove from hardware lists | |
1039 | * completions normally happen asynchronously | |
1040 | */ | |
1041 | ||
1042 | static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) | |
1043 | { | |
1044 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1045 | struct ehci_qh *qh; | |
1046 | unsigned long flags; | |
1047 | ||
1048 | spin_lock_irqsave (&ehci->lock, flags); | |
1049 | switch (usb_pipetype (urb->pipe)) { | |
1050 | // case PIPE_CONTROL: | |
1051 | // case PIPE_BULK: | |
1052 | default: | |
1053 | qh = (struct ehci_qh *) urb->hcpriv; | |
1054 | if (!qh) | |
1055 | break; | |
1056 | unlink_async (ehci, qh); | |
1057 | break; | |
1058 | ||
1059 | case PIPE_INTERRUPT: | |
1060 | qh = (struct ehci_qh *) urb->hcpriv; | |
1061 | if (!qh) | |
1062 | break; | |
1063 | switch (qh->qh_state) { | |
1064 | case QH_STATE_LINKED: | |
1065 | intr_deschedule (ehci, qh); | |
1066 | /* FALL THROUGH */ | |
1067 | case QH_STATE_IDLE: | |
1068 | qh_completions (ehci, qh, NULL); | |
1069 | break; | |
1070 | default: | |
1071 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
1072 | qh, qh->qh_state); | |
1073 | goto done; | |
1074 | } | |
1075 | ||
1076 | /* reschedule QH iff another request is queued */ | |
1077 | if (!list_empty (&qh->qtd_list) | |
1078 | && HC_IS_RUNNING (hcd->state)) { | |
1079 | int status; | |
1080 | ||
1081 | status = qh_schedule (ehci, qh); | |
1082 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1083 | ||
1084 | if (status != 0) { | |
1085 | // shouldn't happen often, but ... | |
1086 | // FIXME kill those tds' urbs | |
1087 | err ("can't reschedule qh %p, err %d", | |
1088 | qh, status); | |
1089 | } | |
1090 | return status; | |
1091 | } | |
1092 | break; | |
1093 | ||
1094 | case PIPE_ISOCHRONOUS: | |
1095 | // itd or sitd ... | |
1096 | ||
1097 | // wait till next completion, do it then. | |
1098 | // completion irqs can wait up to 1024 msec, | |
1099 | break; | |
1100 | } | |
1101 | done: | |
1102 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | /*-------------------------------------------------------------------------*/ | |
1107 | ||
1108 | // bulk qh holds the data toggle | |
1109 | ||
1110 | static void | |
1111 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1112 | { | |
1113 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1114 | unsigned long flags; | |
1115 | struct ehci_qh *qh, *tmp; | |
1116 | ||
1117 | /* ASSERT: any requests/urbs are being unlinked */ | |
1118 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
1119 | ||
1120 | rescan: | |
1121 | spin_lock_irqsave (&ehci->lock, flags); | |
1122 | qh = ep->hcpriv; | |
1123 | if (!qh) | |
1124 | goto done; | |
1125 | ||
1126 | /* endpoints can be iso streams. for now, we don't | |
1127 | * accelerate iso completions ... so spin a while. | |
1128 | */ | |
1129 | if (qh->hw_info1 == 0) { | |
1130 | ehci_vdbg (ehci, "iso delay\n"); | |
1131 | goto idle_timeout; | |
1132 | } | |
1133 | ||
1134 | if (!HC_IS_RUNNING (hcd->state)) | |
1135 | qh->qh_state = QH_STATE_IDLE; | |
1136 | switch (qh->qh_state) { | |
1137 | case QH_STATE_LINKED: | |
1138 | for (tmp = ehci->async->qh_next.qh; | |
1139 | tmp && tmp != qh; | |
1140 | tmp = tmp->qh_next.qh) | |
1141 | continue; | |
1142 | /* periodic qh self-unlinks on empty */ | |
1143 | if (!tmp) | |
1144 | goto nogood; | |
1145 | unlink_async (ehci, qh); | |
1146 | /* FALL THROUGH */ | |
1147 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
1148 | idle_timeout: | |
1149 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 1150 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
1151 | goto rescan; |
1152 | case QH_STATE_IDLE: /* fully unlinked */ | |
1153 | if (list_empty (&qh->qtd_list)) { | |
1154 | qh_put (qh); | |
1155 | break; | |
1156 | } | |
1157 | /* else FALL THROUGH */ | |
1158 | default: | |
1159 | nogood: | |
1160 | /* caller was supposed to have unlinked any requests; | |
1161 | * that's not our job. just leak this memory. | |
1162 | */ | |
1163 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
1164 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
1165 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
1166 | break; | |
1167 | } | |
1168 | ep->hcpriv = NULL; | |
1169 | done: | |
1170 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1171 | return; | |
1172 | } | |
1173 | ||
1174 | /*-------------------------------------------------------------------------*/ | |
1175 | ||
1176 | static const struct hc_driver ehci_driver = { | |
1177 | .description = hcd_name, | |
1178 | .product_desc = "EHCI Host Controller", | |
1179 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
1180 | ||
1181 | /* | |
1182 | * generic hardware linkage | |
1183 | */ | |
1184 | .irq = ehci_irq, | |
1185 | .flags = HCD_MEMORY | HCD_USB2, | |
1186 | ||
1187 | /* | |
1188 | * basic lifecycle operations | |
1189 | */ | |
1190 | .reset = ehci_hc_reset, | |
1191 | .start = ehci_start, | |
1192 | #ifdef CONFIG_PM | |
1193 | .suspend = ehci_suspend, | |
1194 | .resume = ehci_resume, | |
1195 | #endif | |
1196 | .stop = ehci_stop, | |
1197 | ||
1198 | /* | |
1199 | * managing i/o requests and associated device resources | |
1200 | */ | |
1201 | .urb_enqueue = ehci_urb_enqueue, | |
1202 | .urb_dequeue = ehci_urb_dequeue, | |
1203 | .endpoint_disable = ehci_endpoint_disable, | |
1204 | ||
1205 | /* | |
1206 | * scheduling support | |
1207 | */ | |
1208 | .get_frame_number = ehci_get_frame, | |
1209 | ||
1210 | /* | |
1211 | * root hub support | |
1212 | */ | |
1213 | .hub_status_data = ehci_hub_status_data, | |
1214 | .hub_control = ehci_hub_control, | |
1215 | .hub_suspend = ehci_hub_suspend, | |
1216 | .hub_resume = ehci_hub_resume, | |
1217 | }; | |
1218 | ||
1219 | /*-------------------------------------------------------------------------*/ | |
1220 | ||
1221 | /* EHCI 1.0 doesn't require PCI */ | |
1222 | ||
1223 | #ifdef CONFIG_PCI | |
1224 | ||
1225 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
1226 | static const struct pci_device_id pci_ids [] = { { | |
1227 | /* handle any USB 2.0 EHCI controller */ | |
1228 | PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0), | |
1229 | .driver_data = (unsigned long) &ehci_driver, | |
1230 | }, | |
1231 | { /* end: all zeroes */ } | |
1232 | }; | |
1233 | MODULE_DEVICE_TABLE (pci, pci_ids); | |
1234 | ||
1235 | /* pci driver glue; this is a "new style" PCI driver module */ | |
1236 | static struct pci_driver ehci_pci_driver = { | |
1237 | .name = (char *) hcd_name, | |
1238 | .id_table = pci_ids, | |
1239 | ||
1240 | .probe = usb_hcd_pci_probe, | |
1241 | .remove = usb_hcd_pci_remove, | |
1242 | ||
1243 | #ifdef CONFIG_PM | |
1244 | .suspend = usb_hcd_pci_suspend, | |
1245 | .resume = usb_hcd_pci_resume, | |
1246 | #endif | |
1247 | }; | |
1248 | ||
1249 | #endif /* PCI */ | |
1250 | ||
1251 | ||
1252 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC | |
1253 | ||
1254 | MODULE_DESCRIPTION (DRIVER_INFO); | |
1255 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
1256 | MODULE_LICENSE ("GPL"); | |
1257 | ||
1258 | static int __init init (void) | |
1259 | { | |
1260 | if (usb_disabled()) | |
1261 | return -ENODEV; | |
1262 | ||
1263 | pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", | |
1264 | hcd_name, | |
1265 | sizeof (struct ehci_qh), sizeof (struct ehci_qtd), | |
1266 | sizeof (struct ehci_itd), sizeof (struct ehci_sitd)); | |
1267 | ||
1268 | return pci_register_driver (&ehci_pci_driver); | |
1269 | } | |
1270 | module_init (init); | |
1271 | ||
1272 | static void __exit cleanup (void) | |
1273 | { | |
1274 | pci_unregister_driver (&ehci_pci_driver); | |
1275 | } | |
1276 | module_exit (cleanup); |