Commit | Line | Data |
---|---|---|
7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #ifndef CONFIG_PCI | |
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | |
23 | #endif | |
24 | ||
4f683843 DB |
25 | /* defined here to avoid adding to pci_ids.h for single instance use */ |
26 | #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 | |
27 | ||
7ff71d6a MP |
28 | /*-------------------------------------------------------------------------*/ |
29 | ||
18807521 DB |
30 | /* called after powerup, by probe or system-pm "wakeup" */ |
31 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
32 | { | |
18807521 | 33 | int retval; |
18807521 | 34 | |
401feafa DB |
35 | /* we expect static quirk code to handle the "extended capabilities" |
36 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
37 | */ | |
18807521 DB |
38 | |
39 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
40 | retval = pci_set_mwi(pdev); | |
41 | if (!retval) | |
42 | ehci_dbg(ehci, "MWI active\n"); | |
43 | ||
18807521 DB |
44 | return 0; |
45 | } | |
46 | ||
8926bfa7 DB |
47 | /* called during probe() after chip reset completes */ |
48 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 49 | { |
abcc9448 DB |
50 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
51 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
b09bc6cb AX |
52 | struct pci_dev *p_smbus; |
53 | u8 rev; | |
7ff71d6a | 54 | u32 temp; |
18807521 | 55 | int retval; |
7ff71d6a | 56 | |
1a49e2ac AS |
57 | ehci->caps = hcd->regs; |
58 | ||
59 | /* | |
60 | * ehci_init() causes memory for DMA transfers to be | |
61 | * allocated. Thus, any vendor-specific workarounds based on | |
62 | * limiting the type of memory used for DMA transfers must | |
63 | * happen before ehci_setup() is called. | |
64 | * | |
65 | * Most other workarounds can be done either before or after | |
66 | * init and reset; they are located here too. | |
67 | */ | |
083522d7 BH |
68 | switch (pdev->vendor) { |
69 | case PCI_VENDOR_ID_TOSHIBA_2: | |
70 | /* celleb's companion chip */ | |
71 | if (pdev->device == 0x01b5) { | |
72 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
73 | ehci->big_endian_mmio = 1; | |
74 | #else | |
75 | ehci_warn(ehci, | |
76 | "unsupported big endian Toshiba quirk\n"); | |
77 | #endif | |
78 | } | |
79 | break; | |
c32ba30f PS |
80 | case PCI_VENDOR_ID_NVIDIA: |
81 | /* NVidia reports that certain chips don't handle | |
82 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
83 | * data buffer, and periodic schedule are normal.) | |
84 | */ | |
85 | switch (pdev->device) { | |
86 | case 0x003c: /* MCP04 */ | |
87 | case 0x005b: /* CK804 */ | |
88 | case 0x00d8: /* CK8 */ | |
89 | case 0x00e8: /* CK8S */ | |
90 | if (pci_set_consistent_dma_mask(pdev, | |
929a22a5 | 91 | DMA_BIT_MASK(31)) < 0) |
c32ba30f PS |
92 | ehci_warn(ehci, "can't enable NVidia " |
93 | "workaround for >2GB RAM\n"); | |
94 | break; | |
7ff71d6a | 95 | |
1a49e2ac AS |
96 | /* Some NForce2 chips have problems with selective suspend; |
97 | * fixed in newer silicon. | |
3d091a6f | 98 | */ |
1a49e2ac AS |
99 | case 0x0068: |
100 | if (pdev->revision < 0xa4) | |
101 | ehci->no_selective_suspend = 1; | |
102 | break; | |
103 | } | |
3681d8f3 | 104 | break; |
403dbd36 | 105 | case PCI_VENDOR_ID_INTEL: |
ae68a83b | 106 | ehci->fs_i_thresh = 1; |
1a49e2ac | 107 | if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) |
4f683843 | 108 | hcd->has_tt = 1; |
403dbd36 | 109 | break; |
abcc9448 | 110 | case PCI_VENDOR_ID_TDI: |
1a49e2ac | 111 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) |
7329e211 | 112 | hcd->has_tt = 1; |
abcc9448 DB |
113 | break; |
114 | case PCI_VENDOR_ID_AMD: | |
ad93562b AX |
115 | /* AMD PLL quirk */ |
116 | if (usb_amd_find_chipset_info()) | |
117 | ehci->amd_pll_fix = 1; | |
abcc9448 DB |
118 | /* AMD8111 EHCI doesn't work, according to AMD errata */ |
119 | if (pdev->device == 0x7463) { | |
120 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
121 | retval = -EIO; |
122 | goto done; | |
abcc9448 | 123 | } |
a85b4e7f | 124 | |
1a49e2ac AS |
125 | /* |
126 | * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
127 | * read/write memory space which does not belong to it when | |
128 | * there is NULL pointer with T-bit set to 1 in the frame list | |
129 | * table. To avoid the issue, the frame list link pointer | |
130 | * should always contain a valid pointer to a inactive qh. | |
a85b4e7f | 131 | */ |
1a49e2ac AS |
132 | if (pdev->device == 0x7808) { |
133 | ehci->use_dummy_qh = 1; | |
134 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); | |
7ff71d6a | 135 | } |
abcc9448 | 136 | break; |
055b93c9 RH |
137 | case PCI_VENDOR_ID_VIA: |
138 | if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { | |
139 | u8 tmp; | |
140 | ||
141 | /* The VT6212 defaults to a 1 usec EHCI sleep time which | |
142 | * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes | |
143 | * that sleep time use the conventional 10 usec. | |
144 | */ | |
145 | pci_read_config_byte(pdev, 0x4b, &tmp); | |
146 | if (tmp & 0x20) | |
147 | break; | |
148 | pci_write_config_byte(pdev, 0x4b, tmp | 0x20); | |
149 | } | |
150 | break; | |
b09bc6cb | 151 | case PCI_VENDOR_ID_ATI: |
ad93562b AX |
152 | /* AMD PLL quirk */ |
153 | if (usb_amd_find_chipset_info()) | |
154 | ehci->amd_pll_fix = 1; | |
1a49e2ac AS |
155 | |
156 | /* | |
157 | * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
158 | * read/write memory space which does not belong to it when | |
159 | * there is NULL pointer with T-bit set to 1 in the frame list | |
160 | * table. To avoid the issue, the frame list link pointer | |
161 | * should always contain a valid pointer to a inactive qh. | |
162 | */ | |
163 | if (pdev->device == 0x4396) { | |
164 | ehci->use_dummy_qh = 1; | |
165 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); | |
166 | } | |
0a99e8ac | 167 | /* SB600 and old version of SB700 have a bug in EHCI controller, |
b09bc6cb AX |
168 | * which causes usb devices lose response in some cases. |
169 | */ | |
0a99e8ac | 170 | if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { |
b09bc6cb AX |
171 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
172 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
173 | NULL); | |
174 | if (!p_smbus) | |
175 | break; | |
176 | rev = p_smbus->revision; | |
0a99e8ac SH |
177 | if ((pdev->device == 0x4386) || (rev == 0x3a) |
178 | || (rev == 0x3b)) { | |
b09bc6cb | 179 | u8 tmp; |
0a99e8ac SH |
180 | ehci_info(ehci, "applying AMD SB600/SB700 USB " |
181 | "freeze workaround\n"); | |
b09bc6cb AX |
182 | pci_read_config_byte(pdev, 0x53, &tmp); |
183 | pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); | |
184 | } | |
185 | pci_dev_put(p_smbus); | |
186 | } | |
187 | break; | |
68aa95d5 AS |
188 | case PCI_VENDOR_ID_NETMOS: |
189 | /* MosChip frame-index-register bug */ | |
190 | ehci_info(ehci, "applying MosChip frame-index workaround\n"); | |
191 | ehci->frame_index_bug = 1; | |
192 | break; | |
abcc9448 | 193 | } |
7ff71d6a | 194 | |
1a49e2ac AS |
195 | retval = ehci_setup(hcd); |
196 | if (retval) | |
197 | return retval; | |
198 | ||
199 | /* These workarounds need to be applied after ehci_setup() */ | |
200 | switch (pdev->vendor) { | |
201 | case PCI_VENDOR_ID_NEC: | |
202 | ehci->need_io_watchdog = 0; | |
203 | break; | |
204 | case PCI_VENDOR_ID_INTEL: | |
205 | ehci->need_io_watchdog = 0; | |
206 | if (pdev->device == 0x0806 || pdev->device == 0x0811 | |
207 | || pdev->device == 0x0829) { | |
208 | ehci_info(ehci, "disable lpm for langwell/penwell\n"); | |
209 | ehci->has_lpm = 0; | |
210 | } | |
211 | break; | |
212 | case PCI_VENDOR_ID_NVIDIA: | |
213 | switch (pdev->device) { | |
214 | /* MCP89 chips on the MacBookAir3,1 give EPROTO when | |
215 | * fetching device descriptors unless LPM is disabled. | |
216 | * There are also intermittent problems enumerating | |
217 | * devices with PPCD enabled. | |
218 | */ | |
219 | case 0x0d9d: | |
220 | ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89"); | |
221 | ehci->has_lpm = 0; | |
222 | ehci->has_ppcd = 0; | |
223 | ehci->command &= ~CMD_PPCEE; | |
224 | break; | |
225 | } | |
226 | break; | |
227 | } | |
228 | ||
8d053c79 JW |
229 | /* optional debug port, normally in the first BAR */ |
230 | temp = pci_find_capability(pdev, 0x0a); | |
231 | if (temp) { | |
232 | pci_read_config_dword(pdev, temp, &temp); | |
233 | temp >>= 16; | |
234 | if ((temp & (3 << 13)) == (1 << 13)) { | |
235 | temp &= 0x1fff; | |
1a49e2ac | 236 | ehci->debug = hcd->regs + temp; |
8d053c79 JW |
237 | temp = ehci_readl(ehci, &ehci->debug->control); |
238 | ehci_info(ehci, "debug port %d%s\n", | |
239 | HCS_DEBUG_PORT(ehci->hcs_params), | |
240 | (temp & DBGP_ENABLED) | |
241 | ? " IN USE" | |
242 | : ""); | |
243 | if (!(temp & DBGP_ENABLED)) | |
244 | ehci->debug = NULL; | |
245 | } | |
246 | } | |
247 | ||
7ff71d6a MP |
248 | /* at least the Genesys GL880S needs fixup here */ |
249 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
250 | temp &= 0x0f; | |
251 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 252 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
253 | "cc=%d x pcc=%d < ports=%d\n", |
254 | HCS_N_CC(ehci->hcs_params), | |
255 | HCS_N_PCC(ehci->hcs_params), | |
256 | HCS_N_PORTS(ehci->hcs_params)); | |
257 | ||
abcc9448 DB |
258 | switch (pdev->vendor) { |
259 | case 0x17a0: /* GENESYS */ | |
260 | /* GL880S: should be PORTS=2 */ | |
261 | temp |= (ehci->hcs_params & ~0xf); | |
262 | ehci->hcs_params = temp; | |
263 | break; | |
264 | case PCI_VENDOR_ID_NVIDIA: | |
265 | /* NF4: should be PCC=10 */ | |
266 | break; | |
7ff71d6a MP |
267 | } |
268 | } | |
269 | ||
abcc9448 | 270 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
3a0bac06 AR |
271 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO |
272 | && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST) | |
1a49e2ac AS |
273 | ; /* ConneXT has no sbrn register */ |
274 | else | |
275 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
7ff71d6a | 276 | |
6fd9086a AS |
277 | /* Keep this around for a while just in case some EHCI |
278 | * implementation uses legacy PCI PM support. This test | |
279 | * can be removed on 17 Dec 2009 if the dev_warn() hasn't | |
280 | * been triggered by then. | |
2c1c3c4c DB |
281 | */ |
282 | if (!device_can_wakeup(&pdev->dev)) { | |
283 | u16 port_wake; | |
284 | ||
285 | pci_read_config_word(pdev, 0x62, &port_wake); | |
6fd9086a AS |
286 | if (port_wake & 0x0001) { |
287 | dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); | |
bcca06ef | 288 | device_set_wakeup_capable(&pdev->dev, 1); |
6fd9086a | 289 | } |
2c1c3c4c | 290 | } |
7ff71d6a | 291 | |
f8aeb3bb DB |
292 | #ifdef CONFIG_USB_SUSPEND |
293 | /* REVISIT: the controller works fine for wakeup iff the root hub | |
294 | * itself is "globally" suspended, but usbcore currently doesn't | |
295 | * understand such things. | |
296 | * | |
297 | * System suspend currently expects to be able to suspend the entire | |
298 | * device tree, device-at-a-time. If we failed selective suspend | |
299 | * reports, system suspend would fail; so the root hub code must claim | |
411c9403 | 300 | * success. That's lying to usbcore, and it matters for runtime |
f8aeb3bb DB |
301 | * PM scenarios with selective suspend and remote wakeup... |
302 | */ | |
303 | if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) | |
304 | ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); | |
305 | #endif | |
306 | ||
aff6d18f | 307 | ehci_port_power(ehci, 1); |
18807521 | 308 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
309 | done: |
310 | return retval; | |
7ff71d6a MP |
311 | } |
312 | ||
313 | /*-------------------------------------------------------------------------*/ | |
314 | ||
315 | #ifdef CONFIG_PM | |
316 | ||
317 | /* suspend/resume, section 4.3 */ | |
318 | ||
f03c17fc | 319 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
320 | * to handle powerdown and wakeup, and currently also on |
321 | * transceivers that don't need any software attention to set up | |
322 | * the right sort of wakeup. | |
f03c17fc | 323 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
324 | */ |
325 | ||
4147200d | 326 | static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
7ff71d6a | 327 | { |
c5cf9212 | 328 | return ehci_suspend(hcd, do_wakeup); |
7ff71d6a MP |
329 | } |
330 | ||
69e848c2 SS |
331 | static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev) |
332 | { | |
333 | return pdev->class == PCI_CLASS_SERIAL_USB_EHCI && | |
334 | pdev->vendor == PCI_VENDOR_ID_INTEL && | |
1c12443a SS |
335 | (pdev->device == 0x1E26 || |
336 | pdev->device == 0x8C2D || | |
337 | pdev->device == 0x8C26); | |
69e848c2 SS |
338 | } |
339 | ||
340 | static void ehci_enable_xhci_companion(void) | |
341 | { | |
342 | struct pci_dev *companion = NULL; | |
343 | ||
344 | /* The xHCI and EHCI controllers are not on the same PCI slot */ | |
345 | for_each_pci_dev(companion) { | |
346 | if (!usb_is_intel_switchable_xhci(companion)) | |
347 | continue; | |
348 | usb_enable_xhci_ports(companion); | |
349 | return; | |
350 | } | |
351 | } | |
352 | ||
6ec4beb5 | 353 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
7ff71d6a | 354 | { |
abcc9448 | 355 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
18807521 | 356 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a | 357 | |
69e848c2 SS |
358 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
359 | * not support xHCI natively. That means that during system resume, it | |
360 | * may switch the ports back to EHCI so that users can use their | |
361 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
362 | * | |
363 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
364 | * enabled before resume, and switch the ports back to xHCI when the | |
365 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
366 | * writers. | |
367 | * | |
368 | * Unconditionally switch the ports back to xHCI after a system resume. | |
369 | * We can't tell whether the EHCI or xHCI controller will be resumed | |
370 | * first, so we have to do the port switchover in both drivers. Writing | |
371 | * a '1' to the port switchover registers should have no effect if the | |
372 | * port was already switched over. | |
373 | */ | |
374 | if (usb_is_intel_switchable_ehci(pdev)) | |
375 | ehci_enable_xhci_companion(); | |
376 | ||
c5cf9212 AS |
377 | if (ehci_resume(hcd, hibernated) != 0) |
378 | (void) ehci_pci_reinit(ehci, pdev); | |
8c03356a | 379 | return 0; |
7ff71d6a MP |
380 | } |
381 | #endif | |
382 | ||
48f24970 AD |
383 | static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
384 | { | |
385 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
386 | int rc = 0; | |
387 | ||
388 | if (!udev->parent) /* udev is root hub itself, impossible */ | |
389 | rc = -1; | |
390 | /* we only support lpm device connected to root hub yet */ | |
391 | if (ehci->has_lpm && !udev->parent->parent) { | |
392 | rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum); | |
393 | if (!rc) | |
394 | rc = ehci_lpm_check(ehci, udev->portnum); | |
395 | } | |
396 | return rc; | |
397 | } | |
398 | ||
7ff71d6a MP |
399 | static const struct hc_driver ehci_pci_hc_driver = { |
400 | .description = hcd_name, | |
401 | .product_desc = "EHCI Host Controller", | |
402 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
403 | ||
404 | /* | |
405 | * generic hardware linkage | |
406 | */ | |
407 | .irq = ehci_irq, | |
408 | .flags = HCD_MEMORY | HCD_USB2, | |
409 | ||
410 | /* | |
411 | * basic lifecycle operations | |
412 | */ | |
8926bfa7 | 413 | .reset = ehci_pci_setup, |
18807521 | 414 | .start = ehci_run, |
7ff71d6a | 415 | #ifdef CONFIG_PM |
7be7d741 AS |
416 | .pci_suspend = ehci_pci_suspend, |
417 | .pci_resume = ehci_pci_resume, | |
7ff71d6a | 418 | #endif |
18807521 | 419 | .stop = ehci_stop, |
64a21d02 | 420 | .shutdown = ehci_shutdown, |
7ff71d6a MP |
421 | |
422 | /* | |
423 | * managing i/o requests and associated device resources | |
424 | */ | |
425 | .urb_enqueue = ehci_urb_enqueue, | |
426 | .urb_dequeue = ehci_urb_dequeue, | |
427 | .endpoint_disable = ehci_endpoint_disable, | |
b18ffd49 | 428 | .endpoint_reset = ehci_endpoint_reset, |
7ff71d6a MP |
429 | |
430 | /* | |
431 | * scheduling support | |
432 | */ | |
433 | .get_frame_number = ehci_get_frame, | |
434 | ||
435 | /* | |
436 | * root hub support | |
437 | */ | |
438 | .hub_status_data = ehci_hub_status_data, | |
439 | .hub_control = ehci_hub_control, | |
0c0382e3 AS |
440 | .bus_suspend = ehci_bus_suspend, |
441 | .bus_resume = ehci_bus_resume, | |
a8e51775 | 442 | .relinquish_port = ehci_relinquish_port, |
3a31155c | 443 | .port_handed_over = ehci_port_handed_over, |
914b7012 | 444 | |
48f24970 AD |
445 | /* |
446 | * call back when device connected and addressed | |
447 | */ | |
448 | .update_device = ehci_update_device, | |
449 | ||
914b7012 | 450 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
7ff71d6a MP |
451 | }; |
452 | ||
453 | /*-------------------------------------------------------------------------*/ | |
454 | ||
455 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
456 | static const struct pci_device_id pci_ids [] = { { | |
457 | /* handle any USB 2.0 EHCI controller */ | |
c67808ee | 458 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), |
7ff71d6a | 459 | .driver_data = (unsigned long) &ehci_pci_hc_driver, |
3a0bac06 AR |
460 | }, { |
461 | PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST), | |
462 | .driver_data = (unsigned long) &ehci_pci_hc_driver, | |
7ff71d6a MP |
463 | }, |
464 | { /* end: all zeroes */ } | |
465 | }; | |
abcc9448 | 466 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
467 | |
468 | /* pci driver glue; this is a "new style" PCI driver module */ | |
469 | static struct pci_driver ehci_pci_driver = { | |
470 | .name = (char *) hcd_name, | |
471 | .id_table = pci_ids, | |
472 | ||
473 | .probe = usb_hcd_pci_probe, | |
474 | .remove = usb_hcd_pci_remove, | |
abb30641 | 475 | .shutdown = usb_hcd_pci_shutdown, |
7ff71d6a | 476 | |
abb30641 AS |
477 | #ifdef CONFIG_PM_SLEEP |
478 | .driver = { | |
479 | .pm = &usb_hcd_pci_pm_ops | |
480 | }, | |
7ff71d6a MP |
481 | #endif |
482 | }; |