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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2004 by David Brownell | |
3 | * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers | |
53bd6a60 | 4 | * |
1da177e4 LT |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software Foundation, | |
17 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | /* this file is part of ehci-hcd.c */ | |
21 | ||
22 | /*-------------------------------------------------------------------------*/ | |
23 | ||
24 | /* | |
25 | * EHCI scheduled transaction support: interrupt, iso, split iso | |
26 | * These are called "periodic" transactions in the EHCI spec. | |
27 | * | |
28 | * Note that for interrupt transfers, the QH/QTD manipulation is shared | |
29 | * with the "asynchronous" transaction support (control/bulk transfers). | |
30 | * The only real difference is in how interrupt transfers are scheduled. | |
31 | * | |
32 | * For ISO, we make an "iso_stream" head to serve the same role as a QH. | |
33 | * It keeps track of every ITD (or SITD) that's linked, and holds enough | |
34 | * pre-calculated schedule data to make appending to the queue be quick. | |
35 | */ | |
36 | ||
37 | static int ehci_get_frame (struct usb_hcd *hcd); | |
38 | ||
1da177e4 LT |
39 | /* |
40 | * periodic_next_shadow - return "next" pointer on shadow list | |
41 | * @periodic: host pointer to qh/itd/sitd | |
42 | * @tag: hardware tag for type of this record | |
43 | */ | |
44 | static union ehci_shadow * | |
6dbd682b SR |
45 | periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic, |
46 | __hc32 tag) | |
1da177e4 | 47 | { |
6dbd682b | 48 | switch (hc32_to_cpu(ehci, tag)) { |
1da177e4 LT |
49 | case Q_TYPE_QH: |
50 | return &periodic->qh->qh_next; | |
51 | case Q_TYPE_FSTN: | |
52 | return &periodic->fstn->fstn_next; | |
53 | case Q_TYPE_ITD: | |
54 | return &periodic->itd->itd_next; | |
55 | // case Q_TYPE_SITD: | |
56 | default: | |
57 | return &periodic->sitd->sitd_next; | |
58 | } | |
59 | } | |
60 | ||
3807e26d AD |
61 | static __hc32 * |
62 | shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic, | |
63 | __hc32 tag) | |
64 | { | |
65 | switch (hc32_to_cpu(ehci, tag)) { | |
66 | /* our ehci_shadow.qh is actually software part */ | |
67 | case Q_TYPE_QH: | |
68 | return &periodic->qh->hw->hw_next; | |
69 | /* others are hw parts */ | |
70 | default: | |
71 | return periodic->hw_next; | |
72 | } | |
73 | } | |
74 | ||
1da177e4 LT |
75 | /* caller must hold ehci->lock */ |
76 | static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr) | |
77 | { | |
6dbd682b SR |
78 | union ehci_shadow *prev_p = &ehci->pshadow[frame]; |
79 | __hc32 *hw_p = &ehci->periodic[frame]; | |
1da177e4 LT |
80 | union ehci_shadow here = *prev_p; |
81 | ||
82 | /* find predecessor of "ptr"; hw and shadow lists are in sync */ | |
83 | while (here.ptr && here.ptr != ptr) { | |
6dbd682b SR |
84 | prev_p = periodic_next_shadow(ehci, prev_p, |
85 | Q_NEXT_TYPE(ehci, *hw_p)); | |
3807e26d AD |
86 | hw_p = shadow_next_periodic(ehci, &here, |
87 | Q_NEXT_TYPE(ehci, *hw_p)); | |
1da177e4 LT |
88 | here = *prev_p; |
89 | } | |
90 | /* an interrupt entry (at list end) could have been shared */ | |
91 | if (!here.ptr) | |
92 | return; | |
93 | ||
94 | /* update shadow and hardware lists ... the old "next" pointers | |
95 | * from ptr may still be in use, the caller updates them. | |
96 | */ | |
6dbd682b SR |
97 | *prev_p = *periodic_next_shadow(ehci, &here, |
98 | Q_NEXT_TYPE(ehci, *hw_p)); | |
3d091a6f AX |
99 | |
100 | if (!ehci->use_dummy_qh || | |
101 | *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p)) | |
102 | != EHCI_LIST_END(ehci)) | |
103 | *hw_p = *shadow_next_periodic(ehci, &here, | |
104 | Q_NEXT_TYPE(ehci, *hw_p)); | |
105 | else | |
106 | *hw_p = ehci->dummy->qh_dma; | |
1da177e4 LT |
107 | } |
108 | ||
109 | /* how many of the uframe's 125 usecs are allocated? */ | |
110 | static unsigned short | |
111 | periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe) | |
112 | { | |
6dbd682b | 113 | __hc32 *hw_p = &ehci->periodic [frame]; |
1da177e4 LT |
114 | union ehci_shadow *q = &ehci->pshadow [frame]; |
115 | unsigned usecs = 0; | |
3807e26d | 116 | struct ehci_qh_hw *hw; |
1da177e4 LT |
117 | |
118 | while (q->ptr) { | |
6dbd682b | 119 | switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) { |
1da177e4 | 120 | case Q_TYPE_QH: |
3807e26d | 121 | hw = q->qh->hw; |
1da177e4 | 122 | /* is it in the S-mask? */ |
3807e26d | 123 | if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe)) |
1da177e4 LT |
124 | usecs += q->qh->usecs; |
125 | /* ... or C-mask? */ | |
3807e26d | 126 | if (hw->hw_info2 & cpu_to_hc32(ehci, |
6dbd682b | 127 | 1 << (8 + uframe))) |
1da177e4 | 128 | usecs += q->qh->c_usecs; |
3807e26d | 129 | hw_p = &hw->hw_next; |
1da177e4 LT |
130 | q = &q->qh->qh_next; |
131 | break; | |
132 | // case Q_TYPE_FSTN: | |
133 | default: | |
134 | /* for "save place" FSTNs, count the relevant INTR | |
135 | * bandwidth from the previous frame | |
136 | */ | |
6dbd682b | 137 | if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) { |
1da177e4 LT |
138 | ehci_dbg (ehci, "ignoring FSTN cost ...\n"); |
139 | } | |
140 | hw_p = &q->fstn->hw_next; | |
141 | q = &q->fstn->fstn_next; | |
142 | break; | |
143 | case Q_TYPE_ITD: | |
3b6fcfd0 KW |
144 | if (q->itd->hw_transaction[uframe]) |
145 | usecs += q->itd->stream->usecs; | |
1da177e4 LT |
146 | hw_p = &q->itd->hw_next; |
147 | q = &q->itd->itd_next; | |
148 | break; | |
149 | case Q_TYPE_SITD: | |
150 | /* is it in the S-mask? (count SPLIT, DATA) */ | |
6dbd682b SR |
151 | if (q->sitd->hw_uframe & cpu_to_hc32(ehci, |
152 | 1 << uframe)) { | |
1da177e4 | 153 | if (q->sitd->hw_fullspeed_ep & |
6dbd682b | 154 | cpu_to_hc32(ehci, 1<<31)) |
1da177e4 LT |
155 | usecs += q->sitd->stream->usecs; |
156 | else /* worst case for OUT start-split */ | |
157 | usecs += HS_USECS_ISO (188); | |
158 | } | |
159 | ||
160 | /* ... C-mask? (count CSPLIT, DATA) */ | |
161 | if (q->sitd->hw_uframe & | |
6dbd682b | 162 | cpu_to_hc32(ehci, 1 << (8 + uframe))) { |
1da177e4 LT |
163 | /* worst case for IN complete-split */ |
164 | usecs += q->sitd->stream->c_usecs; | |
165 | } | |
166 | ||
167 | hw_p = &q->sitd->hw_next; | |
168 | q = &q->sitd->sitd_next; | |
169 | break; | |
170 | } | |
171 | } | |
172 | #ifdef DEBUG | |
cc62a7eb | 173 | if (usecs > ehci->uframe_periodic_max) |
1da177e4 LT |
174 | ehci_err (ehci, "uframe %d sched overrun: %d usecs\n", |
175 | frame * 8 + uframe, usecs); | |
176 | #endif | |
177 | return usecs; | |
178 | } | |
179 | ||
180 | /*-------------------------------------------------------------------------*/ | |
181 | ||
182 | static int same_tt (struct usb_device *dev1, struct usb_device *dev2) | |
183 | { | |
184 | if (!dev1->tt || !dev2->tt) | |
185 | return 0; | |
186 | if (dev1->tt != dev2->tt) | |
187 | return 0; | |
188 | if (dev1->tt->multi) | |
189 | return dev1->ttport == dev2->ttport; | |
190 | else | |
191 | return 1; | |
192 | } | |
193 | ||
ba47f66b DS |
194 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED |
195 | ||
196 | /* Which uframe does the low/fullspeed transfer start in? | |
197 | * | |
198 | * The parameter is the mask of ssplits in "H-frame" terms | |
199 | * and this returns the transfer start uframe in "B-frame" terms, | |
200 | * which allows both to match, e.g. a ssplit in "H-frame" uframe 0 | |
201 | * will cause a transfer in "B-frame" uframe 0. "B-frames" lag | |
202 | * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7. | |
203 | */ | |
6dbd682b | 204 | static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask) |
ba47f66b | 205 | { |
6dbd682b | 206 | unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask); |
ba47f66b DS |
207 | if (!smask) { |
208 | ehci_err(ehci, "invalid empty smask!\n"); | |
209 | /* uframe 7 can't have bw so this will indicate failure */ | |
210 | return 7; | |
211 | } | |
212 | return ffs(smask) - 1; | |
213 | } | |
214 | ||
215 | static const unsigned char | |
fdc03438 | 216 | max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 }; |
ba47f66b DS |
217 | |
218 | /* carryover low/fullspeed bandwidth that crosses uframe boundries */ | |
219 | static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8]) | |
220 | { | |
221 | int i; | |
222 | for (i=0; i<7; i++) { | |
223 | if (max_tt_usecs[i] < tt_usecs[i]) { | |
224 | tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i]; | |
225 | tt_usecs[i] = max_tt_usecs[i]; | |
226 | } | |
227 | } | |
228 | } | |
229 | ||
230 | /* How many of the tt's periodic downstream 1000 usecs are allocated? | |
231 | * | |
232 | * While this measures the bandwidth in terms of usecs/uframe, | |
233 | * the low/fullspeed bus has no notion of uframes, so any particular | |
234 | * low/fullspeed transfer can "carry over" from one uframe to the next, | |
235 | * since the TT just performs downstream transfers in sequence. | |
236 | * | |
dc0d5c1e | 237 | * For example two separate 100 usec transfers can start in the same uframe, |
ba47f66b DS |
238 | * and the second one would "carry over" 75 usecs into the next uframe. |
239 | */ | |
240 | static void | |
241 | periodic_tt_usecs ( | |
242 | struct ehci_hcd *ehci, | |
243 | struct usb_device *dev, | |
244 | unsigned frame, | |
245 | unsigned short tt_usecs[8] | |
246 | ) | |
247 | { | |
6dbd682b | 248 | __hc32 *hw_p = &ehci->periodic [frame]; |
ba47f66b DS |
249 | union ehci_shadow *q = &ehci->pshadow [frame]; |
250 | unsigned char uf; | |
251 | ||
252 | memset(tt_usecs, 0, 16); | |
253 | ||
254 | while (q->ptr) { | |
6dbd682b | 255 | switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) { |
ba47f66b DS |
256 | case Q_TYPE_ITD: |
257 | hw_p = &q->itd->hw_next; | |
258 | q = &q->itd->itd_next; | |
259 | continue; | |
260 | case Q_TYPE_QH: | |
261 | if (same_tt(dev, q->qh->dev)) { | |
3807e26d | 262 | uf = tt_start_uframe(ehci, q->qh->hw->hw_info2); |
ba47f66b DS |
263 | tt_usecs[uf] += q->qh->tt_usecs; |
264 | } | |
3807e26d | 265 | hw_p = &q->qh->hw->hw_next; |
ba47f66b DS |
266 | q = &q->qh->qh_next; |
267 | continue; | |
268 | case Q_TYPE_SITD: | |
269 | if (same_tt(dev, q->sitd->urb->dev)) { | |
270 | uf = tt_start_uframe(ehci, q->sitd->hw_uframe); | |
271 | tt_usecs[uf] += q->sitd->stream->tt_usecs; | |
272 | } | |
273 | hw_p = &q->sitd->hw_next; | |
274 | q = &q->sitd->sitd_next; | |
275 | continue; | |
276 | // case Q_TYPE_FSTN: | |
277 | default: | |
6dbd682b SR |
278 | ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n", |
279 | frame); | |
ba47f66b DS |
280 | hw_p = &q->fstn->hw_next; |
281 | q = &q->fstn->fstn_next; | |
282 | } | |
283 | } | |
284 | ||
285 | carryover_tt_bandwidth(tt_usecs); | |
286 | ||
287 | if (max_tt_usecs[7] < tt_usecs[7]) | |
288 | ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n", | |
289 | frame, tt_usecs[7] - max_tt_usecs[7]); | |
290 | } | |
291 | ||
292 | /* | |
293 | * Return true if the device's tt's downstream bus is available for a | |
294 | * periodic transfer of the specified length (usecs), starting at the | |
295 | * specified frame/uframe. Note that (as summarized in section 11.19 | |
296 | * of the usb 2.0 spec) TTs can buffer multiple transactions for each | |
297 | * uframe. | |
298 | * | |
299 | * The uframe parameter is when the fullspeed/lowspeed transfer | |
300 | * should be executed in "B-frame" terms, which is the same as the | |
301 | * highspeed ssplit's uframe (which is in "H-frame" terms). For example | |
302 | * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0. | |
303 | * See the EHCI spec sec 4.5 and fig 4.7. | |
304 | * | |
305 | * This checks if the full/lowspeed bus, at the specified starting uframe, | |
306 | * has the specified bandwidth available, according to rules listed | |
307 | * in USB 2.0 spec section 11.18.1 fig 11-60. | |
308 | * | |
309 | * This does not check if the transfer would exceed the max ssplit | |
310 | * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4, | |
311 | * since proper scheduling limits ssplits to less than 16 per uframe. | |
312 | */ | |
313 | static int tt_available ( | |
314 | struct ehci_hcd *ehci, | |
315 | unsigned period, | |
316 | struct usb_device *dev, | |
317 | unsigned frame, | |
318 | unsigned uframe, | |
319 | u16 usecs | |
320 | ) | |
321 | { | |
322 | if ((period == 0) || (uframe >= 7)) /* error */ | |
323 | return 0; | |
324 | ||
325 | for (; frame < ehci->periodic_size; frame += period) { | |
326 | unsigned short tt_usecs[8]; | |
327 | ||
328 | periodic_tt_usecs (ehci, dev, frame, tt_usecs); | |
329 | ||
330 | ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in" | |
331 | " schedule %d/%d/%d/%d/%d/%d/%d/%d\n", | |
332 | frame, usecs, uframe, | |
333 | tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3], | |
334 | tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]); | |
335 | ||
336 | if (max_tt_usecs[uframe] <= tt_usecs[uframe]) { | |
337 | ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n", | |
338 | frame, uframe); | |
339 | return 0; | |
340 | } | |
341 | ||
342 | /* special case for isoc transfers larger than 125us: | |
343 | * the first and each subsequent fully used uframe | |
344 | * must be empty, so as to not illegally delay | |
345 | * already scheduled transactions | |
346 | */ | |
347 | if (125 < usecs) { | |
c065c60e | 348 | int ufs = (usecs / 125); |
ba47f66b DS |
349 | int i; |
350 | for (i = uframe; i < (uframe + ufs) && i < 8; i++) | |
351 | if (0 < tt_usecs[i]) { | |
352 | ehci_vdbg(ehci, | |
353 | "multi-uframe xfer can't fit " | |
354 | "in frame %d uframe %d\n", | |
355 | frame, i); | |
356 | return 0; | |
357 | } | |
358 | } | |
359 | ||
360 | tt_usecs[uframe] += usecs; | |
361 | ||
362 | carryover_tt_bandwidth(tt_usecs); | |
363 | ||
364 | /* fail if the carryover pushed bw past the last uframe's limit */ | |
365 | if (max_tt_usecs[7] < tt_usecs[7]) { | |
366 | ehci_vdbg(ehci, | |
367 | "tt unavailable usecs %d frame %d uframe %d\n", | |
368 | usecs, frame, uframe); | |
369 | return 0; | |
370 | } | |
371 | } | |
372 | ||
373 | return 1; | |
374 | } | |
375 | ||
376 | #else | |
377 | ||
1da177e4 LT |
378 | /* return true iff the device's transaction translator is available |
379 | * for a periodic transfer starting at the specified frame, using | |
380 | * all the uframes in the mask. | |
381 | */ | |
382 | static int tt_no_collision ( | |
383 | struct ehci_hcd *ehci, | |
384 | unsigned period, | |
385 | struct usb_device *dev, | |
386 | unsigned frame, | |
387 | u32 uf_mask | |
388 | ) | |
389 | { | |
390 | if (period == 0) /* error */ | |
391 | return 0; | |
392 | ||
393 | /* note bandwidth wastage: split never follows csplit | |
394 | * (different dev or endpoint) until the next uframe. | |
395 | * calling convention doesn't make that distinction. | |
396 | */ | |
397 | for (; frame < ehci->periodic_size; frame += period) { | |
398 | union ehci_shadow here; | |
6dbd682b | 399 | __hc32 type; |
3807e26d | 400 | struct ehci_qh_hw *hw; |
1da177e4 LT |
401 | |
402 | here = ehci->pshadow [frame]; | |
6dbd682b | 403 | type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]); |
1da177e4 | 404 | while (here.ptr) { |
6dbd682b | 405 | switch (hc32_to_cpu(ehci, type)) { |
1da177e4 | 406 | case Q_TYPE_ITD: |
6dbd682b | 407 | type = Q_NEXT_TYPE(ehci, here.itd->hw_next); |
1da177e4 LT |
408 | here = here.itd->itd_next; |
409 | continue; | |
410 | case Q_TYPE_QH: | |
3807e26d | 411 | hw = here.qh->hw; |
1da177e4 LT |
412 | if (same_tt (dev, here.qh->dev)) { |
413 | u32 mask; | |
414 | ||
6dbd682b | 415 | mask = hc32_to_cpu(ehci, |
3807e26d | 416 | hw->hw_info2); |
1da177e4 LT |
417 | /* "knows" no gap is needed */ |
418 | mask |= mask >> 8; | |
419 | if (mask & uf_mask) | |
420 | break; | |
421 | } | |
3807e26d | 422 | type = Q_NEXT_TYPE(ehci, hw->hw_next); |
1da177e4 LT |
423 | here = here.qh->qh_next; |
424 | continue; | |
425 | case Q_TYPE_SITD: | |
426 | if (same_tt (dev, here.sitd->urb->dev)) { | |
427 | u16 mask; | |
428 | ||
6dbd682b | 429 | mask = hc32_to_cpu(ehci, here.sitd |
1da177e4 LT |
430 | ->hw_uframe); |
431 | /* FIXME assumes no gap for IN! */ | |
432 | mask |= mask >> 8; | |
433 | if (mask & uf_mask) | |
434 | break; | |
435 | } | |
6dbd682b | 436 | type = Q_NEXT_TYPE(ehci, here.sitd->hw_next); |
1da177e4 LT |
437 | here = here.sitd->sitd_next; |
438 | continue; | |
439 | // case Q_TYPE_FSTN: | |
440 | default: | |
441 | ehci_dbg (ehci, | |
442 | "periodic frame %d bogus type %d\n", | |
443 | frame, type); | |
444 | } | |
445 | ||
446 | /* collision or error */ | |
447 | return 0; | |
448 | } | |
449 | } | |
450 | ||
451 | /* no collision */ | |
452 | return 1; | |
453 | } | |
454 | ||
ba47f66b DS |
455 | #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */ |
456 | ||
1da177e4 LT |
457 | /*-------------------------------------------------------------------------*/ |
458 | ||
b015cb79 | 459 | static void enable_periodic(struct ehci_hcd *ehci) |
1da177e4 | 460 | { |
3ca9aeba | 461 | if (ehci->periodic_count++) |
b015cb79 | 462 | return; |
01c17142 | 463 | |
3ca9aeba AS |
464 | /* Stop waiting to turn off the periodic schedule */ |
465 | ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_PERIODIC); | |
1da177e4 | 466 | |
3ca9aeba AS |
467 | /* Don't start the schedule until PSS is 0 */ |
468 | ehci_poll_PSS(ehci); | |
18aafe64 | 469 | turn_on_io_watchdog(ehci); |
1da177e4 LT |
470 | } |
471 | ||
b015cb79 | 472 | static void disable_periodic(struct ehci_hcd *ehci) |
1da177e4 | 473 | { |
3ca9aeba | 474 | if (--ehci->periodic_count) |
b015cb79 | 475 | return; |
01c17142 | 476 | |
3ca9aeba AS |
477 | /* Don't turn off the schedule until PSS is 1 */ |
478 | ehci_poll_PSS(ehci); | |
1da177e4 LT |
479 | } |
480 | ||
481 | /*-------------------------------------------------------------------------*/ | |
482 | ||
483 | /* periodic schedule slots have iso tds (normal or split) first, then a | |
484 | * sparse tree for active interrupt transfers. | |
485 | * | |
486 | * this just links in a qh; caller guarantees uframe masks are set right. | |
487 | * no FSTN support (yet; ehci 0.96+) | |
488 | */ | |
b015cb79 | 489 | static void qh_link_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 LT |
490 | { |
491 | unsigned i; | |
492 | unsigned period = qh->period; | |
493 | ||
494 | dev_dbg (&qh->dev->dev, | |
495 | "link qh%d-%04x/%p start %d [%d/%d us]\n", | |
3807e26d AD |
496 | period, hc32_to_cpup(ehci, &qh->hw->hw_info2) |
497 | & (QH_CMASK | QH_SMASK), | |
1da177e4 LT |
498 | qh, qh->start, qh->usecs, qh->c_usecs); |
499 | ||
500 | /* high bandwidth, or otherwise every microframe */ | |
501 | if (period == 0) | |
502 | period = 1; | |
503 | ||
504 | for (i = qh->start; i < ehci->periodic_size; i += period) { | |
6dbd682b SR |
505 | union ehci_shadow *prev = &ehci->pshadow[i]; |
506 | __hc32 *hw_p = &ehci->periodic[i]; | |
1da177e4 | 507 | union ehci_shadow here = *prev; |
6dbd682b | 508 | __hc32 type = 0; |
1da177e4 LT |
509 | |
510 | /* skip the iso nodes at list head */ | |
511 | while (here.ptr) { | |
6dbd682b SR |
512 | type = Q_NEXT_TYPE(ehci, *hw_p); |
513 | if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) | |
1da177e4 | 514 | break; |
6dbd682b | 515 | prev = periodic_next_shadow(ehci, prev, type); |
3807e26d | 516 | hw_p = shadow_next_periodic(ehci, &here, type); |
1da177e4 LT |
517 | here = *prev; |
518 | } | |
519 | ||
520 | /* sorting each branch by period (slow-->fast) | |
521 | * enables sharing interior tree nodes | |
522 | */ | |
523 | while (here.ptr && qh != here.qh) { | |
524 | if (qh->period > here.qh->period) | |
525 | break; | |
526 | prev = &here.qh->qh_next; | |
3807e26d | 527 | hw_p = &here.qh->hw->hw_next; |
1da177e4 LT |
528 | here = *prev; |
529 | } | |
530 | /* link in this qh, unless some earlier pass did that */ | |
531 | if (qh != here.qh) { | |
532 | qh->qh_next = here; | |
533 | if (here.qh) | |
3807e26d | 534 | qh->hw->hw_next = *hw_p; |
1da177e4 LT |
535 | wmb (); |
536 | prev->qh = qh; | |
6dbd682b | 537 | *hw_p = QH_NEXT (ehci, qh->qh_dma); |
1da177e4 LT |
538 | } |
539 | } | |
540 | qh->qh_state = QH_STATE_LINKED; | |
ef4638f9 | 541 | qh->xacterrs = 0; |
7bc782d7 | 542 | qh->exception = 0; |
1da177e4 LT |
543 | |
544 | /* update per-qh bandwidth for usbfs */ | |
545 | ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period | |
546 | ? ((qh->usecs + qh->c_usecs) / qh->period) | |
547 | : (qh->usecs * 8); | |
548 | ||
569b394f AS |
549 | list_add(&qh->intr_node, &ehci->intr_qh_list); |
550 | ||
1da177e4 | 551 | /* maybe enable periodic schedule processing */ |
569b394f | 552 | ++ehci->intr_count; |
b015cb79 | 553 | enable_periodic(ehci); |
1da177e4 LT |
554 | } |
555 | ||
b015cb79 | 556 | static void qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 LT |
557 | { |
558 | unsigned i; | |
559 | unsigned period; | |
560 | ||
df202255 AS |
561 | /* |
562 | * If qh is for a low/full-speed device, simply unlinking it | |
563 | * could interfere with an ongoing split transaction. To unlink | |
564 | * it safely would require setting the QH_INACTIVATE bit and | |
565 | * waiting at least one frame, as described in EHCI 4.12.2.5. | |
566 | * | |
567 | * We won't bother with any of this. Instead, we assume that the | |
568 | * only reason for unlinking an interrupt QH while the current URB | |
569 | * is still active is to dequeue all the URBs (flush the whole | |
570 | * endpoint queue). | |
571 | * | |
572 | * If rebalancing the periodic schedule is ever implemented, this | |
573 | * approach will no longer be valid. | |
574 | */ | |
1da177e4 LT |
575 | |
576 | /* high bandwidth, or otherwise part of every microframe */ | |
577 | if ((period = qh->period) == 0) | |
578 | period = 1; | |
579 | ||
580 | for (i = qh->start; i < ehci->periodic_size; i += period) | |
581 | periodic_unlink (ehci, i, qh); | |
582 | ||
583 | /* update per-qh bandwidth for usbfs */ | |
584 | ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period | |
585 | ? ((qh->usecs + qh->c_usecs) / qh->period) | |
586 | : (qh->usecs * 8); | |
587 | ||
588 | dev_dbg (&qh->dev->dev, | |
589 | "unlink qh%d-%04x/%p start %d [%d/%d us]\n", | |
7dedacf4 | 590 | qh->period, |
3807e26d | 591 | hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK), |
1da177e4 LT |
592 | qh, qh->start, qh->usecs, qh->c_usecs); |
593 | ||
594 | /* qh->qh_next still "live" to HC */ | |
595 | qh->qh_state = QH_STATE_UNLINK; | |
596 | qh->qh_next.ptr = NULL; | |
569b394f AS |
597 | |
598 | if (ehci->qh_scan_next == qh) | |
599 | ehci->qh_scan_next = list_entry(qh->intr_node.next, | |
600 | struct ehci_qh, intr_node); | |
601 | list_del(&qh->intr_node); | |
1da177e4 LT |
602 | } |
603 | ||
df202255 | 604 | static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 | 605 | { |
7bc782d7 AS |
606 | /* If the QH isn't linked then there's nothing we can do. */ |
607 | if (qh->qh_state != QH_STATE_LINKED) | |
a448c9d8 | 608 | return; |
1da177e4 LT |
609 | |
610 | qh_unlink_periodic (ehci, qh); | |
611 | ||
df202255 AS |
612 | /* Make sure the unlinks are visible before starting the timer */ |
613 | wmb(); | |
614 | ||
615 | /* | |
616 | * The EHCI spec doesn't say how long it takes the controller to | |
617 | * stop accessing an unlinked interrupt QH. The timer delay is | |
618 | * 9 uframes; presumably that will be long enough. | |
1da177e4 | 619 | */ |
df202255 AS |
620 | qh->unlink_cycle = ehci->intr_unlink_cycle; |
621 | ||
622 | /* New entries go at the end of the intr_unlink list */ | |
6e018751 | 623 | list_add_tail(&qh->unlink_node, &ehci->intr_unlink); |
df202255 AS |
624 | |
625 | if (ehci->intr_unlinking) | |
626 | ; /* Avoid recursive calls */ | |
627 | else if (ehci->rh_state < EHCI_RH_RUNNING) | |
628 | ehci_handle_intr_unlinks(ehci); | |
6e018751 | 629 | else if (ehci->intr_unlink.next == &qh->unlink_node) { |
df202255 AS |
630 | ehci_enable_event(ehci, EHCI_HRTIMER_UNLINK_INTR, true); |
631 | ++ehci->intr_unlink_cycle; | |
632 | } | |
633 | } | |
634 | ||
635 | static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh) | |
636 | { | |
637 | struct ehci_qh_hw *hw = qh->hw; | |
638 | int rc; | |
1da177e4 | 639 | |
1da177e4 | 640 | qh->qh_state = QH_STATE_IDLE; |
3807e26d | 641 | hw->hw_next = EHCI_LIST_END(ehci); |
a448c9d8 | 642 | |
79bcf7b0 AS |
643 | if (!list_empty(&qh->qtd_list)) |
644 | qh_completions(ehci, qh); | |
a448c9d8 AS |
645 | |
646 | /* reschedule QH iff another request is queued */ | |
df202255 | 647 | if (!list_empty(&qh->qtd_list) && ehci->rh_state == EHCI_RH_RUNNING) { |
a448c9d8 | 648 | rc = qh_schedule(ehci, qh); |
077f5f1c AS |
649 | if (rc == 0) { |
650 | qh_refresh(ehci, qh); | |
651 | qh_link_periodic(ehci, qh); | |
652 | } | |
a448c9d8 AS |
653 | |
654 | /* An error here likely indicates handshake failure | |
655 | * or no space left in the schedule. Neither fault | |
656 | * should happen often ... | |
657 | * | |
658 | * FIXME kill the now-dysfunctional queued urbs | |
659 | */ | |
077f5f1c | 660 | else { |
a448c9d8 AS |
661 | ehci_err(ehci, "can't reschedule qh %p, err %d\n", |
662 | qh, rc); | |
077f5f1c | 663 | } |
a448c9d8 | 664 | } |
3ca9aeba AS |
665 | |
666 | /* maybe turn off periodic schedule */ | |
569b394f | 667 | --ehci->intr_count; |
3ca9aeba | 668 | disable_periodic(ehci); |
1da177e4 LT |
669 | } |
670 | ||
671 | /*-------------------------------------------------------------------------*/ | |
672 | ||
673 | static int check_period ( | |
53bd6a60 | 674 | struct ehci_hcd *ehci, |
1da177e4 LT |
675 | unsigned frame, |
676 | unsigned uframe, | |
677 | unsigned period, | |
678 | unsigned usecs | |
679 | ) { | |
680 | int claimed; | |
681 | ||
682 | /* complete split running into next frame? | |
683 | * given FSTN support, we could sometimes check... | |
684 | */ | |
685 | if (uframe >= 8) | |
686 | return 0; | |
687 | ||
cc62a7eb KS |
688 | /* convert "usecs we need" to "max already claimed" */ |
689 | usecs = ehci->uframe_periodic_max - usecs; | |
1da177e4 LT |
690 | |
691 | /* we "know" 2 and 4 uframe intervals were rejected; so | |
692 | * for period 0, check _every_ microframe in the schedule. | |
693 | */ | |
694 | if (unlikely (period == 0)) { | |
695 | do { | |
696 | for (uframe = 0; uframe < 7; uframe++) { | |
697 | claimed = periodic_usecs (ehci, frame, uframe); | |
698 | if (claimed > usecs) | |
699 | return 0; | |
700 | } | |
701 | } while ((frame += 1) < ehci->periodic_size); | |
702 | ||
703 | /* just check the specified uframe, at that period */ | |
704 | } else { | |
705 | do { | |
706 | claimed = periodic_usecs (ehci, frame, uframe); | |
707 | if (claimed > usecs) | |
708 | return 0; | |
709 | } while ((frame += period) < ehci->periodic_size); | |
710 | } | |
711 | ||
712 | // success! | |
713 | return 1; | |
714 | } | |
715 | ||
716 | static int check_intr_schedule ( | |
53bd6a60 | 717 | struct ehci_hcd *ehci, |
1da177e4 LT |
718 | unsigned frame, |
719 | unsigned uframe, | |
720 | const struct ehci_qh *qh, | |
6dbd682b | 721 | __hc32 *c_maskp |
1da177e4 LT |
722 | ) |
723 | { | |
53bd6a60 | 724 | int retval = -ENOSPC; |
ba47f66b | 725 | u8 mask = 0; |
1da177e4 LT |
726 | |
727 | if (qh->c_usecs && uframe >= 6) /* FSTN territory? */ | |
728 | goto done; | |
729 | ||
730 | if (!check_period (ehci, frame, uframe, qh->period, qh->usecs)) | |
731 | goto done; | |
732 | if (!qh->c_usecs) { | |
733 | retval = 0; | |
734 | *c_maskp = 0; | |
735 | goto done; | |
736 | } | |
737 | ||
ba47f66b DS |
738 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED |
739 | if (tt_available (ehci, qh->period, qh->dev, frame, uframe, | |
740 | qh->tt_usecs)) { | |
741 | unsigned i; | |
742 | ||
743 | /* TODO : this may need FSTN for SSPLIT in uframe 5. */ | |
744 | for (i=uframe+1; i<8 && i<uframe+4; i++) | |
745 | if (!check_period (ehci, frame, i, | |
746 | qh->period, qh->c_usecs)) | |
747 | goto done; | |
748 | else | |
749 | mask |= 1 << i; | |
750 | ||
751 | retval = 0; | |
752 | ||
6dbd682b | 753 | *c_maskp = cpu_to_hc32(ehci, mask << 8); |
ba47f66b DS |
754 | } |
755 | #else | |
1da177e4 LT |
756 | /* Make sure this tt's buffer is also available for CSPLITs. |
757 | * We pessimize a bit; probably the typical full speed case | |
758 | * doesn't need the second CSPLIT. | |
53bd6a60 | 759 | * |
1da177e4 LT |
760 | * NOTE: both SPLIT and CSPLIT could be checked in just |
761 | * one smart pass... | |
762 | */ | |
763 | mask = 0x03 << (uframe + qh->gap_uf); | |
6dbd682b | 764 | *c_maskp = cpu_to_hc32(ehci, mask << 8); |
1da177e4 LT |
765 | |
766 | mask |= 1 << uframe; | |
767 | if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) { | |
768 | if (!check_period (ehci, frame, uframe + qh->gap_uf + 1, | |
769 | qh->period, qh->c_usecs)) | |
770 | goto done; | |
771 | if (!check_period (ehci, frame, uframe + qh->gap_uf, | |
772 | qh->period, qh->c_usecs)) | |
773 | goto done; | |
774 | retval = 0; | |
775 | } | |
ba47f66b | 776 | #endif |
1da177e4 LT |
777 | done: |
778 | return retval; | |
779 | } | |
780 | ||
781 | /* "first fit" scheduling policy used the first time through, | |
782 | * or when the previous schedule slot can't be re-used. | |
783 | */ | |
6dbd682b | 784 | static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 | 785 | { |
53bd6a60 | 786 | int status; |
1da177e4 | 787 | unsigned uframe; |
6dbd682b | 788 | __hc32 c_mask; |
1da177e4 | 789 | unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */ |
3807e26d | 790 | struct ehci_qh_hw *hw = qh->hw; |
1da177e4 | 791 | |
3807e26d | 792 | hw->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
793 | frame = qh->start; |
794 | ||
795 | /* reuse the previous schedule slots, if we can */ | |
796 | if (frame < qh->period) { | |
3807e26d | 797 | uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK); |
1da177e4 LT |
798 | status = check_intr_schedule (ehci, frame, --uframe, |
799 | qh, &c_mask); | |
800 | } else { | |
801 | uframe = 0; | |
802 | c_mask = 0; | |
803 | status = -ENOSPC; | |
804 | } | |
805 | ||
806 | /* else scan the schedule to find a group of slots such that all | |
807 | * uframes have enough periodic bandwidth available. | |
808 | */ | |
809 | if (status) { | |
810 | /* "normal" case, uframing flexible except with splits */ | |
811 | if (qh->period) { | |
68335e81 AS |
812 | int i; |
813 | ||
814 | for (i = qh->period; status && i > 0; --i) { | |
815 | frame = ++ehci->random_frame % qh->period; | |
1da177e4 LT |
816 | for (uframe = 0; uframe < 8; uframe++) { |
817 | status = check_intr_schedule (ehci, | |
818 | frame, uframe, qh, | |
819 | &c_mask); | |
820 | if (status == 0) | |
821 | break; | |
822 | } | |
68335e81 | 823 | } |
1da177e4 LT |
824 | |
825 | /* qh->period == 0 means every uframe */ | |
826 | } else { | |
827 | frame = 0; | |
828 | status = check_intr_schedule (ehci, 0, 0, qh, &c_mask); | |
829 | } | |
830 | if (status) | |
831 | goto done; | |
832 | qh->start = frame; | |
833 | ||
834 | /* reset S-frame and (maybe) C-frame masks */ | |
3807e26d AD |
835 | hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK)); |
836 | hw->hw_info2 |= qh->period | |
6dbd682b SR |
837 | ? cpu_to_hc32(ehci, 1 << uframe) |
838 | : cpu_to_hc32(ehci, QH_SMASK); | |
3807e26d | 839 | hw->hw_info2 |= c_mask; |
1da177e4 LT |
840 | } else |
841 | ehci_dbg (ehci, "reused qh %p schedule\n", qh); | |
842 | ||
1da177e4 LT |
843 | done: |
844 | return status; | |
845 | } | |
846 | ||
847 | static int intr_submit ( | |
848 | struct ehci_hcd *ehci, | |
1da177e4 LT |
849 | struct urb *urb, |
850 | struct list_head *qtd_list, | |
55016f10 | 851 | gfp_t mem_flags |
1da177e4 LT |
852 | ) { |
853 | unsigned epnum; | |
854 | unsigned long flags; | |
855 | struct ehci_qh *qh; | |
e9df41c5 | 856 | int status; |
1da177e4 LT |
857 | struct list_head empty; |
858 | ||
859 | /* get endpoint and transfer/schedule data */ | |
e9df41c5 | 860 | epnum = urb->ep->desc.bEndpointAddress; |
1da177e4 LT |
861 | |
862 | spin_lock_irqsave (&ehci->lock, flags); | |
863 | ||
541c7d43 | 864 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 865 | status = -ESHUTDOWN; |
e9df41c5 | 866 | goto done_not_linked; |
8de98402 | 867 | } |
e9df41c5 AS |
868 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); |
869 | if (unlikely(status)) | |
870 | goto done_not_linked; | |
8de98402 | 871 | |
1da177e4 LT |
872 | /* get qh and force any scheduling errors */ |
873 | INIT_LIST_HEAD (&empty); | |
e9df41c5 | 874 | qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv); |
1da177e4 LT |
875 | if (qh == NULL) { |
876 | status = -ENOMEM; | |
877 | goto done; | |
878 | } | |
879 | if (qh->qh_state == QH_STATE_IDLE) { | |
880 | if ((status = qh_schedule (ehci, qh)) != 0) | |
881 | goto done; | |
882 | } | |
883 | ||
884 | /* then queue the urb's tds to the qh */ | |
e9df41c5 | 885 | qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); |
1da177e4 LT |
886 | BUG_ON (qh == NULL); |
887 | ||
c1fdb68e AS |
888 | /* stuff into the periodic schedule */ |
889 | if (qh->qh_state == QH_STATE_IDLE) { | |
890 | qh_refresh(ehci, qh); | |
891 | qh_link_periodic(ehci, qh); | |
892 | } | |
893 | ||
1da177e4 LT |
894 | /* ... update usbfs periodic stats */ |
895 | ehci_to_hcd(ehci)->self.bandwidth_int_reqs++; | |
896 | ||
897 | done: | |
e9df41c5 AS |
898 | if (unlikely(status)) |
899 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
900 | done_not_linked: | |
1da177e4 LT |
901 | spin_unlock_irqrestore (&ehci->lock, flags); |
902 | if (status) | |
903 | qtd_list_free (ehci, urb, qtd_list); | |
904 | ||
905 | return status; | |
906 | } | |
907 | ||
569b394f AS |
908 | static void scan_intr(struct ehci_hcd *ehci) |
909 | { | |
910 | struct ehci_qh *qh; | |
911 | ||
912 | list_for_each_entry_safe(qh, ehci->qh_scan_next, &ehci->intr_qh_list, | |
913 | intr_node) { | |
79bcf7b0 | 914 | |
569b394f AS |
915 | /* clean any finished work for this qh */ |
916 | if (!list_empty(&qh->qtd_list)) { | |
917 | int temp; | |
918 | ||
919 | /* | |
920 | * Unlinks could happen here; completion reporting | |
921 | * drops the lock. That's why ehci->qh_scan_next | |
922 | * always holds the next qh to scan; if the next qh | |
923 | * gets unlinked then ehci->qh_scan_next is adjusted | |
924 | * in qh_unlink_periodic(). | |
925 | */ | |
926 | temp = qh_completions(ehci, qh); | |
79bcf7b0 AS |
927 | if (unlikely(temp || (list_empty(&qh->qtd_list) && |
928 | qh->qh_state == QH_STATE_LINKED))) | |
569b394f | 929 | start_unlink_intr(ehci, qh); |
569b394f AS |
930 | } |
931 | } | |
932 | } | |
933 | ||
1da177e4 LT |
934 | /*-------------------------------------------------------------------------*/ |
935 | ||
936 | /* ehci_iso_stream ops work with both ITD and SITD */ | |
937 | ||
938 | static struct ehci_iso_stream * | |
55016f10 | 939 | iso_stream_alloc (gfp_t mem_flags) |
1da177e4 LT |
940 | { |
941 | struct ehci_iso_stream *stream; | |
942 | ||
7b842b6e | 943 | stream = kzalloc(sizeof *stream, mem_flags); |
1da177e4 | 944 | if (likely (stream != NULL)) { |
1da177e4 LT |
945 | INIT_LIST_HEAD(&stream->td_list); |
946 | INIT_LIST_HEAD(&stream->free_list); | |
947 | stream->next_uframe = -1; | |
1da177e4 LT |
948 | } |
949 | return stream; | |
950 | } | |
951 | ||
952 | static void | |
953 | iso_stream_init ( | |
954 | struct ehci_hcd *ehci, | |
955 | struct ehci_iso_stream *stream, | |
956 | struct usb_device *dev, | |
957 | int pipe, | |
958 | unsigned interval | |
959 | ) | |
960 | { | |
961 | static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f }; | |
962 | ||
963 | u32 buf1; | |
964 | unsigned epnum, maxp; | |
965 | int is_input; | |
966 | long bandwidth; | |
967 | ||
968 | /* | |
969 | * this might be a "high bandwidth" highspeed endpoint, | |
970 | * as encoded in the ep descriptor's wMaxPacket field | |
971 | */ | |
972 | epnum = usb_pipeendpoint (pipe); | |
973 | is_input = usb_pipein (pipe) ? USB_DIR_IN : 0; | |
974 | maxp = usb_maxpacket(dev, pipe, !is_input); | |
975 | if (is_input) { | |
976 | buf1 = (1 << 11); | |
977 | } else { | |
978 | buf1 = 0; | |
979 | } | |
980 | ||
981 | /* knows about ITD vs SITD */ | |
982 | if (dev->speed == USB_SPEED_HIGH) { | |
983 | unsigned multi = hb_mult(maxp); | |
984 | ||
985 | stream->highspeed = 1; | |
986 | ||
987 | maxp = max_packet(maxp); | |
988 | buf1 |= maxp; | |
989 | maxp *= multi; | |
990 | ||
6dbd682b SR |
991 | stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum); |
992 | stream->buf1 = cpu_to_hc32(ehci, buf1); | |
993 | stream->buf2 = cpu_to_hc32(ehci, multi); | |
1da177e4 LT |
994 | |
995 | /* usbfs wants to report the average usecs per frame tied up | |
996 | * when transfers on this endpoint are scheduled ... | |
997 | */ | |
998 | stream->usecs = HS_USECS_ISO (maxp); | |
999 | bandwidth = stream->usecs * 8; | |
372dd6e8 | 1000 | bandwidth /= interval; |
1da177e4 LT |
1001 | |
1002 | } else { | |
1003 | u32 addr; | |
d0384200 | 1004 | int think_time; |
469d0229 | 1005 | int hs_transfers; |
1da177e4 LT |
1006 | |
1007 | addr = dev->ttport << 24; | |
1008 | if (!ehci_is_TDI(ehci) | |
1009 | || (dev->tt->hub != | |
1010 | ehci_to_hcd(ehci)->self.root_hub)) | |
1011 | addr |= dev->tt->hub->devnum << 16; | |
1012 | addr |= epnum << 8; | |
1013 | addr |= dev->devnum; | |
1014 | stream->usecs = HS_USECS_ISO (maxp); | |
d0384200 | 1015 | think_time = dev->tt ? dev->tt->think_time : 0; |
1016 | stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time ( | |
1017 | dev->speed, is_input, 1, maxp)); | |
469d0229 | 1018 | hs_transfers = max (1u, (maxp + 187) / 188); |
1da177e4 LT |
1019 | if (is_input) { |
1020 | u32 tmp; | |
1021 | ||
1022 | addr |= 1 << 31; | |
1023 | stream->c_usecs = stream->usecs; | |
1024 | stream->usecs = HS_USECS_ISO (1); | |
1025 | stream->raw_mask = 1; | |
1026 | ||
469d0229 CL |
1027 | /* c-mask as specified in USB 2.0 11.18.4 3.c */ |
1028 | tmp = (1 << (hs_transfers + 2)) - 1; | |
1029 | stream->raw_mask |= tmp << (8 + 2); | |
1da177e4 | 1030 | } else |
469d0229 | 1031 | stream->raw_mask = smask_out [hs_transfers - 1]; |
1da177e4 | 1032 | bandwidth = stream->usecs + stream->c_usecs; |
372dd6e8 | 1033 | bandwidth /= interval << 3; |
1da177e4 LT |
1034 | |
1035 | /* stream->splits gets created from raw_mask later */ | |
6dbd682b | 1036 | stream->address = cpu_to_hc32(ehci, addr); |
1da177e4 LT |
1037 | } |
1038 | stream->bandwidth = bandwidth; | |
1039 | ||
1040 | stream->udev = dev; | |
1041 | ||
1042 | stream->bEndpointAddress = is_input | epnum; | |
1043 | stream->interval = interval; | |
1044 | stream->maxp = maxp; | |
1045 | } | |
1046 | ||
1da177e4 LT |
1047 | static struct ehci_iso_stream * |
1048 | iso_stream_find (struct ehci_hcd *ehci, struct urb *urb) | |
1049 | { | |
1050 | unsigned epnum; | |
1051 | struct ehci_iso_stream *stream; | |
1052 | struct usb_host_endpoint *ep; | |
1053 | unsigned long flags; | |
1054 | ||
1055 | epnum = usb_pipeendpoint (urb->pipe); | |
1056 | if (usb_pipein(urb->pipe)) | |
1057 | ep = urb->dev->ep_in[epnum]; | |
1058 | else | |
1059 | ep = urb->dev->ep_out[epnum]; | |
1060 | ||
1061 | spin_lock_irqsave (&ehci->lock, flags); | |
1062 | stream = ep->hcpriv; | |
1063 | ||
1064 | if (unlikely (stream == NULL)) { | |
1065 | stream = iso_stream_alloc(GFP_ATOMIC); | |
1066 | if (likely (stream != NULL)) { | |
1da177e4 LT |
1067 | ep->hcpriv = stream; |
1068 | stream->ep = ep; | |
1069 | iso_stream_init(ehci, stream, urb->dev, urb->pipe, | |
1070 | urb->interval); | |
1071 | } | |
1072 | ||
1082f57a CL |
1073 | /* if dev->ep [epnum] is a QH, hw is set */ |
1074 | } else if (unlikely (stream->hw != NULL)) { | |
1da177e4 LT |
1075 | ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n", |
1076 | urb->dev->devpath, epnum, | |
1077 | usb_pipein(urb->pipe) ? "in" : "out"); | |
1078 | stream = NULL; | |
1079 | } | |
1080 | ||
1da177e4 LT |
1081 | spin_unlock_irqrestore (&ehci->lock, flags); |
1082 | return stream; | |
1083 | } | |
1084 | ||
1085 | /*-------------------------------------------------------------------------*/ | |
1086 | ||
1087 | /* ehci_iso_sched ops can be ITD-only or SITD-only */ | |
1088 | ||
1089 | static struct ehci_iso_sched * | |
55016f10 | 1090 | iso_sched_alloc (unsigned packets, gfp_t mem_flags) |
1da177e4 LT |
1091 | { |
1092 | struct ehci_iso_sched *iso_sched; | |
1093 | int size = sizeof *iso_sched; | |
1094 | ||
1095 | size += packets * sizeof (struct ehci_iso_packet); | |
80b6ca48 | 1096 | iso_sched = kzalloc(size, mem_flags); |
1da177e4 | 1097 | if (likely (iso_sched != NULL)) { |
1da177e4 LT |
1098 | INIT_LIST_HEAD (&iso_sched->td_list); |
1099 | } | |
1100 | return iso_sched; | |
1101 | } | |
1102 | ||
1103 | static inline void | |
6dbd682b SR |
1104 | itd_sched_init( |
1105 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1106 | struct ehci_iso_sched *iso_sched, |
1107 | struct ehci_iso_stream *stream, | |
1108 | struct urb *urb | |
1109 | ) | |
1110 | { | |
1111 | unsigned i; | |
1112 | dma_addr_t dma = urb->transfer_dma; | |
1113 | ||
1114 | /* how many uframes are needed for these transfers */ | |
1115 | iso_sched->span = urb->number_of_packets * stream->interval; | |
1116 | ||
1117 | /* figure out per-uframe itd fields that we'll need later | |
1118 | * when we fit new itds into the schedule. | |
1119 | */ | |
1120 | for (i = 0; i < urb->number_of_packets; i++) { | |
1121 | struct ehci_iso_packet *uframe = &iso_sched->packet [i]; | |
1122 | unsigned length; | |
1123 | dma_addr_t buf; | |
1124 | u32 trans; | |
1125 | ||
1126 | length = urb->iso_frame_desc [i].length; | |
1127 | buf = dma + urb->iso_frame_desc [i].offset; | |
1128 | ||
1129 | trans = EHCI_ISOC_ACTIVE; | |
1130 | trans |= buf & 0x0fff; | |
1131 | if (unlikely (((i + 1) == urb->number_of_packets)) | |
1132 | && !(urb->transfer_flags & URB_NO_INTERRUPT)) | |
1133 | trans |= EHCI_ITD_IOC; | |
1134 | trans |= length << 16; | |
6dbd682b | 1135 | uframe->transaction = cpu_to_hc32(ehci, trans); |
1da177e4 | 1136 | |
77078570 | 1137 | /* might need to cross a buffer page within a uframe */ |
1da177e4 LT |
1138 | uframe->bufp = (buf & ~(u64)0x0fff); |
1139 | buf += length; | |
1140 | if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff)))) | |
1141 | uframe->cross = 1; | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | static void | |
1146 | iso_sched_free ( | |
1147 | struct ehci_iso_stream *stream, | |
1148 | struct ehci_iso_sched *iso_sched | |
1149 | ) | |
1150 | { | |
1151 | if (!iso_sched) | |
1152 | return; | |
1153 | // caller must hold ehci->lock! | |
1154 | list_splice (&iso_sched->td_list, &stream->free_list); | |
1155 | kfree (iso_sched); | |
1156 | } | |
1157 | ||
1158 | static int | |
1159 | itd_urb_transaction ( | |
1160 | struct ehci_iso_stream *stream, | |
1161 | struct ehci_hcd *ehci, | |
1162 | struct urb *urb, | |
55016f10 | 1163 | gfp_t mem_flags |
1da177e4 LT |
1164 | ) |
1165 | { | |
1166 | struct ehci_itd *itd; | |
1167 | dma_addr_t itd_dma; | |
1168 | int i; | |
1169 | unsigned num_itds; | |
1170 | struct ehci_iso_sched *sched; | |
1171 | unsigned long flags; | |
1172 | ||
1173 | sched = iso_sched_alloc (urb->number_of_packets, mem_flags); | |
1174 | if (unlikely (sched == NULL)) | |
1175 | return -ENOMEM; | |
1176 | ||
6dbd682b | 1177 | itd_sched_init(ehci, sched, stream, urb); |
1da177e4 LT |
1178 | |
1179 | if (urb->interval < 8) | |
1180 | num_itds = 1 + (sched->span + 7) / 8; | |
1181 | else | |
1182 | num_itds = urb->number_of_packets; | |
1183 | ||
1184 | /* allocate/init ITDs */ | |
1185 | spin_lock_irqsave (&ehci->lock, flags); | |
1186 | for (i = 0; i < num_itds; i++) { | |
1187 | ||
55934eb3 AS |
1188 | /* |
1189 | * Use iTDs from the free list, but not iTDs that may | |
1190 | * still be in use by the hardware. | |
1da177e4 | 1191 | */ |
55934eb3 AS |
1192 | if (likely(!list_empty(&stream->free_list))) { |
1193 | itd = list_first_entry(&stream->free_list, | |
6dbd682b | 1194 | struct ehci_itd, itd_list); |
f4289078 | 1195 | if (itd->frame == ehci->now_frame) |
55934eb3 | 1196 | goto alloc_itd; |
1da177e4 LT |
1197 | list_del (&itd->itd_list); |
1198 | itd_dma = itd->itd_dma; | |
3d01f0fe | 1199 | } else { |
55934eb3 | 1200 | alloc_itd: |
1da177e4 LT |
1201 | spin_unlock_irqrestore (&ehci->lock, flags); |
1202 | itd = dma_pool_alloc (ehci->itd_pool, mem_flags, | |
1203 | &itd_dma); | |
1204 | spin_lock_irqsave (&ehci->lock, flags); | |
3d01f0fe KW |
1205 | if (!itd) { |
1206 | iso_sched_free(stream, sched); | |
1207 | spin_unlock_irqrestore(&ehci->lock, flags); | |
1208 | return -ENOMEM; | |
1209 | } | |
1da177e4 LT |
1210 | } |
1211 | ||
1da177e4 LT |
1212 | memset (itd, 0, sizeof *itd); |
1213 | itd->itd_dma = itd_dma; | |
85ecd032 | 1214 | itd->frame = 9999; /* an invalid value */ |
1da177e4 LT |
1215 | list_add (&itd->itd_list, &sched->td_list); |
1216 | } | |
1217 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1218 | ||
1219 | /* temporarily store schedule info in hcpriv */ | |
1220 | urb->hcpriv = sched; | |
1221 | urb->error_count = 0; | |
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | /*-------------------------------------------------------------------------*/ | |
1226 | ||
1227 | static inline int | |
1228 | itd_slot_ok ( | |
1229 | struct ehci_hcd *ehci, | |
1230 | u32 mod, | |
1231 | u32 uframe, | |
1232 | u8 usecs, | |
1233 | u32 period | |
1234 | ) | |
1235 | { | |
1236 | uframe %= period; | |
1237 | do { | |
cc62a7eb | 1238 | /* can't commit more than uframe_periodic_max usec */ |
1da177e4 | 1239 | if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7) |
cc62a7eb | 1240 | > (ehci->uframe_periodic_max - usecs)) |
1da177e4 LT |
1241 | return 0; |
1242 | ||
1243 | /* we know urb->interval is 2^N uframes */ | |
1244 | uframe += period; | |
1245 | } while (uframe < mod); | |
1246 | return 1; | |
1247 | } | |
1248 | ||
1249 | static inline int | |
1250 | sitd_slot_ok ( | |
1251 | struct ehci_hcd *ehci, | |
1252 | u32 mod, | |
1253 | struct ehci_iso_stream *stream, | |
1254 | u32 uframe, | |
1255 | struct ehci_iso_sched *sched, | |
1256 | u32 period_uframes | |
1257 | ) | |
1258 | { | |
1259 | u32 mask, tmp; | |
1260 | u32 frame, uf; | |
1261 | ||
1262 | mask = stream->raw_mask << (uframe & 7); | |
1263 | ||
1264 | /* for IN, don't wrap CSPLIT into the next frame */ | |
1265 | if (mask & ~0xffff) | |
1266 | return 0; | |
1267 | ||
65b8e5cb AS |
1268 | /* check bandwidth */ |
1269 | uframe %= period_uframes; | |
1270 | frame = uframe >> 3; | |
1271 | ||
1272 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED | |
1273 | /* The tt's fullspeed bus bandwidth must be available. | |
1274 | * tt_available scheduling guarantees 10+% for control/bulk. | |
1275 | */ | |
1276 | uf = uframe & 7; | |
1277 | if (!tt_available(ehci, period_uframes >> 3, | |
1278 | stream->udev, frame, uf, stream->tt_usecs)) | |
1279 | return 0; | |
1280 | #else | |
1281 | /* tt must be idle for start(s), any gap, and csplit. | |
1282 | * assume scheduling slop leaves 10+% for control/bulk. | |
1283 | */ | |
1284 | if (!tt_no_collision(ehci, period_uframes >> 3, | |
1285 | stream->udev, frame, mask)) | |
1286 | return 0; | |
1287 | #endif | |
1288 | ||
1da177e4 LT |
1289 | /* this multi-pass logic is simple, but performance may |
1290 | * suffer when the schedule data isn't cached. | |
1291 | */ | |
1da177e4 LT |
1292 | do { |
1293 | u32 max_used; | |
1294 | ||
1295 | frame = uframe >> 3; | |
1296 | uf = uframe & 7; | |
1297 | ||
1da177e4 | 1298 | /* check starts (OUT uses more than one) */ |
cc62a7eb | 1299 | max_used = ehci->uframe_periodic_max - stream->usecs; |
1da177e4 LT |
1300 | for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) { |
1301 | if (periodic_usecs (ehci, frame, uf) > max_used) | |
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | /* for IN, check CSPLIT */ | |
1306 | if (stream->c_usecs) { | |
0c734622 | 1307 | uf = uframe & 7; |
cc62a7eb | 1308 | max_used = ehci->uframe_periodic_max - stream->c_usecs; |
1da177e4 LT |
1309 | do { |
1310 | tmp = 1 << uf; | |
1311 | tmp <<= 8; | |
1312 | if ((stream->raw_mask & tmp) == 0) | |
1313 | continue; | |
1314 | if (periodic_usecs (ehci, frame, uf) | |
1315 | > max_used) | |
1316 | return 0; | |
1317 | } while (++uf < 8); | |
1318 | } | |
1319 | ||
1320 | /* we know urb->interval is 2^N uframes */ | |
1321 | uframe += period_uframes; | |
1322 | } while (uframe < mod); | |
1323 | ||
6dbd682b | 1324 | stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7)); |
1da177e4 LT |
1325 | return 1; |
1326 | } | |
1327 | ||
1328 | /* | |
1329 | * This scheduler plans almost as far into the future as it has actual | |
1330 | * periodic schedule slots. (Affected by TUNE_FLS, which defaults to | |
1331 | * "as small as possible" to be cache-friendlier.) That limits the size | |
1332 | * transfers you can stream reliably; avoid more than 64 msec per urb. | |
1333 | * Also avoid queue depths of less than ehci's worst irq latency (affected | |
1334 | * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter, | |
1335 | * and other factors); or more than about 230 msec total (for portability, | |
1336 | * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler! | |
1337 | */ | |
1338 | ||
c3ee9b76 | 1339 | #define SCHEDULING_DELAY 40 /* microframes */ |
1da177e4 LT |
1340 | |
1341 | static int | |
1342 | iso_stream_schedule ( | |
1343 | struct ehci_hcd *ehci, | |
1344 | struct urb *urb, | |
1345 | struct ehci_iso_stream *stream | |
1346 | ) | |
1347 | { | |
c3ee9b76 | 1348 | u32 now, base, next, start, period, span; |
1da177e4 LT |
1349 | int status; |
1350 | unsigned mod = ehci->periodic_size << 3; | |
1351 | struct ehci_iso_sched *sched = urb->hcpriv; | |
1352 | ||
ffda0803 AS |
1353 | period = urb->interval; |
1354 | span = sched->span; | |
1355 | if (!stream->highspeed) { | |
1356 | period <<= 3; | |
1357 | span <<= 3; | |
1358 | } | |
1359 | ||
68aa95d5 | 1360 | now = ehci_read_frame_index(ehci) & (mod - 1); |
1da177e4 | 1361 | |
b40e43fc AS |
1362 | /* Typical case: reuse current schedule, stream is still active. |
1363 | * Hopefully there are no gaps from the host falling behind | |
4005ad43 AS |
1364 | * (irq delays etc). If there are, the behavior depends on |
1365 | * whether URB_ISO_ASAP is set. | |
1da177e4 LT |
1366 | */ |
1367 | if (likely (!list_empty (&stream->td_list))) { | |
dccd574c | 1368 | |
98cae42d AS |
1369 | /* Take the isochronous scheduling threshold into account */ |
1370 | if (ehci->i_thresh) | |
1371 | next = now + ehci->i_thresh; /* uframe cache */ | |
dccd574c | 1372 | else |
98cae42d | 1373 | next = (now + 2 + 7) & ~0x07; /* full frame cache */ |
b40e43fc | 1374 | |
c3ee9b76 AS |
1375 | /* |
1376 | * Use ehci->last_iso_frame as the base. There can't be any | |
1377 | * TDs scheduled for earlier than that. | |
1fb2e055 | 1378 | */ |
c3ee9b76 AS |
1379 | base = ehci->last_iso_frame << 3; |
1380 | next = (next - base) & (mod - 1); | |
1381 | start = (stream->next_uframe - base) & (mod - 1); | |
1382 | ||
1383 | /* Is the schedule already full? */ | |
1384 | if (unlikely(start < period)) { | |
1385 | ehci_dbg(ehci, "iso sched full %p (%u-%u < %u mod %u)\n", | |
1386 | urb, stream->next_uframe, base, | |
1387 | period, mod); | |
1388 | status = -ENOSPC; | |
b40e43fc AS |
1389 | goto fail; |
1390 | } | |
c3ee9b76 | 1391 | |
4005ad43 AS |
1392 | /* Behind the scheduling threshold? */ |
1393 | if (unlikely(start < next)) { | |
24f53137 | 1394 | unsigned now2 = (now - base) & (mod - 1); |
4005ad43 AS |
1395 | |
1396 | /* USB_ISO_ASAP: Round up to the first available slot */ | |
1397 | if (urb->transfer_flags & URB_ISO_ASAP) | |
1398 | start += (next - start + period - 1) & -period; | |
1399 | ||
1400 | /* | |
24f53137 AS |
1401 | * Not ASAP: Use the next slot in the stream, |
1402 | * no matter what. | |
4005ad43 | 1403 | */ |
24f53137 AS |
1404 | else if (start + span - period < now2) { |
1405 | ehci_dbg(ehci, "iso underrun %p (%u+%u < %u)\n", | |
4005ad43 | 1406 | urb, start + base, |
24f53137 | 1407 | span - period, now2 + base); |
4005ad43 AS |
1408 | } |
1409 | } | |
c3ee9b76 AS |
1410 | |
1411 | start += base; | |
1da177e4 LT |
1412 | } |
1413 | ||
1414 | /* need to schedule; when's the next (u)frame we could start? | |
1415 | * this is bigger than ehci->i_thresh allows; scheduling itself | |
c3ee9b76 | 1416 | * isn't free, the delay should handle reasonably slow cpus. it |
1da177e4 LT |
1417 | * can also help high bandwidth if the dma and irq loads don't |
1418 | * jump until after the queue is primed. | |
1419 | */ | |
1fb2e055 | 1420 | else { |
e3420901 | 1421 | int done = 0; |
1fb2e055 | 1422 | |
c3ee9b76 AS |
1423 | base = now & ~0x07; |
1424 | start = base + SCHEDULING_DELAY; | |
1fb2e055 | 1425 | |
811c926c TP |
1426 | /* find a uframe slot with enough bandwidth. |
1427 | * Early uframes are more precious because full-speed | |
1428 | * iso IN transfers can't use late uframes, | |
1429 | * and therefore they should be allocated last. | |
1430 | */ | |
1431 | next = start; | |
1432 | start += period; | |
1433 | do { | |
1434 | start--; | |
1fb2e055 AS |
1435 | /* check schedule: enough space? */ |
1436 | if (stream->highspeed) { | |
1437 | if (itd_slot_ok(ehci, mod, start, | |
1438 | stream->usecs, period)) | |
e3420901 | 1439 | done = 1; |
1fb2e055 AS |
1440 | } else { |
1441 | if ((start % 8) >= 6) | |
1442 | continue; | |
1443 | if (sitd_slot_ok(ehci, mod, stream, | |
1444 | start, sched, period)) | |
e3420901 | 1445 | done = 1; |
1fb2e055 | 1446 | } |
e3420901 | 1447 | } while (start > next && !done); |
1da177e4 | 1448 | |
1fb2e055 | 1449 | /* no room in the schedule */ |
e3420901 | 1450 | if (!done) { |
c3ee9b76 | 1451 | ehci_dbg(ehci, "iso sched full %p", urb); |
1fb2e055 AS |
1452 | status = -ENOSPC; |
1453 | goto fail; | |
1da177e4 LT |
1454 | } |
1455 | } | |
1456 | ||
1fb2e055 | 1457 | /* Tried to schedule too far into the future? */ |
c3ee9b76 AS |
1458 | if (unlikely(start - base + span - period >= mod)) { |
1459 | ehci_dbg(ehci, "request %p would overflow (%u+%u >= %u)\n", | |
1460 | urb, start - base, span - period, mod); | |
1fb2e055 AS |
1461 | status = -EFBIG; |
1462 | goto fail; | |
1463 | } | |
1da177e4 | 1464 | |
1fb2e055 | 1465 | stream->next_uframe = start & (mod - 1); |
1da177e4 | 1466 | |
1da177e4 LT |
1467 | /* report high speed start in uframes; full speed, in frames */ |
1468 | urb->start_frame = stream->next_uframe; | |
1469 | if (!stream->highspeed) | |
1470 | urb->start_frame >>= 3; | |
569b394f AS |
1471 | |
1472 | /* Make sure scan_isoc() sees these */ | |
1473 | if (ehci->isoc_count == 0) | |
c3ee9b76 | 1474 | ehci->last_iso_frame = now >> 3; |
1da177e4 | 1475 | return 0; |
1fb2e055 AS |
1476 | |
1477 | fail: | |
1478 | iso_sched_free(stream, sched); | |
1479 | urb->hcpriv = NULL; | |
1480 | return status; | |
1da177e4 LT |
1481 | } |
1482 | ||
1483 | /*-------------------------------------------------------------------------*/ | |
1484 | ||
1485 | static inline void | |
6dbd682b SR |
1486 | itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream, |
1487 | struct ehci_itd *itd) | |
1da177e4 LT |
1488 | { |
1489 | int i; | |
1490 | ||
77078570 | 1491 | /* it's been recently zeroed */ |
6dbd682b | 1492 | itd->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
1493 | itd->hw_bufp [0] = stream->buf0; |
1494 | itd->hw_bufp [1] = stream->buf1; | |
1495 | itd->hw_bufp [2] = stream->buf2; | |
1496 | ||
1497 | for (i = 0; i < 8; i++) | |
1498 | itd->index[i] = -1; | |
1499 | ||
1500 | /* All other fields are filled when scheduling */ | |
1501 | } | |
1502 | ||
1503 | static inline void | |
6dbd682b SR |
1504 | itd_patch( |
1505 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1506 | struct ehci_itd *itd, |
1507 | struct ehci_iso_sched *iso_sched, | |
1508 | unsigned index, | |
77078570 | 1509 | u16 uframe |
1da177e4 LT |
1510 | ) |
1511 | { | |
1512 | struct ehci_iso_packet *uf = &iso_sched->packet [index]; | |
1513 | unsigned pg = itd->pg; | |
1514 | ||
1515 | // BUG_ON (pg == 6 && uf->cross); | |
1516 | ||
1517 | uframe &= 0x07; | |
1518 | itd->index [uframe] = index; | |
1519 | ||
6dbd682b SR |
1520 | itd->hw_transaction[uframe] = uf->transaction; |
1521 | itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12); | |
1522 | itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0); | |
1523 | itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32)); | |
1da177e4 LT |
1524 | |
1525 | /* iso_frame_desc[].offset must be strictly increasing */ | |
77078570 | 1526 | if (unlikely (uf->cross)) { |
1da177e4 | 1527 | u64 bufp = uf->bufp + 4096; |
6dbd682b | 1528 | |
1da177e4 | 1529 | itd->pg = ++pg; |
6dbd682b SR |
1530 | itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0); |
1531 | itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32)); | |
1da177e4 LT |
1532 | } |
1533 | } | |
1534 | ||
1535 | static inline void | |
1536 | itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd) | |
1537 | { | |
92bc3648 CL |
1538 | union ehci_shadow *prev = &ehci->pshadow[frame]; |
1539 | __hc32 *hw_p = &ehci->periodic[frame]; | |
1540 | union ehci_shadow here = *prev; | |
1541 | __hc32 type = 0; | |
1542 | ||
1543 | /* skip any iso nodes which might belong to previous microframes */ | |
1544 | while (here.ptr) { | |
1545 | type = Q_NEXT_TYPE(ehci, *hw_p); | |
1546 | if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) | |
1547 | break; | |
1548 | prev = periodic_next_shadow(ehci, prev, type); | |
1549 | hw_p = shadow_next_periodic(ehci, &here, type); | |
1550 | here = *prev; | |
1551 | } | |
1552 | ||
1553 | itd->itd_next = here; | |
1554 | itd->hw_next = *hw_p; | |
1555 | prev->itd = itd; | |
1da177e4 LT |
1556 | itd->frame = frame; |
1557 | wmb (); | |
92bc3648 | 1558 | *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD); |
1da177e4 LT |
1559 | } |
1560 | ||
1561 | /* fit urb's itds into the selected schedule slot; activate as needed */ | |
b015cb79 | 1562 | static void itd_link_urb( |
1da177e4 LT |
1563 | struct ehci_hcd *ehci, |
1564 | struct urb *urb, | |
1565 | unsigned mod, | |
1566 | struct ehci_iso_stream *stream | |
1567 | ) | |
1568 | { | |
77078570 | 1569 | int packet; |
1da177e4 LT |
1570 | unsigned next_uframe, uframe, frame; |
1571 | struct ehci_iso_sched *iso_sched = urb->hcpriv; | |
1572 | struct ehci_itd *itd; | |
1573 | ||
bccbefaa | 1574 | next_uframe = stream->next_uframe & (mod - 1); |
1da177e4 LT |
1575 | |
1576 | if (unlikely (list_empty(&stream->td_list))) { | |
1577 | ehci_to_hcd(ehci)->self.bandwidth_allocated | |
1578 | += stream->bandwidth; | |
1579 | ehci_vdbg (ehci, | |
1580 | "schedule devp %s ep%d%s-iso period %d start %d.%d\n", | |
1581 | urb->dev->devpath, stream->bEndpointAddress & 0x0f, | |
1582 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out", | |
1583 | urb->interval, | |
1584 | next_uframe >> 3, next_uframe & 0x7); | |
1da177e4 | 1585 | } |
05570297 AH |
1586 | |
1587 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | |
ad93562b AX |
1588 | if (ehci->amd_pll_fix == 1) |
1589 | usb_amd_quirk_pll_disable(); | |
05570297 AH |
1590 | } |
1591 | ||
1da177e4 LT |
1592 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
1593 | ||
1594 | /* fill iTDs uframe by uframe */ | |
1595 | for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) { | |
1596 | if (itd == NULL) { | |
1597 | /* ASSERT: we have all necessary itds */ | |
1598 | // BUG_ON (list_empty (&iso_sched->td_list)); | |
1599 | ||
1600 | /* ASSERT: no itds for this endpoint in this uframe */ | |
1601 | ||
1602 | itd = list_entry (iso_sched->td_list.next, | |
1603 | struct ehci_itd, itd_list); | |
1604 | list_move_tail (&itd->itd_list, &stream->td_list); | |
8c5bf7be | 1605 | itd->stream = stream; |
508db8c9 | 1606 | itd->urb = urb; |
6dbd682b | 1607 | itd_init (ehci, stream, itd); |
1da177e4 LT |
1608 | } |
1609 | ||
1610 | uframe = next_uframe & 0x07; | |
1611 | frame = next_uframe >> 3; | |
1612 | ||
6dbd682b | 1613 | itd_patch(ehci, itd, iso_sched, packet, uframe); |
1da177e4 LT |
1614 | |
1615 | next_uframe += stream->interval; | |
bccbefaa | 1616 | next_uframe &= mod - 1; |
1da177e4 LT |
1617 | packet++; |
1618 | ||
1619 | /* link completed itds into the schedule */ | |
1620 | if (((next_uframe >> 3) != frame) | |
1621 | || packet == urb->number_of_packets) { | |
bccbefaa | 1622 | itd_link(ehci, frame & (ehci->periodic_size - 1), itd); |
1da177e4 LT |
1623 | itd = NULL; |
1624 | } | |
1625 | } | |
1626 | stream->next_uframe = next_uframe; | |
1627 | ||
1628 | /* don't need that schedule data any more */ | |
1629 | iso_sched_free (stream, iso_sched); | |
2656a9ab | 1630 | urb->hcpriv = stream; |
1da177e4 | 1631 | |
569b394f | 1632 | ++ehci->isoc_count; |
b015cb79 | 1633 | enable_periodic(ehci); |
1da177e4 LT |
1634 | } |
1635 | ||
1636 | #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR) | |
1637 | ||
30bf54e6 DB |
1638 | /* Process and recycle a completed ITD. Return true iff its urb completed, |
1639 | * and hence its completion callback probably added things to the hardware | |
1640 | * schedule. | |
1641 | * | |
1642 | * Note that we carefully avoid recycling this descriptor until after any | |
1643 | * completion callback runs, so that it won't be reused quickly. That is, | |
1644 | * assuming (a) no more than two urbs per frame on this endpoint, and also | |
1645 | * (b) only this endpoint's completions submit URBs. It seems some silicon | |
1646 | * corrupts things if you reuse completed descriptors very quickly... | |
1647 | */ | |
f4289078 AS |
1648 | static bool itd_complete(struct ehci_hcd *ehci, struct ehci_itd *itd) |
1649 | { | |
1da177e4 LT |
1650 | struct urb *urb = itd->urb; |
1651 | struct usb_iso_packet_descriptor *desc; | |
1652 | u32 t; | |
1653 | unsigned uframe; | |
1654 | int urb_index = -1; | |
1655 | struct ehci_iso_stream *stream = itd->stream; | |
1656 | struct usb_device *dev; | |
f4289078 | 1657 | bool retval = false; |
1da177e4 LT |
1658 | |
1659 | /* for each uframe with a packet */ | |
1660 | for (uframe = 0; uframe < 8; uframe++) { | |
1661 | if (likely (itd->index[uframe] == -1)) | |
1662 | continue; | |
1663 | urb_index = itd->index[uframe]; | |
1664 | desc = &urb->iso_frame_desc [urb_index]; | |
1665 | ||
6dbd682b | 1666 | t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]); |
1da177e4 | 1667 | itd->hw_transaction [uframe] = 0; |
1da177e4 LT |
1668 | |
1669 | /* report transfer status */ | |
1670 | if (unlikely (t & ISO_ERRS)) { | |
1671 | urb->error_count++; | |
1672 | if (t & EHCI_ISOC_BUF_ERR) | |
1673 | desc->status = usb_pipein (urb->pipe) | |
1674 | ? -ENOSR /* hc couldn't read */ | |
1675 | : -ECOMM; /* hc couldn't write */ | |
1676 | else if (t & EHCI_ISOC_BABBLE) | |
1677 | desc->status = -EOVERFLOW; | |
1678 | else /* (t & EHCI_ISOC_XACTERR) */ | |
1679 | desc->status = -EPROTO; | |
1680 | ||
1681 | /* HC need not update length with this error */ | |
ec6d67e3 AS |
1682 | if (!(t & EHCI_ISOC_BABBLE)) { |
1683 | desc->actual_length = EHCI_ITD_LENGTH(t); | |
1684 | urb->actual_length += desc->actual_length; | |
1685 | } | |
1da177e4 LT |
1686 | } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) { |
1687 | desc->status = 0; | |
ec6d67e3 AS |
1688 | desc->actual_length = EHCI_ITD_LENGTH(t); |
1689 | urb->actual_length += desc->actual_length; | |
b40e43fc AS |
1690 | } else { |
1691 | /* URB was too late */ | |
4005ad43 | 1692 | urb->error_count++; |
1da177e4 LT |
1693 | } |
1694 | } | |
1695 | ||
1da177e4 LT |
1696 | /* handle completion now? */ |
1697 | if (likely ((urb_index + 1) != urb->number_of_packets)) | |
30bf54e6 | 1698 | goto done; |
1da177e4 LT |
1699 | |
1700 | /* ASSERT: it's really the last itd for this urb | |
1701 | list_for_each_entry (itd, &stream->td_list, itd_list) | |
1702 | BUG_ON (itd->urb == urb); | |
1703 | */ | |
1704 | ||
aa16ca30 | 1705 | /* give urb back to the driver; completion often (re)submits */ |
6a8e87b2 | 1706 | dev = urb->dev; |
14c04c0f | 1707 | ehci_urb_done(ehci, urb, 0); |
30bf54e6 | 1708 | retval = true; |
1da177e4 | 1709 | urb = NULL; |
569b394f AS |
1710 | |
1711 | --ehci->isoc_count; | |
b015cb79 | 1712 | disable_periodic(ehci); |
1da177e4 | 1713 | |
569b394f | 1714 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
05570297 | 1715 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { |
ad93562b AX |
1716 | if (ehci->amd_pll_fix == 1) |
1717 | usb_amd_quirk_pll_enable(); | |
05570297 AH |
1718 | } |
1719 | ||
508db8c9 | 1720 | if (unlikely(list_is_singular(&stream->td_list))) { |
1da177e4 LT |
1721 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
1722 | -= stream->bandwidth; | |
1723 | ehci_vdbg (ehci, | |
1724 | "deschedule devp %s ep%d%s-iso\n", | |
1725 | dev->devpath, stream->bEndpointAddress & 0x0f, | |
1726 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out"); | |
1727 | } | |
9aa09d2f | 1728 | |
30bf54e6 | 1729 | done: |
30bf54e6 | 1730 | itd->urb = NULL; |
55934eb3 AS |
1731 | |
1732 | /* Add to the end of the free list for later reuse */ | |
1733 | list_move_tail(&itd->itd_list, &stream->free_list); | |
1734 | ||
1735 | /* Recycle the iTDs when the pipeline is empty (ep no longer in use) */ | |
1736 | if (list_empty(&stream->td_list)) { | |
1737 | list_splice_tail_init(&stream->free_list, | |
1738 | &ehci->cached_itd_list); | |
1739 | start_free_itds(ehci); | |
9aa09d2f | 1740 | } |
55934eb3 | 1741 | |
30bf54e6 | 1742 | return retval; |
1da177e4 LT |
1743 | } |
1744 | ||
1745 | /*-------------------------------------------------------------------------*/ | |
1746 | ||
5db539e4 | 1747 | static int itd_submit (struct ehci_hcd *ehci, struct urb *urb, |
55016f10 | 1748 | gfp_t mem_flags) |
1da177e4 LT |
1749 | { |
1750 | int status = -EINVAL; | |
1751 | unsigned long flags; | |
1752 | struct ehci_iso_stream *stream; | |
1753 | ||
1754 | /* Get iso_stream head */ | |
1755 | stream = iso_stream_find (ehci, urb); | |
1756 | if (unlikely (stream == NULL)) { | |
1757 | ehci_dbg (ehci, "can't get iso stream\n"); | |
1758 | return -ENOMEM; | |
1759 | } | |
1760 | if (unlikely (urb->interval != stream->interval)) { | |
1761 | ehci_dbg (ehci, "can't change iso interval %d --> %d\n", | |
1762 | stream->interval, urb->interval); | |
1763 | goto done; | |
1764 | } | |
1765 | ||
1766 | #ifdef EHCI_URB_TRACE | |
1767 | ehci_dbg (ehci, | |
1768 | "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n", | |
441b62c1 | 1769 | __func__, urb->dev->devpath, urb, |
1da177e4 LT |
1770 | usb_pipeendpoint (urb->pipe), |
1771 | usb_pipein (urb->pipe) ? "in" : "out", | |
1772 | urb->transfer_buffer_length, | |
1773 | urb->number_of_packets, urb->interval, | |
1774 | stream); | |
1775 | #endif | |
1776 | ||
1777 | /* allocate ITDs w/o locking anything */ | |
1778 | status = itd_urb_transaction (stream, ehci, urb, mem_flags); | |
1779 | if (unlikely (status < 0)) { | |
1780 | ehci_dbg (ehci, "can't init itds\n"); | |
1781 | goto done; | |
1782 | } | |
1783 | ||
1784 | /* schedule ... need to lock */ | |
1785 | spin_lock_irqsave (&ehci->lock, flags); | |
541c7d43 | 1786 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 1787 | status = -ESHUTDOWN; |
e9df41c5 AS |
1788 | goto done_not_linked; |
1789 | } | |
1790 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); | |
1791 | if (unlikely(status)) | |
1792 | goto done_not_linked; | |
1793 | status = iso_stream_schedule(ehci, urb, stream); | |
53bd6a60 | 1794 | if (likely (status == 0)) |
1da177e4 | 1795 | itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream); |
e9df41c5 AS |
1796 | else |
1797 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
8c5bf7be | 1798 | done_not_linked: |
1da177e4 | 1799 | spin_unlock_irqrestore (&ehci->lock, flags); |
8c5bf7be | 1800 | done: |
1da177e4 LT |
1801 | return status; |
1802 | } | |
1803 | ||
1da177e4 LT |
1804 | /*-------------------------------------------------------------------------*/ |
1805 | ||
1806 | /* | |
1807 | * "Split ISO TDs" ... used for USB 1.1 devices going through the | |
1808 | * TTs in USB 2.0 hubs. These need microframe scheduling. | |
1809 | */ | |
1810 | ||
1811 | static inline void | |
6dbd682b SR |
1812 | sitd_sched_init( |
1813 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1814 | struct ehci_iso_sched *iso_sched, |
1815 | struct ehci_iso_stream *stream, | |
1816 | struct urb *urb | |
1817 | ) | |
1818 | { | |
1819 | unsigned i; | |
1820 | dma_addr_t dma = urb->transfer_dma; | |
1821 | ||
1822 | /* how many frames are needed for these transfers */ | |
1823 | iso_sched->span = urb->number_of_packets * stream->interval; | |
1824 | ||
1825 | /* figure out per-frame sitd fields that we'll need later | |
1826 | * when we fit new sitds into the schedule. | |
1827 | */ | |
1828 | for (i = 0; i < urb->number_of_packets; i++) { | |
1829 | struct ehci_iso_packet *packet = &iso_sched->packet [i]; | |
1830 | unsigned length; | |
1831 | dma_addr_t buf; | |
1832 | u32 trans; | |
1833 | ||
1834 | length = urb->iso_frame_desc [i].length & 0x03ff; | |
1835 | buf = dma + urb->iso_frame_desc [i].offset; | |
1836 | ||
1837 | trans = SITD_STS_ACTIVE; | |
1838 | if (((i + 1) == urb->number_of_packets) | |
1839 | && !(urb->transfer_flags & URB_NO_INTERRUPT)) | |
1840 | trans |= SITD_IOC; | |
1841 | trans |= length << 16; | |
6dbd682b | 1842 | packet->transaction = cpu_to_hc32(ehci, trans); |
1da177e4 LT |
1843 | |
1844 | /* might need to cross a buffer page within a td */ | |
1845 | packet->bufp = buf; | |
1846 | packet->buf1 = (buf + length) & ~0x0fff; | |
1847 | if (packet->buf1 != (buf & ~(u64)0x0fff)) | |
1848 | packet->cross = 1; | |
1849 | ||
53bd6a60 | 1850 | /* OUT uses multiple start-splits */ |
1da177e4 LT |
1851 | if (stream->bEndpointAddress & USB_DIR_IN) |
1852 | continue; | |
1853 | length = (length + 187) / 188; | |
1854 | if (length > 1) /* BEGIN vs ALL */ | |
1855 | length |= 1 << 3; | |
1856 | packet->buf1 |= length; | |
1857 | } | |
1858 | } | |
1859 | ||
1860 | static int | |
1861 | sitd_urb_transaction ( | |
1862 | struct ehci_iso_stream *stream, | |
1863 | struct ehci_hcd *ehci, | |
1864 | struct urb *urb, | |
55016f10 | 1865 | gfp_t mem_flags |
1da177e4 LT |
1866 | ) |
1867 | { | |
1868 | struct ehci_sitd *sitd; | |
1869 | dma_addr_t sitd_dma; | |
1870 | int i; | |
1871 | struct ehci_iso_sched *iso_sched; | |
1872 | unsigned long flags; | |
1873 | ||
1874 | iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags); | |
1875 | if (iso_sched == NULL) | |
1876 | return -ENOMEM; | |
1877 | ||
6dbd682b | 1878 | sitd_sched_init(ehci, iso_sched, stream, urb); |
1da177e4 LT |
1879 | |
1880 | /* allocate/init sITDs */ | |
1881 | spin_lock_irqsave (&ehci->lock, flags); | |
1882 | for (i = 0; i < urb->number_of_packets; i++) { | |
1883 | ||
1884 | /* NOTE: for now, we don't try to handle wraparound cases | |
1885 | * for IN (using sitd->hw_backpointer, like a FSTN), which | |
1886 | * means we never need two sitds for full speed packets. | |
1887 | */ | |
1888 | ||
55934eb3 AS |
1889 | /* |
1890 | * Use siTDs from the free list, but not siTDs that may | |
1891 | * still be in use by the hardware. | |
1da177e4 | 1892 | */ |
55934eb3 AS |
1893 | if (likely(!list_empty(&stream->free_list))) { |
1894 | sitd = list_first_entry(&stream->free_list, | |
1da177e4 | 1895 | struct ehci_sitd, sitd_list); |
f4289078 | 1896 | if (sitd->frame == ehci->now_frame) |
55934eb3 | 1897 | goto alloc_sitd; |
1da177e4 LT |
1898 | list_del (&sitd->sitd_list); |
1899 | sitd_dma = sitd->sitd_dma; | |
3d01f0fe | 1900 | } else { |
55934eb3 | 1901 | alloc_sitd: |
1da177e4 LT |
1902 | spin_unlock_irqrestore (&ehci->lock, flags); |
1903 | sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags, | |
1904 | &sitd_dma); | |
1905 | spin_lock_irqsave (&ehci->lock, flags); | |
3d01f0fe KW |
1906 | if (!sitd) { |
1907 | iso_sched_free(stream, iso_sched); | |
1908 | spin_unlock_irqrestore(&ehci->lock, flags); | |
1909 | return -ENOMEM; | |
1910 | } | |
1da177e4 LT |
1911 | } |
1912 | ||
1da177e4 LT |
1913 | memset (sitd, 0, sizeof *sitd); |
1914 | sitd->sitd_dma = sitd_dma; | |
85ecd032 | 1915 | sitd->frame = 9999; /* an invalid value */ |
1da177e4 LT |
1916 | list_add (&sitd->sitd_list, &iso_sched->td_list); |
1917 | } | |
1918 | ||
1919 | /* temporarily store schedule info in hcpriv */ | |
1920 | urb->hcpriv = iso_sched; | |
1921 | urb->error_count = 0; | |
1922 | ||
1923 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1924 | return 0; | |
1925 | } | |
1926 | ||
1927 | /*-------------------------------------------------------------------------*/ | |
1928 | ||
1929 | static inline void | |
6dbd682b SR |
1930 | sitd_patch( |
1931 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1932 | struct ehci_iso_stream *stream, |
1933 | struct ehci_sitd *sitd, | |
1934 | struct ehci_iso_sched *iso_sched, | |
1935 | unsigned index | |
1936 | ) | |
1937 | { | |
1938 | struct ehci_iso_packet *uf = &iso_sched->packet [index]; | |
1939 | u64 bufp = uf->bufp; | |
1940 | ||
6dbd682b | 1941 | sitd->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
1942 | sitd->hw_fullspeed_ep = stream->address; |
1943 | sitd->hw_uframe = stream->splits; | |
1944 | sitd->hw_results = uf->transaction; | |
6dbd682b | 1945 | sitd->hw_backpointer = EHCI_LIST_END(ehci); |
1da177e4 LT |
1946 | |
1947 | bufp = uf->bufp; | |
6dbd682b SR |
1948 | sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp); |
1949 | sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32); | |
1da177e4 | 1950 | |
6dbd682b | 1951 | sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1); |
1da177e4 LT |
1952 | if (uf->cross) |
1953 | bufp += 4096; | |
6dbd682b | 1954 | sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32); |
1da177e4 LT |
1955 | sitd->index = index; |
1956 | } | |
1957 | ||
1958 | static inline void | |
1959 | sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd) | |
1960 | { | |
1961 | /* note: sitd ordering could matter (CSPLIT then SSPLIT) */ | |
1962 | sitd->sitd_next = ehci->pshadow [frame]; | |
1963 | sitd->hw_next = ehci->periodic [frame]; | |
1964 | ehci->pshadow [frame].sitd = sitd; | |
1965 | sitd->frame = frame; | |
1966 | wmb (); | |
6dbd682b | 1967 | ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD); |
1da177e4 LT |
1968 | } |
1969 | ||
1970 | /* fit urb's sitds into the selected schedule slot; activate as needed */ | |
b015cb79 | 1971 | static void sitd_link_urb( |
1da177e4 LT |
1972 | struct ehci_hcd *ehci, |
1973 | struct urb *urb, | |
1974 | unsigned mod, | |
1975 | struct ehci_iso_stream *stream | |
1976 | ) | |
1977 | { | |
1978 | int packet; | |
1979 | unsigned next_uframe; | |
1980 | struct ehci_iso_sched *sched = urb->hcpriv; | |
1981 | struct ehci_sitd *sitd; | |
1982 | ||
1983 | next_uframe = stream->next_uframe; | |
1984 | ||
1985 | if (list_empty(&stream->td_list)) { | |
1986 | /* usbfs ignores TT bandwidth */ | |
1987 | ehci_to_hcd(ehci)->self.bandwidth_allocated | |
1988 | += stream->bandwidth; | |
1989 | ehci_vdbg (ehci, | |
1990 | "sched devp %s ep%d%s-iso [%d] %dms/%04x\n", | |
1991 | urb->dev->devpath, stream->bEndpointAddress & 0x0f, | |
1992 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out", | |
bccbefaa | 1993 | (next_uframe >> 3) & (ehci->periodic_size - 1), |
6dbd682b | 1994 | stream->interval, hc32_to_cpu(ehci, stream->splits)); |
1da177e4 | 1995 | } |
05570297 AH |
1996 | |
1997 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | |
ad93562b AX |
1998 | if (ehci->amd_pll_fix == 1) |
1999 | usb_amd_quirk_pll_disable(); | |
05570297 AH |
2000 | } |
2001 | ||
1da177e4 LT |
2002 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
2003 | ||
2004 | /* fill sITDs frame by frame */ | |
2005 | for (packet = 0, sitd = NULL; | |
2006 | packet < urb->number_of_packets; | |
2007 | packet++) { | |
2008 | ||
2009 | /* ASSERT: we have all necessary sitds */ | |
2010 | BUG_ON (list_empty (&sched->td_list)); | |
2011 | ||
2012 | /* ASSERT: no itds for this endpoint in this frame */ | |
2013 | ||
2014 | sitd = list_entry (sched->td_list.next, | |
2015 | struct ehci_sitd, sitd_list); | |
2016 | list_move_tail (&sitd->sitd_list, &stream->td_list); | |
8c5bf7be | 2017 | sitd->stream = stream; |
508db8c9 | 2018 | sitd->urb = urb; |
1da177e4 | 2019 | |
6dbd682b | 2020 | sitd_patch(ehci, stream, sitd, sched, packet); |
bccbefaa | 2021 | sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1), |
1da177e4 LT |
2022 | sitd); |
2023 | ||
2024 | next_uframe += stream->interval << 3; | |
1da177e4 | 2025 | } |
bccbefaa | 2026 | stream->next_uframe = next_uframe & (mod - 1); |
1da177e4 LT |
2027 | |
2028 | /* don't need that schedule data any more */ | |
2029 | iso_sched_free (stream, sched); | |
2656a9ab | 2030 | urb->hcpriv = stream; |
1da177e4 | 2031 | |
569b394f | 2032 | ++ehci->isoc_count; |
b015cb79 | 2033 | enable_periodic(ehci); |
1da177e4 LT |
2034 | } |
2035 | ||
2036 | /*-------------------------------------------------------------------------*/ | |
2037 | ||
2038 | #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \ | |
53bd6a60 | 2039 | | SITD_STS_XACT | SITD_STS_MMF) |
1da177e4 | 2040 | |
30bf54e6 DB |
2041 | /* Process and recycle a completed SITD. Return true iff its urb completed, |
2042 | * and hence its completion callback probably added things to the hardware | |
2043 | * schedule. | |
2044 | * | |
2045 | * Note that we carefully avoid recycling this descriptor until after any | |
2046 | * completion callback runs, so that it won't be reused quickly. That is, | |
2047 | * assuming (a) no more than two urbs per frame on this endpoint, and also | |
2048 | * (b) only this endpoint's completions submit URBs. It seems some silicon | |
2049 | * corrupts things if you reuse completed descriptors very quickly... | |
2050 | */ | |
f4289078 AS |
2051 | static bool sitd_complete(struct ehci_hcd *ehci, struct ehci_sitd *sitd) |
2052 | { | |
1da177e4 LT |
2053 | struct urb *urb = sitd->urb; |
2054 | struct usb_iso_packet_descriptor *desc; | |
2055 | u32 t; | |
2056 | int urb_index = -1; | |
2057 | struct ehci_iso_stream *stream = sitd->stream; | |
2058 | struct usb_device *dev; | |
f4289078 | 2059 | bool retval = false; |
1da177e4 LT |
2060 | |
2061 | urb_index = sitd->index; | |
2062 | desc = &urb->iso_frame_desc [urb_index]; | |
6dbd682b | 2063 | t = hc32_to_cpup(ehci, &sitd->hw_results); |
1da177e4 LT |
2064 | |
2065 | /* report transfer status */ | |
4005ad43 | 2066 | if (unlikely(t & SITD_ERRS)) { |
1da177e4 LT |
2067 | urb->error_count++; |
2068 | if (t & SITD_STS_DBE) | |
2069 | desc->status = usb_pipein (urb->pipe) | |
2070 | ? -ENOSR /* hc couldn't read */ | |
2071 | : -ECOMM; /* hc couldn't write */ | |
2072 | else if (t & SITD_STS_BABBLE) | |
2073 | desc->status = -EOVERFLOW; | |
2074 | else /* XACT, MMF, etc */ | |
2075 | desc->status = -EPROTO; | |
4005ad43 AS |
2076 | } else if (unlikely(t & SITD_STS_ACTIVE)) { |
2077 | /* URB was too late */ | |
2078 | urb->error_count++; | |
1da177e4 LT |
2079 | } else { |
2080 | desc->status = 0; | |
ec6d67e3 AS |
2081 | desc->actual_length = desc->length - SITD_LENGTH(t); |
2082 | urb->actual_length += desc->actual_length; | |
1da177e4 | 2083 | } |
1da177e4 LT |
2084 | |
2085 | /* handle completion now? */ | |
2086 | if ((urb_index + 1) != urb->number_of_packets) | |
30bf54e6 | 2087 | goto done; |
1da177e4 LT |
2088 | |
2089 | /* ASSERT: it's really the last sitd for this urb | |
2090 | list_for_each_entry (sitd, &stream->td_list, sitd_list) | |
2091 | BUG_ON (sitd->urb == urb); | |
2092 | */ | |
2093 | ||
aa16ca30 | 2094 | /* give urb back to the driver; completion often (re)submits */ |
6a8e87b2 | 2095 | dev = urb->dev; |
14c04c0f | 2096 | ehci_urb_done(ehci, urb, 0); |
30bf54e6 | 2097 | retval = true; |
1da177e4 | 2098 | urb = NULL; |
569b394f AS |
2099 | |
2100 | --ehci->isoc_count; | |
b015cb79 | 2101 | disable_periodic(ehci); |
1da177e4 | 2102 | |
569b394f | 2103 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
05570297 | 2104 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { |
ad93562b AX |
2105 | if (ehci->amd_pll_fix == 1) |
2106 | usb_amd_quirk_pll_enable(); | |
05570297 AH |
2107 | } |
2108 | ||
508db8c9 | 2109 | if (list_is_singular(&stream->td_list)) { |
1da177e4 LT |
2110 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
2111 | -= stream->bandwidth; | |
2112 | ehci_vdbg (ehci, | |
2113 | "deschedule devp %s ep%d%s-iso\n", | |
2114 | dev->devpath, stream->bEndpointAddress & 0x0f, | |
2115 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out"); | |
2116 | } | |
0e5f231b | 2117 | |
30bf54e6 | 2118 | done: |
30bf54e6 | 2119 | sitd->urb = NULL; |
55934eb3 AS |
2120 | |
2121 | /* Add to the end of the free list for later reuse */ | |
2122 | list_move_tail(&sitd->sitd_list, &stream->free_list); | |
2123 | ||
2124 | /* Recycle the siTDs when the pipeline is empty (ep no longer in use) */ | |
2125 | if (list_empty(&stream->td_list)) { | |
2126 | list_splice_tail_init(&stream->free_list, | |
2127 | &ehci->cached_sitd_list); | |
2128 | start_free_itds(ehci); | |
0e5f231b | 2129 | } |
55934eb3 | 2130 | |
30bf54e6 | 2131 | return retval; |
1da177e4 LT |
2132 | } |
2133 | ||
2134 | ||
5db539e4 | 2135 | static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb, |
55016f10 | 2136 | gfp_t mem_flags) |
1da177e4 LT |
2137 | { |
2138 | int status = -EINVAL; | |
2139 | unsigned long flags; | |
2140 | struct ehci_iso_stream *stream; | |
2141 | ||
2142 | /* Get iso_stream head */ | |
2143 | stream = iso_stream_find (ehci, urb); | |
2144 | if (stream == NULL) { | |
2145 | ehci_dbg (ehci, "can't get iso stream\n"); | |
2146 | return -ENOMEM; | |
2147 | } | |
2148 | if (urb->interval != stream->interval) { | |
2149 | ehci_dbg (ehci, "can't change iso interval %d --> %d\n", | |
2150 | stream->interval, urb->interval); | |
2151 | goto done; | |
2152 | } | |
2153 | ||
2154 | #ifdef EHCI_URB_TRACE | |
2155 | ehci_dbg (ehci, | |
2156 | "submit %p dev%s ep%d%s-iso len %d\n", | |
2157 | urb, urb->dev->devpath, | |
2158 | usb_pipeendpoint (urb->pipe), | |
2159 | usb_pipein (urb->pipe) ? "in" : "out", | |
2160 | urb->transfer_buffer_length); | |
2161 | #endif | |
2162 | ||
2163 | /* allocate SITDs */ | |
2164 | status = sitd_urb_transaction (stream, ehci, urb, mem_flags); | |
2165 | if (status < 0) { | |
2166 | ehci_dbg (ehci, "can't init sitds\n"); | |
2167 | goto done; | |
2168 | } | |
2169 | ||
2170 | /* schedule ... need to lock */ | |
2171 | spin_lock_irqsave (&ehci->lock, flags); | |
541c7d43 | 2172 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 2173 | status = -ESHUTDOWN; |
e9df41c5 AS |
2174 | goto done_not_linked; |
2175 | } | |
2176 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); | |
2177 | if (unlikely(status)) | |
2178 | goto done_not_linked; | |
2179 | status = iso_stream_schedule(ehci, urb, stream); | |
53bd6a60 | 2180 | if (status == 0) |
1da177e4 | 2181 | sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream); |
e9df41c5 AS |
2182 | else |
2183 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
8c5bf7be | 2184 | done_not_linked: |
1da177e4 | 2185 | spin_unlock_irqrestore (&ehci->lock, flags); |
8c5bf7be | 2186 | done: |
1da177e4 LT |
2187 | return status; |
2188 | } | |
2189 | ||
1da177e4 LT |
2190 | /*-------------------------------------------------------------------------*/ |
2191 | ||
569b394f | 2192 | static void scan_isoc(struct ehci_hcd *ehci) |
1da177e4 | 2193 | { |
f4289078 AS |
2194 | unsigned uf, now_frame, frame; |
2195 | unsigned fmask = ehci->periodic_size - 1; | |
2196 | bool modified, live; | |
1da177e4 LT |
2197 | |
2198 | /* | |
2199 | * When running, scan from last scan point up to "now" | |
2200 | * else clean up by scanning everything that's left. | |
2201 | * Touches as few pages as possible: cache-friendly. | |
2202 | */ | |
c0c53dbc | 2203 | if (ehci->rh_state >= EHCI_RH_RUNNING) { |
f4289078 AS |
2204 | uf = ehci_read_frame_index(ehci); |
2205 | now_frame = (uf >> 3) & fmask; | |
2206 | live = true; | |
9aa09d2f | 2207 | } else { |
c3ee9b76 | 2208 | now_frame = (ehci->last_iso_frame - 1) & fmask; |
f4289078 | 2209 | live = false; |
9aa09d2f | 2210 | } |
f4289078 | 2211 | ehci->now_frame = now_frame; |
1da177e4 | 2212 | |
b09a61cc | 2213 | frame = ehci->last_iso_frame; |
1da177e4 LT |
2214 | for (;;) { |
2215 | union ehci_shadow q, *q_p; | |
6dbd682b | 2216 | __hc32 type, *hw_p; |
1da177e4 LT |
2217 | |
2218 | restart: | |
2219 | /* scan each element in frame's queue for completions */ | |
2220 | q_p = &ehci->pshadow [frame]; | |
2221 | hw_p = &ehci->periodic [frame]; | |
2222 | q.ptr = q_p->ptr; | |
6dbd682b | 2223 | type = Q_NEXT_TYPE(ehci, *hw_p); |
f4289078 | 2224 | modified = false; |
1da177e4 LT |
2225 | |
2226 | while (q.ptr != NULL) { | |
6dbd682b | 2227 | switch (hc32_to_cpu(ehci, type)) { |
1da177e4 | 2228 | case Q_TYPE_ITD: |
79592b72 DB |
2229 | /* If this ITD is still active, leave it for |
2230 | * later processing ... check the next entry. | |
b40e43fc AS |
2231 | * No need to check for activity unless the |
2232 | * frame is current. | |
79592b72 | 2233 | */ |
f4289078 | 2234 | if (frame == now_frame && live) { |
b40e43fc AS |
2235 | rmb(); |
2236 | for (uf = 0; uf < 8; uf++) { | |
2237 | if (q.itd->hw_transaction[uf] & | |
2238 | ITD_ACTIVE(ehci)) | |
2239 | break; | |
2240 | } | |
2241 | if (uf < 8) { | |
b40e43fc AS |
2242 | q_p = &q.itd->itd_next; |
2243 | hw_p = &q.itd->hw_next; | |
2244 | type = Q_NEXT_TYPE(ehci, | |
6dbd682b | 2245 | q.itd->hw_next); |
b40e43fc AS |
2246 | q = *q_p; |
2247 | break; | |
2248 | } | |
1da177e4 | 2249 | } |
1da177e4 | 2250 | |
79592b72 DB |
2251 | /* Take finished ITDs out of the schedule |
2252 | * and process them: recycle, maybe report | |
2253 | * URB completion. HC won't cache the | |
1da177e4 LT |
2254 | * pointer for much longer, if at all. |
2255 | */ | |
2256 | *q_p = q.itd->itd_next; | |
3d091a6f AX |
2257 | if (!ehci->use_dummy_qh || |
2258 | q.itd->hw_next != EHCI_LIST_END(ehci)) | |
2259 | *hw_p = q.itd->hw_next; | |
2260 | else | |
2261 | *hw_p = ehci->dummy->qh_dma; | |
6dbd682b | 2262 | type = Q_NEXT_TYPE(ehci, q.itd->hw_next); |
1da177e4 | 2263 | wmb(); |
7d12e780 | 2264 | modified = itd_complete (ehci, q.itd); |
1da177e4 LT |
2265 | q = *q_p; |
2266 | break; | |
2267 | case Q_TYPE_SITD: | |
79592b72 DB |
2268 | /* If this SITD is still active, leave it for |
2269 | * later processing ... check the next entry. | |
b40e43fc AS |
2270 | * No need to check for activity unless the |
2271 | * frame is current. | |
79592b72 | 2272 | */ |
f4289078 AS |
2273 | if (((frame == now_frame) || |
2274 | (((frame + 1) & fmask) == now_frame)) | |
22e18694 DE |
2275 | && live |
2276 | && (q.sitd->hw_results & | |
2277 | SITD_ACTIVE(ehci))) { | |
2278 | ||
1da177e4 LT |
2279 | q_p = &q.sitd->sitd_next; |
2280 | hw_p = &q.sitd->hw_next; | |
6dbd682b SR |
2281 | type = Q_NEXT_TYPE(ehci, |
2282 | q.sitd->hw_next); | |
1da177e4 LT |
2283 | q = *q_p; |
2284 | break; | |
2285 | } | |
79592b72 DB |
2286 | |
2287 | /* Take finished SITDs out of the schedule | |
2288 | * and process them: recycle, maybe report | |
2289 | * URB completion. | |
2290 | */ | |
1da177e4 | 2291 | *q_p = q.sitd->sitd_next; |
3d091a6f AX |
2292 | if (!ehci->use_dummy_qh || |
2293 | q.sitd->hw_next != EHCI_LIST_END(ehci)) | |
2294 | *hw_p = q.sitd->hw_next; | |
2295 | else | |
2296 | *hw_p = ehci->dummy->qh_dma; | |
6dbd682b | 2297 | type = Q_NEXT_TYPE(ehci, q.sitd->hw_next); |
1da177e4 | 2298 | wmb(); |
7d12e780 | 2299 | modified = sitd_complete (ehci, q.sitd); |
1da177e4 LT |
2300 | q = *q_p; |
2301 | break; | |
2302 | default: | |
2d0fe1bb | 2303 | ehci_dbg(ehci, "corrupt type %d frame %d shadow %p\n", |
1da177e4 LT |
2304 | type, frame, q.ptr); |
2305 | // BUG (); | |
569b394f AS |
2306 | /* FALL THROUGH */ |
2307 | case Q_TYPE_QH: | |
2308 | case Q_TYPE_FSTN: | |
2309 | /* End of the iTDs and siTDs */ | |
1da177e4 | 2310 | q.ptr = NULL; |
569b394f | 2311 | break; |
1da177e4 LT |
2312 | } |
2313 | ||
2314 | /* assume completion callbacks modify the queue */ | |
f4289078 AS |
2315 | if (unlikely(modified && ehci->isoc_count > 0)) |
2316 | goto restart; | |
1da177e4 LT |
2317 | } |
2318 | ||
f4289078 AS |
2319 | /* Stop when we have reached the current frame */ |
2320 | if (frame == now_frame) | |
79592b72 | 2321 | break; |
b09a61cc AS |
2322 | |
2323 | /* The last frame may still have active siTDs */ | |
2324 | ehci->last_iso_frame = frame; | |
2325 | frame = (frame + 1) & fmask; | |
53bd6a60 | 2326 | } |
1da177e4 | 2327 | } |