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usb: isp1760: Merge platform and OF glue codes
[deliverable/linux.git] / drivers / usb / host / isp1760-hcd.c
CommitLineData
db11e47d
SS		 1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
71a9f9d2
AB		 11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
12 *
db11e47d 13 */
7eb42c6e 14#include <linux/gpio/consumer.h>
db11e47d
SS		 15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/list.h>
19#include <linux/usb.h>
27729aad 20#include <linux/usb/hcd.h>
db11e47d
SS		 21#include <linux/debugfs.h>
22#include <linux/uaccess.h>
23#include <linux/io.h>
db8516f6 24#include <linux/mm.h>
6d50c60e 25#include <linux/timer.h>
db11e47d 26#include <asm/unaligned.h>
db8516f6 27#include <asm/cacheflush.h>
db11e47d 28
db11e47d
SS		 29#include "isp1760-hcd.h"
30
31static struct kmem_cache *qtd_cachep;
32static struct kmem_cache *qh_cachep;
71a9f9d2 33static struct kmem_cache *urb_listitem_cachep;
db11e47d 34
e08f6a27
AB		 35enum queue_head_types {
36 QH_CONTROL,
37 QH_BULK,
38 QH_INTERRUPT,
39 QH_END
40};
41
db11e47d
SS		 42struct isp1760_hcd {
43 u32 hcs_params;
44 spinlock_t lock;
71a9f9d2 45 struct slotinfo atl_slots[32];
d05b6ec0 46 int atl_done_map;
71a9f9d2 47 struct slotinfo int_slots[32];
d05b6ec0 48 int int_done_map;
db11e47d 49 struct memory_chunk memory_pool[BLOCKS];
e08f6a27 50 struct list_head qh_list[QH_END];
db11e47d
SS		 51
52 /* periodic schedule support */
53#define DEFAULT_I_TDPS 1024
54 unsigned periodic_size;
55 unsigned i_thresh;
56 unsigned long reset_done;
57 unsigned long next_statechange;
3faefc88 58 unsigned int devflags;
3a7655fc 59
7eb42c6e 60 struct gpio_desc *rst_gpio;
db11e47d
SS		 61};
62
63static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
64{
65 return (struct isp1760_hcd *) (hcd->hcd_priv);
66}
db11e47d
SS		 67
68/* Section 2.2 Host Controller Capability Registers */
69#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
70#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
71#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
72#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
73#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
74#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
75#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
76
77/* Section 2.3 Host Controller Operational Registers */
78#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
79#define CMD_RESET (1<<1) /* reset HC not bus */
80#define CMD_RUN (1<<0) /* start/stop HC */
81#define STS_PCD (1<<2) /* port change detect */
82#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
83
84#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
85#define PORT_POWER (1<<12) /* true: has power (see PPC) */
86#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
87#define PORT_RESET (1<<8) /* reset port */
88#define PORT_SUSPEND (1<<7) /* suspend port */
89#define PORT_RESUME (1<<6) /* resume it */
90#define PORT_PE (1<<2) /* port enable */
91#define PORT_CSC (1<<1) /* connect status change */
92#define PORT_CONNECT (1<<0) /* device connected */
93#define PORT_RWC_BITS (PORT_CSC)
94
95struct isp1760_qtd {
db11e47d 96 u8 packet_type;
db11e47d 97 void *data_buffer;
a041d8e4
AB		 98 u32 payload_addr;
99
db11e47d
SS		 100 /* the rest is HCD-private */
101 struct list_head qtd_list;
102 struct urb *urb;
103 size_t length;
71a9f9d2
AB		 104 size_t actual_length;
105
106 /* QTD_ENQUEUED: waiting for transfer (inactive) */
107 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
108 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
109 interrupt handler may touch this qtd! */
110 /* QTD_XFER_COMPLETE: payload has been transferred successfully */
111 /* QTD_RETIRE: transfer error/abort qtd */
112#define QTD_ENQUEUED 0
113#define QTD_PAYLOAD_ALLOC 1
114#define QTD_XFER_STARTED 2
115#define QTD_XFER_COMPLETE 3
116#define QTD_RETIRE 4
db11e47d 117 u32 status;
db11e47d
SS		 118};
119
71a9f9d2 120/* Queue head, one for each active endpoint */
db11e47d 121struct isp1760_qh {
71a9f9d2 122 struct list_head qh_list;
db11e47d 123 struct list_head qtd_list;
db11e47d
SS		 124 u32 toggle;
125 u32 ping;
71a9f9d2 126 int slot;
74ad6029 127 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
71a9f9d2
AB		 128};
129
130struct urb_listitem {
131 struct list_head urb_list;
132 struct urb *urb;
db11e47d
SS		 133};
134
bedc0c31
AB		 135/*
136 * Access functions for isp176x registers (addresses 0..0x03FF).
137 */
138static u32 reg_read32(void __iomem *base, u32 reg)
db11e47d 139{
bedc0c31 140 return readl(base + reg);
db11e47d
SS		 141}
142
bedc0c31 143static void reg_write32(void __iomem *base, u32 reg, u32 val)
db11e47d 144{
bedc0c31 145 writel(val, base + reg);
db11e47d
SS		 146}
147
148/*
bedc0c31
AB		 149 * Access functions for isp176x memory (offset >= 0x0400).
150 *
151 * bank_reads8() reads memory locations prefetched by an earlier write to
152 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
153 * bank optimizations, you should use the more generic mem_reads8() below.
154 *
155 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
156 * below.
157 *
158 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
db11e47d
SS		 159 * doesn't quite work because some people have to enforce 32-bit access
160 */
bedc0c31
AB		 161static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
162 __u32 *dst, u32 bytes)
db11e47d 163{
bedc0c31 164 __u32 __iomem *src;
db11e47d 165 u32 val;
bedc0c31
AB		 166 __u8 *src_byteptr;
167 __u8 *dst_byteptr;
db11e47d 168
bedc0c31 169 src = src_base + (bank_addr | src_offset);
db11e47d 170
bedc0c31
AB		 171 if (src_offset < PAYLOAD_OFFSET) {
172 while (bytes >= 4) {
173 *dst = le32_to_cpu(__raw_readl(src));
174 bytes -= 4;
175 src++;
176 dst++;
177 }
178 } else {
179 while (bytes >= 4) {
180 *dst = __raw_readl(src);
181 bytes -= 4;
182 src++;
183 dst++;
184 }
db11e47d
SS		 185 }
186
bedc0c31 187 if (!bytes)
db11e47d
SS		 188 return;
189
190 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
191 * allocated.
192 */
bedc0c31
AB		 193 if (src_offset < PAYLOAD_OFFSET)
194 val = le32_to_cpu(__raw_readl(src));
195 else
196 val = __raw_readl(src);
197
198 dst_byteptr = (void *) dst;
199 src_byteptr = (void *) &val;
200 while (bytes > 0) {
201 *dst_byteptr = *src_byteptr;
202 dst_byteptr++;
203 src_byteptr++;
204 bytes--;
db11e47d
SS		 205 }
206}
207
bedc0c31
AB		 208static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
209 u32 bytes)
db11e47d 210{
bedc0c31
AB		 211 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
212 ndelay(90);
213 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
214}
215
216static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
217 __u32 const *src, u32 bytes)
218{
219 __u32 __iomem *dst;
220
221 dst = dst_base + dst_offset;
222
223 if (dst_offset < PAYLOAD_OFFSET) {
224 while (bytes >= 4) {
225 __raw_writel(cpu_to_le32(*src), dst);
226 bytes -= 4;
227 src++;
228 dst++;
229 }
230 } else {
231 while (bytes >= 4) {
232 __raw_writel(*src, dst);
233 bytes -= 4;
234 src++;
235 dst++;
236 }
db11e47d
SS		 237 }
238
bedc0c31 239 if (!bytes)
db11e47d 240 return;
bedc0c31
AB		 241 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
242 * extra bytes should not be read by the HW.
db11e47d
SS		 243 */
244
bedc0c31
AB		 245 if (dst_offset < PAYLOAD_OFFSET)
246 __raw_writel(cpu_to_le32(*src), dst);
247 else
248 __raw_writel(*src, dst);
db11e47d
SS		 249}
250
bedc0c31
AB		 251/*
252 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
253 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
254 */
255static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
256 struct ptd *ptd)
257{
258 reg_write32(base, HC_MEMORY_REG,
259 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
260 ndelay(90);
261 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
262 (void *) ptd, sizeof(*ptd));
263}
264
265static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
266 struct ptd *ptd)
267{
268 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
269 &ptd->dw1, 7*sizeof(ptd->dw1));
270 /* Make sure dw0 gets written last (after other dw's and after payload)
271 since it contains the enable bit */
272 wmb();
273 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
274 sizeof(ptd->dw0));
275}
276
277
db11e47d
SS		 278/* memory management of the 60kb on the chip from 0x1000 to 0xffff */
279static void init_memory(struct isp1760_hcd *priv)
280{
a041d8e4
AB		 281 int i, curr;
282 u32 payload_addr;
db11e47d 283
a041d8e4 284 payload_addr = PAYLOAD_OFFSET;
db11e47d 285 for (i = 0; i < BLOCK_1_NUM; i++) {
a041d8e4 286 priv->memory_pool[i].start = payload_addr;
db11e47d
SS		 287 priv->memory_pool[i].size = BLOCK_1_SIZE;
288 priv->memory_pool[i].free = 1;
a041d8e4 289 payload_addr += priv->memory_pool[i].size;
db11e47d
SS		 290 }
291
a041d8e4
AB		 292 curr = i;
293 for (i = 0; i < BLOCK_2_NUM; i++) {
294 priv->memory_pool[curr + i].start = payload_addr;
295 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
296 priv->memory_pool[curr + i].free = 1;
297 payload_addr += priv->memory_pool[curr + i].size;
db11e47d
SS		 298 }
299
a041d8e4
AB		 300 curr = i;
301 for (i = 0; i < BLOCK_3_NUM; i++) {
302 priv->memory_pool[curr + i].start = payload_addr;
303 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
304 priv->memory_pool[curr + i].free = 1;
305 payload_addr += priv->memory_pool[curr + i].size;
db11e47d
SS		 306 }
307
34537731 308 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
db11e47d
SS		 309}
310
6bda21bc 311static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
db11e47d 312{
6bda21bc 313 struct isp1760_hcd *priv = hcd_to_priv(hcd);
db11e47d
SS		 314 int i;
315
34537731 316 WARN_ON(qtd->payload_addr);
a041d8e4
AB		 317
318 if (!qtd->length)
319 return;
db11e47d
SS		 320
321 for (i = 0; i < BLOCKS; i++) {
a041d8e4 322 if (priv->memory_pool[i].size >= qtd->length &&
db11e47d 323 priv->memory_pool[i].free) {
db11e47d 324 priv->memory_pool[i].free = 0;
a041d8e4
AB		 325 qtd->payload_addr = priv->memory_pool[i].start;
326 return;
db11e47d
SS		 327 }
328 }
db11e47d
SS		 329}
330
6bda21bc 331static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
db11e47d 332{
6bda21bc 333 struct isp1760_hcd *priv = hcd_to_priv(hcd);
db11e47d
SS		 334 int i;
335
a041d8e4 336 if (!qtd->payload_addr)
db11e47d
SS		 337 return;
338
339 for (i = 0; i < BLOCKS; i++) {
a041d8e4 340 if (priv->memory_pool[i].start == qtd->payload_addr) {
34537731 341 WARN_ON(priv->memory_pool[i].free);
db11e47d 342 priv->memory_pool[i].free = 1;
a041d8e4
AB		 343 qtd->payload_addr = 0;
344 return;
db11e47d
SS		 345 }
346 }
347
6bda21bc
AB		 348 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
349 __func__, qtd->payload_addr);
71a9f9d2
AB		 350 WARN_ON(1);
351 qtd->payload_addr = 0;
db11e47d
SS		 352}
353
bedc0c31 354static int handshake(struct usb_hcd *hcd, u32 reg,
db11e47d
SS		 355 u32 mask, u32 done, int usec)
356{
357 u32 result;
358
359 do {
bedc0c31 360 result = reg_read32(hcd->regs, reg);
db11e47d
SS		 361 if (result == ~0)
362 return -ENODEV;
363 result &= mask;
364 if (result == done)
365 return 0;
366 udelay(1);
367 usec--;
368 } while (usec > 0);
369 return -ETIMEDOUT;
370}
371
372/* reset a non-running (STS_HALT == 1) controller */
6bda21bc 373static int ehci_reset(struct usb_hcd *hcd)
db11e47d
SS		 374{
375 int retval;
6bda21bc
AB		 376 struct isp1760_hcd *priv = hcd_to_priv(hcd);
377
bedc0c31 378 u32 command = reg_read32(hcd->regs, HC_USBCMD);
db11e47d
SS		 379
380 command |= CMD_RESET;
bedc0c31 381 reg_write32(hcd->regs, HC_USBCMD, command);
db11e47d
SS		 382 hcd->state = HC_STATE_HALT;
383 priv->next_statechange = jiffies;
bedc0c31 384 retval = handshake(hcd, HC_USBCMD,
db11e47d
SS		 385 CMD_RESET, 0, 250 * 1000);
386 return retval;
387}
388
71a9f9d2 389static struct isp1760_qh *qh_alloc(gfp_t flags)
db11e47d
SS		 390{
391 struct isp1760_qh *qh;
392
393 qh = kmem_cache_zalloc(qh_cachep, flags);
394 if (!qh)
71a9f9d2 395 return NULL;
db11e47d 396
71a9f9d2 397 INIT_LIST_HEAD(&qh->qh_list);
db11e47d 398 INIT_LIST_HEAD(&qh->qtd_list);
71a9f9d2
AB		 399 qh->slot = -1;
400
db11e47d
SS		 401 return qh;
402}
403
71a9f9d2
AB		 404static void qh_free(struct isp1760_qh *qh)
405{
406 WARN_ON(!list_empty(&qh->qtd_list));
407 WARN_ON(qh->slot > -1);
408 kmem_cache_free(qh_cachep, qh);
409}
db11e47d
SS		 410
411/* one-time init, only for memory state */
412static int priv_init(struct usb_hcd *hcd)
413{
414 struct isp1760_hcd *priv = hcd_to_priv(hcd);
415 u32 hcc_params;
e08f6a27 416 int i;
db11e47d
SS		 417
418 spin_lock_init(&priv->lock);
419
e08f6a27
AB		 420 for (i = 0; i < QH_END; i++)
421 INIT_LIST_HEAD(&priv->qh_list[i]);
71a9f9d2 422
db11e47d
SS		 423 /*
424 * hw default: 1K periodic list heads, one per frame.
425 * periodic_size can shrink by USBCMD update if hcc_params allows.
426 */
427 priv->periodic_size = DEFAULT_I_TDPS;
428
429 /* controllers may cache some of the periodic schedule ... */
bedc0c31 430 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
db11e47d
SS		 431 /* full frame cache */
432 if (HCC_ISOC_CACHE(hcc_params))
433 priv->i_thresh = 8;
434 else /* N microframes cached */
435 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
436
437 return 0;
438}
439
440static int isp1760_hc_setup(struct usb_hcd *hcd)
441{
442 struct isp1760_hcd *priv = hcd_to_priv(hcd);
443 int result;
3faefc88
NC		 444 u32 scratch, hwmode;
445
3a7655fc 446 /* low-level chip reset */
7eb42c6e
LP		 447 if (priv->rst_gpio) {
448 gpiod_set_value_cansleep(priv->rst_gpio, 1);
3a7655fc 449 mdelay(50);
7eb42c6e 450 gpiod_set_value_cansleep(priv->rst_gpio, 0);
3a7655fc
JF		 451 }
452
3faefc88
NC		 453 /* Setup HW Mode Control: This assumes a level active-low interrupt */
454 hwmode = HW_DATA_BUS_32BIT;
455
456 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
457 hwmode &= ~HW_DATA_BUS_32BIT;
458 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
459 hwmode |= HW_ANA_DIGI_OC;
460 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
461 hwmode |= HW_DACK_POL_HIGH;
462 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
463 hwmode |= HW_DREQ_POL_HIGH;
9da69c60
MH		 464 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
465 hwmode |= HW_INTR_HIGH_ACT;
466 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
467 hwmode |= HW_INTR_EDGE_TRIG;
3faefc88
NC		 468
469 /*
470 * We have to set this first in case we're in 16-bit mode.
471 * Write it twice to ensure correct upper bits if switching
472 * to 16-bit mode.
473 */
bedc0c31
AB		 474 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
475 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
db11e47d 476
bedc0c31 477 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
3faefc88 478 /* Change bus pattern */
bedc0c31
AB		 479 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
480 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
db11e47d 481 if (scratch != 0xdeadbabe) {
6bda21bc 482 dev_err(hcd->self.controller, "Scratch test failed.\n");
db11e47d
SS		 483 return -ENODEV;
484 }
485
486 /* pre reset */
71a9f9d2
AB		 487 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
488 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
489 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
490 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
db11e47d
SS		 491
492 /* reset */
bedc0c31 493 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
db11e47d
SS		 494 mdelay(100);
495
bedc0c31 496 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
db11e47d
SS		 497 mdelay(100);
498
6bda21bc 499 result = ehci_reset(hcd);
db11e47d
SS		 500 if (result)
501 return result;
502
503 /* Step 11 passed */
504
6bda21bc 505 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
3faefc88
NC		 506 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
507 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
508 "analog" : "digital");
db11e47d
SS		 509
510 /* ATL reset */
bedc0c31 511 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
db11e47d 512 mdelay(10);
bedc0c31 513 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
db11e47d 514
bedc0c31 515 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
3faefc88
NC		 516
517 /*
518 * PORT 1 Control register of the ISP1760 is the OTG control
42c65396
TH		 519 * register on ISP1761. Since there is no OTG or device controller
520 * support in this driver, we use port 1 as a "normal" USB host port on
521 * both chips.
3faefc88 522 */
bedc0c31 523 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
42c65396 524 mdelay(10);
db11e47d 525
bedc0c31 526 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
db11e47d
SS		 527
528 return priv_init(hcd);
529}
530
db11e47d
SS		 531static u32 base_to_chip(u32 base)
532{
533 return ((base - 0x400) >> 3);
534}
535
7adc14b1
AB		 536static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
537{
538 struct urb *urb;
539
540 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
541 return 1;
542
543 urb = qtd->urb;
544 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
545 return (qtd->urb != urb);
546}
547
71a9f9d2
AB		 548/* magic numbers that can affect system performance */
549#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
550#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
551#define EHCI_TUNE_RL_TT 0
552#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
553#define EHCI_TUNE_MULT_TT 1
554#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
555
556static void create_ptd_atl(struct isp1760_qh *qh,
a041d8e4 557 struct isp1760_qtd *qtd, struct ptd *ptd)
db11e47d 558{
db11e47d
SS		 559 u32 maxpacket;
560 u32 multi;
db11e47d
SS		 561 u32 rl = RL_COUNTER;
562 u32 nak = NAK_COUNTER;
563
bedc0c31
AB		 564 memset(ptd, 0, sizeof(*ptd));
565
db11e47d 566 /* according to 3.6.2, max packet len can not be > 0x400 */
a041d8e4
AB		 567 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
568 usb_pipeout(qtd->urb->pipe));
db11e47d
SS		 569 multi = 1 + ((maxpacket >> 11) & 0x3);
570 maxpacket &= 0x7ff;
571
572 /* DW0 */
71a9f9d2
AB		 573 ptd->dw0 = DW0_VALID_BIT;
574 ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
575 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
576 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
db11e47d
SS		 577
578 /* DW1 */
a041d8e4 579 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
71a9f9d2
AB		 580 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
581 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
db11e47d 582
a041d8e4 583 if (usb_pipebulk(qtd->urb->pipe))
71a9f9d2 584 ptd->dw1 |= DW1_TRANS_BULK;
a041d8e4 585 else if (usb_pipeint(qtd->urb->pipe))
71a9f9d2 586 ptd->dw1 |= DW1_TRANS_INT;
db11e47d 587
a041d8e4 588 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
db11e47d
SS		 589 /* split transaction */
590
71a9f9d2 591 ptd->dw1 |= DW1_TRANS_SPLIT;
a041d8e4 592 if (qtd->urb->dev->speed == USB_SPEED_LOW)
71a9f9d2 593 ptd->dw1 |= DW1_SE_USB_LOSPEED;
db11e47d 594
71a9f9d2
AB		 595 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
596 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
db11e47d
SS		 597
598 /* SE bit for Split INT transfers */
a041d8e4
AB		 599 if (usb_pipeint(qtd->urb->pipe) &&
600 (qtd->urb->dev->speed == USB_SPEED_LOW))
bedc0c31 601 ptd->dw1 |= 2 << 16;
db11e47d 602
db11e47d
SS		 603 rl = 0;
604 nak = 0;
605 } else {
71a9f9d2 606 ptd->dw0 |= TO_DW0_MULTI(multi);
a041d8e4
AB		 607 if (usb_pipecontrol(qtd->urb->pipe) ||
608 usb_pipebulk(qtd->urb->pipe))
71a9f9d2 609 ptd->dw3 |= TO_DW3_PING(qh->ping);
db11e47d
SS		 610 }
611 /* DW2 */
bedc0c31 612 ptd->dw2 = 0;
71a9f9d2
AB		 613 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
614 ptd->dw2 |= TO_DW2_RL(rl);
db11e47d
SS		 615
616 /* DW3 */
71a9f9d2
AB		 617 ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
618 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
7adc14b1
AB		 619 if (usb_pipecontrol(qtd->urb->pipe)) {
620 if (qtd->data_buffer == qtd->urb->setup_packet)
71a9f9d2 621 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
7adc14b1 622 else if (last_qtd_of_urb(qtd, qh))
71a9f9d2 623 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
7adc14b1 624 }
db11e47d 625
71a9f9d2 626 ptd->dw3 |= DW3_ACTIVE_BIT;
db11e47d 627 /* Cerr */
71a9f9d2 628 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
db11e47d
SS		 629}
630
6bda21bc 631static void transform_add_int(struct isp1760_qh *qh,
a041d8e4 632 struct isp1760_qtd *qtd, struct ptd *ptd)
db11e47d 633{
65f1b525 634 u32 usof;
db11e47d
SS		 635 u32 period;
636
65f1b525
AB		 637 /*
638 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
639 * the algorithm from the original Philips driver code, which was
640 * pretty much used in this driver before as well, is quite horrendous
641 * and, i believe, incorrect. The code below follows the datasheet and
642 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
643 * more reliable this way (fingers crossed...).
644 */
db11e47d 645
65f1b525
AB		 646 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
647 /* urb->interval is in units of microframes (1/8 ms) */
648 period = qtd->urb->interval >> 3;
649
650 if (qtd->urb->interval > 4)
651 usof = 0x01; /* One bit set =>
652 interval 1 ms * uFrame-match */
653 else if (qtd->urb->interval > 2)
654 usof = 0x22; /* Two bits set => interval 1/2 ms */
655 else if (qtd->urb->interval > 1)
656 usof = 0x55; /* Four bits set => interval 1/4 ms */
db11e47d 657 else
65f1b525 658 usof = 0xff; /* All bits set => interval 1/8 ms */
db11e47d 659 } else {
65f1b525
AB		 660 /* urb->interval is in units of frames (1 ms) */
661 period = qtd->urb->interval;
662 usof = 0x0f; /* Execute Start Split on any of the
663 four first uFrames */
664
665 /*
666 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
667 * complete split needs to be sent. Valid only for IN." Also,
668 * "All bits can be set to one for every transfer." (p 82,
669 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
670 * that number come from? 0xff seems to work fine...
671 */
672 /* ptd->dw5 = 0x1c; */
673 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
db11e47d
SS		 674 }
675
65f1b525
AB		 676 period = period >> 1;/* Ensure equal or shorter period than requested */
677 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
678
bedc0c31
AB		 679 ptd->dw2 |= period;
680 ptd->dw4 = usof;
db11e47d
SS		 681}
682
71a9f9d2 683static void create_ptd_int(struct isp1760_qh *qh,
a041d8e4 684 struct isp1760_qtd *qtd, struct ptd *ptd)
db11e47d 685{
71a9f9d2 686 create_ptd_atl(qh, qtd, ptd);
6bda21bc 687 transform_add_int(qh, qtd, ptd);
db11e47d
SS		 688}
689
6bda21bc 690static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
db11e47d
SS		 691__releases(priv->lock)
692__acquires(priv->lock)
693{
6bda21bc
AB		 694 struct isp1760_hcd *priv = hcd_to_priv(hcd);
695
db11e47d 696 if (!urb->unlinked) {
6bda21bc
AB		 697 if (urb->status == -EINPROGRESS)
698 urb->status = 0;
db11e47d
SS		 699 }
700
db8516f6
CM		 701 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
702 void *ptr;
703 for (ptr = urb->transfer_buffer;
704 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
705 ptr += PAGE_SIZE)
706 flush_dcache_page(virt_to_page(ptr));
707 }
708
db11e47d 709 /* complete() can reenter this HCD */
6bda21bc 710 usb_hcd_unlink_urb_from_ep(hcd, urb);
db11e47d 711 spin_unlock(&priv->lock);
6bda21bc 712 usb_hcd_giveback_urb(hcd, urb, urb->status);
db11e47d
SS		 713 spin_lock(&priv->lock);
714}
715
34537731
AB		 716static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
717 u8 packet_type)
db11e47d 718{
34537731
AB		 719 struct isp1760_qtd *qtd;
720
721 qtd = kmem_cache_zalloc(qtd_cachep, flags);
722 if (!qtd)
723 return NULL;
724
725 INIT_LIST_HEAD(&qtd->qtd_list);
726 qtd->urb = urb;
727 qtd->packet_type = packet_type;
71a9f9d2
AB		 728 qtd->status = QTD_ENQUEUED;
729 qtd->actual_length = 0;
34537731
AB		 730
731 return qtd;
732}
733
734static void qtd_free(struct isp1760_qtd *qtd)
735{
736 WARN_ON(qtd->payload_addr);
db11e47d
SS		 737 kmem_cache_free(qtd_cachep, qtd);
738}
739
71a9f9d2
AB		 740static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
741 struct slotinfo *slots, struct isp1760_qtd *qtd,
742 struct isp1760_qh *qh, struct ptd *ptd)
db11e47d 743{
71a9f9d2 744 struct isp1760_hcd *priv = hcd_to_priv(hcd);
d05b6ec0
AB		 745 int skip_map;
746
71a9f9d2
AB		 747 WARN_ON((slot < 0) || (slot > 31));
748 WARN_ON(qtd->length && !qtd->payload_addr);
749 WARN_ON(slots[slot].qtd);
750 WARN_ON(slots[slot].qh);
751 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
752
d05b6ec0
AB		 753 /* Make sure done map has not triggered from some unlinked transfer */
754 if (ptd_offset == ATL_PTD_OFFSET) {
755 priv->atl_done_map |= reg_read32(hcd->regs,
756 HC_ATL_PTD_DONEMAP_REG);
6477acc0
AB		 757 priv->atl_done_map &= ~(1 << slot);
758 } else {
759 priv->int_done_map |= reg_read32(hcd->regs,
760 HC_INT_PTD_DONEMAP_REG);
761 priv->int_done_map &= ~(1 << slot);
762 }
d05b6ec0 763
6477acc0
AB		 764 qh->slot = slot;
765 qtd->status = QTD_XFER_STARTED;
766 slots[slot].timestamp = jiffies;
767 slots[slot].qtd = qtd;
768 slots[slot].qh = qh;
769 ptd_write(hcd->regs, ptd_offset, slot, ptd);
770
771 if (ptd_offset == ATL_PTD_OFFSET) {
d05b6ec0
AB		 772 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
773 skip_map &= ~(1 << qh->slot);
774 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
775 } else {
d05b6ec0
AB		 776 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
777 skip_map &= ~(1 << qh->slot);
778 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
779 }
db11e47d
SS		 780}
781
71a9f9d2 782static int is_short_bulk(struct isp1760_qtd *qtd)
db11e47d 783{
71a9f9d2
AB		 784 return (usb_pipebulk(qtd->urb->pipe) &&
785 (qtd->actual_length < qtd->length));
db11e47d
SS		 786}
787
71a9f9d2
AB		 788static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
789 struct list_head *urb_list)
db11e47d 790{
71a9f9d2
AB		 791 int last_qtd;
792 struct isp1760_qtd *qtd, *qtd_next;
793 struct urb_listitem *urb_listitem;
db11e47d 794
71a9f9d2
AB		 795 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
796 if (qtd->status < QTD_XFER_COMPLETE)
797 break;
db11e47d 798
38679b72 799 last_qtd = last_qtd_of_urb(qtd, qh);
71a9f9d2
AB		 800
801 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
802 qtd_next->status = QTD_RETIRE;
803
804 if (qtd->status == QTD_XFER_COMPLETE) {
805 if (qtd->actual_length) {
806 switch (qtd->packet_type) {
807 case IN_PID:
808 mem_reads8(hcd->regs, qtd->payload_addr,
809 qtd->data_buffer,
810 qtd->actual_length);
811 /* Fall through (?) */
812 case OUT_PID:
813 qtd->urb->actual_length +=
814 qtd->actual_length;
815 /* Fall through ... */
816 case SETUP_PID:
817 break;
818 }
819 }
db11e47d 820
71a9f9d2
AB		 821 if (is_short_bulk(qtd)) {
822 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
823 qtd->urb->status = -EREMOTEIO;
824 if (!last_qtd)
825 qtd_next->status = QTD_RETIRE;
826 }
827 }
db11e47d 828
71a9f9d2
AB		 829 if (qtd->payload_addr)
830 free_mem(hcd, qtd);
db11e47d 831
71a9f9d2
AB		 832 if (last_qtd) {
833 if ((qtd->status == QTD_RETIRE) &&
834 (qtd->urb->status == -EINPROGRESS))
835 qtd->urb->status = -EPIPE;
836 /* Defer calling of urb_done() since it releases lock */
837 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
838 GFP_ATOMIC);
839 if (unlikely(!urb_listitem))
38679b72 840 break; /* Try again on next call */
71a9f9d2
AB		 841 urb_listitem->urb = qtd->urb;
842 list_add_tail(&urb_listitem->urb_list, urb_list);
843 }
847ed3e8 844
71a9f9d2
AB		 845 list_del(&qtd->qtd_list);
846 qtd_free(qtd);
847 }
848}
3f02a957 849
71a9f9d2
AB		 850#define ENQUEUE_DEPTH 2
851static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
852{
853 struct isp1760_hcd *priv = hcd_to_priv(hcd);
854 int ptd_offset;
855 struct slotinfo *slots;
856 int curr_slot, free_slot;
857 int n;
858 struct ptd ptd;
859 struct isp1760_qtd *qtd;
db11e47d 860
71a9f9d2
AB		 861 if (unlikely(list_empty(&qh->qtd_list))) {
862 WARN_ON(1);
863 return;
864 }
db11e47d 865
74ad6029
AB		 866 /* Make sure this endpoint's TT buffer is clean before queueing ptds */
867 if (qh->tt_buffer_dirty)
868 return;
869
71a9f9d2
AB		 870 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
871 qtd_list)->urb->pipe)) {
872 ptd_offset = INT_PTD_OFFSET;
873 slots = priv->int_slots;
874 } else {
875 ptd_offset = ATL_PTD_OFFSET;
876 slots = priv->atl_slots;
877 }
db11e47d 878
71a9f9d2
AB		 879 free_slot = -1;
880 for (curr_slot = 0; curr_slot < 32; curr_slot++) {
881 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
882 free_slot = curr_slot;
883 if (slots[curr_slot].qh == qh)
884 break;
885 }
db11e47d 886
71a9f9d2
AB		 887 n = 0;
888 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
889 if (qtd->status == QTD_ENQUEUED) {
890 WARN_ON(qtd->payload_addr);
891 alloc_mem(hcd, qtd);
892 if ((qtd->length) && (!qtd->payload_addr))
893 break;
db11e47d 894
71a9f9d2
AB		 895 if ((qtd->length) &&
896 ((qtd->packet_type == SETUP_PID) ||
897 (qtd->packet_type == OUT_PID))) {
898 mem_writes8(hcd->regs, qtd->payload_addr,
899 qtd->data_buffer, qtd->length);
900 }
db11e47d 901
71a9f9d2 902 qtd->status = QTD_PAYLOAD_ALLOC;
db11e47d
SS		 903 }
904
71a9f9d2
AB		 905 if (qtd->status == QTD_PAYLOAD_ALLOC) {
906/*
907 if ((curr_slot > 31) && (free_slot == -1))
908 dev_dbg(hcd->self.controller, "%s: No slot "
909 "available for transfer\n", __func__);
910*/
911 /* Start xfer for this endpoint if not already done */
912 if ((curr_slot > 31) && (free_slot > -1)) {
913 if (usb_pipeint(qtd->urb->pipe))
914 create_ptd_int(qh, qtd, &ptd);
915 else
916 create_ptd_atl(qh, qtd, &ptd);
917
918 start_bus_transfer(hcd, ptd_offset, free_slot,
919 slots, qtd, qh, &ptd);
920 curr_slot = free_slot;
921 }
db11e47d 922
71a9f9d2
AB		 923 n++;
924 if (n >= ENQUEUE_DEPTH)
925 break;
926 }
927 }
928}
db11e47d 929
de9c6307 930static void schedule_ptds(struct usb_hcd *hcd)
71a9f9d2
AB		 931{
932 struct isp1760_hcd *priv;
933 struct isp1760_qh *qh, *qh_next;
934 struct list_head *ep_queue;
71a9f9d2
AB		 935 LIST_HEAD(urb_list);
936 struct urb_listitem *urb_listitem, *urb_listitem_next;
e08f6a27 937 int i;
71a9f9d2
AB		 938
939 if (!hcd) {
940 WARN_ON(1);
941 return;
942 }
db11e47d 943
71a9f9d2 944 priv = hcd_to_priv(hcd);
db11e47d 945
71a9f9d2
AB		 946 /*
947 * check finished/retired xfers, transfer payloads, call urb_done()
948 */
e08f6a27
AB		 949 for (i = 0; i < QH_END; i++) {
950 ep_queue = &priv->qh_list[i];
71a9f9d2 951 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
71a9f9d2 952 collect_qtds(hcd, qh, &urb_list);
c64391f2 953 if (list_empty(&qh->qtd_list))
71a9f9d2 954 list_del(&qh->qh_list);
db11e47d 955 }
71a9f9d2 956 }
db11e47d 957
71a9f9d2
AB		 958 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
959 urb_list) {
960 isp1760_urb_done(hcd, urb_listitem->urb);
961 kmem_cache_free(urb_listitem_cachep, urb_listitem);
962 }
db11e47d 963
71a9f9d2
AB		 964 /*
965 * Schedule packets for transfer.
966 *
967 * According to USB2.0 specification:
968 *
969 * 1st prio: interrupt xfers, up to 80 % of bandwidth
970 * 2nd prio: control xfers
971 * 3rd prio: bulk xfers
972 *
973 * ... but let's use a simpler scheme here (mostly because ISP1761 doc
974 * is very unclear on how to prioritize traffic):
975 *
976 * 1) Enqueue any queued control transfers, as long as payload chip mem
977 * and PTD ATL slots are available.
978 * 2) Enqueue any queued INT transfers, as long as payload chip mem
979 * and PTD INT slots are available.
980 * 3) Enqueue any queued bulk transfers, as long as payload chip mem
981 * and PTD ATL slots are available.
982 *
983 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
984 * conservation of chip mem and performance.
985 *
986 * I'm sure this scheme could be improved upon!
987 */
e08f6a27
AB		 988 for (i = 0; i < QH_END; i++) {
989 ep_queue = &priv->qh_list[i];
71a9f9d2
AB		 990 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
991 enqueue_qtds(hcd, qh);
71a9f9d2
AB		 992 }
993}
db11e47d 994
71a9f9d2
AB		 995#define PTD_STATE_QTD_DONE 1
996#define PTD_STATE_QTD_RELOAD 2
997#define PTD_STATE_URB_RETIRE 3
db11e47d 998
71a9f9d2
AB		 999static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1000 struct urb *urb)
1001{
1002 __dw dw4;
1003 int i;
db11e47d 1004
71a9f9d2
AB		 1005 dw4 = ptd->dw4;
1006 dw4 >>= 8;
db11e47d 1007
71a9f9d2
AB		 1008 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1009 need to handle these errors? Is it done in hardware? */
db11e47d 1010
71a9f9d2 1011 if (ptd->dw3 & DW3_HALT_BIT) {
db11e47d 1012
71a9f9d2 1013 urb->status = -EPROTO; /* Default unknown error */
db11e47d 1014
71a9f9d2
AB		 1015 for (i = 0; i < 8; i++) {
1016 switch (dw4 & 0x7) {
1017 case INT_UNDERRUN:
1018 dev_dbg(hcd->self.controller, "%s: underrun "
1019 "during uFrame %d\n",
1020 __func__, i);
1021 urb->status = -ECOMM; /* Could not write data */
1022 break;
1023 case INT_EXACT:
1024 dev_dbg(hcd->self.controller, "%s: transaction "
1025 "error during uFrame %d\n",
1026 __func__, i);
1027 urb->status = -EPROTO; /* timeout, bad CRC, PID
1028 error etc. */
1029 break;
1030 case INT_BABBLE:
1031 dev_dbg(hcd->self.controller, "%s: babble "
1032 "error during uFrame %d\n",
1033 __func__, i);
1034 urb->status = -EOVERFLOW;
1035 break;
1036 }
1037 dw4 >>= 3;
1038 }
db11e47d 1039
71a9f9d2
AB		 1040 return PTD_STATE_URB_RETIRE;
1041 }
db11e47d 1042
71a9f9d2
AB		 1043 return PTD_STATE_QTD_DONE;
1044}
db11e47d 1045
71a9f9d2
AB		 1046static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1047 struct urb *urb)
1048{
1049 WARN_ON(!ptd);
1050 if (ptd->dw3 & DW3_HALT_BIT) {
1051 if (ptd->dw3 & DW3_BABBLE_BIT)
1052 urb->status = -EOVERFLOW;
1053 else if (FROM_DW3_CERR(ptd->dw3))
1054 urb->status = -EPIPE; /* Stall */
1055 else if (ptd->dw3 & DW3_ERROR_BIT)
1056 urb->status = -EPROTO; /* XactErr */
1057 else
1058 urb->status = -EPROTO; /* Unknown */
1059/*
1060 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1061 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1062 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1063 __func__,
1064 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1065 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1066*/
1067 return PTD_STATE_URB_RETIRE;
1068 }
db11e47d 1069
71a9f9d2
AB		 1070 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1071 /* Transfer Error, *but* active and no HALT -> reload */
1072 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1073 return PTD_STATE_QTD_RELOAD;
1074 }
db11e47d 1075
71a9f9d2
AB		 1076 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1077 /*
1078 * NAKs are handled in HW by the chip. Usually if the
1079 * device is not able to send data fast enough.
1080 * This happens mostly on slower hardware.
1081 */
1082 return PTD_STATE_QTD_RELOAD;
db11e47d 1083 }
71a9f9d2
AB		 1084
1085 return PTD_STATE_QTD_DONE;
db11e47d
SS		 1086}
1087
6d50c60e 1088static void handle_done_ptds(struct usb_hcd *hcd)
db11e47d 1089{
bedc0c31 1090 struct isp1760_hcd *priv = hcd_to_priv(hcd);
db11e47d 1091 struct ptd ptd;
db11e47d 1092 struct isp1760_qh *qh;
71a9f9d2
AB		 1093 int slot;
1094 int state;
1095 struct slotinfo *slots;
1096 u32 ptd_offset;
1097 struct isp1760_qtd *qtd;
1098 int modified;
6d50c60e 1099 int skip_map;
71a9f9d2 1100
6d50c60e
AB		 1101 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1102 priv->int_done_map &= ~skip_map;
1103 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1104 priv->atl_done_map &= ~skip_map;
71a9f9d2 1105
6d50c60e 1106 modified = priv->int_done_map || priv->atl_done_map;
d05b6ec0
AB		 1107
1108 while (priv->int_done_map || priv->atl_done_map) {
1109 if (priv->int_done_map) {
71a9f9d2 1110 /* INT ptd */
d05b6ec0
AB		 1111 slot = __ffs(priv->int_done_map);
1112 priv->int_done_map &= ~(1 << slot);
71a9f9d2 1113 slots = priv->int_slots;
d05b6ec0
AB		 1114 /* This should not trigger, and could be removed if
1115 noone have any problems with it triggering: */
1116 if (!slots[slot].qh) {
1117 WARN_ON(1);
71a9f9d2 1118 continue;
d05b6ec0 1119 }
71a9f9d2
AB		 1120 ptd_offset = INT_PTD_OFFSET;
1121 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1122 state = check_int_transfer(hcd, &ptd,
1123 slots[slot].qtd->urb);
db11e47d 1124 } else {
71a9f9d2 1125 /* ATL ptd */
d05b6ec0
AB		 1126 slot = __ffs(priv->atl_done_map);
1127 priv->atl_done_map &= ~(1 << slot);
71a9f9d2 1128 slots = priv->atl_slots;
d05b6ec0
AB		 1129 /* This should not trigger, and could be removed if
1130 noone have any problems with it triggering: */
1131 if (!slots[slot].qh) {
1132 WARN_ON(1);
71a9f9d2 1133 continue;
d05b6ec0 1134 }
71a9f9d2
AB		 1135 ptd_offset = ATL_PTD_OFFSET;
1136 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1137 state = check_atl_transfer(hcd, &ptd,
1138 slots[slot].qtd->urb);
db11e47d
SS		 1139 }
1140
71a9f9d2
AB		 1141 qtd = slots[slot].qtd;
1142 slots[slot].qtd = NULL;
1143 qh = slots[slot].qh;
1144 slots[slot].qh = NULL;
71a9f9d2
AB		 1145 qh->slot = -1;
1146
1147 WARN_ON(qtd->status != QTD_XFER_STARTED);
1148
1149 switch (state) {
1150 case PTD_STATE_QTD_DONE:
1151 if ((usb_pipeint(qtd->urb->pipe)) &&
1152 (qtd->urb->dev->speed != USB_SPEED_HIGH))
1153 qtd->actual_length =
1154 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1155 else
1156 qtd->actual_length =
1157 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
db11e47d 1158
71a9f9d2
AB		 1159 qtd->status = QTD_XFER_COMPLETE;
1160 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1161 is_short_bulk(qtd))
1162 qtd = NULL;
1163 else
1164 qtd = list_entry(qtd->qtd_list.next,
1165 typeof(*qtd), qtd_list);
db11e47d 1166
71a9f9d2
AB		 1167 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1168 qh->ping = FROM_DW3_PING(ptd.dw3);
1169 break;
db11e47d 1170
71a9f9d2
AB		 1171 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1172 qtd->status = QTD_PAYLOAD_ALLOC;
1173 ptd.dw0 |= DW0_VALID_BIT;
1174 /* RL counter = ERR counter */
1175 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1176 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1177 ptd.dw3 &= ~TO_DW3_CERR(3);
1178 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1179 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1180 qh->ping = FROM_DW3_PING(ptd.dw3);
1181 break;
db11e47d 1182
71a9f9d2
AB		 1183 case PTD_STATE_URB_RETIRE:
1184 qtd->status = QTD_RETIRE;
74ad6029
AB		 1185 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
1186 (qtd->urb->status != -EPIPE) &&
1187 (qtd->urb->status != -EREMOTEIO)) {
1188 qh->tt_buffer_dirty = 1;
1189 if (usb_hub_clear_tt_buffer(qtd->urb))
1190 /* Clear failed; let's hope things work
1191 anyway */
1192 qh->tt_buffer_dirty = 0;
1193 }
71a9f9d2
AB		 1194 qtd = NULL;
1195 qh->toggle = 0;
1196 qh->ping = 0;
1197 break;
db11e47d 1198
71a9f9d2
AB		 1199 default:
1200 WARN_ON(1);
1201 continue;
1202 }
db11e47d 1203
71a9f9d2
AB		 1204 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1205 if (slots == priv->int_slots) {
1206 if (state == PTD_STATE_QTD_RELOAD)
1207 dev_err(hcd->self.controller,
1208 "%s: PTD_STATE_QTD_RELOAD on "
1209 "interrupt packet\n", __func__);
1210 if (state != PTD_STATE_QTD_RELOAD)
1211 create_ptd_int(qh, qtd, &ptd);
1212 } else {
1213 if (state != PTD_STATE_QTD_RELOAD)
1214 create_ptd_atl(qh, qtd, &ptd);
1215 }
db11e47d 1216
71a9f9d2
AB		 1217 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1218 qh, &ptd);
1219 }
1220 }
db11e47d 1221
71a9f9d2
AB		 1222 if (modified)
1223 schedule_ptds(hcd);
6d50c60e 1224}
db11e47d 1225
6d50c60e
AB		 1226static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1227{
1228 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1229 u32 imask;
1230 irqreturn_t irqret = IRQ_NONE;
db11e47d 1231
6d50c60e
AB		 1232 spin_lock(&priv->lock);
1233
1234 if (!(hcd->state & HC_STATE_RUNNING))
1235 goto leave;
1236
1237 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1238 if (unlikely(!imask))
1239 goto leave;
1240 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1241
1242 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1243 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1244
1245 handle_done_ptds(hcd);
db11e47d 1246
71a9f9d2
AB		 1247 irqret = IRQ_HANDLED;
1248leave:
1249 spin_unlock(&priv->lock);
db11e47d 1250
71a9f9d2 1251 return irqret;
db11e47d
SS		 1252}
1253
6d50c60e
AB		 1254/*
1255 * Workaround for problem described in chip errata 2:
1256 *
1257 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
1258 * One solution suggested in the errata is to use SOF interrupts _instead_of_
1259 * ATL done interrupts (the "instead of" might be important since it seems
1260 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
1261 * to set the PTD's done bit in addition to not generating an interrupt!).
1262 *
1263 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
1264 * done bit is not being set. This is bad - it blocks the endpoint until reboot.
1265 *
1266 * If we use SOF interrupts only, we get latency between ptd completion and the
1267 * actual handling. This is very noticeable in testusb runs which takes several
1268 * minutes longer without ATL interrupts.
1269 *
1270 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
1271 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
1272 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
1273 * completed and its done map bit is set.
1274 *
1275 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
1276 * not to cause too much lag when this HW bug occurs, while still hopefully
1277 * ensuring that the check does not falsely trigger.
1278 */
6477acc0 1279#define SLOT_TIMEOUT 300
6d50c60e
AB		 1280#define SLOT_CHECK_PERIOD 200
1281static struct timer_list errata2_timer;
1282
de9c6307 1283static void errata2_function(unsigned long data)
6d50c60e
AB		 1284{
1285 struct usb_hcd *hcd = (struct usb_hcd *) data;
1286 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1287 int slot;
1288 struct ptd ptd;
1289 unsigned long spinflags;
1290
1291 spin_lock_irqsave(&priv->lock, spinflags);
1292
1293 for (slot = 0; slot < 32; slot++)
6477acc0
AB		 1294 if (priv->atl_slots[slot].qh && time_after(jiffies,
1295 priv->atl_slots[slot].timestamp +
1296 SLOT_TIMEOUT * HZ / 1000)) {
6d50c60e
AB		 1297 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1298 if (!FROM_DW0_VALID(ptd.dw0) &&
1299 !FROM_DW3_ACTIVE(ptd.dw3))
1300 priv->atl_done_map |= 1 << slot;
1301 }
1302
6477acc0
AB		 1303 if (priv->atl_done_map)
1304 handle_done_ptds(hcd);
6d50c60e
AB		 1305
1306 spin_unlock_irqrestore(&priv->lock, spinflags);
1307
1308 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1309 add_timer(&errata2_timer);
1310}
1311
0ba7905e
AB		 1312static int isp1760_run(struct usb_hcd *hcd)
1313{
1314 int retval;
1315 u32 temp;
1316 u32 command;
1317 u32 chipid;
1318
1319 hcd->uses_new_polling = 1;
1320
1321 hcd->state = HC_STATE_RUNNING;
1322
1323 /* Set PTD interrupt AND & OR maps */
1324 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1325 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1326 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1327 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1328 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1329 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1330 /* step 23 passed */
1331
1332 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1333 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1334
1335 command = reg_read32(hcd->regs, HC_USBCMD);
1336 command &= ~(CMD_LRESET|CMD_RESET);
1337 command |= CMD_RUN;
1338 reg_write32(hcd->regs, HC_USBCMD, command);
1339
1340 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1341 if (retval)
1342 return retval;
1343
1344 /*
1345 * XXX
1346 * Spec says to write FLAG_CF as last config action, priv code grabs
1347 * the semaphore while doing so.
1348 */
1349 down_write(&ehci_cf_port_reset_rwsem);
1350 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1351
1352 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1353 up_write(&ehci_cf_port_reset_rwsem);
1354 if (retval)
1355 return retval;
1356
6d50c60e
AB		 1357 init_timer(&errata2_timer);
1358 errata2_timer.function = errata2_function;
1359 errata2_timer.data = (unsigned long) hcd;
1360 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
1361 add_timer(&errata2_timer);
1362
0ba7905e
AB		 1363 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1364 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1365 chipid & 0xffff, chipid >> 16);
1366
1367 /* PTD Register Init Part 2, Step 28 */
1368
1369 /* Setup registers controlling PTD checking */
1370 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1371 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1372 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1373 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1374 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1375 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1376 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1377 ATL_BUF_FILL | INT_BUF_FILL);
1378
1379 /* GRR this is run-once init(), being done every time the HC starts.
1380 * So long as they're part of class devices, we can't do it init()
1381 * since the class device isn't created that early.
1382 */
1383 return 0;
1384}
1385
34537731 1386static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
db11e47d 1387{
34537731 1388 qtd->data_buffer = databuffer;
db11e47d 1389
34537731
AB		 1390 if (len > MAX_PAYLOAD_SIZE)
1391 len = MAX_PAYLOAD_SIZE;
1392 qtd->length = len;
db11e47d 1393
34537731 1394 return qtd->length;
db11e47d
SS		 1395}
1396
34537731 1397static void qtd_list_free(struct list_head *qtd_list)
db11e47d 1398{
34537731 1399 struct isp1760_qtd *qtd, *qtd_next;
db11e47d 1400
34537731 1401 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
db11e47d 1402 list_del(&qtd->qtd_list);
34537731 1403 qtd_free(qtd);
db11e47d
SS		 1404 }
1405}
1406
db11e47d 1407/*
34537731
AB		 1408 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1409 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
db11e47d 1410 */
6bda21bc 1411#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
34537731 1412static void packetize_urb(struct usb_hcd *hcd,
db11e47d
SS		 1413 struct urb *urb, struct list_head *head, gfp_t flags)
1414{
fd436aee 1415 struct isp1760_qtd *qtd;
db11e47d 1416 void *buf;
34537731
AB		 1417 int len, maxpacketsize;
1418 u8 packet_type;
db11e47d
SS		 1419
1420 /*
1421 * URBs map to sequences of QTDs: one logical transaction
1422 */
db11e47d 1423
34537731
AB		 1424 if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1425 /* XXX This looks like usb storage / SCSI bug */
1426 dev_err(hcd->self.controller,
1427 "buf is null, dma is %08lx len is %d\n",
1428 (long unsigned)urb->transfer_dma,
1429 urb->transfer_buffer_length);
1430 WARN_ON(1);
1431 }
db11e47d 1432
34537731
AB		 1433 if (usb_pipein(urb->pipe))
1434 packet_type = IN_PID;
1435 else
1436 packet_type = OUT_PID;
db11e47d 1437
db11e47d 1438 if (usb_pipecontrol(urb->pipe)) {
34537731 1439 qtd = qtd_alloc(flags, urb, SETUP_PID);
db11e47d
SS		 1440 if (!qtd)
1441 goto cleanup;
34537731 1442 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
db11e47d
SS		 1443 list_add_tail(&qtd->qtd_list, head);
1444
1445 /* for zero length DATA stages, STATUS is always IN */
34537731
AB		 1446 if (urb->transfer_buffer_length == 0)
1447 packet_type = IN_PID;
db11e47d
SS		 1448 }
1449
34537731
AB		 1450 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1451 usb_pipeout(urb->pipe)));
db11e47d
SS		 1452
1453 /*
1454 * buffer gets wrapped in one or more qtds;
1455 * last one may be "short" (including zero len)
1456 * and may serve as a control status ack
1457 */
34537731
AB		 1458 buf = urb->transfer_buffer;
1459 len = urb->transfer_buffer_length;
1460
db11e47d
SS		 1461 for (;;) {
1462 int this_qtd_len;
1463
34537731
AB		 1464 qtd = qtd_alloc(flags, urb, packet_type);
1465 if (!qtd)
1466 goto cleanup;
1467 this_qtd_len = qtd_fill(qtd, buf, len);
1468 list_add_tail(&qtd->qtd_list, head);
db11e47d 1469
db11e47d
SS		 1470 len -= this_qtd_len;
1471 buf += this_qtd_len;
1472
db11e47d
SS		 1473 if (len <= 0)
1474 break;
db11e47d
SS		 1475 }
1476
1477 /*
1478 * control requests may need a terminating data "status" ack;
1479 * bulk ones may need a terminating short packet (zero length).
1480 */
1481 if (urb->transfer_buffer_length != 0) {
1482 int one_more = 0;
1483
1484 if (usb_pipecontrol(urb->pipe)) {
1485 one_more = 1;
34537731
AB		 1486 if (packet_type == IN_PID)
1487 packet_type = OUT_PID;
1488 else
1489 packet_type = IN_PID;
db11e47d
SS		 1490 } else if (usb_pipebulk(urb->pipe)
1491 && (urb->transfer_flags & URB_ZERO_PACKET)
34537731
AB		 1492 && !(urb->transfer_buffer_length %
1493 maxpacketsize)) {
db11e47d
SS		 1494 one_more = 1;
1495 }
1496 if (one_more) {
34537731 1497 qtd = qtd_alloc(flags, urb, packet_type);
db11e47d
SS		 1498 if (!qtd)
1499 goto cleanup;
db11e47d
SS		 1500
1501 /* never any data in such packets */
34537731
AB		 1502 qtd_fill(qtd, NULL, 0);
1503 list_add_tail(&qtd->qtd_list, head);
db11e47d
SS		 1504 }
1505 }
1506
34537731 1507 return;
db11e47d
SS		 1508
1509cleanup:
34537731
AB		 1510 qtd_list_free(head);
1511}
1512
db11e47d
SS		 1513static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1514 gfp_t mem_flags)
1515{
71a9f9d2
AB		 1516 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1517 struct list_head *ep_queue;
1518 struct isp1760_qh *qh, *qhit;
1519 unsigned long spinflags;
1520 LIST_HEAD(new_qtds);
1521 int retval;
1522 int qh_in_queue;
db11e47d
SS		 1523
1524 switch (usb_pipetype(urb->pipe)) {
1525 case PIPE_CONTROL:
e08f6a27 1526 ep_queue = &priv->qh_list[QH_CONTROL];
71a9f9d2 1527 break;
db11e47d 1528 case PIPE_BULK:
e08f6a27 1529 ep_queue = &priv->qh_list[QH_BULK];
db11e47d 1530 break;
db11e47d 1531 case PIPE_INTERRUPT:
71a9f9d2
AB		 1532 if (urb->interval < 0)
1533 return -EINVAL;
1534 /* FIXME: Check bandwidth */
e08f6a27 1535 ep_queue = &priv->qh_list[QH_INTERRUPT];
db11e47d 1536 break;
db11e47d 1537 case PIPE_ISOCHRONOUS:
71a9f9d2
AB		 1538 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1539 "not yet supported\n",
1540 __func__);
1541 return -EPIPE;
db11e47d 1542 default:
71a9f9d2
AB		 1543 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1544 __func__);
db11e47d
SS		 1545 return -EPIPE;
1546 }
1547
71a9f9d2
AB		 1548 if (usb_pipein(urb->pipe))
1549 urb->actual_length = 0;
db11e47d 1550
71a9f9d2
AB		 1551 packetize_urb(hcd, urb, &new_qtds, mem_flags);
1552 if (list_empty(&new_qtds))
1553 return -ENOMEM;
db11e47d 1554
71a9f9d2
AB		 1555 retval = 0;
1556 spin_lock_irqsave(&priv->lock, spinflags);
db11e47d 1557
71a9f9d2
AB		 1558 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1559 retval = -ESHUTDOWN;
8788fa03 1560 qtd_list_free(&new_qtds);
71a9f9d2 1561 goto out;
db11e47d 1562 }
71a9f9d2 1563 retval = usb_hcd_link_urb_to_ep(hcd, urb);
8788fa03
MG		 1564 if (retval) {
1565 qtd_list_free(&new_qtds);
71a9f9d2 1566 goto out;
8788fa03 1567 }
db11e47d 1568
71a9f9d2
AB		 1569 qh = urb->ep->hcpriv;
1570 if (qh) {
1571 qh_in_queue = 0;
1572 list_for_each_entry(qhit, ep_queue, qh_list) {
1573 if (qhit == qh) {
1574 qh_in_queue = 1;
0afb20e0 1575 break;
71a9f9d2
AB		 1576 }
1577 }
1578 if (!qh_in_queue)
1579 list_add_tail(&qh->qh_list, ep_queue);
1580 } else {
1581 qh = qh_alloc(GFP_ATOMIC);
1582 if (!qh) {
1583 retval = -ENOMEM;
38679b72 1584 usb_hcd_unlink_urb_from_ep(hcd, urb);
8788fa03 1585 qtd_list_free(&new_qtds);
71a9f9d2 1586 goto out;
db11e47d 1587 }
71a9f9d2
AB		 1588 list_add_tail(&qh->qh_list, ep_queue);
1589 urb->ep->hcpriv = qh;
db11e47d
SS		 1590 }
1591
71a9f9d2
AB		 1592 list_splice_tail(&new_qtds, &qh->qtd_list);
1593 schedule_ptds(hcd);
1594
1595out:
1596 spin_unlock_irqrestore(&priv->lock, spinflags);
1597 return retval;
db11e47d
SS		 1598}
1599
d05b6ec0
AB		 1600static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1601 struct isp1760_qh *qh)
1602{
1603 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1604 int skip_map;
1605
1606 WARN_ON(qh->slot == -1);
1607
1608 /* We need to forcefully reclaim the slot since some transfers never
1609 return, e.g. interrupt transfers and NAKed bulk transfers. */
8b1ab60c 1610 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
d05b6ec0
AB		 1611 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1612 skip_map |= (1 << qh->slot);
1613 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1614 priv->atl_slots[qh->slot].qh = NULL;
1615 priv->atl_slots[qh->slot].qtd = NULL;
1616 } else {
1617 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1618 skip_map |= (1 << qh->slot);
1619 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1620 priv->int_slots[qh->slot].qh = NULL;
1621 priv->int_slots[qh->slot].qtd = NULL;
1622 }
1623
1624 qh->slot = -1;
d05b6ec0
AB		 1625}
1626
74ad6029
AB		 1627/*
1628 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
1629 * any active transfer belonging to the urb in the process.
1630 */
1631static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
1632 struct isp1760_qtd *qtd)
1633{
1634 struct urb *urb;
1635 int urb_was_running;
1636
1637 urb = qtd->urb;
1638 urb_was_running = 0;
1639 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
1640 if (qtd->urb != urb)
1641 break;
1642
1643 if (qtd->status >= QTD_XFER_STARTED)
1644 urb_was_running = 1;
1645 if (last_qtd_of_urb(qtd, qh) &&
1646 (qtd->status >= QTD_XFER_COMPLETE))
1647 urb_was_running = 0;
1648
1649 if (qtd->status == QTD_XFER_STARTED)
1650 kill_transfer(hcd, urb, qh);
1651 qtd->status = QTD_RETIRE;
1652 }
1653
1654 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
1655 qh->tt_buffer_dirty = 1;
1656 if (usb_hub_clear_tt_buffer(urb))
1657 /* Clear failed; let's hope things work anyway */
1658 qh->tt_buffer_dirty = 0;
1659 }
1660}
1661
71a9f9d2
AB		 1662static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1663 int status)
db11e47d 1664{
6bda21bc 1665 struct isp1760_hcd *priv = hcd_to_priv(hcd);
d05b6ec0 1666 unsigned long spinflags;
71a9f9d2
AB		 1667 struct isp1760_qh *qh;
1668 struct isp1760_qtd *qtd;
71a9f9d2 1669 int retval = 0;
db11e47d 1670
71a9f9d2 1671 spin_lock_irqsave(&priv->lock, spinflags);
17d3e145
AB		 1672 retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1673 if (retval)
1674 goto out;
db11e47d 1675
71a9f9d2
AB		 1676 qh = urb->ep->hcpriv;
1677 if (!qh) {
1678 retval = -EINVAL;
1679 goto out;
1680 }
db11e47d 1681
d05b6ec0
AB		 1682 list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1683 if (qtd->urb == urb) {
74ad6029 1684 dequeue_urb_from_qtd(hcd, qh, qtd);
8cb22680 1685 list_move(&qtd->qtd_list, &qh->qtd_list);
74ad6029 1686 break;
d05b6ec0 1687 }
db11e47d 1688
71a9f9d2
AB		 1689 urb->status = status;
1690 schedule_ptds(hcd);
db11e47d 1691
71a9f9d2
AB		 1692out:
1693 spin_unlock_irqrestore(&priv->lock, spinflags);
71a9f9d2 1694 return retval;
db11e47d
SS		 1695}
1696
079cdb09
AB		 1697static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1698 struct usb_host_endpoint *ep)
1699{
1700 struct isp1760_hcd *priv = hcd_to_priv(hcd);
d05b6ec0 1701 unsigned long spinflags;
c64391f2
AB		 1702 struct isp1760_qh *qh, *qh_iter;
1703 int i;
079cdb09
AB		 1704
1705 spin_lock_irqsave(&priv->lock, spinflags);
d05b6ec0 1706
079cdb09
AB		 1707 qh = ep->hcpriv;
1708 if (!qh)
1709 goto out;
1710
c64391f2 1711 WARN_ON(!list_empty(&qh->qtd_list));
d05b6ec0 1712
c64391f2
AB		 1713 for (i = 0; i < QH_END; i++)
1714 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
1715 if (qh_iter == qh) {
1716 list_del(&qh_iter->qh_list);
1717 i = QH_END;
1718 break;
1719 }
1720 qh_free(qh);
079cdb09 1721 ep->hcpriv = NULL;
079cdb09 1722
d05b6ec0
AB		 1723 schedule_ptds(hcd);
1724
079cdb09
AB		 1725out:
1726 spin_unlock_irqrestore(&priv->lock, spinflags);
1727}
1728
db11e47d
SS		 1729static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1730{
1731 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1732 u32 temp, status = 0;
1733 u32 mask;
1734 int retval = 1;
1735 unsigned long flags;
1736
464ed18e 1737 /* if !PM, root hub timers won't get shut down ... */
db11e47d
SS		 1738 if (!HC_IS_RUNNING(hcd->state))
1739 return 0;
1740
1741 /* init status to no-changes */
1742 buf[0] = 0;
1743 mask = PORT_CSC;
1744
1745 spin_lock_irqsave(&priv->lock, flags);
bedc0c31 1746 temp = reg_read32(hcd->regs, HC_PORTSC1);
db11e47d
SS		 1747
1748 if (temp & PORT_OWNER) {
1749 if (temp & PORT_CSC) {
1750 temp &= ~PORT_CSC;
bedc0c31 1751 reg_write32(hcd->regs, HC_PORTSC1, temp);
db11e47d
SS		 1752 goto done;
1753 }
1754 }
1755
1756 /*
1757 * Return status information even for ports with OWNER set.
37ebb549 1758 * Otherwise hub_wq wouldn't see the disconnect event when a
db11e47d
SS		 1759 * high-speed device is switched over to the companion
1760 * controller by the user.
1761 */
1762
1763 if ((temp & mask) != 0
1764 || ((temp & PORT_RESUME) != 0
1765 && time_after_eq(jiffies,
1766 priv->reset_done))) {
1767 buf [0] |= 1 << (0 + 1);
1768 status = STS_PCD;
1769 }
1770 /* FIXME autosuspend idle root hubs */
1771done:
1772 spin_unlock_irqrestore(&priv->lock, flags);
1773 return status ? retval : 0;
1774}
1775
1776static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1777 struct usb_hub_descriptor *desc)
1778{
1779 int ports = HCS_N_PORTS(priv->hcs_params);
1780 u16 temp;
1781
1782 desc->bDescriptorType = 0x29;
1783 /* priv 1.0, 2.3.9 says 20ms max */
1784 desc->bPwrOn2PwrGood = 10;
1785 desc->bHubContrCurrent = 0;
1786
1787 desc->bNbrPorts = ports;
1788 temp = 1 + (ports / 8);
1789 desc->bDescLength = 7 + 2 * temp;
1790
da13051c 1791 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
dbe79bbe
JY		 1792 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1793 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
db11e47d
SS		 1794
1795 /* per-port overcurrent reporting */
1796 temp = 0x0008;
1797 if (HCS_PPC(priv->hcs_params))
1798 /* per-port power control */
1799 temp |= 0x0001;
1800 else
1801 /* no power switching */
1802 temp |= 0x0002;
1803 desc->wHubCharacteristics = cpu_to_le16(temp);
1804}
1805
1806#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1807
bedc0c31
AB		 1808static int check_reset_complete(struct usb_hcd *hcd, int index,
1809 int port_status)
db11e47d
SS		 1810{
1811 if (!(port_status & PORT_CONNECT))
1812 return port_status;
1813
1814 /* if reset finished and it's still not enabled -- handoff */
1815 if (!(port_status & PORT_PE)) {
1816
71a9f9d2 1817 dev_info(hcd->self.controller,
6bda21bc
AB		 1818 "port %d full speed --> companion\n",
1819 index + 1);
db11e47d
SS		 1820
1821 port_status |= PORT_OWNER;
1822 port_status &= ~PORT_RWC_BITS;
bedc0c31 1823 reg_write32(hcd->regs, HC_PORTSC1, port_status);
db11e47d
SS		 1824
1825 } else
71a9f9d2 1826 dev_info(hcd->self.controller, "port %d high speed\n",
6bda21bc 1827 index + 1);
db11e47d
SS		 1828
1829 return port_status;
1830}
1831
1832static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1833 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1834{
1835 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1836 int ports = HCS_N_PORTS(priv->hcs_params);
db11e47d
SS		 1837 u32 temp, status;
1838 unsigned long flags;
1839 int retval = 0;
1840 unsigned selector;
1841
1842 /*
1843 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1844 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1845 * (track current state ourselves) ... blink for diagnostics,
1846 * power, "this is the one", etc. EHCI spec supports this.
1847 */
1848
1849 spin_lock_irqsave(&priv->lock, flags);
1850 switch (typeReq) {
1851 case ClearHubFeature:
1852 switch (wValue) {
1853 case C_HUB_LOCAL_POWER:
1854 case C_HUB_OVER_CURRENT:
1855 /* no hub-wide feature/status flags */
1856 break;
1857 default:
1858 goto error;
1859 }
1860 break;
1861 case ClearPortFeature:
1862 if (!wIndex || wIndex > ports)
1863 goto error;
1864 wIndex--;
bedc0c31 1865 temp = reg_read32(hcd->regs, HC_PORTSC1);
db11e47d
SS		 1866
1867 /*
1868 * Even if OWNER is set, so the port is owned by the
37ebb549 1869 * companion controller, hub_wq needs to be able to clear
db11e47d 1870 * the port-change status bits (especially
749da5f8 1871 * USB_PORT_STAT_C_CONNECTION).
db11e47d
SS		 1872 */
1873
1874 switch (wValue) {
1875 case USB_PORT_FEAT_ENABLE:
bedc0c31 1876 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
db11e47d
SS		 1877 break;
1878 case USB_PORT_FEAT_C_ENABLE:
1879 /* XXX error? */
1880 break;
1881 case USB_PORT_FEAT_SUSPEND:
1882 if (temp & PORT_RESET)
1883 goto error;
1884
1885 if (temp & PORT_SUSPEND) {
1886 if ((temp & PORT_PE) == 0)
1887 goto error;
1888 /* resume signaling for 20 msec */
1889 temp &= ~(PORT_RWC_BITS);
bedc0c31
AB		 1890 reg_write32(hcd->regs, HC_PORTSC1,
1891 temp | PORT_RESUME);
db11e47d
SS		 1892 priv->reset_done = jiffies +
1893 msecs_to_jiffies(20);
1894 }
1895 break;
1896 case USB_PORT_FEAT_C_SUSPEND:
1897 /* we auto-clear this feature */
1898 break;
1899 case USB_PORT_FEAT_POWER:
1900 if (HCS_PPC(priv->hcs_params))
bedc0c31
AB		 1901 reg_write32(hcd->regs, HC_PORTSC1,
1902 temp & ~PORT_POWER);
db11e47d
SS		 1903 break;
1904 case USB_PORT_FEAT_C_CONNECTION:
bedc0c31 1905 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
db11e47d
SS		 1906 break;
1907 case USB_PORT_FEAT_C_OVER_CURRENT:
1908 /* XXX error ?*/
1909 break;
1910 case USB_PORT_FEAT_C_RESET:
1911 /* GetPortStatus clears reset */
1912 break;
1913 default:
1914 goto error;
1915 }
bedc0c31 1916 reg_read32(hcd->regs, HC_USBCMD);
db11e47d
SS		 1917 break;
1918 case GetHubDescriptor:
1919 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1920 buf);
1921 break;
1922 case GetHubStatus:
1923 /* no hub-wide feature/status flags */
1924 memset(buf, 0, 4);
1925 break;
1926 case GetPortStatus:
1927 if (!wIndex || wIndex > ports)
1928 goto error;
1929 wIndex--;
1930 status = 0;
bedc0c31 1931 temp = reg_read32(hcd->regs, HC_PORTSC1);
db11e47d
SS		 1932
1933 /* wPortChange bits */
1934 if (temp & PORT_CSC)
749da5f8 1935 status |= USB_PORT_STAT_C_CONNECTION << 16;
db11e47d
SS		 1936
1937
1938 /* whoever resumes must GetPortStatus to complete it!! */
1939 if (temp & PORT_RESUME) {
6bda21bc 1940 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
db11e47d
SS		 1941
1942 /* Remote Wakeup received? */
1943 if (!priv->reset_done) {
1944 /* resume signaling for 20 msec */
1945 priv->reset_done = jiffies
1946 + msecs_to_jiffies(20);
1947 /* check the port again */
6bda21bc 1948 mod_timer(&hcd->rh_timer, priv->reset_done);
db11e47d
SS		 1949 }
1950
1951 /* resume completed? */
1952 else if (time_after_eq(jiffies,
1953 priv->reset_done)) {
749da5f8 1954 status |= USB_PORT_STAT_C_SUSPEND << 16;
db11e47d
SS		 1955 priv->reset_done = 0;
1956
1957 /* stop resume signaling */
bedc0c31
AB		 1958 temp = reg_read32(hcd->regs, HC_PORTSC1);
1959 reg_write32(hcd->regs, HC_PORTSC1,
1960 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1961 retval = handshake(hcd, HC_PORTSC1,
db11e47d
SS		 1962 PORT_RESUME, 0, 2000 /* 2msec */);
1963 if (retval != 0) {
6bda21bc 1964 dev_err(hcd->self.controller,
db11e47d
SS		 1965 "port %d resume error %d\n",
1966 wIndex + 1, retval);
1967 goto error;
1968 }
1969 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1970 }
1971 }
1972
1973 /* whoever resets must GetPortStatus to complete it!! */
1974 if ((temp & PORT_RESET)
1975 && time_after_eq(jiffies,
1976 priv->reset_done)) {
749da5f8 1977 status |= USB_PORT_STAT_C_RESET << 16;
db11e47d
SS		 1978 priv->reset_done = 0;
1979
1980 /* force reset to complete */
bedc0c31 1981 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
db11e47d
SS		 1982 /* REVISIT: some hardware needs 550+ usec to clear
1983 * this bit; seems too long to spin routinely...
1984 */
bedc0c31 1985 retval = handshake(hcd, HC_PORTSC1,
db11e47d
SS		 1986 PORT_RESET, 0, 750);
1987 if (retval != 0) {
6bda21bc 1988 dev_err(hcd->self.controller, "port %d reset error %d\n",
db11e47d
SS		 1989 wIndex + 1, retval);
1990 goto error;
1991 }
1992
1993 /* see what we found out */
bedc0c31
AB		 1994 temp = check_reset_complete(hcd, wIndex,
1995 reg_read32(hcd->regs, HC_PORTSC1));
db11e47d
SS		 1996 }
1997 /*
37ebb549 1998 * Even if OWNER is set, there's no harm letting hub_wq
db11e47d
SS		 1999 * see the wPortStatus values (they should all be 0 except
2000 * for PORT_POWER anyway).
2001 */
2002
2003 if (temp & PORT_OWNER)
6bda21bc 2004 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
db11e47d
SS		 2005
2006 if (temp & PORT_CONNECT) {
749da5f8 2007 status |= USB_PORT_STAT_CONNECTION;
db11e47d 2008 /* status may be from integrated TT */
6bda21bc 2009 status |= USB_PORT_STAT_HIGH_SPEED;
db11e47d
SS		 2010 }
2011 if (temp & PORT_PE)
749da5f8 2012 status |= USB_PORT_STAT_ENABLE;
db11e47d 2013 if (temp & (PORT_SUSPEND|PORT_RESUME))
749da5f8 2014 status |= USB_PORT_STAT_SUSPEND;
db11e47d 2015 if (temp & PORT_RESET)
749da5f8 2016 status |= USB_PORT_STAT_RESET;
db11e47d 2017 if (temp & PORT_POWER)
749da5f8 2018 status |= USB_PORT_STAT_POWER;
db11e47d
SS		 2019
2020 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2021 break;
2022 case SetHubFeature:
2023 switch (wValue) {
2024 case C_HUB_LOCAL_POWER:
2025 case C_HUB_OVER_CURRENT:
2026 /* no hub-wide feature/status flags */
2027 break;
2028 default:
2029 goto error;
2030 }
2031 break;
2032 case SetPortFeature:
2033 selector = wIndex >> 8;
2034 wIndex &= 0xff;
2035 if (!wIndex || wIndex > ports)
2036 goto error;
2037 wIndex--;
bedc0c31 2038 temp = reg_read32(hcd->regs, HC_PORTSC1);
db11e47d
SS		 2039 if (temp & PORT_OWNER)
2040 break;
2041
2042/* temp &= ~PORT_RWC_BITS; */
2043 switch (wValue) {
2044 case USB_PORT_FEAT_ENABLE:
bedc0c31 2045 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
db11e47d
SS		 2046 break;
2047
2048 case USB_PORT_FEAT_SUSPEND:
2049 if ((temp & PORT_PE) == 0
2050 || (temp & PORT_RESET) != 0)
2051 goto error;
2052
bedc0c31 2053 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
db11e47d
SS		 2054 break;
2055 case USB_PORT_FEAT_POWER:
2056 if (HCS_PPC(priv->hcs_params))
bedc0c31
AB		 2057 reg_write32(hcd->regs, HC_PORTSC1,
2058 temp | PORT_POWER);
db11e47d
SS		 2059 break;
2060 case USB_PORT_FEAT_RESET:
2061 if (temp & PORT_RESUME)
2062 goto error;
2063 /* line status bits may report this as low speed,
2064 * which can be fine if this root hub has a
2065 * transaction translator built in.
2066 */
2067 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2068 && PORT_USB11(temp)) {
2069 temp |= PORT_OWNER;
2070 } else {
2071 temp |= PORT_RESET;
2072 temp &= ~PORT_PE;
2073
2074 /*
2075 * caller must wait, then call GetPortStatus
2076 * usb 2.0 spec says 50 ms resets on root
2077 */
2078 priv->reset_done = jiffies +
2079 msecs_to_jiffies(50);
2080 }
bedc0c31 2081 reg_write32(hcd->regs, HC_PORTSC1, temp);
db11e47d
SS		 2082 break;
2083 default:
2084 goto error;
2085 }
bedc0c31 2086 reg_read32(hcd->regs, HC_USBCMD);
db11e47d
SS		 2087 break;
2088
2089 default:
2090error:
2091 /* "stall" on error */
2092 retval = -EPIPE;
2093 }
2094 spin_unlock_irqrestore(&priv->lock, flags);
2095 return retval;
2096}
2097
db11e47d
SS		 2098static int isp1760_get_frame(struct usb_hcd *hcd)
2099{
2100 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2101 u32 fr;
2102
bedc0c31 2103 fr = reg_read32(hcd->regs, HC_FRINDEX);
db11e47d
SS		 2104 return (fr >> 3) % priv->periodic_size;
2105}
2106
2107static void isp1760_stop(struct usb_hcd *hcd)
2108{
2109 struct isp1760_hcd *priv = hcd_to_priv(hcd);
3faefc88 2110 u32 temp;
db11e47d 2111
6d50c60e
AB		 2112 del_timer(&errata2_timer);
2113
db11e47d
SS		 2114 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2115 NULL, 0);
2116 mdelay(20);
2117
2118 spin_lock_irq(&priv->lock);
6bda21bc 2119 ehci_reset(hcd);
db11e47d 2120 /* Disable IRQ */
bedc0c31
AB		 2121 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2122 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
db11e47d
SS		 2123 spin_unlock_irq(&priv->lock);
2124
bedc0c31 2125 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
db11e47d
SS		 2126}
2127
2128static void isp1760_shutdown(struct usb_hcd *hcd)
2129{
3faefc88 2130 u32 command, temp;
db11e47d
SS		 2131
2132 isp1760_stop(hcd);
bedc0c31
AB		 2133 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2134 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
db11e47d 2135
bedc0c31 2136 command = reg_read32(hcd->regs, HC_USBCMD);
db11e47d 2137 command &= ~CMD_RUN;
bedc0c31 2138 reg_write32(hcd->regs, HC_USBCMD, command);
db11e47d
SS		 2139}
2140
74ad6029
AB		 2141static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd,
2142 struct usb_host_endpoint *ep)
2143{
2144 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2145 struct isp1760_qh *qh = ep->hcpriv;
2146 unsigned long spinflags;
2147
2148 if (!qh)
2149 return;
2150
2151 spin_lock_irqsave(&priv->lock, spinflags);
2152 qh->tt_buffer_dirty = 0;
2153 schedule_ptds(hcd);
2154 spin_unlock_irqrestore(&priv->lock, spinflags);
2155}
2156
2157
db11e47d
SS		 2158static const struct hc_driver isp1760_hc_driver = {
2159 .description = "isp1760-hcd",
2160 .product_desc = "NXP ISP1760 USB Host Controller",
2161 .hcd_priv_size = sizeof(struct isp1760_hcd),
2162 .irq = isp1760_irq,
2163 .flags = HCD_MEMORY | HCD_USB2,
2164 .reset = isp1760_hc_setup,
2165 .start = isp1760_run,
2166 .stop = isp1760_stop,
2167 .shutdown = isp1760_shutdown,
2168 .urb_enqueue = isp1760_urb_enqueue,
2169 .urb_dequeue = isp1760_urb_dequeue,
2170 .endpoint_disable = isp1760_endpoint_disable,
2171 .get_frame_number = isp1760_get_frame,
2172 .hub_status_data = isp1760_hub_status_data,
2173 .hub_control = isp1760_hub_control,
74ad6029 2174 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete,
db11e47d
SS		 2175};
2176
2177int __init init_kmem_once(void)
2178{
94011ec2 2179 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem",
71a9f9d2
AB		 2180 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2181 SLAB_MEM_SPREAD, NULL);
2182
2183 if (!urb_listitem_cachep)
2184 return -ENOMEM;
2185
db11e47d
SS		 2186 qtd_cachep = kmem_cache_create("isp1760_qtd",
2187 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2188 SLAB_MEM_SPREAD, NULL);
2189
2190 if (!qtd_cachep)
2191 return -ENOMEM;
2192
2193 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2194 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2195
2196 if (!qh_cachep) {
2197 kmem_cache_destroy(qtd_cachep);
2198 return -ENOMEM;
2199 }
2200
2201 return 0;
2202}
2203
2204void deinit_kmem_cache(void)
2205{
2206 kmem_cache_destroy(qtd_cachep);
2207 kmem_cache_destroy(qh_cachep);
71a9f9d2 2208 kmem_cache_destroy(urb_listitem_cachep);
db11e47d
SS		 2209}
2210
f9031f2c
CM		 2211struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2212 int irq, unsigned long irqflags,
2213 struct device *dev, const char *busname,
2214 unsigned int devflags)
db11e47d
SS		 2215{
2216 struct usb_hcd *hcd;
2217 struct isp1760_hcd *priv;
2218 int ret;
2219
2220 if (usb_disabled())
2221 return ERR_PTR(-ENODEV);
2222
2223 /* prevent usb-core allocating DMA pages */
2224 dev->dma_mask = NULL;
2225
0031a06e 2226 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
db11e47d
SS		 2227 if (!hcd)
2228 return ERR_PTR(-ENOMEM);
2229
2230 priv = hcd_to_priv(hcd);
3faefc88 2231 priv->devflags = devflags;
7eb42c6e
LP		 2232
2233 priv->rst_gpio = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
2234 if (IS_ERR(priv->rst_gpio)) {
2235 ret = PTR_ERR(priv->rst_gpio);
2236 goto err_put;
2237 }
2238
db11e47d
SS		 2239 init_memory(priv);
2240 hcd->regs = ioremap(res_start, res_len);
2241 if (!hcd->regs) {
2242 ret = -EIO;
2243 goto err_put;
2244 }
2245
db11e47d
SS		 2246 hcd->irq = irq;
2247 hcd->rsrc_start = res_start;
2248 hcd->rsrc_len = res_len;
2249
e6942d63
NC		 2250 ret = usb_add_hcd(hcd, irq, irqflags);
2251 if (ret)
2252 goto err_unmap;
3c9740a1 2253 device_wakeup_enable(hcd->self.controller);
e6942d63 2254
db11e47d
SS		 2255 return hcd;
2256
2257err_unmap:
2258 iounmap(hcd->regs);
2259
2260err_put:
2261 usb_put_hcd(hcd);
2262
2263 return ERR_PTR(ret);
2264}
2265
2266MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2267MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2268MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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