Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 6 | * |
1da177e4 LT |
7 | * [ Initialisation is based on Linus' ] |
8 | * [ uhci code and gregs ohci fragments ] | |
9 | * [ (C) Copyright 1999 Linus Torvalds ] | |
10 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
11 | * |
12 | * | |
1da177e4 LT |
13 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
14 | * interfaces (though some non-x86 Intel chips use it). It supports | |
15 | * smarter hardware than UHCI. A download link for the spec available | |
16 | * through the http://www.usb.org website. | |
17 | * | |
1da177e4 LT |
18 | * This file is licenced under the GPL. |
19 | */ | |
dd9048af | 20 | |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/slab.h> | |
1da177e4 LT |
29 | #include <linux/errno.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/timer.h> | |
32 | #include <linux/list.h> | |
1da177e4 | 33 | #include <linux/usb.h> |
3a16f7b4 | 34 | #include <linux/usb/otg.h> |
27729aad | 35 | #include <linux/usb/hcd.h> |
dd9048af | 36 | #include <linux/dma-mapping.h> |
f4df0e33 | 37 | #include <linux/dmapool.h> |
d576bb9f | 38 | #include <linux/workqueue.h> |
684c19e0 | 39 | #include <linux/debugfs.h> |
1da177e4 LT |
40 | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/unaligned.h> | |
45 | #include <asm/byteorder.h> | |
46 | ||
47 | ||
1da177e4 LT |
48 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
49 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
50 | ||
51 | /*-------------------------------------------------------------------------*/ | |
52 | ||
8de98402 | 53 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
1da177e4 LT |
54 | |
55 | /* For initializing controller (mask in an HCFS mode too) */ | |
d413984a | 56 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 57 | #define OHCI_INTR_INIT \ |
d413984a DB |
58 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
59 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
60 | |
61 | #ifdef __hppa__ | |
62 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
63 | #define IR_DISABLE | |
64 | #endif | |
65 | ||
66 | #ifdef CONFIG_ARCH_OMAP | |
67 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
68 | #define IR_DISABLE | |
69 | #endif | |
70 | ||
71 | /*-------------------------------------------------------------------------*/ | |
72 | ||
73 | static const char hcd_name [] = "ohci_hcd"; | |
74 | ||
d413984a DB |
75 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
76 | ||
1da177e4 LT |
77 | #include "ohci.h" |
78 | ||
79 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | |
80 | static int ohci_init (struct ohci_hcd *ohci); | |
81 | static void ohci_stop (struct usb_hcd *hcd); | |
da6fb570 DB |
82 | |
83 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) | |
d576bb9f | 84 | static int ohci_restart (struct ohci_hcd *ohci); |
da6fb570 | 85 | #endif |
1da177e4 | 86 | |
ab1666c1 LY |
87 | #ifdef CONFIG_PCI |
88 | static void quirk_amd_pll(int state); | |
89 | static void amd_iso_dev_put(void); | |
a1f17a87 | 90 | static void sb800_prefetch(struct ohci_hcd *ohci, int on); |
ab1666c1 LY |
91 | #else |
92 | static inline void quirk_amd_pll(int state) | |
93 | { | |
94 | return; | |
95 | } | |
96 | static inline void amd_iso_dev_put(void) | |
97 | { | |
98 | return; | |
99 | } | |
a1f17a87 LY |
100 | static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) |
101 | { | |
102 | return; | |
103 | } | |
ab1666c1 LY |
104 | #endif |
105 | ||
106 | ||
1da177e4 LT |
107 | #include "ohci-hub.c" |
108 | #include "ohci-dbg.c" | |
109 | #include "ohci-mem.c" | |
110 | #include "ohci-q.c" | |
111 | ||
112 | ||
113 | /* | |
114 | * On architectures with edge-triggered interrupts we must never return | |
115 | * IRQ_NONE. | |
116 | */ | |
117 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
118 | #define IRQ_NOTMINE IRQ_HANDLED | |
119 | #else | |
120 | #define IRQ_NOTMINE IRQ_NONE | |
121 | #endif | |
122 | ||
123 | ||
124 | /* Some boards misreport power switching/overcurrent */ | |
125 | static int distrust_firmware = 1; | |
126 | module_param (distrust_firmware, bool, 0); | |
127 | MODULE_PARM_DESC (distrust_firmware, | |
128 | "true to distrust firmware power/overcurrent setup"); | |
129 | ||
130 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
131 | static int no_handshake = 0; | |
132 | module_param (no_handshake, bool, 0); | |
133 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
134 | ||
135 | /*-------------------------------------------------------------------------*/ | |
136 | ||
137 | /* | |
138 | * queue up an urb for anything except the root hub | |
139 | */ | |
140 | static int ohci_urb_enqueue ( | |
141 | struct usb_hcd *hcd, | |
1da177e4 | 142 | struct urb *urb, |
55016f10 | 143 | gfp_t mem_flags |
1da177e4 LT |
144 | ) { |
145 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
146 | struct ed *ed; | |
147 | urb_priv_t *urb_priv; | |
148 | unsigned int pipe = urb->pipe; | |
149 | int i, size = 0; | |
150 | unsigned long flags; | |
151 | int retval = 0; | |
dd9048af | 152 | |
1da177e4 | 153 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 154 | urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); |
1da177e4 | 155 | #endif |
dd9048af | 156 | |
1da177e4 | 157 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
e9df41c5 | 158 | if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) |
1da177e4 LT |
159 | return -ENOMEM; |
160 | ||
161 | /* for the private part of the URB we need the number of TDs (size) */ | |
162 | switch (ed->type) { | |
163 | case PIPE_CONTROL: | |
164 | /* td_submit_urb() doesn't yet handle these */ | |
165 | if (urb->transfer_buffer_length > 4096) | |
166 | return -EMSGSIZE; | |
167 | ||
168 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
169 | size = 2; | |
170 | /* FALLTHROUGH */ | |
171 | // case PIPE_INTERRUPT: | |
172 | // case PIPE_BULK: | |
173 | default: | |
174 | /* one TD for every 4096 Bytes (can be upto 8K) */ | |
175 | size += urb->transfer_buffer_length / 4096; | |
176 | /* ... and for any remaining bytes ... */ | |
177 | if ((urb->transfer_buffer_length % 4096) != 0) | |
178 | size++; | |
179 | /* ... and maybe a zero length packet to wrap it up */ | |
180 | if (size == 0) | |
181 | size++; | |
182 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
183 | && (urb->transfer_buffer_length | |
184 | % usb_maxpacket (urb->dev, pipe, | |
185 | usb_pipeout (pipe))) == 0) | |
186 | size++; | |
187 | break; | |
188 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
189 | size = urb->number_of_packets; | |
190 | break; | |
191 | } | |
192 | ||
193 | /* allocate the private part of the URB */ | |
dd00cc48 | 194 | urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), |
1da177e4 LT |
195 | mem_flags); |
196 | if (!urb_priv) | |
197 | return -ENOMEM; | |
1da177e4 LT |
198 | INIT_LIST_HEAD (&urb_priv->pending); |
199 | urb_priv->length = size; | |
dd9048af | 200 | urb_priv->ed = ed; |
1da177e4 LT |
201 | |
202 | /* allocate the TDs (deferring hash chain updates) */ | |
203 | for (i = 0; i < size; i++) { | |
204 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
205 | if (!urb_priv->td [i]) { | |
206 | urb_priv->length = i; | |
207 | urb_free_priv (ohci, urb_priv); | |
208 | return -ENOMEM; | |
209 | } | |
dd9048af | 210 | } |
1da177e4 LT |
211 | |
212 | spin_lock_irqsave (&ohci->lock, flags); | |
213 | ||
214 | /* don't submit to a dead HC */ | |
8de98402 BH |
215 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
216 | retval = -ENODEV; | |
217 | goto fail; | |
218 | } | |
1da177e4 LT |
219 | if (!HC_IS_RUNNING(hcd->state)) { |
220 | retval = -ENODEV; | |
221 | goto fail; | |
222 | } | |
e9df41c5 AS |
223 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
224 | if (retval) | |
1da177e4 | 225 | goto fail; |
1da177e4 LT |
226 | |
227 | /* schedule the ed if needed */ | |
228 | if (ed->state == ED_IDLE) { | |
229 | retval = ed_schedule (ohci, ed); | |
e9df41c5 AS |
230 | if (retval < 0) { |
231 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
232 | goto fail; | |
233 | } | |
1da177e4 LT |
234 | if (ed->type == PIPE_ISOCHRONOUS) { |
235 | u16 frame = ohci_frame_no(ohci); | |
236 | ||
237 | /* delay a few frames before the first TD */ | |
238 | frame += max_t (u16, 8, ed->interval); | |
239 | frame &= ~(ed->interval - 1); | |
240 | frame |= ed->branch; | |
241 | urb->start_frame = frame; | |
242 | ||
243 | /* yes, only URB_ISO_ASAP is supported, and | |
244 | * urb->start_frame is never used as input. | |
245 | */ | |
246 | } | |
247 | } else if (ed->type == PIPE_ISOCHRONOUS) | |
248 | urb->start_frame = ed->last_iso + ed->interval; | |
249 | ||
250 | /* fill the TDs and link them to the ed; and | |
251 | * enable that part of the schedule, if needed | |
252 | * and update count of queued periodic urbs | |
253 | */ | |
254 | urb->hcpriv = urb_priv; | |
255 | td_submit_urb (ohci, urb); | |
256 | ||
1da177e4 LT |
257 | fail: |
258 | if (retval) | |
259 | urb_free_priv (ohci, urb_priv); | |
260 | spin_unlock_irqrestore (&ohci->lock, flags); | |
261 | return retval; | |
262 | } | |
263 | ||
264 | /* | |
55d84968 AS |
265 | * decouple the URB from the HC queues (TDs, urb_priv). |
266 | * reporting is always done | |
1da177e4 LT |
267 | * asynchronously, and we might be dealing with an urb that's |
268 | * partially transferred, or an ED with other urbs being unlinked. | |
269 | */ | |
e9df41c5 | 270 | static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
271 | { |
272 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
273 | unsigned long flags; | |
e9df41c5 | 274 | int rc; |
dd9048af | 275 | |
1da177e4 | 276 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 277 | urb_print(urb, "UNLINK", 1, status); |
dd9048af | 278 | #endif |
1da177e4 LT |
279 | |
280 | spin_lock_irqsave (&ohci->lock, flags); | |
e9df41c5 AS |
281 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
282 | if (rc) { | |
283 | ; /* Do nothing */ | |
284 | } else if (HC_IS_RUNNING(hcd->state)) { | |
1da177e4 LT |
285 | urb_priv_t *urb_priv; |
286 | ||
287 | /* Unless an IRQ completed the unlink while it was being | |
288 | * handed to us, flag it for unlink and giveback, and force | |
289 | * some upcoming INTR_SF to call finish_unlinks() | |
290 | */ | |
291 | urb_priv = urb->hcpriv; | |
292 | if (urb_priv) { | |
293 | if (urb_priv->ed->state == ED_OPER) | |
294 | start_ed_unlink (ohci, urb_priv->ed); | |
295 | } | |
296 | } else { | |
297 | /* | |
298 | * with HC dead, we won't respect hc queue pointers | |
299 | * any more ... just clean up every urb's memory. | |
300 | */ | |
301 | if (urb->hcpriv) | |
55d84968 | 302 | finish_urb(ohci, urb, status); |
1da177e4 LT |
303 | } |
304 | spin_unlock_irqrestore (&ohci->lock, flags); | |
e9df41c5 | 305 | return rc; |
1da177e4 LT |
306 | } |
307 | ||
308 | /*-------------------------------------------------------------------------*/ | |
309 | ||
310 | /* frees config/altsetting state for endpoints, | |
311 | * including ED memory, dummy TD, and bulk/intr data toggle | |
312 | */ | |
313 | ||
314 | static void | |
315 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
316 | { | |
317 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
318 | unsigned long flags; | |
319 | struct ed *ed = ep->hcpriv; | |
320 | unsigned limit = 1000; | |
321 | ||
322 | /* ASSERT: any requests/urbs are being unlinked */ | |
323 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
324 | ||
325 | if (!ed) | |
326 | return; | |
327 | ||
328 | rescan: | |
329 | spin_lock_irqsave (&ohci->lock, flags); | |
330 | ||
331 | if (!HC_IS_RUNNING (hcd->state)) { | |
332 | sanitize: | |
333 | ed->state = ED_IDLE; | |
89a0fd18 MN |
334 | if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) |
335 | ohci->eds_scheduled--; | |
7d12e780 | 336 | finish_unlinks (ohci, 0); |
1da177e4 LT |
337 | } |
338 | ||
339 | switch (ed->state) { | |
340 | case ED_UNLINK: /* wait for hw to finish? */ | |
341 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
342 | if (limit-- == 0) { | |
89a0fd18 MN |
343 | ohci_warn(ohci, "ED unlink timeout\n"); |
344 | if (quirk_zfmicro(ohci)) { | |
345 | ohci_warn(ohci, "Attempting ZF TD recovery\n"); | |
346 | ohci->ed_to_check = ed; | |
347 | ohci->zf_delay = 2; | |
348 | } | |
1da177e4 LT |
349 | goto sanitize; |
350 | } | |
351 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 352 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
353 | goto rescan; |
354 | case ED_IDLE: /* fully unlinked */ | |
355 | if (list_empty (&ed->td_list)) { | |
356 | td_free (ohci, ed->dummy); | |
357 | ed_free (ohci, ed); | |
358 | break; | |
359 | } | |
360 | /* else FALL THROUGH */ | |
361 | default: | |
362 | /* caller was supposed to have unlinked any requests; | |
363 | * that's not our job. can't recover; must leak ed. | |
364 | */ | |
365 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
366 | ed, ep->desc.bEndpointAddress, ed->state, | |
367 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
368 | td_free (ohci, ed->dummy); | |
369 | break; | |
370 | } | |
371 | ep->hcpriv = NULL; | |
372 | spin_unlock_irqrestore (&ohci->lock, flags); | |
373 | return; | |
374 | } | |
375 | ||
376 | static int ohci_get_frame (struct usb_hcd *hcd) | |
377 | { | |
378 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
379 | ||
380 | return ohci_frame_no(ohci); | |
381 | } | |
382 | ||
383 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
384 | { | |
385 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
386 | ohci->hc_control &= OHCI_CTRL_RWC; | |
387 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
388 | } | |
389 | ||
64a21d02 | 390 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
391 | * other cases where the next software may expect clean state from the |
392 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
393 | */ | |
64a21d02 AG |
394 | static void |
395 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
396 | { |
397 | struct ohci_hcd *ohci; | |
398 | ||
64a21d02 | 399 | ohci = hcd_to_ohci (hcd); |
f4df0e33 DB |
400 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
401 | ohci_usb_reset (ohci); | |
402 | /* flush the writes */ | |
403 | (void) ohci_readl (ohci, &ohci->regs->control); | |
f4df0e33 DB |
404 | } |
405 | ||
89a0fd18 MN |
406 | static int check_ed(struct ohci_hcd *ohci, struct ed *ed) |
407 | { | |
408 | return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 | |
409 | && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) | |
410 | == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) | |
411 | && !list_empty(&ed->td_list); | |
412 | } | |
413 | ||
414 | /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes | |
415 | * an interrupt TD but neglects to add it to the donelist. On systems with | |
416 | * this chipset, we need to periodically check the state of the queues to look | |
417 | * for such "lost" TDs. | |
418 | */ | |
419 | static void unlink_watchdog_func(unsigned long _ohci) | |
420 | { | |
da6fb570 | 421 | unsigned long flags; |
89a0fd18 MN |
422 | unsigned max; |
423 | unsigned seen_count = 0; | |
424 | unsigned i; | |
425 | struct ed **seen = NULL; | |
426 | struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; | |
427 | ||
428 | spin_lock_irqsave(&ohci->lock, flags); | |
429 | max = ohci->eds_scheduled; | |
430 | if (!max) | |
431 | goto done; | |
432 | ||
433 | if (ohci->ed_to_check) | |
434 | goto out; | |
435 | ||
436 | seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); | |
437 | if (!seen) | |
438 | goto out; | |
439 | ||
440 | for (i = 0; i < NUM_INTS; i++) { | |
441 | struct ed *ed = ohci->periodic[i]; | |
442 | ||
443 | while (ed) { | |
444 | unsigned temp; | |
445 | ||
446 | /* scan this branch of the periodic schedule tree */ | |
447 | for (temp = 0; temp < seen_count; temp++) { | |
448 | if (seen[temp] == ed) { | |
449 | /* we've checked it and what's after */ | |
450 | ed = NULL; | |
451 | break; | |
452 | } | |
453 | } | |
454 | if (!ed) | |
455 | break; | |
456 | seen[seen_count++] = ed; | |
457 | if (!check_ed(ohci, ed)) { | |
458 | ed = ed->ed_next; | |
459 | continue; | |
460 | } | |
461 | ||
462 | /* HC's TD list is empty, but HCD sees at least one | |
463 | * TD that's not been sent through the donelist. | |
464 | */ | |
465 | ohci->ed_to_check = ed; | |
466 | ohci->zf_delay = 2; | |
467 | ||
468 | /* The HC may wait until the next frame to report the | |
469 | * TD as done through the donelist and INTR_WDH. (We | |
470 | * just *assume* it's not a multi-TD interrupt URB; | |
471 | * those could defer the IRQ more than one frame, using | |
472 | * DI...) Check again after the next INTR_SF. | |
473 | */ | |
474 | ohci_writel(ohci, OHCI_INTR_SF, | |
475 | &ohci->regs->intrstatus); | |
476 | ohci_writel(ohci, OHCI_INTR_SF, | |
477 | &ohci->regs->intrenable); | |
478 | ||
479 | /* flush those writes */ | |
480 | (void) ohci_readl(ohci, &ohci->regs->control); | |
481 | ||
482 | goto out; | |
483 | } | |
484 | } | |
485 | out: | |
486 | kfree(seen); | |
487 | if (ohci->eds_scheduled) | |
9cebcdc7 | 488 | mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); |
89a0fd18 MN |
489 | done: |
490 | spin_unlock_irqrestore(&ohci->lock, flags); | |
491 | } | |
492 | ||
1da177e4 LT |
493 | /*-------------------------------------------------------------------------* |
494 | * HC functions | |
495 | *-------------------------------------------------------------------------*/ | |
496 | ||
497 | /* init memory, and kick BIOS/SMM off */ | |
498 | ||
499 | static int ohci_init (struct ohci_hcd *ohci) | |
500 | { | |
501 | int ret; | |
6a9062f3 | 502 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 503 | |
1133cd8a DB |
504 | if (distrust_firmware) |
505 | ohci->flags |= OHCI_QUIRK_HUB_POWER; | |
506 | ||
1da177e4 | 507 | disable (ohci); |
6a9062f3 | 508 | ohci->regs = hcd->regs; |
1da177e4 | 509 | |
6a9062f3 DB |
510 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
511 | * was never needed for most non-PCI systems ... remove the code? | |
512 | */ | |
513 | ||
1da177e4 LT |
514 | #ifndef IR_DISABLE |
515 | /* SMM owns the HC? not for long! */ | |
516 | if (!no_handshake && ohci_readl (ohci, | |
517 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
518 | u32 temp; | |
519 | ||
520 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
521 | ||
522 | /* this timeout is arbitrary. we make it long, so systems | |
523 | * depending on usb keyboards may be usable even if the | |
524 | * BIOS/SMM code seems pretty broken. | |
525 | */ | |
526 | temp = 500; /* arbitrary: five seconds */ | |
527 | ||
528 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
529 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
530 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
531 | msleep (10); | |
532 | if (--temp == 0) { | |
533 | ohci_err (ohci, "USB HC takeover failed!" | |
534 | " (BIOS/SMM bug)\n"); | |
535 | return -EBUSY; | |
536 | } | |
537 | } | |
538 | ohci_usb_reset (ohci); | |
539 | } | |
540 | #endif | |
541 | ||
542 | /* Disable HC interrupts */ | |
543 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
544 | |
545 | /* flush the writes, and save key bits like RWC */ | |
546 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
547 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 548 | |
fdd13b36 DB |
549 | /* Read the number of ports unless overridden */ |
550 | if (ohci->num_ports == 0) | |
551 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
552 | ||
1da177e4 LT |
553 | if (ohci->hcca) |
554 | return 0; | |
555 | ||
6a9062f3 | 556 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
1da177e4 LT |
557 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
558 | if (!ohci->hcca) | |
559 | return -ENOMEM; | |
560 | ||
561 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
562 | ohci_stop (hcd); |
563 | else { | |
6a9062f3 DB |
564 | create_debug_files (ohci); |
565 | } | |
1da177e4 LT |
566 | |
567 | return ret; | |
1da177e4 LT |
568 | } |
569 | ||
570 | /*-------------------------------------------------------------------------*/ | |
571 | ||
572 | /* Start an OHCI controller, set the BUS operational | |
573 | * resets USB and controller | |
dd9048af | 574 | * enable interrupts |
1da177e4 LT |
575 | */ |
576 | static int ohci_run (struct ohci_hcd *ohci) | |
577 | { | |
96f90a8b | 578 | u32 mask, val; |
1da177e4 | 579 | int first = ohci->fminterval == 0; |
6a9062f3 | 580 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
581 | |
582 | disable (ohci); | |
583 | ||
584 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
585 | if (first) { | |
586 | ||
96f90a8b HS |
587 | val = ohci_readl (ohci, &ohci->regs->fminterval); |
588 | ohci->fminterval = val & 0x3fff; | |
1da177e4 LT |
589 | if (ohci->fminterval != FI) |
590 | ohci_dbg (ohci, "fminterval delta %d\n", | |
591 | ohci->fminterval - FI); | |
592 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
593 | /* also: power/overcurrent flags in roothub.a */ | |
594 | } | |
595 | ||
6fd9086a AS |
596 | /* Reset USB nearly "by the book". RemoteWakeupConnected has |
597 | * to be checked in case boot firmware (BIOS/SMM/...) has set up | |
598 | * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). | |
599 | * If the bus glue detected wakeup capability then it should | |
bcca06ef | 600 | * already be enabled; if so we'll just enable it again. |
1da177e4 | 601 | */ |
bcca06ef AS |
602 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) |
603 | device_set_wakeup_capable(hcd->self.controller, 1); | |
1da177e4 LT |
604 | |
605 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
606 | case OHCI_USB_OPER: | |
96f90a8b | 607 | val = 0; |
1da177e4 LT |
608 | break; |
609 | case OHCI_USB_SUSPEND: | |
610 | case OHCI_USB_RESUME: | |
611 | ohci->hc_control &= OHCI_CTRL_RWC; | |
612 | ohci->hc_control |= OHCI_USB_RESUME; | |
96f90a8b | 613 | val = 10 /* msec wait */; |
1da177e4 LT |
614 | break; |
615 | // case OHCI_USB_RESET: | |
616 | default: | |
617 | ohci->hc_control &= OHCI_CTRL_RWC; | |
618 | ohci->hc_control |= OHCI_USB_RESET; | |
96f90a8b | 619 | val = 50 /* msec wait */; |
1da177e4 LT |
620 | break; |
621 | } | |
622 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
623 | // flush the writes | |
624 | (void) ohci_readl (ohci, &ohci->regs->control); | |
96f90a8b | 625 | msleep(val); |
383975d7 | 626 | |
1da177e4 LT |
627 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); |
628 | ||
629 | /* 2msec timelimit here means no irqs/preempt */ | |
630 | spin_lock_irq (&ohci->lock); | |
631 | ||
632 | retry: | |
633 | /* HC Reset requires max 10 us delay */ | |
634 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
96f90a8b | 635 | val = 30; /* ... allow extra time */ |
1da177e4 | 636 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { |
96f90a8b | 637 | if (--val == 0) { |
1da177e4 LT |
638 | spin_unlock_irq (&ohci->lock); |
639 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
640 | return -1; | |
641 | } | |
642 | udelay (1); | |
643 | } | |
644 | ||
645 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
646 | * within 2msec else HC enters RESUME | |
647 | * | |
648 | * ... but some hardware won't init fmInterval "by the book" | |
649 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
650 | * this if we write fmInterval after we're OPERATIONAL. | |
651 | * Unclear about ALi, ServerWorks, and others ... this could | |
652 | * easily be a longstanding bug in chip init on Linux. | |
653 | */ | |
654 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
655 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
656 | // flush those writes | |
657 | (void) ohci_readl (ohci, &ohci->regs->control); | |
658 | } | |
659 | ||
660 | /* Tell the controller where the control and bulk lists are | |
661 | * The lists are empty now. */ | |
662 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
663 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
664 | ||
665 | /* a reset clears this */ | |
666 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
667 | ||
668 | periodic_reinit (ohci); | |
669 | ||
670 | /* some OHCI implementations are finicky about how they init. | |
671 | * bogus values here mean not even enumeration could work. | |
672 | */ | |
673 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
674 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
675 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
676 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
677 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
678 | goto retry; | |
679 | } | |
680 | spin_unlock_irq (&ohci->lock); | |
681 | ohci_err (ohci, "init err (%08x %04x)\n", | |
682 | ohci_readl (ohci, &ohci->regs->fminterval), | |
683 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
684 | return -EOVERFLOW; | |
685 | } | |
686 | ||
d413984a DB |
687 | /* use rhsc irqs after khubd is fully initialized */ |
688 | hcd->poll_rh = 1; | |
689 | hcd->uses_new_polling = 1; | |
690 | ||
691 | /* start controller operations */ | |
1da177e4 | 692 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
693 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
694 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
6a9062f3 | 695 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
696 | |
697 | /* wake on ConnectStatusChange, matching external hubs */ | |
698 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
699 | ||
700 | /* Choose the interrupts we care about now, others later on demand */ | |
701 | mask = OHCI_INTR_INIT; | |
d413984a | 702 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
703 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
704 | ||
705 | /* handle root hub init quirks ... */ | |
96f90a8b HS |
706 | val = roothub_a (ohci); |
707 | val &= ~(RH_A_PSM | RH_A_OCPM); | |
1da177e4 LT |
708 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { |
709 | /* NSC 87560 and maybe others */ | |
96f90a8b HS |
710 | val |= RH_A_NOCP; |
711 | val &= ~(RH_A_POTPGT | RH_A_NPS); | |
712 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1133cd8a DB |
713 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || |
714 | (ohci->flags & OHCI_QUIRK_HUB_POWER)) { | |
1da177e4 LT |
715 | /* hub power always on; required for AMD-756 and some |
716 | * Mac platforms. ganged overcurrent reporting, if any. | |
717 | */ | |
96f90a8b HS |
718 | val |= RH_A_NPS; |
719 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1da177e4 LT |
720 | } |
721 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
96f90a8b | 722 | ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, |
1da177e4 LT |
723 | &ohci->regs->roothub.b); |
724 | // flush those writes | |
725 | (void) ohci_readl (ohci, &ohci->regs->control); | |
726 | ||
d413984a | 727 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
728 | spin_unlock_irq (&ohci->lock); |
729 | ||
730 | // POTPGT delay is bits 24-31, in 2 ms units. | |
96f90a8b | 731 | mdelay ((val >> 23) & 0x1fe); |
6a9062f3 | 732 | hcd->state = HC_STATE_RUNNING; |
1da177e4 | 733 | |
89a0fd18 MN |
734 | if (quirk_zfmicro(ohci)) { |
735 | /* Create timer to watch for bad queue state on ZF Micro */ | |
736 | setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, | |
737 | (unsigned long) ohci); | |
738 | ||
739 | ohci->eds_scheduled = 0; | |
740 | ohci->ed_to_check = NULL; | |
741 | } | |
742 | ||
1da177e4 LT |
743 | ohci_dump (ohci, 1); |
744 | ||
1da177e4 LT |
745 | return 0; |
746 | } | |
747 | ||
748 | /*-------------------------------------------------------------------------*/ | |
749 | ||
750 | /* an interrupt happens */ | |
751 | ||
7d12e780 | 752 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
753 | { |
754 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
755 | struct ohci_regs __iomem *regs = ohci->regs; | |
89a0fd18 | 756 | int ints; |
1da177e4 | 757 | |
565227c0 BH |
758 | /* Read interrupt status (and flush pending writes). We ignore the |
759 | * optimization of checking the LSB of hcca->done_head; it doesn't | |
760 | * work on all systems (edge triggering for OHCI can be a factor). | |
89a0fd18 | 761 | */ |
565227c0 | 762 | ints = ohci_readl(ohci, ®s->intrstatus); |
1da177e4 | 763 | |
565227c0 BH |
764 | /* Check for an all 1's result which is a typical consequence |
765 | * of dead, unclocked, or unplugged (CardBus...) devices | |
766 | */ | |
767 | if (ints == ~(u32)0) { | |
1da177e4 LT |
768 | disable (ohci); |
769 | ohci_dbg (ohci, "device removed!\n"); | |
770 | return IRQ_HANDLED; | |
565227c0 BH |
771 | } |
772 | ||
773 | /* We only care about interrupts that are enabled */ | |
774 | ints &= ohci_readl(ohci, ®s->intrenable); | |
1da177e4 LT |
775 | |
776 | /* interrupt for some other device? */ | |
565227c0 | 777 | if (ints == 0) |
1da177e4 | 778 | return IRQ_NOTMINE; |
d413984a | 779 | |
1da177e4 | 780 | if (ints & OHCI_INTR_UE) { |
1da177e4 | 781 | // e.g. due to PCI Master/Target Abort |
89a0fd18 | 782 | if (quirk_nec(ohci)) { |
d576bb9f MH |
783 | /* Workaround for a silicon bug in some NEC chips used |
784 | * in Apple's PowerBooks. Adapted from Darwin code. | |
785 | */ | |
786 | ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); | |
787 | ||
788 | ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); | |
789 | ||
790 | schedule_work (&ohci->nec_work); | |
791 | } else { | |
792 | disable (ohci); | |
793 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); | |
794 | } | |
1da177e4 LT |
795 | |
796 | ohci_dump (ohci, 1); | |
797 | ohci_usb_reset (ohci); | |
798 | } | |
799 | ||
583ceada AS |
800 | if (ints & OHCI_INTR_RHSC) { |
801 | ohci_vdbg(ohci, "rhsc\n"); | |
802 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; | |
803 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
804 | ®s->intrstatus); | |
052ac01a AS |
805 | |
806 | /* NOTE: Vendors didn't always make the same implementation | |
807 | * choices for RHSC. Many followed the spec; RHSC triggers | |
808 | * on an edge, like setting and maybe clearing a port status | |
809 | * change bit. With others it's level-triggered, active | |
810 | * until khubd clears all the port status change bits. We'll | |
811 | * always disable it here and rely on polling until khubd | |
812 | * re-enables it. | |
813 | */ | |
814 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
815 | usb_hcd_poll_rh_status(hcd); |
816 | } | |
817 | ||
818 | /* For connect and disconnect events, we expect the controller | |
819 | * to turn on RHSC along with RD. But for remote wakeup events | |
820 | * this might not happen. | |
821 | */ | |
822 | else if (ints & OHCI_INTR_RD) { | |
823 | ohci_vdbg(ohci, "resume detect\n"); | |
824 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); | |
8d1a243b AS |
825 | hcd->poll_rh = 1; |
826 | if (ohci->autostop) { | |
827 | spin_lock (&ohci->lock); | |
828 | ohci_rh_resume (ohci); | |
829 | spin_unlock (&ohci->lock); | |
830 | } else | |
f197b2c5 | 831 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
832 | } |
833 | ||
834 | if (ints & OHCI_INTR_WDH) { | |
1da177e4 | 835 | spin_lock (&ohci->lock); |
7d12e780 | 836 | dl_done_list (ohci); |
1da177e4 | 837 | spin_unlock (&ohci->lock); |
1da177e4 | 838 | } |
dd9048af | 839 | |
89a0fd18 MN |
840 | if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { |
841 | spin_lock(&ohci->lock); | |
842 | if (ohci->ed_to_check) { | |
843 | struct ed *ed = ohci->ed_to_check; | |
844 | ||
845 | if (check_ed(ohci, ed)) { | |
846 | /* HC thinks the TD list is empty; HCD knows | |
847 | * at least one TD is outstanding | |
848 | */ | |
849 | if (--ohci->zf_delay == 0) { | |
850 | struct td *td = list_entry( | |
851 | ed->td_list.next, | |
852 | struct td, td_list); | |
853 | ohci_warn(ohci, | |
854 | "Reclaiming orphan TD %p\n", | |
855 | td); | |
856 | takeback_td(ohci, td); | |
857 | ohci->ed_to_check = NULL; | |
858 | } | |
859 | } else | |
860 | ohci->ed_to_check = NULL; | |
861 | } | |
862 | spin_unlock(&ohci->lock); | |
863 | } | |
864 | ||
1da177e4 LT |
865 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
866 | ||
867 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
868 | * when there's still unlinking to be done (next frame). | |
869 | */ | |
870 | spin_lock (&ohci->lock); | |
871 | if (ohci->ed_rm_list) | |
7d12e780 | 872 | finish_unlinks (ohci, ohci_frame_no(ohci)); |
89a0fd18 MN |
873 | if ((ints & OHCI_INTR_SF) != 0 |
874 | && !ohci->ed_rm_list | |
875 | && !ohci->ed_to_check | |
1da177e4 | 876 | && HC_IS_RUNNING(hcd->state)) |
dd9048af | 877 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 LT |
878 | spin_unlock (&ohci->lock); |
879 | ||
880 | if (HC_IS_RUNNING(hcd->state)) { | |
881 | ohci_writel (ohci, ints, ®s->intrstatus); | |
dd9048af | 882 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
883 | // flush those writes |
884 | (void) ohci_readl (ohci, &ohci->regs->control); | |
885 | } | |
886 | ||
887 | return IRQ_HANDLED; | |
888 | } | |
889 | ||
890 | /*-------------------------------------------------------------------------*/ | |
891 | ||
892 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 893 | { |
1da177e4 LT |
894 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
895 | ||
1da177e4 LT |
896 | ohci_dump (ohci, 1); |
897 | ||
898 | flush_scheduled_work(); | |
899 | ||
900 | ohci_usb_reset (ohci); | |
901 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
71795c1d PZ |
902 | free_irq(hcd->irq, hcd); |
903 | hcd->irq = -1; | |
904 | ||
89a0fd18 MN |
905 | if (quirk_zfmicro(ohci)) |
906 | del_timer(&ohci->unlink_watchdog); | |
ab1666c1 LY |
907 | if (quirk_amdiso(ohci)) |
908 | amd_iso_dev_put(); | |
89a0fd18 | 909 | |
1da177e4 LT |
910 | remove_debug_files (ohci); |
911 | ohci_mem_cleanup (ohci); | |
912 | if (ohci->hcca) { | |
dd9048af DB |
913 | dma_free_coherent (hcd->self.controller, |
914 | sizeof *ohci->hcca, | |
1da177e4 LT |
915 | ohci->hcca, ohci->hcca_dma); |
916 | ohci->hcca = NULL; | |
917 | ohci->hcca_dma = 0; | |
918 | } | |
919 | } | |
920 | ||
921 | /*-------------------------------------------------------------------------*/ | |
922 | ||
da6fb570 DB |
923 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) |
924 | ||
1da177e4 | 925 | /* must not be called from interrupt context */ |
1da177e4 LT |
926 | static int ohci_restart (struct ohci_hcd *ohci) |
927 | { | |
928 | int temp; | |
929 | int i; | |
930 | struct urb_priv *priv; | |
1da177e4 | 931 | |
1da177e4 LT |
932 | spin_lock_irq(&ohci->lock); |
933 | disable (ohci); | |
d576bb9f MH |
934 | |
935 | /* Recycle any "live" eds/tds (and urbs). */ | |
1da177e4 LT |
936 | if (!list_empty (&ohci->pending)) |
937 | ohci_dbg(ohci, "abort schedule...\n"); | |
938 | list_for_each_entry (priv, &ohci->pending, pending) { | |
939 | struct urb *urb = priv->td[0]->urb; | |
940 | struct ed *ed = priv->ed; | |
941 | ||
942 | switch (ed->state) { | |
943 | case ED_OPER: | |
944 | ed->state = ED_UNLINK; | |
945 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
946 | ed_deschedule (ohci, ed); | |
947 | ||
948 | ed->ed_next = ohci->ed_rm_list; | |
949 | ed->ed_prev = NULL; | |
950 | ohci->ed_rm_list = ed; | |
951 | /* FALLTHROUGH */ | |
952 | case ED_UNLINK: | |
953 | break; | |
954 | default: | |
955 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
956 | ed, ed->state); | |
957 | } | |
958 | ||
55d84968 AS |
959 | if (!urb->unlinked) |
960 | urb->unlinked = -ESHUTDOWN; | |
1da177e4 | 961 | } |
7d12e780 | 962 | finish_unlinks (ohci, 0); |
1da177e4 LT |
963 | spin_unlock_irq(&ohci->lock); |
964 | ||
965 | /* paranoia, in case that didn't work: */ | |
966 | ||
967 | /* empty the interrupt branches */ | |
968 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
969 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 970 | |
1da177e4 LT |
971 | /* no EDs to remove */ |
972 | ohci->ed_rm_list = NULL; | |
973 | ||
dd9048af | 974 | /* empty control and bulk lists */ |
1da177e4 LT |
975 | ohci->ed_controltail = NULL; |
976 | ohci->ed_bulktail = NULL; | |
977 | ||
978 | if ((temp = ohci_run (ohci)) < 0) { | |
979 | ohci_err (ohci, "can't restart, %d\n", temp); | |
980 | return temp; | |
1da177e4 | 981 | } |
383975d7 | 982 | ohci_dbg(ohci, "restart complete\n"); |
1da177e4 LT |
983 | return 0; |
984 | } | |
d576bb9f | 985 | |
da6fb570 DB |
986 | #endif |
987 | ||
d576bb9f MH |
988 | /*-------------------------------------------------------------------------*/ |
989 | ||
1da177e4 | 990 | MODULE_AUTHOR (DRIVER_AUTHOR); |
2b70f073 | 991 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
992 | MODULE_LICENSE ("GPL"); |
993 | ||
994 | #ifdef CONFIG_PCI | |
995 | #include "ohci-pci.c" | |
5e16fabe | 996 | #define PCI_DRIVER ohci_pci_driver |
1da177e4 LT |
997 | #endif |
998 | ||
6381fad7 | 999 | #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) |
1da177e4 | 1000 | #include "ohci-sa1111.c" |
5e16fabe | 1001 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
1002 | #endif |
1003 | ||
3ba5f38f | 1004 | #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) |
3eb0c5f4 | 1005 | #include "ohci-s3c2410.c" |
5e16fabe | 1006 | #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver |
3eb0c5f4 BD |
1007 | #endif |
1008 | ||
968b448b | 1009 | #ifdef CONFIG_USB_OHCI_HCD_OMAP1 |
1da177e4 | 1010 | #include "ohci-omap.c" |
968b448b AG |
1011 | #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver |
1012 | #endif | |
1013 | ||
1014 | #ifdef CONFIG_USB_OHCI_HCD_OMAP3 | |
1015 | #include "ohci-omap3.c" | |
1016 | #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver | |
1da177e4 LT |
1017 | #endif |
1018 | ||
1019 | #ifdef CONFIG_ARCH_LH7A404 | |
1020 | #include "ohci-lh7a404.c" | |
5e16fabe | 1021 | #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver |
1da177e4 LT |
1022 | #endif |
1023 | ||
e77ec189 | 1024 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
1da177e4 | 1025 | #include "ohci-pxa27x.c" |
5e16fabe | 1026 | #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver |
1da177e4 LT |
1027 | #endif |
1028 | ||
a5b7474a LB |
1029 | #ifdef CONFIG_ARCH_EP93XX |
1030 | #include "ohci-ep93xx.c" | |
5e16fabe | 1031 | #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver |
a5b7474a LB |
1032 | #endif |
1033 | ||
42a4f17d | 1034 | #ifdef CONFIG_MIPS_ALCHEMY |
1da177e4 | 1035 | #include "ohci-au1xxx.c" |
5e16fabe | 1036 | #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver |
1da177e4 LT |
1037 | #endif |
1038 | ||
5151d040 VW |
1039 | #ifdef CONFIG_PNX8550 |
1040 | #include "ohci-pnx8550.c" | |
5e16fabe | 1041 | #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver |
5151d040 VW |
1042 | #endif |
1043 | ||
1da177e4 LT |
1044 | #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC |
1045 | #include "ohci-ppc-soc.c" | |
5e16fabe | 1046 | #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver |
1da177e4 LT |
1047 | #endif |
1048 | ||
58a0cd78 | 1049 | #ifdef CONFIG_ARCH_AT91 |
39a269c0 | 1050 | #include "ohci-at91.c" |
5e16fabe | 1051 | #define PLATFORM_DRIVER ohci_hcd_at91_driver |
39a269c0 AV |
1052 | #endif |
1053 | ||
60bbfc84 VW |
1054 | #ifdef CONFIG_ARCH_PNX4008 |
1055 | #include "ohci-pnx4008.c" | |
5e16fabe | 1056 | #define PLATFORM_DRIVER usb_hcd_pnx4008_driver |
60bbfc84 VW |
1057 | #endif |
1058 | ||
efe7daf2 SS |
1059 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX |
1060 | #include "ohci-da8xx.c" | |
1061 | #define PLATFORM_DRIVER ohci_hcd_da8xx_driver | |
1062 | #endif | |
1063 | ||
828d55c5 YS |
1064 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
1065 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | |
4c3f450b KM |
1066 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
1067 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
828d55c5 YS |
1068 | #include "ohci-sh.c" |
1069 | #define PLATFORM_DRIVER ohci_hcd_sh_driver | |
1070 | #endif | |
1071 | ||
5e16fabe | 1072 | |
495a678f SM |
1073 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
1074 | #include "ohci-ppc-of.c" | |
1075 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
1076 | #endif | |
1077 | ||
6a6c957e GL |
1078 | #ifdef CONFIG_PPC_PS3 |
1079 | #include "ohci-ps3.c" | |
7a4eb7fd | 1080 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver |
6a6c957e GL |
1081 | #endif |
1082 | ||
c604e851 MB |
1083 | #ifdef CONFIG_USB_OHCI_HCD_SSB |
1084 | #include "ohci-ssb.c" | |
1085 | #define SSB_OHCI_DRIVER ssb_ohci_driver | |
1086 | #endif | |
1087 | ||
f54aab6e MD |
1088 | #ifdef CONFIG_MFD_SM501 |
1089 | #include "ohci-sm501.c" | |
3ee38d8b | 1090 | #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver |
f54aab6e MD |
1091 | #endif |
1092 | ||
78c73414 DB |
1093 | #ifdef CONFIG_MFD_TC6393XB |
1094 | #include "ohci-tmio.c" | |
1095 | #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver | |
1096 | #endif | |
1097 | ||
5e16fabe SM |
1098 | #if !defined(PCI_DRIVER) && \ |
1099 | !defined(PLATFORM_DRIVER) && \ | |
968b448b AG |
1100 | !defined(OMAP1_PLATFORM_DRIVER) && \ |
1101 | !defined(OMAP3_PLATFORM_DRIVER) && \ | |
495a678f | 1102 | !defined(OF_PLATFORM_DRIVER) && \ |
6a6c957e | 1103 | !defined(SA1111_DRIVER) && \ |
c604e851 | 1104 | !defined(PS3_SYSTEM_BUS_DRIVER) && \ |
3ee38d8b | 1105 | !defined(SM501_OHCI_DRIVER) && \ |
78c73414 | 1106 | !defined(TMIO_OHCI_DRIVER) && \ |
c604e851 | 1107 | !defined(SSB_OHCI_DRIVER) |
1da177e4 LT |
1108 | #error "missing bus glue for ohci-hcd" |
1109 | #endif | |
5e16fabe SM |
1110 | |
1111 | static int __init ohci_hcd_mod_init(void) | |
1112 | { | |
1113 | int retval = 0; | |
5e16fabe SM |
1114 | |
1115 | if (usb_disabled()) | |
1116 | return -ENODEV; | |
1117 | ||
2b70f073 | 1118 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); |
5e16fabe SM |
1119 | pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, |
1120 | sizeof (struct ed), sizeof (struct td)); | |
9beeee65 | 1121 | set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe | 1122 | |
684c19e0 | 1123 | #ifdef DEBUG |
485f4f39 | 1124 | ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); |
684c19e0 TJ |
1125 | if (!ohci_debug_root) { |
1126 | retval = -ENOENT; | |
1127 | goto error_debug; | |
1128 | } | |
1129 | #endif | |
1130 | ||
6a6c957e | 1131 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd GL |
1132 | retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
1133 | if (retval < 0) | |
1134 | goto error_ps3; | |
6a6c957e GL |
1135 | #endif |
1136 | ||
5e16fabe SM |
1137 | #ifdef PLATFORM_DRIVER |
1138 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
1139 | if (retval < 0) | |
de44743b | 1140 | goto error_platform; |
5e16fabe SM |
1141 | #endif |
1142 | ||
968b448b AG |
1143 | #ifdef OMAP1_PLATFORM_DRIVER |
1144 | retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER); | |
1145 | if (retval < 0) | |
1146 | goto error_omap1_platform; | |
1147 | #endif | |
1148 | ||
1149 | #ifdef OMAP3_PLATFORM_DRIVER | |
1150 | retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER); | |
1151 | if (retval < 0) | |
1152 | goto error_omap3_platform; | |
1153 | #endif | |
1154 | ||
495a678f SM |
1155 | #ifdef OF_PLATFORM_DRIVER |
1156 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
1157 | if (retval < 0) | |
de44743b | 1158 | goto error_of_platform; |
495a678f SM |
1159 | #endif |
1160 | ||
5e16fabe SM |
1161 | #ifdef SA1111_DRIVER |
1162 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
1163 | if (retval < 0) | |
de44743b | 1164 | goto error_sa1111; |
5e16fabe SM |
1165 | #endif |
1166 | ||
1167 | #ifdef PCI_DRIVER | |
1168 | retval = pci_register_driver(&PCI_DRIVER); | |
1169 | if (retval < 0) | |
de44743b | 1170 | goto error_pci; |
5e16fabe SM |
1171 | #endif |
1172 | ||
c604e851 MB |
1173 | #ifdef SSB_OHCI_DRIVER |
1174 | retval = ssb_driver_register(&SSB_OHCI_DRIVER); | |
1175 | if (retval) | |
1176 | goto error_ssb; | |
1177 | #endif | |
1178 | ||
3ee38d8b BD |
1179 | #ifdef SM501_OHCI_DRIVER |
1180 | retval = platform_driver_register(&SM501_OHCI_DRIVER); | |
1181 | if (retval < 0) | |
1182 | goto error_sm501; | |
1183 | #endif | |
1184 | ||
78c73414 DB |
1185 | #ifdef TMIO_OHCI_DRIVER |
1186 | retval = platform_driver_register(&TMIO_OHCI_DRIVER); | |
1187 | if (retval < 0) | |
1188 | goto error_tmio; | |
1189 | #endif | |
1190 | ||
5e16fabe SM |
1191 | return retval; |
1192 | ||
1193 | /* Error path */ | |
78c73414 DB |
1194 | #ifdef TMIO_OHCI_DRIVER |
1195 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1196 | error_tmio: | |
1197 | #endif | |
3ee38d8b | 1198 | #ifdef SM501_OHCI_DRIVER |
78c73414 | 1199 | platform_driver_unregister(&SM501_OHCI_DRIVER); |
3ee38d8b BD |
1200 | error_sm501: |
1201 | #endif | |
c604e851 | 1202 | #ifdef SSB_OHCI_DRIVER |
78c73414 | 1203 | ssb_driver_unregister(&SSB_OHCI_DRIVER); |
c604e851 MB |
1204 | error_ssb: |
1205 | #endif | |
de44743b | 1206 | #ifdef PCI_DRIVER |
c604e851 | 1207 | pci_unregister_driver(&PCI_DRIVER); |
de44743b BH |
1208 | error_pci: |
1209 | #endif | |
1210 | #ifdef SA1111_DRIVER | |
1211 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1212 | error_sa1111: | |
5e16fabe | 1213 | #endif |
495a678f | 1214 | #ifdef OF_PLATFORM_DRIVER |
de44743b BH |
1215 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); |
1216 | error_of_platform: | |
495a678f | 1217 | #endif |
de44743b BH |
1218 | #ifdef PLATFORM_DRIVER |
1219 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1220 | error_platform: | |
6a6c957e | 1221 | #endif |
968b448b AG |
1222 | #ifdef OMAP1_PLATFORM_DRIVER |
1223 | platform_driver_unregister(&OMAP1_PLATFORM_DRIVER); | |
1224 | error_omap1_platform: | |
1225 | #endif | |
1226 | #ifdef OMAP3_PLATFORM_DRIVER | |
1227 | platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); | |
1228 | error_omap3_platform: | |
1229 | #endif | |
6a6c957e | 1230 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1231 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1232 | error_ps3: |
5e16fabe | 1233 | #endif |
684c19e0 TJ |
1234 | #ifdef DEBUG |
1235 | debugfs_remove(ohci_debug_root); | |
1236 | ohci_debug_root = NULL; | |
1237 | error_debug: | |
1238 | #endif | |
1239 | ||
9beeee65 | 1240 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1241 | return retval; |
1242 | } | |
1243 | module_init(ohci_hcd_mod_init); | |
1244 | ||
1245 | static void __exit ohci_hcd_mod_exit(void) | |
1246 | { | |
78c73414 DB |
1247 | #ifdef TMIO_OHCI_DRIVER |
1248 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1249 | #endif | |
3ee38d8b BD |
1250 | #ifdef SM501_OHCI_DRIVER |
1251 | platform_driver_unregister(&SM501_OHCI_DRIVER); | |
1252 | #endif | |
c604e851 MB |
1253 | #ifdef SSB_OHCI_DRIVER |
1254 | ssb_driver_unregister(&SSB_OHCI_DRIVER); | |
1255 | #endif | |
5e16fabe SM |
1256 | #ifdef PCI_DRIVER |
1257 | pci_unregister_driver(&PCI_DRIVER); | |
1258 | #endif | |
1259 | #ifdef SA1111_DRIVER | |
1260 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1261 | #endif | |
495a678f SM |
1262 | #ifdef OF_PLATFORM_DRIVER |
1263 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1264 | #endif | |
5e16fabe SM |
1265 | #ifdef PLATFORM_DRIVER |
1266 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1267 | #endif | |
6a6c957e | 1268 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1269 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1270 | #endif |
684c19e0 TJ |
1271 | #ifdef DEBUG |
1272 | debugfs_remove(ohci_debug_root); | |
1273 | #endif | |
9beeee65 | 1274 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1275 | } |
1276 | module_exit(ohci_hcd_mod_exit); | |
1277 |