[deliverable/linux.git] / drivers / usb / host / ohci-pxa27x.c

/*
 * OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
 * (C) Copyright 2002 Hewlett-Packard Company
 *
 * Bus Glue for pxa27x
 *
 * Written by Christopher Hoover <ch@hpl.hp.com>
 * Based on fragments of previous driver by Russell King et al.
 *
 * Modified for LH7A404 from ohci-sa1111.c
 *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
 *
 * Modified for pxa27x from ohci-lh7a404.c
 *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
 *
 * This file is licenced under the GPL.
 */

#include <linux/device.h>
#include <linux/signal.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <mach/hardware.h>
#include <mach/ohci.h>
#include <mach/pxa3xx-u2d.h>

/*
 * UHC: USB Host Controller (OHCI-like) register definitions
 */
#define UHCREV		(0x0000) /* UHC HCI Spec Revision */
#define UHCHCON		(0x0004) /* UHC Host Control Register */
#define UHCCOMS		(0x0008) /* UHC Command Status Register */
#define UHCINTS		(0x000C) /* UHC Interrupt Status Register */
#define UHCINTE		(0x0010) /* UHC Interrupt Enable */
#define UHCINTD		(0x0014) /* UHC Interrupt Disable */
#define UHCHCCA		(0x0018) /* UHC Host Controller Comm. Area */
#define UHCPCED		(0x001C) /* UHC Period Current Endpt Descr */
#define UHCCHED		(0x0020) /* UHC Control Head Endpt Descr */
#define UHCCCED		(0x0024) /* UHC Control Current Endpt Descr */
#define UHCBHED		(0x0028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED		(0x002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD	(0x0030) /* UHC Done Head */
#define UHCFMI		(0x0034) /* UHC Frame Interval */
#define UHCFMR		(0x0038) /* UHC Frame Remaining */
#define UHCFMN		(0x003C) /* UHC Frame Number */
#define UHCPERS		(0x0040) /* UHC Periodic Start */
#define UHCLS		(0x0044) /* UHC Low Speed Threshold */

#define UHCRHDA		(0x0048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP	(1 << 12)	/* No over current protection */
#define UHCRHDA_OCPM	(1 << 11)	/* Over Current Protection Mode */
#define UHCRHDA_POTPGT(x) \
			(((x) & 0xff) << 24) /* Power On To Power Good Time */

#define UHCRHDB		(0x004C) /* UHC Root Hub Descriptor B */
#define UHCRHS		(0x0050) /* UHC Root Hub Status */
#define UHCRHPS1	(0x0054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2	(0x0058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3	(0x005C) /* UHC Root Hub Port 3 Status */

#define UHCSTAT		(0x0060) /* UHC Status Register */
#define UHCSTAT_UPS3	(1 << 16)	/* USB Power Sense Port3 */
#define UHCSTAT_SBMAI	(1 << 15)	/* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI	(1 << 14)	/* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI	(1 << 13)	/* USB Port Resume Interrupt */
#define UHCSTAT_UPS2	(1 << 12)	/* USB Power Sense Port 2 */
#define UHCSTAT_UPS1	(1 << 11)	/* USB Power Sense Port 1 */
#define UHCSTAT_HTA	(1 << 10)	/* HCI Target Abort */
#define UHCSTAT_HBA	(1 << 8)	/* HCI Buffer Active */
#define UHCSTAT_RWUE	(1 << 7)	/* HCI Remote Wake Up Event */

#define UHCHR           (0x0064) /* UHC Reset Register */
#define UHCHR_SSEP3	(1 << 11)	/* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2	(1 << 10)	/* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1	(1 << 9)	/* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL	(1 << 7)	/* Power control polarity low */
#define UHCHR_PSPL	(1 << 6)	/* Power sense polarity low */
#define UHCHR_SSE	(1 << 5)	/* Sleep Standby Enable */
#define UHCHR_UIT	(1 << 4)	/* USB Interrupt Test */
#define UHCHR_SSDC	(1 << 3)	/* Simulation Scale Down Clock */
#define UHCHR_CGR	(1 << 2)	/* Clock Generation Reset */
#define UHCHR_FHR	(1 << 1)	/* Force Host Controller Reset */
#define UHCHR_FSBIR	(1 << 0)	/* Force System Bus Iface Reset */

#define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE	(1 << 14)	/* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE	(1 << 13)	/* Port Resume IntEn */
#define UHCHIE_UPS2IE	(1 << 12)	/* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE	(1 << 11)	/* Power Sense Port1 IntEn */
#define UHCHIE_TAIE	(1 << 10)	/* HCI Interface Transfer Abort
					   Interrupt Enable*/
#define UHCHIE_HBAIE	(1 << 8)	/* HCI Buffer Active IntEn */
#define UHCHIE_RWIE	(1 << 7)	/* Remote Wake-up IntEn */

#define UHCHIT          (0x006C) /* UHC Interrupt Test register */

#define PXA_UHC_MAX_PORTNUM    3

struct pxa27x_ohci {
	/* must be 1st member here for hcd_to_ohci() to work */
	struct ohci_hcd ohci;

	struct device	*dev;
	struct clk	*clk;
	void __iomem	*mmio_base;
};

#define to_pxa27x_ohci(hcd)	(struct pxa27x_ohci *)hcd_to_ohci(hcd)

/*
  PMM_NPS_MODE -- PMM Non-power switching mode
      Ports are powered continuously.

  PMM_GLOBAL_MODE -- PMM global switching mode
      All ports are powered at the same time.

  PMM_PERPORT_MODE -- PMM per port switching mode
      Ports are powered individually.
 */
static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
{
	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
	uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);

	switch (mode) {
	case PMM_NPS_MODE:
		uhcrhda |= RH_A_NPS;
		break;
	case PMM_GLOBAL_MODE:
		uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
		break;
	case PMM_PERPORT_MODE:
		uhcrhda &= ~(RH_A_NPS);
		uhcrhda |= RH_A_PSM;

		/* Set port power control mask bits, only 3 ports. */
		uhcrhdb |= (0x7<<17);
		break;
	default:
		printk( KERN_ERR
			"Invalid mode %d, set to non-power switch mode.\n",
			mode );

		uhcrhda |= RH_A_NPS;
	}

	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
	__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
	return 0;
}

extern int usb_disabled(void);

/*-------------------------------------------------------------------------*/

static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
				   struct pxaohci_platform_data *inf)
{
	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);

	if (inf->flags & ENABLE_PORT1)
		uhchr &= ~UHCHR_SSEP1;

	if (inf->flags & ENABLE_PORT2)
		uhchr &= ~UHCHR_SSEP2;

	if (inf->flags & ENABLE_PORT3)
		uhchr &= ~UHCHR_SSEP3;

	if (inf->flags & POWER_CONTROL_LOW)
		uhchr |= UHCHR_PCPL;

	if (inf->flags & POWER_SENSE_LOW)
		uhchr |= UHCHR_PSPL;

	if (inf->flags & NO_OC_PROTECTION)
		uhcrhda |= UHCRHDA_NOCP;
	else
		uhcrhda &= ~UHCRHDA_NOCP;

	if (inf->flags & OC_MODE_PERPORT)
		uhcrhda |= UHCRHDA_OCPM;
	else
		uhcrhda &= ~UHCRHDA_OCPM;

	if (inf->power_on_delay) {
		uhcrhda &= ~UHCRHDA_POTPGT(0xff);
		uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	}

	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
}

static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
{
	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);

	__raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
	udelay(11);
	__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
}

#ifdef CONFIG_PXA27x
extern void pxa27x_clear_otgph(void);
#else
#define pxa27x_clear_otgph()	do {} while (0)
#endif

static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
	int retval = 0;
	struct pxaohci_platform_data *inf;
	uint32_t uhchr;

	inf = dev->platform_data;

	clk_prepare_enable(ohci->clk);

	pxa27x_reset_hc(ohci);

	uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
	__raw_writel(uhchr, ohci->mmio_base + UHCHR);

	while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
		cpu_relax();

	pxa27x_setup_hc(ohci, inf);

	if (inf->init)
		retval = inf->init(dev);

	if (retval < 0)
		return retval;

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);

	uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);

	/* Clear any OTG Pin Hold */
	pxa27x_clear_otgph();
	return 0;
}

static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
	struct pxaohci_platform_data *inf;
	uint32_t uhccoms;

	inf = dev->platform_data;

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);

	if (inf->exit)
		inf->exit(dev);

	pxa27x_reset_hc(ohci);

	/* Host Controller Reset */
	uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
	__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
	udelay(10);

	clk_disable_unprepare(ohci->clk);
}


/*-------------------------------------------------------------------------*/

/* configure so an HC device and id are always provided */
/* always called with process context; sleeping is OK */


/**
 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
 * Context: !in_interrupt()
 *
 * Allocates basic resources for this USB host controller, and
 * then invokes the start() method for the HCD associated with it
 * through the hotplug entry's driver_data.
 *
 */
int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
{
	int retval, irq;
	struct usb_hcd *hcd;
	struct pxaohci_platform_data *inf;
	struct pxa27x_ohci *ohci;
	struct resource *r;
	struct clk *usb_clk;

	inf = pdev->dev.platform_data;

	if (!inf)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		pr_err("no resource of IORESOURCE_IRQ");
		return -ENXIO;
	}

	usb_clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(usb_clk))
		return PTR_ERR(usb_clk);

	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
	if (!hcd) {
		retval = -ENOMEM;
		goto err0;
	}

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		pr_err("no resource of IORESOURCE_MEM");
		retval = -ENXIO;
		goto err1;
	}

	hcd->rsrc_start = r->start;
	hcd->rsrc_len = resource_size(r);

	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
		pr_debug("request_mem_region failed");
		retval = -EBUSY;
		goto err1;
	}

	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	if (!hcd->regs) {
		pr_debug("ioremap failed");
		retval = -ENOMEM;
		goto err2;
	}

	/* initialize "struct pxa27x_ohci" */
	ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
	ohci->dev = &pdev->dev;
	ohci->clk = usb_clk;
	ohci->mmio_base = (void __iomem *)hcd->regs;

	if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
		pr_debug("pxa27x_start_hc failed");
		goto err3;
	}

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(ohci, inf->port_mode);

	if (inf->power_budget)
		hcd->power_budget = inf->power_budget;

	ohci_hcd_init(hcd_to_ohci(hcd));

	retval = usb_add_hcd(hcd, irq, 0);
	if (retval == 0)
		return retval;

	pxa27x_stop_hc(ohci, &pdev->dev);
 err3:
	iounmap(hcd->regs);
 err2:
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 err1:
	usb_put_hcd(hcd);
 err0:
	clk_put(usb_clk);
	return retval;
}


/* may be called without controller electrically present */
/* may be called with controller, bus, and devices active */

/**
 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
 * @dev: USB Host Controller being removed
 * Context: !in_interrupt()
 *
 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
 * the HCD's stop() method.  It is always called from a thread
 * context, normally "rmmod", "apmd", or something similar.
 *
 */
void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
{
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);

	usb_remove_hcd(hcd);
	pxa27x_stop_hc(ohci, &pdev->dev);
	iounmap(hcd->regs);
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	usb_put_hcd(hcd);
	clk_put(ohci->clk);
}

/*-------------------------------------------------------------------------*/

static int __devinit
ohci_pxa27x_start (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int		ret;

	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);

	/* The value of NDP in roothub_a is incorrect on this hardware */
	ohci->num_ports = 3;

	if ((ret = ohci_init(ohci)) < 0)
		return ret;

	if ((ret = ohci_run (ohci)) < 0) {
		dev_err(hcd->self.controller, "can't start %s",
			hcd->self.bus_name);
		ohci_stop (hcd);
		return ret;
	}

	return 0;
}

/*-------------------------------------------------------------------------*/

static const struct hc_driver ohci_pxa27x_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"PXA27x OHCI",
	.hcd_priv_size =	sizeof(struct pxa27x_ohci),

	/*
	 * generic hardware linkage
	 */
	.irq =			ohci_irq,
	.flags =		HCD_USB11 | HCD_MEMORY,

	/*
	 * basic lifecycle operations
	 */
	.start =		ohci_pxa27x_start,
	.stop =			ohci_stop,
	.shutdown =		ohci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ohci_urb_enqueue,
	.urb_dequeue =		ohci_urb_dequeue,
	.endpoint_disable =	ohci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ohci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ohci_hub_status_data,
	.hub_control =		ohci_hub_control,
#ifdef  CONFIG_PM
	.bus_suspend =		ohci_bus_suspend,
	.bus_resume =		ohci_bus_resume,
#endif
	.start_port_reset =	ohci_start_port_reset,
};

/*-------------------------------------------------------------------------*/

static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
{
	pr_debug ("In ohci_hcd_pxa27x_drv_probe");

	if (usb_disabled())
		return -ENODEV;

	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
}

static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);

	usb_hcd_pxa27x_remove(hcd, pdev);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

#ifdef CONFIG_PM
static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);

	if (time_before(jiffies, ohci->ohci.next_statechange))
		msleep(5);
	ohci->ohci.next_statechange = jiffies;

	pxa27x_stop_hc(ohci, dev);
	return 0;
}

static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
	struct pxaohci_platform_data *inf = dev->platform_data;
	int status;

	if (time_before(jiffies, ohci->ohci.next_statechange))
		msleep(5);
	ohci->ohci.next_statechange = jiffies;

	if ((status = pxa27x_start_hc(ohci, dev)) < 0)
		return status;

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(ohci, inf->port_mode);

	ohci_finish_controller_resume(hcd);
	return 0;
}

static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
	.suspend	= ohci_hcd_pxa27x_drv_suspend,
	.resume		= ohci_hcd_pxa27x_drv_resume,
};
#endif

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:pxa27x-ohci");

static struct platform_driver ohci_hcd_pxa27x_driver = {
	.probe		= ohci_hcd_pxa27x_drv_probe,
	.remove		= ohci_hcd_pxa27x_drv_remove,
	.shutdown	= usb_hcd_platform_shutdown,
	.driver		= {
		.name	= "pxa27x-ohci",
		.owner	= THIS_MODULE,
#ifdef CONFIG_PM
		.pm	= &ohci_hcd_pxa27x_pm_ops,
#endif
	},
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
	6	* (C) Copyright 2002 Hewlett-Packard Company
	7	*
	8	* Bus Glue for pxa27x
	9	*
	10	* Written by Christopher Hoover <ch@hpl.hp.com>
	11	* Based on fragments of previous driver by Russell King et al.
	12	*
	13	* Modified for LH7A404 from ohci-sa1111.c
	14	* by Durgesh Pattamatta <pattamattad@sharpsec.com>
	15	*
	16	* Modified for pxa27x from ohci-lh7a404.c
	17	* by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
	18	*
	19	* This file is licenced under the GPL.
	20	*/
	21
	22	#include <linux/device.h>
4e57b681	23	#include <linux/signal.h>
d052d1be	24	#include <linux/platform_device.h>
a8bcf410	25	#include <linux/clk.h>
60b9bd8d	26	#include <mach/hardware.h>
a09e64fb	27	#include <mach/ohci.h>
6dc3ae84	28	#include <mach/pxa3xx-u2d.h>
1da177e4	29
596050bc EM	30	/*
	31	* UHC: USB Host Controller (OHCI-like) register definitions
	32	*/
0c392ed9 EM	33	#define UHCREV (0x0000) /* UHC HCI Spec Revision */
	34	#define UHCHCON (0x0004) /* UHC Host Control Register */
	35	#define UHCCOMS (0x0008) /* UHC Command Status Register */
	36	#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
	37	#define UHCINTE (0x0010) /* UHC Interrupt Enable */
	38	#define UHCINTD (0x0014) /* UHC Interrupt Disable */
	39	#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
	40	#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
	41	#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
	42	#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
	43	#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
	44	#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
	45	#define UHCDHEAD (0x0030) /* UHC Done Head */
	46	#define UHCFMI (0x0034) /* UHC Frame Interval */
	47	#define UHCFMR (0x0038) /* UHC Frame Remaining */
	48	#define UHCFMN (0x003C) /* UHC Frame Number */
	49	#define UHCPERS (0x0040) /* UHC Periodic Start */
	50	#define UHCLS (0x0044) /* UHC Low Speed Threshold */
	51
	52	#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
596050bc EM	53	#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
	54	#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
	55	#define UHCRHDA_POTPGT(x) \
	56	(((x) & 0xff) << 24) /* Power On To Power Good Time */
	57
0c392ed9 EM	58	#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
	59	#define UHCRHS (0x0050) /* UHC Root Hub Status */
	60	#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
	61	#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
	62	#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
596050bc	63
0c392ed9	64	#define UHCSTAT (0x0060) /* UHC Status Register */
596050bc EM	65	#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
	66	#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
	67	#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
	68	#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
	69	#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
	70	#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
	71	#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
	72	#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
	73	#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
	74
0c392ed9	75	#define UHCHR (0x0064) /* UHC Reset Register */
596050bc EM	76	#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
	77	#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
	78	#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
	79	#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
	80	#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
	81	#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
	82	#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
	83	#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
	84	#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
	85	#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
	86	#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
	87
0c392ed9	88	#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
596050bc EM	89	#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
	90	#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
	91	#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
	92	#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
	93	#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
	94	Interrupt Enable*/
	95	#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
	96	#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
	97
0c392ed9	98	#define UHCHIT (0x006C) /* UHC Interrupt Test register */
596050bc	99
1da177e4 LT	100	#define PXA_UHC_MAX_PORTNUM 3
1da177e4 LT	101
0c392ed9 EM	102	struct pxa27x_ohci {
	103	/* must be 1st member here for hcd_to_ohci() to work */
	104	struct ohci_hcd ohci;
1da177e4	105
0c392ed9 EM	106	struct device *dev;
	107	struct clk *clk;
	108	void __iomem *mmio_base;
	109	};
	110
	111	#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
a8bcf410	112
1da177e4 LT	113	/*
	114	PMM_NPS_MODE -- PMM Non-power switching mode
	115	Ports are powered continuously.
	116
	117	PMM_GLOBAL_MODE -- PMM global switching mode
	118	All ports are powered at the same time.
	119
	120	PMM_PERPORT_MODE -- PMM per port switching mode
	121	Ports are powered individually.
	122	*/
0c392ed9	123	static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
1da177e4	124	{
0c392ed9 EM	125	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
	126	uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
	127
	128	switch (mode) {
1da177e4	129	case PMM_NPS_MODE:
0c392ed9	130	uhcrhda \|= RH_A_NPS;
dd9048af	131	break;
1da177e4	132	case PMM_GLOBAL_MODE:
0c392ed9	133	uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
1da177e4 LT	134	break;
1da177e4 LT	135	case PMM_PERPORT_MODE:
0c392ed9 EM	136	uhcrhda &= ~(RH_A_NPS);
0c392ed9 EM	137	uhcrhda \|= RH_A_PSM;
1da177e4 LT	138
1da177e4 LT	139	/* Set port power control mask bits, only 3 ports. */
0c392ed9	140	uhcrhdb \|= (0x7<<17);
1da177e4 LT	141	break;
	142	default:
	143	printk( KERN_ERR
dd9048af	144	"Invalid mode %d, set to non-power switch mode.\n",
1da177e4 LT	145	mode );
1da177e4 LT	146
0c392ed9	147	uhcrhda \|= RH_A_NPS;
1da177e4 LT	148	}
1da177e4 LT	149
0c392ed9 EM	150	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
0c392ed9 EM	151	__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
1da177e4 LT	152	return 0;
	153	}
	154
1da177e4 LT	155	extern int usb_disabled(void);
	156
	157	/-------------------------------------------------------------------------/
	158
0c392ed9 EM	159	static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
0c392ed9 EM	160	struct pxaohci_platform_data *inf)
097b5334	161	{
0c392ed9 EM	162	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
0c392ed9 EM	163	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
097b5334 EM	164
	165	if (inf->flags & ENABLE_PORT1)
	166	uhchr &= ~UHCHR_SSEP1;
	167
	168	if (inf->flags & ENABLE_PORT2)
	169	uhchr &= ~UHCHR_SSEP2;
	170
	171	if (inf->flags & ENABLE_PORT3)
	172	uhchr &= ~UHCHR_SSEP3;
	173
	174	if (inf->flags & POWER_CONTROL_LOW)
	175	uhchr \|= UHCHR_PCPL;
	176
	177	if (inf->flags & POWER_SENSE_LOW)
	178	uhchr \|= UHCHR_PSPL;
	179
	180	if (inf->flags & NO_OC_PROTECTION)
	181	uhcrhda \|= UHCRHDA_NOCP;
7b4361f0 AB	182	else
7b4361f0 AB	183	uhcrhda &= ~UHCRHDA_NOCP;
097b5334 EM	184
	185	if (inf->flags & OC_MODE_PERPORT)
	186	uhcrhda \|= UHCRHDA_OCPM;
7b4361f0 AB	187	else
7b4361f0 AB	188	uhcrhda &= ~UHCRHDA_OCPM;
097b5334 EM	189
	190	if (inf->power_on_delay) {
	191	uhcrhda &= ~UHCRHDA_POTPGT(0xff);
	192	uhcrhda \|= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	193	}
	194
0c392ed9 EM	195	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	196	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
	197	}
	198
	199	static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
	200	{
	201	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
	202
	203	__raw_writel(uhchr \| UHCHR_FHR, ohci->mmio_base + UHCHR);
	204	udelay(11);
	205	__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
097b5334 EM	206	}
097b5334 EM	207
59376cc3	208	#ifdef CONFIG_PXA27x
0cb0b0d3 EM	209	extern void pxa27x_clear_otgph(void);
	210	#else
	211	#define pxa27x_clear_otgph() do {} while (0)
	212	#endif
	213
0c392ed9	214	static int pxa27x_start_hc(struct pxa27x_ohci ohci, struct device dev)
1da177e4	215	{
81f280e2 RP	216	int retval = 0;
81f280e2 RP	217	struct pxaohci_platform_data *inf;
0c392ed9	218	uint32_t uhchr;
81f280e2 RP	219
	220	inf = dev->platform_data;
	221
4bf34b8c	222	clk_prepare_enable(ohci->clk);
1da177e4	223
0c392ed9	224	pxa27x_reset_hc(ohci);
1da177e4	225
0c392ed9 EM	226	uhchr = __raw_readl(ohci->mmio_base + UHCHR) \| UHCHR_FSBIR;
	227	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	228
	229	while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
1da177e4 LT	230	cpu_relax();
1da177e4 LT	231
0c392ed9	232	pxa27x_setup_hc(ohci, inf);
097b5334	233
81f280e2 RP	234	if (inf->init)
81f280e2 RP	235	retval = inf->init(dev);
155faf5e	236
81f280e2 RP	237	if (retval < 0)
81f280e2 RP	238	return retval;
1da177e4	239
6dc3ae84 IG	240	if (cpu_is_pxa3xx())
	241	pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);
	242
0c392ed9 EM	243	uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	244	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	245	__raw_writel(UHCHIE_UPRIE \| UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
155faf5e DB	246
155faf5e DB	247	/* Clear any OTG Pin Hold */
0cb0b0d3	248	pxa27x_clear_otgph();
81f280e2	249	return 0;
1da177e4 LT	250	}
1da177e4 LT	251
0c392ed9	252	static void pxa27x_stop_hc(struct pxa27x_ohci ohci, struct device dev)
1da177e4	253	{
81f280e2	254	struct pxaohci_platform_data *inf;
0c392ed9	255	uint32_t uhccoms;
81f280e2 RP	256
	257	inf = dev->platform_data;
	258
6dc3ae84 IG	259	if (cpu_is_pxa3xx())
	260	pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);
	261
81f280e2 RP	262	if (inf->exit)
	263	inf->exit(dev);
	264
0c392ed9	265	pxa27x_reset_hc(ohci);
1da177e4	266
0c392ed9 EM	267	/* Host Controller Reset */
	268	uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) \| 0x01;
	269	__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
1da177e4 LT	270	udelay(10);
1da177e4 LT	271
4bf34b8c	272	clk_disable_unprepare(ohci->clk);
1da177e4 LT	273	}
	274
	275
	276	/-------------------------------------------------------------------------/
	277
	278	/* configure so an HC device and id are always provided */
	279	/* always called with process context; sleeping is OK */
	280
	281
	282	/**
	283	* usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
	284	* Context: !in_interrupt()
	285	*
	286	* Allocates basic resources for this USB host controller, and
	287	* then invokes the start() method for the HCD associated with it
	288	* through the hotplug entry's driver_data.
	289	*
	290	*/
81f280e2	291	int usb_hcd_pxa27x_probe (const struct hc_driver driver, struct platform_device pdev)
1da177e4	292	{
84bab739	293	int retval, irq;
1da177e4	294	struct usb_hcd *hcd;
81f280e2	295	struct pxaohci_platform_data *inf;
0c392ed9	296	struct pxa27x_ohci *ohci;
84bab739	297	struct resource *r;
0c392ed9	298	struct clk *usb_clk;
81f280e2 RP	299
81f280e2 RP	300	inf = pdev->dev.platform_data;
1da177e4	301
81f280e2 RP	302	if (!inf)
	303	return -ENODEV;
	304
84bab739 EM	305	irq = platform_get_irq(pdev, 0);
	306	if (irq < 0) {
	307	pr_err("no resource of IORESOURCE_IRQ");
	308	return -ENXIO;
1da177e4 LT	309	}
1da177e4 LT	310
e0d8b13a	311	usb_clk = clk_get(&pdev->dev, NULL);
a8bcf410	312	if (IS_ERR(usb_clk))
	313	return PTR_ERR(usb_clk);
	314
81f280e2	315	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
7febe2be JL	316	if (!hcd) {
	317	retval = -ENOMEM;
	318	goto err0;
	319	}
84bab739 EM	320
	321	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	322	if (!r) {
	323	pr_err("no resource of IORESOURCE_MEM");
	324	retval = -ENXIO;
	325	goto err1;
	326	}
	327
	328	hcd->rsrc_start = r->start;
	329	hcd->rsrc_len = resource_size(r);
1da177e4 LT	330
	331	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
	332	pr_debug("request_mem_region failed");
	333	retval = -EBUSY;
	334	goto err1;
	335	}
	336
	337	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	338	if (!hcd->regs) {
	339	pr_debug("ioremap failed");
	340	retval = -ENOMEM;
	341	goto err2;
	342	}
	343
0c392ed9 EM	344	/* initialize "struct pxa27x_ohci" */
	345	ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
	346	ohci->dev = &pdev->dev;
	347	ohci->clk = usb_clk;
	348	ohci->mmio_base = (void __iomem *)hcd->regs;
	349
	350	if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
81f280e2 RP	351	pr_debug("pxa27x_start_hc failed");
	352	goto err3;
	353	}
1da177e4 LT	354
1da177e4 LT	355	/* Select Power Management Mode */
0c392ed9	356	pxa27x_ohci_select_pmm(ohci, inf->port_mode);
1da177e4	357
0c27c5d5 RP	358	if (inf->power_budget)
	359	hcd->power_budget = inf->power_budget;
	360
1da177e4 LT	361	ohci_hcd_init(hcd_to_ohci(hcd));
1da177e4 LT	362
b5dd18d8	363	retval = usb_add_hcd(hcd, irq, 0);
1da177e4 LT	364	if (retval == 0)
	365	return retval;
	366
0c392ed9	367	pxa27x_stop_hc(ohci, &pdev->dev);
81f280e2	368	err3:
1da177e4 LT	369	iounmap(hcd->regs);
	370	err2:
	371	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	372	err1:
	373	usb_put_hcd(hcd);
7febe2be	374	err0:
a8bcf410	375	clk_put(usb_clk);
1da177e4 LT	376	return retval;
	377	}
	378
	379
	380	/* may be called without controller electrically present */
	381	/* may be called with controller, bus, and devices active */
	382
	383	/**
	384	* usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
	385	* @dev: USB Host Controller being removed
	386	* Context: !in_interrupt()
	387	*
	388	* Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
	389	* the HCD's stop() method. It is always called from a thread
	390	* context, normally "rmmod", "apmd", or something similar.
	391	*
	392	*/
81f280e2	393	void usb_hcd_pxa27x_remove (struct usb_hcd hcd, struct platform_device pdev)
1da177e4	394	{
0c392ed9 EM	395	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
0c392ed9 EM	396
1da177e4	397	usb_remove_hcd(hcd);
0c392ed9	398	pxa27x_stop_hc(ohci, &pdev->dev);
1da177e4 LT	399	iounmap(hcd->regs);
	400	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	401	usb_put_hcd(hcd);
0c392ed9	402	clk_put(ohci->clk);
1da177e4 LT	403	}
	404
	405	/-------------------------------------------------------------------------/
	406
	407	static int __devinit
	408	ohci_pxa27x_start (struct usb_hcd *hcd)
	409	{
	410	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	411	int ret;
	412
	413	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
	414
fdd13b36 DB	415	/* The value of NDP in roothub_a is incorrect on this hardware */
	416	ohci->num_ports = 3;
	417
1da177e4 LT	418	if ((ret = ohci_init(ohci)) < 0)
	419	return ret;
	420
	421	if ((ret = ohci_run (ohci)) < 0) {
ade749a6 PG	422	dev_err(hcd->self.controller, "can't start %s",
ade749a6 PG	423	hcd->self.bus_name);
1da177e4 LT	424	ohci_stop (hcd);
	425	return ret;
	426	}
	427
	428	return 0;
	429	}
	430
	431	/-------------------------------------------------------------------------/
	432
	433	static const struct hc_driver ohci_pxa27x_hc_driver = {
	434	.description = hcd_name,
	435	.product_desc = "PXA27x OHCI",
0c392ed9	436	.hcd_priv_size = sizeof(struct pxa27x_ohci),
1da177e4 LT	437
	438	/*
	439	* generic hardware linkage
	440	*/
	441	.irq = ohci_irq,
	442	.flags = HCD_USB11 \| HCD_MEMORY,
	443
	444	/*
	445	* basic lifecycle operations
	446	*/
	447	.start = ohci_pxa27x_start,
	448	.stop = ohci_stop,
dd9048af	449	.shutdown = ohci_shutdown,
1da177e4 LT	450
	451	/*
	452	* managing i/o requests and associated device resources
	453	*/
	454	.urb_enqueue = ohci_urb_enqueue,
	455	.urb_dequeue = ohci_urb_dequeue,
	456	.endpoint_disable = ohci_endpoint_disable,
	457
	458	/*
	459	* scheduling support
	460	*/
	461	.get_frame_number = ohci_get_frame,
	462
	463	/*
	464	* root hub support
	465	*/
	466	.hub_status_data = ohci_hub_status_data,
	467	.hub_control = ohci_hub_control,
8ad7fe16	468	#ifdef CONFIG_PM
0c0382e3 AS	469	.bus_suspend = ohci_bus_suspend,
0c0382e3 AS	470	.bus_resume = ohci_bus_resume,
1da177e4	471	#endif
9293677a	472	.start_port_reset = ohci_start_port_reset,
1da177e4 LT	473	};
	474
	475	/-------------------------------------------------------------------------/
	476
3ae5eaec	477	static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
1da177e4	478	{
1da177e4 LT	479	pr_debug ("In ohci_hcd_pxa27x_drv_probe");
	480
	481	if (usb_disabled())
	482	return -ENODEV;
	483
81f280e2	484	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
1da177e4 LT	485	}
1da177e4 LT	486
3ae5eaec	487	static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
1da177e4	488	{
3ae5eaec	489	struct usb_hcd *hcd = platform_get_drvdata(pdev);
1da177e4 LT	490
1da177e4 LT	491	usb_hcd_pxa27x_remove(hcd, pdev);
a5e36d20	492	platform_set_drvdata(pdev, NULL);
1da177e4 LT	493	return 0;
	494	}
	495
b7f3f59b MR	496	#ifdef CONFIG_PM
b7f3f59b MR	497	static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
1da177e4	498	{
b7f3f59b	499	struct usb_hcd *hcd = dev_get_drvdata(dev);
0c392ed9	500	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
2e1dcc16	501
0c392ed9	502	if (time_before(jiffies, ohci->ohci.next_statechange))
2e1dcc16	503	msleep(5);
0c392ed9	504	ohci->ohci.next_statechange = jiffies;
2e1dcc16	505
b7f3f59b	506	pxa27x_stop_hc(ohci, dev);
1da177e4 LT	507	return 0;
	508	}
	509
b7f3f59b	510	static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
1da177e4	511	{
b7f3f59b	512	struct usb_hcd *hcd = dev_get_drvdata(dev);
0c392ed9	513	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
a75d048e	514	struct pxaohci_platform_data *inf = dev->platform_data;
2e1dcc16 RP	515	int status;
2e1dcc16 RP	516
0c392ed9	517	if (time_before(jiffies, ohci->ohci.next_statechange))
2e1dcc16	518	msleep(5);
0c392ed9	519	ohci->ohci.next_statechange = jiffies;
2e1dcc16	520
b7f3f59b	521	if ((status = pxa27x_start_hc(ohci, dev)) < 0)
2e1dcc16 RP	522	return status;
2e1dcc16 RP	523
a75d048e AB	524	/* Select Power Management Mode */
	525	pxa27x_ohci_select_pmm(ohci, inf->port_mode);
	526
43bbb7e0	527	ohci_finish_controller_resume(hcd);
1da177e4 LT	528	return 0;
1da177e4 LT	529	}
b7f3f59b	530
47145210	531	static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
b7f3f59b MR	532	.suspend = ohci_hcd_pxa27x_drv_suspend,
	533	.resume = ohci_hcd_pxa27x_drv_resume,
	534	};
2e1dcc16	535	#endif
1da177e4	536
f4fce61d KS	537	/* work with hotplug and coldplug */
f4fce61d KS	538	MODULE_ALIAS("platform:pxa27x-ohci");
1da177e4	539
3ae5eaec	540	static struct platform_driver ohci_hcd_pxa27x_driver = {
1da177e4 LT	541	.probe = ohci_hcd_pxa27x_drv_probe,
1da177e4 LT	542	.remove = ohci_hcd_pxa27x_drv_remove,
dd9048af	543	.shutdown = usb_hcd_platform_shutdown,
3ae5eaec RK	544	.driver = {
3ae5eaec RK	545	.name = "pxa27x-ohci",
f4fce61d	546	.owner = THIS_MODULE,
b7f3f59b MR	547	#ifdef CONFIG_PM
	548	.pm = &ohci_hcd_pxa27x_pm_ops,
	549	#endif
3ae5eaec	550	},
1da177e4 LT	551	};
1da177e4 LT	552