Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
16 | * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu | |
17 | * | |
18 | * Intel documents this fairly well, and as far as I know there | |
19 | * are no royalties or anything like that, but even so there are | |
20 | * people who decided that they want to do the same thing in a | |
21 | * completely different way. | |
22 | * | |
23 | * WARNING! The USB documentation is downright evil. Most of it | |
24 | * is just crap, written by a committee. You're better off ignoring | |
25 | * most of it, the important stuff is: | |
26 | * - the low-level protocol (fairly simple but lots of small details) | |
27 | * - working around the horridness of the rest | |
28 | */ | |
29 | ||
30 | #include <linux/config.h> | |
31 | #ifdef CONFIG_USB_DEBUG | |
32 | #define DEBUG | |
33 | #else | |
34 | #undef DEBUG | |
35 | #endif | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/kernel.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/sched.h> | |
43 | #include <linux/slab.h> | |
44 | #include <linux/smp_lock.h> | |
45 | #include <linux/errno.h> | |
46 | #include <linux/unistd.h> | |
47 | #include <linux/interrupt.h> | |
48 | #include <linux/spinlock.h> | |
49 | #include <linux/debugfs.h> | |
50 | #include <linux/pm.h> | |
51 | #include <linux/dmapool.h> | |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/usb.h> | |
54 | #include <linux/bitops.h> | |
55 | ||
56 | #include <asm/uaccess.h> | |
57 | #include <asm/io.h> | |
58 | #include <asm/irq.h> | |
59 | #include <asm/system.h> | |
60 | ||
61 | #include "../core/hcd.h" | |
62 | #include "uhci-hcd.h" | |
63 | ||
64 | /* | |
65 | * Version Information | |
66 | */ | |
c8f4fe43 | 67 | #define DRIVER_VERSION "v2.3" |
1da177e4 LT |
68 | #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ |
69 | Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ | |
70 | Alan Stern" | |
71 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" | |
72 | ||
73 | /* | |
74 | * debug = 0, no debugging messages | |
75 | * debug = 1, dump failed URB's except for stalls | |
76 | * debug = 2, dump all failed URB's (including stalls) | |
77 | * show all queues in /debug/uhci/[pci_addr] | |
78 | * debug = 3, show all TD's in URB's when dumping | |
79 | */ | |
80 | #ifdef DEBUG | |
81 | static int debug = 1; | |
82 | #else | |
83 | static int debug = 0; | |
84 | #endif | |
85 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
86 | MODULE_PARM_DESC(debug, "Debug level"); | |
87 | static char *errbuf; | |
88 | #define ERRBUF_LEN (32 * 1024) | |
89 | ||
90 | static kmem_cache_t *uhci_up_cachep; /* urb_priv */ | |
91 | ||
92 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); | |
1da177e4 LT |
93 | |
94 | /* If a transfer is still active after this much time, turn off FSBR */ | |
95 | #define IDLE_TIMEOUT msecs_to_jiffies(50) | |
96 | #define FSBR_DELAY msecs_to_jiffies(50) | |
97 | ||
98 | /* When we timeout an idle transfer for FSBR, we'll switch it over to */ | |
99 | /* depth first traversal. We'll do it in groups of this number of TD's */ | |
100 | /* to make sure it doesn't hog all of the bandwidth */ | |
101 | #define DEPTH_INTERVAL 5 | |
102 | ||
f5946f82 AS |
103 | static inline void restart_timer(struct uhci_hcd *uhci) |
104 | { | |
105 | mod_timer(&uhci->stall_timer, jiffies + msecs_to_jiffies(100)); | |
106 | } | |
107 | ||
1da177e4 LT |
108 | #include "uhci-hub.c" |
109 | #include "uhci-debug.c" | |
110 | #include "uhci-q.c" | |
111 | ||
a8bed8b6 AS |
112 | /* |
113 | * Make sure the controller is completely inactive, unable to | |
114 | * generate interrupts or do DMA. | |
115 | */ | |
1da177e4 LT |
116 | static void reset_hc(struct uhci_hcd *uhci) |
117 | { | |
a8bed8b6 AS |
118 | /* Turn off PIRQ enable and SMI enable. (This also turns off the |
119 | * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. | |
120 | */ | |
121 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
122 | USBLEGSUP_RWC); | |
1da177e4 | 123 | |
a8bed8b6 AS |
124 | /* Reset the HC - this will force us to get a |
125 | * new notification of any already connected | |
126 | * ports due to the virtual disconnect that it | |
127 | * implies. | |
1da177e4 | 128 | */ |
a8bed8b6 AS |
129 | outw(USBCMD_HCRESET, uhci->io_addr + USBCMD); |
130 | mb(); | |
131 | udelay(5); | |
132 | if (inw(uhci->io_addr + USBCMD) & USBCMD_HCRESET) | |
133 | dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); | |
1da177e4 | 134 | |
a8bed8b6 AS |
135 | /* Just to be safe, disable interrupt requests and |
136 | * make sure the controller is stopped. | |
137 | */ | |
138 | outw(0, uhci->io_addr + USBINTR); | |
139 | outw(0, uhci->io_addr + USBCMD); | |
1da177e4 | 140 | |
1da177e4 | 141 | uhci->resume_detect = 0; |
a8bed8b6 AS |
142 | uhci->port_c_suspend = uhci->suspended_ports = |
143 | uhci->resuming_ports = 0; | |
c8f4fe43 | 144 | uhci->rh_state = UHCI_RH_RESET; |
a8bed8b6 AS |
145 | uhci->is_stopped = UHCI_IS_STOPPED; |
146 | uhci_to_hcd(uhci)->state = HC_STATE_HALT; | |
1da177e4 LT |
147 | } |
148 | ||
a8bed8b6 AS |
149 | /* |
150 | * Initialize a controller that was newly discovered or has just been | |
151 | * resumed. In either case we can't be sure of its previous state. | |
152 | */ | |
153 | static void check_and_reset_hc(struct uhci_hcd *uhci) | |
154 | { | |
155 | u16 legsup; | |
156 | unsigned int cmd, intr; | |
157 | ||
158 | /* | |
159 | * When restarting a suspended controller, we expect all the | |
160 | * settings to be the same as we left them: | |
161 | * | |
162 | * PIRQ and SMI disabled, no R/WC bits set in USBLEGSUP; | |
163 | * Controller is stopped and configured with EGSM set; | |
164 | * No interrupts enabled except possibly Resume Detect. | |
165 | * | |
166 | * If any of these conditions are violated we do a complete reset. | |
167 | */ | |
168 | pci_read_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, &legsup); | |
169 | if (legsup & ~USBLEGSUP_RO) { | |
170 | dev_dbg(uhci_dev(uhci), "%s: legsup = 0x%04x\n", | |
171 | __FUNCTION__, legsup); | |
172 | goto reset_needed; | |
173 | } | |
174 | ||
175 | cmd = inw(uhci->io_addr + USBCMD); | |
176 | if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { | |
177 | dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", | |
178 | __FUNCTION__, cmd); | |
179 | goto reset_needed; | |
180 | } | |
181 | ||
182 | intr = inw(uhci->io_addr + USBINTR); | |
183 | if (intr & (~USBINTR_RESUME)) { | |
184 | dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", | |
185 | __FUNCTION__, intr); | |
186 | goto reset_needed; | |
187 | } | |
188 | return; | |
189 | ||
190 | reset_needed: | |
191 | dev_dbg(uhci_dev(uhci), "Performing full reset\n"); | |
192 | reset_hc(uhci); | |
193 | } | |
194 | ||
195 | /* | |
196 | * Store the basic register settings needed by the controller. | |
197 | */ | |
198 | static void configure_hc(struct uhci_hcd *uhci) | |
199 | { | |
200 | /* Set the frame length to the default: 1 ms exactly */ | |
201 | outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); | |
202 | ||
203 | /* Store the frame list base address */ | |
204 | outl(uhci->fl->dma_handle, uhci->io_addr + USBFLBASEADD); | |
205 | ||
206 | /* Set the current frame number */ | |
207 | outw(uhci->frame_number, uhci->io_addr + USBFRNUM); | |
208 | ||
209 | /* Mark controller as running before we enable interrupts */ | |
210 | uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; | |
211 | mb(); | |
212 | ||
213 | /* Enable PIRQ */ | |
214 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
215 | USBLEGSUP_DEFAULT); | |
216 | } | |
217 | ||
218 | ||
c8f4fe43 | 219 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
1da177e4 | 220 | { |
c8f4fe43 | 221 | int port; |
1da177e4 | 222 | |
c8f4fe43 AS |
223 | switch (to_pci_dev(uhci_dev(uhci))->vendor) { |
224 | default: | |
225 | break; | |
226 | ||
227 | case PCI_VENDOR_ID_GENESYS: | |
228 | /* Genesys Logic's GL880S controllers don't generate | |
229 | * resume-detect interrupts. | |
230 | */ | |
231 | return 1; | |
232 | ||
233 | case PCI_VENDOR_ID_INTEL: | |
234 | /* Some of Intel's USB controllers have a bug that causes | |
235 | * resume-detect interrupts if any port has an over-current | |
236 | * condition. To make matters worse, some motherboards | |
237 | * hardwire unused USB ports' over-current inputs active! | |
238 | * To prevent problems, we will not enable resume-detect | |
239 | * interrupts if any ports are OC. | |
240 | */ | |
241 | for (port = 0; port < uhci->rh_numports; ++port) { | |
242 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | |
243 | USBPORTSC_OC) | |
244 | return 1; | |
245 | } | |
246 | break; | |
247 | } | |
248 | return 0; | |
249 | } | |
250 | ||
a8bed8b6 | 251 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
c8f4fe43 AS |
252 | __releases(uhci->lock) |
253 | __acquires(uhci->lock) | |
254 | { | |
255 | int auto_stop; | |
256 | int int_enable; | |
257 | ||
258 | auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); | |
259 | dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__, | |
260 | (auto_stop ? " (auto-stop)" : "")); | |
261 | ||
262 | /* If we get a suspend request when we're already auto-stopped | |
263 | * then there's nothing to do. | |
264 | */ | |
265 | if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) { | |
266 | uhci->rh_state = new_state; | |
267 | return; | |
268 | } | |
269 | ||
270 | /* Enable resume-detect interrupts if they work. | |
271 | * Then enter Global Suspend mode, still configured. | |
272 | */ | |
273 | int_enable = (resume_detect_interrupts_are_broken(uhci) ? | |
274 | 0 : USBINTR_RESUME); | |
275 | outw(int_enable, uhci->io_addr + USBINTR); | |
276 | outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 277 | mb(); |
c8f4fe43 AS |
278 | udelay(5); |
279 | ||
280 | /* If we're auto-stopping then no devices have been attached | |
281 | * for a while, so there shouldn't be any active URBs and the | |
282 | * controller should stop after a few microseconds. Otherwise | |
283 | * we will give the controller one frame to stop. | |
284 | */ | |
285 | if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { | |
286 | uhci->rh_state = UHCI_RH_SUSPENDING; | |
287 | spin_unlock_irq(&uhci->lock); | |
288 | msleep(1); | |
289 | spin_lock_irq(&uhci->lock); | |
290 | } | |
291 | if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) | |
292 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); | |
1da177e4 | 293 | |
1da177e4 | 294 | uhci_get_current_frame_number(uhci); |
c8f4fe43 AS |
295 | smp_wmb(); |
296 | ||
297 | uhci->rh_state = new_state; | |
1da177e4 | 298 | uhci->is_stopped = UHCI_IS_STOPPED; |
c8f4fe43 | 299 | uhci->resume_detect = 0; |
1da177e4 LT |
300 | |
301 | uhci_scan_schedule(uhci, NULL); | |
302 | } | |
303 | ||
a8bed8b6 AS |
304 | static void start_rh(struct uhci_hcd *uhci) |
305 | { | |
306 | uhci->rh_state = UHCI_RH_RUNNING; | |
307 | uhci->is_stopped = 0; | |
308 | smp_wmb(); | |
309 | ||
310 | /* Mark it configured and running with a 64-byte max packet. | |
311 | * All interrupts are enabled, even though RESUME won't do anything. | |
312 | */ | |
313 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); | |
314 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | |
315 | uhci->io_addr + USBINTR); | |
316 | mb(); | |
317 | } | |
318 | ||
319 | static void wakeup_rh(struct uhci_hcd *uhci) | |
c8f4fe43 AS |
320 | __releases(uhci->lock) |
321 | __acquires(uhci->lock) | |
1da177e4 | 322 | { |
c8f4fe43 AS |
323 | dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__, |
324 | uhci->rh_state == UHCI_RH_AUTO_STOPPED ? | |
325 | " (auto-start)" : ""); | |
1da177e4 | 326 | |
c8f4fe43 AS |
327 | /* If we are auto-stopped then no devices are attached so there's |
328 | * no need for wakeup signals. Otherwise we send Global Resume | |
329 | * for 20 ms. | |
330 | */ | |
331 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
332 | uhci->rh_state = UHCI_RH_RESUMING; | |
333 | outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF, | |
334 | uhci->io_addr + USBCMD); | |
335 | spin_unlock_irq(&uhci->lock); | |
336 | msleep(20); | |
337 | spin_lock_irq(&uhci->lock); | |
1da177e4 | 338 | |
c8f4fe43 AS |
339 | /* End Global Resume and wait for EOP to be sent */ |
340 | outw(USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 341 | mb(); |
c8f4fe43 AS |
342 | udelay(4); |
343 | if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) | |
344 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); | |
345 | } | |
1da177e4 | 346 | |
a8bed8b6 | 347 | start_rh(uhci); |
1da177e4 LT |
348 | } |
349 | ||
c8f4fe43 | 350 | static void rh_state_transitions(struct uhci_hcd *uhci) |
1da177e4 | 351 | { |
c8f4fe43 AS |
352 | switch (uhci->rh_state) { |
353 | case UHCI_RH_RUNNING: | |
354 | /* are any devices attached? */ | |
355 | if (!any_ports_active(uhci)) { | |
356 | uhci->rh_state = UHCI_RH_RUNNING_NODEVS; | |
357 | uhci->auto_stop_time = jiffies + HZ; | |
358 | } | |
359 | break; | |
360 | ||
361 | case UHCI_RH_RUNNING_NODEVS: | |
362 | /* auto-stop if nothing connected for 1 second */ | |
363 | if (any_ports_active(uhci)) | |
364 | uhci->rh_state = UHCI_RH_RUNNING; | |
365 | else if (time_after_eq(jiffies, uhci->auto_stop_time)) | |
a8bed8b6 | 366 | suspend_rh(uhci, UHCI_RH_AUTO_STOPPED); |
c8f4fe43 AS |
367 | break; |
368 | ||
369 | case UHCI_RH_AUTO_STOPPED: | |
370 | /* wakeup if requested by a device */ | |
371 | if (uhci->resume_detect) | |
a8bed8b6 | 372 | wakeup_rh(uhci); |
c8f4fe43 AS |
373 | break; |
374 | ||
375 | default: | |
376 | break; | |
1da177e4 LT |
377 | } |
378 | } | |
379 | ||
f5946f82 | 380 | static void stall_callback(unsigned long _uhci) |
1da177e4 | 381 | { |
f5946f82 | 382 | struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci; |
014e73c9 AS |
383 | unsigned long flags; |
384 | ||
385 | spin_lock_irqsave(&uhci->lock, flags); | |
386 | uhci_scan_schedule(uhci, NULL); | |
f5946f82 | 387 | check_fsbr(uhci); |
014e73c9 AS |
388 | |
389 | /* Poll for and perform state transitions */ | |
c8f4fe43 | 390 | rh_state_transitions(uhci); |
a8bed8b6 | 391 | if (uhci->suspended_ports && !uhci->hc_inaccessible) |
014e73c9 AS |
392 | uhci_check_ports(uhci); |
393 | ||
f5946f82 | 394 | restart_timer(uhci); |
014e73c9 | 395 | spin_unlock_irqrestore(&uhci->lock, flags); |
1da177e4 LT |
396 | } |
397 | ||
014e73c9 AS |
398 | static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs) |
399 | { | |
400 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
014e73c9 | 401 | unsigned short status; |
1da177e4 LT |
402 | |
403 | /* | |
014e73c9 AS |
404 | * Read the interrupt status, and write it back to clear the |
405 | * interrupt cause. Contrary to the UHCI specification, the | |
406 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 407 | */ |
a8bed8b6 | 408 | status = inw(uhci->io_addr + USBSTS); |
014e73c9 AS |
409 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
410 | return IRQ_NONE; | |
a8bed8b6 | 411 | outw(status, uhci->io_addr + USBSTS); /* Clear it */ |
014e73c9 AS |
412 | |
413 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | |
414 | if (status & USBSTS_HSE) | |
415 | dev_err(uhci_dev(uhci), "host system error, " | |
416 | "PCI problems?\n"); | |
417 | if (status & USBSTS_HCPE) | |
418 | dev_err(uhci_dev(uhci), "host controller process " | |
419 | "error, something bad happened!\n"); | |
c8f4fe43 AS |
420 | if ((status & USBSTS_HCH) && |
421 | uhci->rh_state >= UHCI_RH_RUNNING) { | |
014e73c9 AS |
422 | dev_err(uhci_dev(uhci), "host controller halted, " |
423 | "very bad!\n"); | |
424 | /* FIXME: Reset the controller, fix the offending TD */ | |
1da177e4 | 425 | } |
1da177e4 LT |
426 | } |
427 | ||
014e73c9 AS |
428 | if (status & USBSTS_RD) |
429 | uhci->resume_detect = 1; | |
1da177e4 | 430 | |
014e73c9 AS |
431 | spin_lock(&uhci->lock); |
432 | uhci_scan_schedule(uhci, regs); | |
433 | spin_unlock(&uhci->lock); | |
1da177e4 | 434 | |
014e73c9 AS |
435 | return IRQ_HANDLED; |
436 | } | |
1da177e4 | 437 | |
014e73c9 AS |
438 | /* |
439 | * Store the current frame number in uhci->frame_number if the controller | |
440 | * is runnning | |
441 | */ | |
442 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
443 | { | |
444 | if (!uhci->is_stopped) | |
445 | uhci->frame_number = inw(uhci->io_addr + USBFRNUM); | |
1da177e4 LT |
446 | } |
447 | ||
448 | /* | |
449 | * De-allocate all resources | |
450 | */ | |
451 | static void release_uhci(struct uhci_hcd *uhci) | |
452 | { | |
453 | int i; | |
454 | ||
455 | for (i = 0; i < UHCI_NUM_SKELQH; i++) | |
456 | if (uhci->skelqh[i]) { | |
457 | uhci_free_qh(uhci, uhci->skelqh[i]); | |
458 | uhci->skelqh[i] = NULL; | |
459 | } | |
460 | ||
461 | if (uhci->term_td) { | |
462 | uhci_free_td(uhci, uhci->term_td); | |
463 | uhci->term_td = NULL; | |
464 | } | |
465 | ||
466 | if (uhci->qh_pool) { | |
467 | dma_pool_destroy(uhci->qh_pool); | |
468 | uhci->qh_pool = NULL; | |
469 | } | |
470 | ||
471 | if (uhci->td_pool) { | |
472 | dma_pool_destroy(uhci->td_pool); | |
473 | uhci->td_pool = NULL; | |
474 | } | |
475 | ||
476 | if (uhci->fl) { | |
477 | dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), | |
478 | uhci->fl, uhci->fl->dma_handle); | |
479 | uhci->fl = NULL; | |
480 | } | |
481 | ||
482 | if (uhci->dentry) { | |
483 | debugfs_remove(uhci->dentry); | |
484 | uhci->dentry = NULL; | |
485 | } | |
486 | } | |
487 | ||
488 | static int uhci_reset(struct usb_hcd *hcd) | |
489 | { | |
490 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
491 | ||
492 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | |
493 | ||
a8bed8b6 AS |
494 | /* Kick BIOS off this hardware and reset if the controller |
495 | * isn't already safely quiescent. | |
1da177e4 | 496 | */ |
a8bed8b6 | 497 | check_and_reset_hc(uhci); |
1da177e4 LT |
498 | return 0; |
499 | } | |
500 | ||
501 | /* | |
502 | * Allocate a frame list, and then setup the skeleton | |
503 | * | |
504 | * The hardware doesn't really know any difference | |
505 | * in the queues, but the order does matter for the | |
506 | * protocols higher up. The order is: | |
507 | * | |
508 | * - any isochronous events handled before any | |
509 | * of the queues. We don't do that here, because | |
510 | * we'll create the actual TD entries on demand. | |
511 | * - The first queue is the interrupt queue. | |
512 | * - The second queue is the control queue, split into low- and full-speed | |
513 | * - The third queue is bulk queue. | |
514 | * - The fourth queue is the bandwidth reclamation queue, which loops back | |
515 | * to the full-speed control queue. | |
516 | */ | |
517 | static int uhci_start(struct usb_hcd *hcd) | |
518 | { | |
519 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
520 | int retval = -EBUSY; | |
521 | int i, port; | |
522 | unsigned io_size; | |
523 | dma_addr_t dma_handle; | |
524 | struct usb_device *udev; | |
525 | struct dentry *dentry; | |
526 | ||
527 | io_size = (unsigned) hcd->rsrc_len; | |
528 | ||
529 | dentry = debugfs_create_file(hcd->self.bus_name, S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci, &uhci_debug_operations); | |
530 | if (!dentry) { | |
531 | dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); | |
532 | retval = -ENOMEM; | |
533 | goto err_create_debug_entry; | |
534 | } | |
535 | uhci->dentry = dentry; | |
536 | ||
537 | uhci->fsbr = 0; | |
538 | uhci->fsbrtimeout = 0; | |
539 | ||
540 | spin_lock_init(&uhci->lock); | |
541 | INIT_LIST_HEAD(&uhci->qh_remove_list); | |
542 | ||
543 | INIT_LIST_HEAD(&uhci->td_remove_list); | |
544 | ||
545 | INIT_LIST_HEAD(&uhci->urb_remove_list); | |
546 | ||
547 | INIT_LIST_HEAD(&uhci->urb_list); | |
548 | ||
549 | INIT_LIST_HEAD(&uhci->complete_list); | |
550 | ||
551 | init_waitqueue_head(&uhci->waitqh); | |
552 | ||
f5946f82 AS |
553 | init_timer(&uhci->stall_timer); |
554 | uhci->stall_timer.function = stall_callback; | |
555 | uhci->stall_timer.data = (unsigned long) uhci; | |
556 | ||
1da177e4 LT |
557 | uhci->fl = dma_alloc_coherent(uhci_dev(uhci), sizeof(*uhci->fl), |
558 | &dma_handle, 0); | |
559 | if (!uhci->fl) { | |
560 | dev_err(uhci_dev(uhci), "unable to allocate " | |
561 | "consistent memory for frame list\n"); | |
562 | goto err_alloc_fl; | |
563 | } | |
564 | ||
565 | memset((void *)uhci->fl, 0, sizeof(*uhci->fl)); | |
566 | ||
567 | uhci->fl->dma_handle = dma_handle; | |
568 | ||
569 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
570 | sizeof(struct uhci_td), 16, 0); | |
571 | if (!uhci->td_pool) { | |
572 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
573 | goto err_create_td_pool; | |
574 | } | |
575 | ||
576 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
577 | sizeof(struct uhci_qh), 16, 0); | |
578 | if (!uhci->qh_pool) { | |
579 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
580 | goto err_create_qh_pool; | |
581 | } | |
582 | ||
583 | /* Initialize the root hub */ | |
584 | ||
585 | /* UHCI specs says devices must have 2 ports, but goes on to say */ | |
586 | /* they may have more but give no way to determine how many they */ | |
587 | /* have. However, according to the UHCI spec, Bit 7 is always set */ | |
588 | /* to 1. So we try to use this to our advantage */ | |
589 | for (port = 0; port < (io_size - 0x10) / 2; port++) { | |
590 | unsigned int portstatus; | |
591 | ||
592 | portstatus = inw(uhci->io_addr + 0x10 + (port * 2)); | |
593 | if (!(portstatus & 0x0080)) | |
594 | break; | |
595 | } | |
596 | if (debug) | |
597 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
598 | ||
599 | /* This is experimental so anything less than 2 or greater than 8 is */ | |
600 | /* something weird and we'll ignore it */ | |
601 | if (port < 2 || port > UHCI_RH_MAXCHILD) { | |
602 | dev_info(uhci_dev(uhci), "port count misdetected? " | |
603 | "forcing to 2 ports\n"); | |
604 | port = 2; | |
605 | } | |
606 | ||
607 | uhci->rh_numports = port; | |
608 | ||
609 | udev = usb_alloc_dev(NULL, &hcd->self, 0); | |
610 | if (!udev) { | |
611 | dev_err(uhci_dev(uhci), "unable to allocate root hub\n"); | |
612 | goto err_alloc_root_hub; | |
613 | } | |
614 | ||
615 | uhci->term_td = uhci_alloc_td(uhci, udev); | |
616 | if (!uhci->term_td) { | |
617 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
618 | goto err_alloc_term_td; | |
619 | } | |
620 | ||
621 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
622 | uhci->skelqh[i] = uhci_alloc_qh(uhci, udev); | |
623 | if (!uhci->skelqh[i]) { | |
624 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
625 | goto err_alloc_skelqh; | |
626 | } | |
627 | } | |
628 | ||
629 | /* | |
630 | * 8 Interrupt queues; link all higher int queues to int1, | |
631 | * then link int1 to control and control to bulk | |
632 | */ | |
633 | uhci->skel_int128_qh->link = | |
634 | uhci->skel_int64_qh->link = | |
635 | uhci->skel_int32_qh->link = | |
636 | uhci->skel_int16_qh->link = | |
637 | uhci->skel_int8_qh->link = | |
638 | uhci->skel_int4_qh->link = | |
639 | uhci->skel_int2_qh->link = | |
640 | cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH; | |
641 | uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH; | |
642 | ||
643 | uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH; | |
644 | uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH; | |
645 | uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH; | |
646 | ||
647 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
648 | uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) | | |
649 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); | |
650 | uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle); | |
651 | ||
652 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
653 | uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle); | |
654 | ||
655 | /* | |
656 | * Fill the frame list: make all entries point to the proper | |
657 | * interrupt queue. | |
658 | * | |
659 | * The interrupt queues will be interleaved as evenly as possible. | |
660 | * There's not much to be done about period-1 interrupts; they have | |
661 | * to occur in every frame. But we can schedule period-2 interrupts | |
662 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
663 | * to 2 (mod 4), and so on. This way each frame only has two | |
664 | * interrupt QHs, which will help spread out bandwidth utilization. | |
665 | */ | |
666 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
667 | int irq; | |
668 | ||
669 | /* | |
670 | * ffs (Find First bit Set) does exactly what we need: | |
671 | * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[6], | |
672 | * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc. | |
673 | * ffs > 6 => not on any high-period queue, so use | |
674 | * skel_int1_qh = skelqh[7]. | |
675 | * Add UHCI_NUMFRAMES to insure at least one bit is set. | |
676 | */ | |
677 | irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES); | |
678 | if (irq < 0) | |
679 | irq = 7; | |
680 | ||
681 | /* Only place we don't use the frame list routines */ | |
682 | uhci->fl->frame[i] = UHCI_PTR_QH | | |
683 | cpu_to_le32(uhci->skelqh[irq]->dma_handle); | |
684 | } | |
685 | ||
686 | /* | |
687 | * Some architectures require a full mb() to enforce completion of | |
a8bed8b6 | 688 | * the memory writes above before the I/O transfers in configure_hc(). |
1da177e4 LT |
689 | */ |
690 | mb(); | |
a8bed8b6 AS |
691 | |
692 | configure_hc(uhci); | |
693 | start_rh(uhci); | |
1da177e4 | 694 | |
f5946f82 | 695 | restart_timer(uhci); |
1da177e4 LT |
696 | |
697 | udev->speed = USB_SPEED_FULL; | |
698 | ||
699 | if (usb_hcd_register_root_hub(udev, hcd) != 0) { | |
700 | dev_err(uhci_dev(uhci), "unable to start root hub\n"); | |
701 | retval = -ENOMEM; | |
702 | goto err_start_root_hub; | |
703 | } | |
704 | ||
705 | return 0; | |
706 | ||
707 | /* | |
708 | * error exits: | |
709 | */ | |
710 | err_start_root_hub: | |
1da177e4 | 711 | del_timer_sync(&uhci->stall_timer); |
a8bed8b6 | 712 | reset_hc(uhci); |
1da177e4 LT |
713 | |
714 | err_alloc_skelqh: | |
715 | for (i = 0; i < UHCI_NUM_SKELQH; i++) | |
716 | if (uhci->skelqh[i]) { | |
717 | uhci_free_qh(uhci, uhci->skelqh[i]); | |
718 | uhci->skelqh[i] = NULL; | |
719 | } | |
720 | ||
721 | uhci_free_td(uhci, uhci->term_td); | |
722 | uhci->term_td = NULL; | |
723 | ||
724 | err_alloc_term_td: | |
725 | usb_put_dev(udev); | |
726 | ||
727 | err_alloc_root_hub: | |
728 | dma_pool_destroy(uhci->qh_pool); | |
729 | uhci->qh_pool = NULL; | |
730 | ||
731 | err_create_qh_pool: | |
732 | dma_pool_destroy(uhci->td_pool); | |
733 | uhci->td_pool = NULL; | |
734 | ||
735 | err_create_td_pool: | |
736 | dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), | |
737 | uhci->fl, uhci->fl->dma_handle); | |
738 | uhci->fl = NULL; | |
739 | ||
740 | err_alloc_fl: | |
741 | debugfs_remove(uhci->dentry); | |
742 | uhci->dentry = NULL; | |
743 | ||
744 | err_create_debug_entry: | |
745 | return retval; | |
746 | } | |
747 | ||
748 | static void uhci_stop(struct usb_hcd *hcd) | |
749 | { | |
750 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
751 | ||
752 | del_timer_sync(&uhci->stall_timer); | |
1da177e4 LT |
753 | |
754 | spin_lock_irq(&uhci->lock); | |
a8bed8b6 | 755 | reset_hc(uhci); |
1da177e4 LT |
756 | uhci_scan_schedule(uhci, NULL); |
757 | spin_unlock_irq(&uhci->lock); | |
758 | ||
759 | release_uhci(uhci); | |
760 | } | |
761 | ||
762 | #ifdef CONFIG_PM | |
a8bed8b6 AS |
763 | static int uhci_rh_suspend(struct usb_hcd *hcd) |
764 | { | |
765 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
766 | ||
767 | spin_lock_irq(&uhci->lock); | |
768 | suspend_rh(uhci, UHCI_RH_SUSPENDED); | |
769 | spin_unlock_irq(&uhci->lock); | |
770 | return 0; | |
771 | } | |
772 | ||
773 | static int uhci_rh_resume(struct usb_hcd *hcd) | |
774 | { | |
775 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
776 | ||
777 | spin_lock_irq(&uhci->lock); | |
778 | wakeup_rh(uhci); | |
779 | spin_unlock_irq(&uhci->lock); | |
780 | return 0; | |
781 | } | |
782 | ||
9a5d3e98 | 783 | static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message) |
1da177e4 LT |
784 | { |
785 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
786 | ||
a8bed8b6 AS |
787 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
788 | ||
1da177e4 | 789 | spin_lock_irq(&uhci->lock); |
a8bed8b6 AS |
790 | |
791 | #ifndef CONFIG_USB_SUSPEND | |
792 | /* Otherwise this would never happen */ | |
793 | suspend_rh(uhci, UHCI_RH_SUSPENDED); | |
794 | #endif | |
795 | ||
796 | /* All PCI host controllers are required to disable IRQ generation | |
797 | * at the source, so we must turn off PIRQ. | |
798 | */ | |
799 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0); | |
800 | uhci->hc_inaccessible = 1; | |
801 | ||
802 | /* FIXME: Enable non-PME# remote wakeup? */ | |
803 | ||
1da177e4 LT |
804 | spin_unlock_irq(&uhci->lock); |
805 | return 0; | |
806 | } | |
807 | ||
808 | static int uhci_resume(struct usb_hcd *hcd) | |
809 | { | |
810 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 811 | |
a8bed8b6 AS |
812 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
813 | ||
1da177e4 | 814 | spin_lock_irq(&uhci->lock); |
1da177e4 | 815 | |
a8bed8b6 AS |
816 | /* FIXME: Disable non-PME# remote wakeup? */ |
817 | ||
818 | uhci->hc_inaccessible = 0; | |
819 | ||
820 | /* The BIOS may have changed the controller settings during a | |
821 | * system wakeup. Check it and reconfigure to avoid problems. | |
822 | */ | |
823 | check_and_reset_hc(uhci); | |
824 | configure_hc(uhci); | |
825 | ||
826 | #ifndef CONFIG_USB_SUSPEND | |
827 | /* Otherwise this would never happen */ | |
828 | wakeup_rh(uhci); | |
829 | #endif | |
830 | if (uhci->rh_state == UHCI_RH_RESET) | |
831 | suspend_rh(uhci, UHCI_RH_SUSPENDED); | |
c8f4fe43 | 832 | |
a8bed8b6 | 833 | spin_unlock_irq(&uhci->lock); |
1da177e4 LT |
834 | return 0; |
835 | } | |
836 | #endif | |
837 | ||
838 | /* Wait until all the URBs for a particular device/endpoint are gone */ | |
839 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, | |
840 | struct usb_host_endpoint *ep) | |
841 | { | |
842 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
843 | ||
844 | wait_event_interruptible(uhci->waitqh, list_empty(&ep->urb_list)); | |
845 | } | |
846 | ||
847 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
848 | { | |
849 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 850 | unsigned long flags; |
c8f4fe43 AS |
851 | int is_stopped; |
852 | int frame_number; | |
1da177e4 LT |
853 | |
854 | /* Minimize latency by avoiding the spinlock */ | |
855 | local_irq_save(flags); | |
c8f4fe43 AS |
856 | is_stopped = uhci->is_stopped; |
857 | smp_rmb(); | |
858 | frame_number = (is_stopped ? uhci->frame_number : | |
1da177e4 LT |
859 | inw(uhci->io_addr + USBFRNUM)); |
860 | local_irq_restore(flags); | |
861 | return frame_number; | |
862 | } | |
863 | ||
864 | static const char hcd_name[] = "uhci_hcd"; | |
865 | ||
866 | static const struct hc_driver uhci_driver = { | |
867 | .description = hcd_name, | |
868 | .product_desc = "UHCI Host Controller", | |
869 | .hcd_priv_size = sizeof(struct uhci_hcd), | |
870 | ||
871 | /* Generic hardware linkage */ | |
872 | .irq = uhci_irq, | |
873 | .flags = HCD_USB11, | |
874 | ||
875 | /* Basic lifecycle operations */ | |
876 | .reset = uhci_reset, | |
877 | .start = uhci_start, | |
878 | #ifdef CONFIG_PM | |
879 | .suspend = uhci_suspend, | |
880 | .resume = uhci_resume, | |
a8bed8b6 AS |
881 | .hub_suspend = uhci_rh_suspend, |
882 | .hub_resume = uhci_rh_resume, | |
1da177e4 LT |
883 | #endif |
884 | .stop = uhci_stop, | |
885 | ||
886 | .urb_enqueue = uhci_urb_enqueue, | |
887 | .urb_dequeue = uhci_urb_dequeue, | |
888 | ||
889 | .endpoint_disable = uhci_hcd_endpoint_disable, | |
890 | .get_frame_number = uhci_hcd_get_frame_number, | |
891 | ||
892 | .hub_status_data = uhci_hub_status_data, | |
893 | .hub_control = uhci_hub_control, | |
894 | }; | |
895 | ||
896 | static const struct pci_device_id uhci_pci_ids[] = { { | |
897 | /* handle any USB UHCI controller */ | |
898 | PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0), | |
899 | .driver_data = (unsigned long) &uhci_driver, | |
900 | }, { /* end: all zeroes */ } | |
901 | }; | |
902 | ||
903 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | |
904 | ||
905 | static struct pci_driver uhci_pci_driver = { | |
906 | .name = (char *)hcd_name, | |
907 | .id_table = uhci_pci_ids, | |
908 | ||
909 | .probe = usb_hcd_pci_probe, | |
910 | .remove = usb_hcd_pci_remove, | |
911 | ||
912 | #ifdef CONFIG_PM | |
913 | .suspend = usb_hcd_pci_suspend, | |
914 | .resume = usb_hcd_pci_resume, | |
915 | #endif /* PM */ | |
916 | }; | |
917 | ||
918 | static int __init uhci_hcd_init(void) | |
919 | { | |
920 | int retval = -ENOMEM; | |
921 | ||
922 | printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n"); | |
923 | ||
924 | if (usb_disabled()) | |
925 | return -ENODEV; | |
926 | ||
927 | if (debug) { | |
928 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); | |
929 | if (!errbuf) | |
930 | goto errbuf_failed; | |
931 | } | |
932 | ||
933 | uhci_debugfs_root = debugfs_create_dir("uhci", NULL); | |
934 | if (!uhci_debugfs_root) | |
935 | goto debug_failed; | |
936 | ||
937 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", | |
938 | sizeof(struct urb_priv), 0, 0, NULL, NULL); | |
939 | if (!uhci_up_cachep) | |
940 | goto up_failed; | |
941 | ||
942 | retval = pci_register_driver(&uhci_pci_driver); | |
943 | if (retval) | |
944 | goto init_failed; | |
945 | ||
946 | return 0; | |
947 | ||
948 | init_failed: | |
949 | if (kmem_cache_destroy(uhci_up_cachep)) | |
950 | warn("not all urb_priv's were freed!"); | |
951 | ||
952 | up_failed: | |
953 | debugfs_remove(uhci_debugfs_root); | |
954 | ||
955 | debug_failed: | |
1bc3c9e1 | 956 | kfree(errbuf); |
1da177e4 LT |
957 | |
958 | errbuf_failed: | |
959 | ||
960 | return retval; | |
961 | } | |
962 | ||
963 | static void __exit uhci_hcd_cleanup(void) | |
964 | { | |
965 | pci_unregister_driver(&uhci_pci_driver); | |
966 | ||
967 | if (kmem_cache_destroy(uhci_up_cachep)) | |
968 | warn("not all urb_priv's were freed!"); | |
969 | ||
970 | debugfs_remove(uhci_debugfs_root); | |
1bc3c9e1 | 971 | kfree(errbuf); |
1da177e4 LT |
972 | } |
973 | ||
974 | module_init(uhci_hcd_init); | |
975 | module_exit(uhci_hcd_cleanup); | |
976 | ||
977 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
978 | MODULE_DESCRIPTION(DRIVER_DESC); | |
979 | MODULE_LICENSE("GPL"); |