Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
4daaa87c | 16 | * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | * |
18 | * Intel documents this fairly well, and as far as I know there | |
19 | * are no royalties or anything like that, but even so there are | |
20 | * people who decided that they want to do the same thing in a | |
21 | * completely different way. | |
22 | * | |
1da177e4 LT |
23 | */ |
24 | ||
25 | #include <linux/config.h> | |
26 | #ifdef CONFIG_USB_DEBUG | |
27 | #define DEBUG | |
28 | #else | |
29 | #undef DEBUG | |
30 | #endif | |
31 | #include <linux/module.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/sched.h> | |
38 | #include <linux/slab.h> | |
39 | #include <linux/smp_lock.h> | |
40 | #include <linux/errno.h> | |
41 | #include <linux/unistd.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/spinlock.h> | |
44 | #include <linux/debugfs.h> | |
45 | #include <linux/pm.h> | |
46 | #include <linux/dmapool.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | #include <linux/usb.h> | |
49 | #include <linux/bitops.h> | |
50 | ||
51 | #include <asm/uaccess.h> | |
52 | #include <asm/io.h> | |
53 | #include <asm/irq.h> | |
54 | #include <asm/system.h> | |
55 | ||
56 | #include "../core/hcd.h" | |
57 | #include "uhci-hcd.h" | |
58 | ||
59 | /* | |
60 | * Version Information | |
61 | */ | |
c8f4fe43 | 62 | #define DRIVER_VERSION "v2.3" |
1da177e4 LT |
63 | #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ |
64 | Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ | |
65 | Alan Stern" | |
66 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" | |
67 | ||
68 | /* | |
69 | * debug = 0, no debugging messages | |
70 | * debug = 1, dump failed URB's except for stalls | |
71 | * debug = 2, dump all failed URB's (including stalls) | |
72 | * show all queues in /debug/uhci/[pci_addr] | |
73 | * debug = 3, show all TD's in URB's when dumping | |
74 | */ | |
75 | #ifdef DEBUG | |
76 | static int debug = 1; | |
77 | #else | |
78 | static int debug = 0; | |
79 | #endif | |
80 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
81 | MODULE_PARM_DESC(debug, "Debug level"); | |
82 | static char *errbuf; | |
83 | #define ERRBUF_LEN (32 * 1024) | |
84 | ||
85 | static kmem_cache_t *uhci_up_cachep; /* urb_priv */ | |
86 | ||
6c1b445c AS |
87 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); |
88 | static void wakeup_rh(struct uhci_hcd *uhci); | |
1da177e4 | 89 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); |
1da177e4 LT |
90 | |
91 | /* If a transfer is still active after this much time, turn off FSBR */ | |
92 | #define IDLE_TIMEOUT msecs_to_jiffies(50) | |
93 | #define FSBR_DELAY msecs_to_jiffies(50) | |
94 | ||
95 | /* When we timeout an idle transfer for FSBR, we'll switch it over to */ | |
96 | /* depth first traversal. We'll do it in groups of this number of TD's */ | |
97 | /* to make sure it doesn't hog all of the bandwidth */ | |
98 | #define DEPTH_INTERVAL 5 | |
99 | ||
f5946f82 AS |
100 | static inline void restart_timer(struct uhci_hcd *uhci) |
101 | { | |
102 | mod_timer(&uhci->stall_timer, jiffies + msecs_to_jiffies(100)); | |
103 | } | |
104 | ||
1da177e4 LT |
105 | #include "uhci-hub.c" |
106 | #include "uhci-debug.c" | |
107 | #include "uhci-q.c" | |
108 | ||
a8bed8b6 AS |
109 | /* |
110 | * Make sure the controller is completely inactive, unable to | |
111 | * generate interrupts or do DMA. | |
112 | */ | |
1da177e4 LT |
113 | static void reset_hc(struct uhci_hcd *uhci) |
114 | { | |
c074b416 AS |
115 | int port; |
116 | ||
a8bed8b6 AS |
117 | /* Turn off PIRQ enable and SMI enable. (This also turns off the |
118 | * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. | |
119 | */ | |
120 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
121 | USBLEGSUP_RWC); | |
1da177e4 | 122 | |
a8bed8b6 AS |
123 | /* Reset the HC - this will force us to get a |
124 | * new notification of any already connected | |
125 | * ports due to the virtual disconnect that it | |
126 | * implies. | |
1da177e4 | 127 | */ |
a8bed8b6 AS |
128 | outw(USBCMD_HCRESET, uhci->io_addr + USBCMD); |
129 | mb(); | |
130 | udelay(5); | |
131 | if (inw(uhci->io_addr + USBCMD) & USBCMD_HCRESET) | |
132 | dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); | |
1da177e4 | 133 | |
a8bed8b6 AS |
134 | /* Just to be safe, disable interrupt requests and |
135 | * make sure the controller is stopped. | |
136 | */ | |
137 | outw(0, uhci->io_addr + USBINTR); | |
138 | outw(0, uhci->io_addr + USBCMD); | |
1da177e4 | 139 | |
c074b416 AS |
140 | /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect |
141 | * bits in the port status and control registers. | |
142 | * We have to clear them by hand. | |
143 | */ | |
144 | for (port = 0; port < uhci->rh_numports; ++port) | |
145 | outw(0, uhci->io_addr + USBPORTSC1 + (port * 2)); | |
146 | ||
a8bed8b6 AS |
147 | uhci->port_c_suspend = uhci->suspended_ports = |
148 | uhci->resuming_ports = 0; | |
c8f4fe43 | 149 | uhci->rh_state = UHCI_RH_RESET; |
a8bed8b6 AS |
150 | uhci->is_stopped = UHCI_IS_STOPPED; |
151 | uhci_to_hcd(uhci)->state = HC_STATE_HALT; | |
6c1b445c | 152 | uhci_to_hcd(uhci)->poll_rh = 0; |
1da177e4 LT |
153 | } |
154 | ||
4daaa87c AS |
155 | /* |
156 | * Last rites for a defunct/nonfunctional controller | |
157 | */ | |
158 | static void hc_died(struct uhci_hcd *uhci) | |
159 | { | |
160 | reset_hc(uhci); | |
161 | uhci->hc_inaccessible = 1; | |
6c1b445c | 162 | del_timer(&uhci->stall_timer); |
4daaa87c AS |
163 | } |
164 | ||
a8bed8b6 AS |
165 | /* |
166 | * Initialize a controller that was newly discovered or has just been | |
167 | * resumed. In either case we can't be sure of its previous state. | |
168 | */ | |
169 | static void check_and_reset_hc(struct uhci_hcd *uhci) | |
170 | { | |
171 | u16 legsup; | |
172 | unsigned int cmd, intr; | |
173 | ||
174 | /* | |
175 | * When restarting a suspended controller, we expect all the | |
176 | * settings to be the same as we left them: | |
177 | * | |
c074b416 | 178 | * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; |
a8bed8b6 AS |
179 | * Controller is stopped and configured with EGSM set; |
180 | * No interrupts enabled except possibly Resume Detect. | |
181 | * | |
182 | * If any of these conditions are violated we do a complete reset. | |
183 | */ | |
184 | pci_read_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, &legsup); | |
c074b416 | 185 | if (legsup & ~(USBLEGSUP_RO | USBLEGSUP_RWC)) { |
a8bed8b6 AS |
186 | dev_dbg(uhci_dev(uhci), "%s: legsup = 0x%04x\n", |
187 | __FUNCTION__, legsup); | |
188 | goto reset_needed; | |
189 | } | |
190 | ||
191 | cmd = inw(uhci->io_addr + USBCMD); | |
192 | if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { | |
193 | dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", | |
194 | __FUNCTION__, cmd); | |
195 | goto reset_needed; | |
196 | } | |
197 | ||
198 | intr = inw(uhci->io_addr + USBINTR); | |
199 | if (intr & (~USBINTR_RESUME)) { | |
200 | dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", | |
201 | __FUNCTION__, intr); | |
202 | goto reset_needed; | |
203 | } | |
204 | return; | |
205 | ||
206 | reset_needed: | |
207 | dev_dbg(uhci_dev(uhci), "Performing full reset\n"); | |
208 | reset_hc(uhci); | |
209 | } | |
210 | ||
211 | /* | |
212 | * Store the basic register settings needed by the controller. | |
213 | */ | |
214 | static void configure_hc(struct uhci_hcd *uhci) | |
215 | { | |
216 | /* Set the frame length to the default: 1 ms exactly */ | |
217 | outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); | |
218 | ||
219 | /* Store the frame list base address */ | |
220 | outl(uhci->fl->dma_handle, uhci->io_addr + USBFLBASEADD); | |
221 | ||
222 | /* Set the current frame number */ | |
223 | outw(uhci->frame_number, uhci->io_addr + USBFRNUM); | |
224 | ||
225 | /* Mark controller as running before we enable interrupts */ | |
226 | uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; | |
227 | mb(); | |
228 | ||
229 | /* Enable PIRQ */ | |
230 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
231 | USBLEGSUP_DEFAULT); | |
232 | } | |
233 | ||
234 | ||
c8f4fe43 | 235 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
1da177e4 | 236 | { |
c8f4fe43 | 237 | int port; |
1da177e4 | 238 | |
c8f4fe43 AS |
239 | switch (to_pci_dev(uhci_dev(uhci))->vendor) { |
240 | default: | |
241 | break; | |
242 | ||
243 | case PCI_VENDOR_ID_GENESYS: | |
244 | /* Genesys Logic's GL880S controllers don't generate | |
245 | * resume-detect interrupts. | |
246 | */ | |
247 | return 1; | |
248 | ||
249 | case PCI_VENDOR_ID_INTEL: | |
250 | /* Some of Intel's USB controllers have a bug that causes | |
251 | * resume-detect interrupts if any port has an over-current | |
252 | * condition. To make matters worse, some motherboards | |
253 | * hardwire unused USB ports' over-current inputs active! | |
254 | * To prevent problems, we will not enable resume-detect | |
255 | * interrupts if any ports are OC. | |
256 | */ | |
257 | for (port = 0; port < uhci->rh_numports; ++port) { | |
258 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | |
259 | USBPORTSC_OC) | |
260 | return 1; | |
261 | } | |
262 | break; | |
263 | } | |
264 | return 0; | |
265 | } | |
266 | ||
a8bed8b6 | 267 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
c8f4fe43 AS |
268 | __releases(uhci->lock) |
269 | __acquires(uhci->lock) | |
270 | { | |
271 | int auto_stop; | |
272 | int int_enable; | |
273 | ||
274 | auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); | |
275 | dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__, | |
276 | (auto_stop ? " (auto-stop)" : "")); | |
277 | ||
278 | /* If we get a suspend request when we're already auto-stopped | |
279 | * then there's nothing to do. | |
280 | */ | |
281 | if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) { | |
282 | uhci->rh_state = new_state; | |
283 | return; | |
284 | } | |
285 | ||
286 | /* Enable resume-detect interrupts if they work. | |
287 | * Then enter Global Suspend mode, still configured. | |
288 | */ | |
289 | int_enable = (resume_detect_interrupts_are_broken(uhci) ? | |
290 | 0 : USBINTR_RESUME); | |
291 | outw(int_enable, uhci->io_addr + USBINTR); | |
292 | outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 293 | mb(); |
c8f4fe43 AS |
294 | udelay(5); |
295 | ||
296 | /* If we're auto-stopping then no devices have been attached | |
297 | * for a while, so there shouldn't be any active URBs and the | |
298 | * controller should stop after a few microseconds. Otherwise | |
299 | * we will give the controller one frame to stop. | |
300 | */ | |
301 | if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { | |
302 | uhci->rh_state = UHCI_RH_SUSPENDING; | |
303 | spin_unlock_irq(&uhci->lock); | |
304 | msleep(1); | |
305 | spin_lock_irq(&uhci->lock); | |
4daaa87c AS |
306 | if (uhci->hc_inaccessible) /* Died */ |
307 | return; | |
c8f4fe43 AS |
308 | } |
309 | if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) | |
310 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); | |
1da177e4 | 311 | |
1da177e4 | 312 | uhci_get_current_frame_number(uhci); |
c8f4fe43 AS |
313 | smp_wmb(); |
314 | ||
315 | uhci->rh_state = new_state; | |
1da177e4 | 316 | uhci->is_stopped = UHCI_IS_STOPPED; |
6c1b445c AS |
317 | del_timer(&uhci->stall_timer); |
318 | uhci_to_hcd(uhci)->poll_rh = !int_enable; | |
1da177e4 LT |
319 | |
320 | uhci_scan_schedule(uhci, NULL); | |
321 | } | |
322 | ||
a8bed8b6 AS |
323 | static void start_rh(struct uhci_hcd *uhci) |
324 | { | |
a8bed8b6 AS |
325 | uhci->is_stopped = 0; |
326 | smp_wmb(); | |
327 | ||
328 | /* Mark it configured and running with a 64-byte max packet. | |
329 | * All interrupts are enabled, even though RESUME won't do anything. | |
330 | */ | |
331 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); | |
332 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | |
333 | uhci->io_addr + USBINTR); | |
334 | mb(); | |
6c1b445c AS |
335 | uhci->rh_state = UHCI_RH_RUNNING; |
336 | uhci_to_hcd(uhci)->poll_rh = 1; | |
337 | restart_timer(uhci); | |
a8bed8b6 AS |
338 | } |
339 | ||
340 | static void wakeup_rh(struct uhci_hcd *uhci) | |
c8f4fe43 AS |
341 | __releases(uhci->lock) |
342 | __acquires(uhci->lock) | |
1da177e4 | 343 | { |
c8f4fe43 AS |
344 | dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__, |
345 | uhci->rh_state == UHCI_RH_AUTO_STOPPED ? | |
346 | " (auto-start)" : ""); | |
1da177e4 | 347 | |
c8f4fe43 AS |
348 | /* If we are auto-stopped then no devices are attached so there's |
349 | * no need for wakeup signals. Otherwise we send Global Resume | |
350 | * for 20 ms. | |
351 | */ | |
352 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
353 | uhci->rh_state = UHCI_RH_RESUMING; | |
354 | outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF, | |
355 | uhci->io_addr + USBCMD); | |
356 | spin_unlock_irq(&uhci->lock); | |
357 | msleep(20); | |
358 | spin_lock_irq(&uhci->lock); | |
4daaa87c AS |
359 | if (uhci->hc_inaccessible) /* Died */ |
360 | return; | |
1da177e4 | 361 | |
c8f4fe43 AS |
362 | /* End Global Resume and wait for EOP to be sent */ |
363 | outw(USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 364 | mb(); |
c8f4fe43 AS |
365 | udelay(4); |
366 | if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) | |
367 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); | |
368 | } | |
1da177e4 | 369 | |
a8bed8b6 | 370 | start_rh(uhci); |
c8f4fe43 | 371 | |
6c1b445c AS |
372 | /* Restart root hub polling */ |
373 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); | |
1da177e4 LT |
374 | } |
375 | ||
f5946f82 | 376 | static void stall_callback(unsigned long _uhci) |
1da177e4 | 377 | { |
f5946f82 | 378 | struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci; |
014e73c9 AS |
379 | unsigned long flags; |
380 | ||
381 | spin_lock_irqsave(&uhci->lock, flags); | |
382 | uhci_scan_schedule(uhci, NULL); | |
f5946f82 | 383 | check_fsbr(uhci); |
014e73c9 | 384 | |
6c1b445c AS |
385 | if (!uhci->is_stopped) |
386 | restart_timer(uhci); | |
014e73c9 | 387 | spin_unlock_irqrestore(&uhci->lock, flags); |
1da177e4 LT |
388 | } |
389 | ||
014e73c9 AS |
390 | static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs) |
391 | { | |
392 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
014e73c9 | 393 | unsigned short status; |
4daaa87c | 394 | unsigned long flags; |
1da177e4 LT |
395 | |
396 | /* | |
014e73c9 AS |
397 | * Read the interrupt status, and write it back to clear the |
398 | * interrupt cause. Contrary to the UHCI specification, the | |
399 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 400 | */ |
a8bed8b6 | 401 | status = inw(uhci->io_addr + USBSTS); |
014e73c9 AS |
402 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
403 | return IRQ_NONE; | |
a8bed8b6 | 404 | outw(status, uhci->io_addr + USBSTS); /* Clear it */ |
014e73c9 AS |
405 | |
406 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | |
407 | if (status & USBSTS_HSE) | |
408 | dev_err(uhci_dev(uhci), "host system error, " | |
409 | "PCI problems?\n"); | |
410 | if (status & USBSTS_HCPE) | |
411 | dev_err(uhci_dev(uhci), "host controller process " | |
412 | "error, something bad happened!\n"); | |
4daaa87c AS |
413 | if (status & USBSTS_HCH) { |
414 | spin_lock_irqsave(&uhci->lock, flags); | |
415 | if (uhci->rh_state >= UHCI_RH_RUNNING) { | |
416 | dev_err(uhci_dev(uhci), | |
417 | "host controller halted, " | |
014e73c9 | 418 | "very bad!\n"); |
4daaa87c AS |
419 | hc_died(uhci); |
420 | spin_unlock_irqrestore(&uhci->lock, flags); | |
421 | return IRQ_HANDLED; | |
422 | } | |
423 | spin_unlock_irqrestore(&uhci->lock, flags); | |
1da177e4 | 424 | } |
1da177e4 LT |
425 | } |
426 | ||
014e73c9 | 427 | if (status & USBSTS_RD) |
6c1b445c | 428 | usb_hcd_poll_rh_status(hcd); |
1da177e4 | 429 | |
4daaa87c | 430 | spin_lock_irqsave(&uhci->lock, flags); |
014e73c9 | 431 | uhci_scan_schedule(uhci, regs); |
4daaa87c | 432 | spin_unlock_irqrestore(&uhci->lock, flags); |
1da177e4 | 433 | |
014e73c9 AS |
434 | return IRQ_HANDLED; |
435 | } | |
1da177e4 | 436 | |
014e73c9 AS |
437 | /* |
438 | * Store the current frame number in uhci->frame_number if the controller | |
439 | * is runnning | |
440 | */ | |
441 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
442 | { | |
443 | if (!uhci->is_stopped) | |
444 | uhci->frame_number = inw(uhci->io_addr + USBFRNUM); | |
1da177e4 LT |
445 | } |
446 | ||
447 | /* | |
448 | * De-allocate all resources | |
449 | */ | |
450 | static void release_uhci(struct uhci_hcd *uhci) | |
451 | { | |
452 | int i; | |
453 | ||
454 | for (i = 0; i < UHCI_NUM_SKELQH; i++) | |
455 | if (uhci->skelqh[i]) { | |
456 | uhci_free_qh(uhci, uhci->skelqh[i]); | |
457 | uhci->skelqh[i] = NULL; | |
458 | } | |
459 | ||
460 | if (uhci->term_td) { | |
461 | uhci_free_td(uhci, uhci->term_td); | |
462 | uhci->term_td = NULL; | |
463 | } | |
464 | ||
465 | if (uhci->qh_pool) { | |
466 | dma_pool_destroy(uhci->qh_pool); | |
467 | uhci->qh_pool = NULL; | |
468 | } | |
469 | ||
470 | if (uhci->td_pool) { | |
471 | dma_pool_destroy(uhci->td_pool); | |
472 | uhci->td_pool = NULL; | |
473 | } | |
474 | ||
475 | if (uhci->fl) { | |
476 | dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), | |
477 | uhci->fl, uhci->fl->dma_handle); | |
478 | uhci->fl = NULL; | |
479 | } | |
480 | ||
481 | if (uhci->dentry) { | |
482 | debugfs_remove(uhci->dentry); | |
483 | uhci->dentry = NULL; | |
484 | } | |
485 | } | |
486 | ||
487 | static int uhci_reset(struct usb_hcd *hcd) | |
488 | { | |
489 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c074b416 AS |
490 | unsigned io_size = (unsigned) hcd->rsrc_len; |
491 | int port; | |
1da177e4 LT |
492 | |
493 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | |
494 | ||
c074b416 AS |
495 | /* The UHCI spec says devices must have 2 ports, and goes on to say |
496 | * they may have more but gives no way to determine how many there | |
497 | * are. However, according to the UHCI spec, Bit 7 of the port | |
498 | * status and control register is always set to 1. So we try to | |
499 | * use this to our advantage. | |
500 | */ | |
501 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | |
502 | unsigned int portstatus; | |
503 | ||
504 | portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2)); | |
505 | if (!(portstatus & 0x0080)) | |
506 | break; | |
507 | } | |
508 | if (debug) | |
509 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
510 | ||
511 | /* Anything less than 2 or greater than 7 is weird, | |
512 | * so we'll ignore it. | |
513 | */ | |
514 | if (port < 2 || port > UHCI_RH_MAXCHILD) { | |
515 | dev_info(uhci_dev(uhci), "port count misdetected? " | |
516 | "forcing to 2 ports\n"); | |
517 | port = 2; | |
518 | } | |
519 | uhci->rh_numports = port; | |
520 | ||
a8bed8b6 AS |
521 | /* Kick BIOS off this hardware and reset if the controller |
522 | * isn't already safely quiescent. | |
1da177e4 | 523 | */ |
a8bed8b6 | 524 | check_and_reset_hc(uhci); |
1da177e4 LT |
525 | return 0; |
526 | } | |
527 | ||
528 | /* | |
529 | * Allocate a frame list, and then setup the skeleton | |
530 | * | |
531 | * The hardware doesn't really know any difference | |
532 | * in the queues, but the order does matter for the | |
533 | * protocols higher up. The order is: | |
534 | * | |
535 | * - any isochronous events handled before any | |
536 | * of the queues. We don't do that here, because | |
537 | * we'll create the actual TD entries on demand. | |
538 | * - The first queue is the interrupt queue. | |
539 | * - The second queue is the control queue, split into low- and full-speed | |
540 | * - The third queue is bulk queue. | |
541 | * - The fourth queue is the bandwidth reclamation queue, which loops back | |
542 | * to the full-speed control queue. | |
543 | */ | |
544 | static int uhci_start(struct usb_hcd *hcd) | |
545 | { | |
546 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
547 | int retval = -EBUSY; | |
c074b416 | 548 | int i; |
1da177e4 LT |
549 | dma_addr_t dma_handle; |
550 | struct usb_device *udev; | |
551 | struct dentry *dentry; | |
552 | ||
6c1b445c | 553 | hcd->uses_new_polling = 1; |
4daaa87c AS |
554 | if (pci_find_capability(to_pci_dev(uhci_dev(uhci)), PCI_CAP_ID_PM)) |
555 | hcd->can_wakeup = 1; /* Assume it supports PME# */ | |
1da177e4 | 556 | |
4daaa87c AS |
557 | dentry = debugfs_create_file(hcd->self.bus_name, |
558 | S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci, | |
559 | &uhci_debug_operations); | |
1da177e4 | 560 | if (!dentry) { |
4daaa87c AS |
561 | dev_err(uhci_dev(uhci), |
562 | "couldn't create uhci debugfs entry\n"); | |
1da177e4 LT |
563 | retval = -ENOMEM; |
564 | goto err_create_debug_entry; | |
565 | } | |
566 | uhci->dentry = dentry; | |
567 | ||
568 | uhci->fsbr = 0; | |
569 | uhci->fsbrtimeout = 0; | |
570 | ||
571 | spin_lock_init(&uhci->lock); | |
572 | INIT_LIST_HEAD(&uhci->qh_remove_list); | |
573 | ||
574 | INIT_LIST_HEAD(&uhci->td_remove_list); | |
575 | ||
576 | INIT_LIST_HEAD(&uhci->urb_remove_list); | |
577 | ||
578 | INIT_LIST_HEAD(&uhci->urb_list); | |
579 | ||
580 | INIT_LIST_HEAD(&uhci->complete_list); | |
581 | ||
582 | init_waitqueue_head(&uhci->waitqh); | |
583 | ||
f5946f82 AS |
584 | init_timer(&uhci->stall_timer); |
585 | uhci->stall_timer.function = stall_callback; | |
586 | uhci->stall_timer.data = (unsigned long) uhci; | |
587 | ||
1da177e4 LT |
588 | uhci->fl = dma_alloc_coherent(uhci_dev(uhci), sizeof(*uhci->fl), |
589 | &dma_handle, 0); | |
590 | if (!uhci->fl) { | |
591 | dev_err(uhci_dev(uhci), "unable to allocate " | |
592 | "consistent memory for frame list\n"); | |
593 | goto err_alloc_fl; | |
594 | } | |
595 | ||
596 | memset((void *)uhci->fl, 0, sizeof(*uhci->fl)); | |
597 | ||
598 | uhci->fl->dma_handle = dma_handle; | |
599 | ||
600 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
601 | sizeof(struct uhci_td), 16, 0); | |
602 | if (!uhci->td_pool) { | |
603 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
604 | goto err_create_td_pool; | |
605 | } | |
606 | ||
607 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
608 | sizeof(struct uhci_qh), 16, 0); | |
609 | if (!uhci->qh_pool) { | |
610 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
611 | goto err_create_qh_pool; | |
612 | } | |
613 | ||
614 | /* Initialize the root hub */ | |
615 | ||
1da177e4 LT |
616 | udev = usb_alloc_dev(NULL, &hcd->self, 0); |
617 | if (!udev) { | |
618 | dev_err(uhci_dev(uhci), "unable to allocate root hub\n"); | |
619 | goto err_alloc_root_hub; | |
620 | } | |
621 | ||
622 | uhci->term_td = uhci_alloc_td(uhci, udev); | |
623 | if (!uhci->term_td) { | |
624 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
625 | goto err_alloc_term_td; | |
626 | } | |
627 | ||
628 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
629 | uhci->skelqh[i] = uhci_alloc_qh(uhci, udev); | |
630 | if (!uhci->skelqh[i]) { | |
631 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
632 | goto err_alloc_skelqh; | |
633 | } | |
634 | } | |
635 | ||
636 | /* | |
637 | * 8 Interrupt queues; link all higher int queues to int1, | |
638 | * then link int1 to control and control to bulk | |
639 | */ | |
640 | uhci->skel_int128_qh->link = | |
641 | uhci->skel_int64_qh->link = | |
642 | uhci->skel_int32_qh->link = | |
643 | uhci->skel_int16_qh->link = | |
644 | uhci->skel_int8_qh->link = | |
645 | uhci->skel_int4_qh->link = | |
646 | uhci->skel_int2_qh->link = | |
647 | cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH; | |
648 | uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH; | |
649 | ||
650 | uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH; | |
651 | uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH; | |
652 | uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH; | |
653 | ||
654 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
655 | uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) | | |
656 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); | |
657 | uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle); | |
658 | ||
659 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
660 | uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle); | |
661 | ||
662 | /* | |
663 | * Fill the frame list: make all entries point to the proper | |
664 | * interrupt queue. | |
665 | * | |
666 | * The interrupt queues will be interleaved as evenly as possible. | |
667 | * There's not much to be done about period-1 interrupts; they have | |
668 | * to occur in every frame. But we can schedule period-2 interrupts | |
669 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
670 | * to 2 (mod 4), and so on. This way each frame only has two | |
671 | * interrupt QHs, which will help spread out bandwidth utilization. | |
672 | */ | |
673 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
674 | int irq; | |
675 | ||
676 | /* | |
677 | * ffs (Find First bit Set) does exactly what we need: | |
678 | * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[6], | |
679 | * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc. | |
680 | * ffs > 6 => not on any high-period queue, so use | |
681 | * skel_int1_qh = skelqh[7]. | |
682 | * Add UHCI_NUMFRAMES to insure at least one bit is set. | |
683 | */ | |
684 | irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES); | |
685 | if (irq < 0) | |
686 | irq = 7; | |
687 | ||
688 | /* Only place we don't use the frame list routines */ | |
689 | uhci->fl->frame[i] = UHCI_PTR_QH | | |
690 | cpu_to_le32(uhci->skelqh[irq]->dma_handle); | |
691 | } | |
692 | ||
693 | /* | |
694 | * Some architectures require a full mb() to enforce completion of | |
a8bed8b6 | 695 | * the memory writes above before the I/O transfers in configure_hc(). |
1da177e4 LT |
696 | */ |
697 | mb(); | |
a8bed8b6 AS |
698 | |
699 | configure_hc(uhci); | |
700 | start_rh(uhci); | |
1da177e4 | 701 | |
1da177e4 LT |
702 | udev->speed = USB_SPEED_FULL; |
703 | ||
704 | if (usb_hcd_register_root_hub(udev, hcd) != 0) { | |
705 | dev_err(uhci_dev(uhci), "unable to start root hub\n"); | |
706 | retval = -ENOMEM; | |
707 | goto err_start_root_hub; | |
708 | } | |
709 | ||
710 | return 0; | |
711 | ||
712 | /* | |
713 | * error exits: | |
714 | */ | |
715 | err_start_root_hub: | |
a8bed8b6 | 716 | reset_hc(uhci); |
6c1b445c | 717 | del_timer_sync(&uhci->stall_timer); |
1da177e4 LT |
718 | |
719 | err_alloc_skelqh: | |
720 | for (i = 0; i < UHCI_NUM_SKELQH; i++) | |
721 | if (uhci->skelqh[i]) { | |
722 | uhci_free_qh(uhci, uhci->skelqh[i]); | |
723 | uhci->skelqh[i] = NULL; | |
724 | } | |
725 | ||
726 | uhci_free_td(uhci, uhci->term_td); | |
727 | uhci->term_td = NULL; | |
728 | ||
729 | err_alloc_term_td: | |
730 | usb_put_dev(udev); | |
731 | ||
732 | err_alloc_root_hub: | |
733 | dma_pool_destroy(uhci->qh_pool); | |
734 | uhci->qh_pool = NULL; | |
735 | ||
736 | err_create_qh_pool: | |
737 | dma_pool_destroy(uhci->td_pool); | |
738 | uhci->td_pool = NULL; | |
739 | ||
740 | err_create_td_pool: | |
741 | dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), | |
742 | uhci->fl, uhci->fl->dma_handle); | |
743 | uhci->fl = NULL; | |
744 | ||
745 | err_alloc_fl: | |
746 | debugfs_remove(uhci->dentry); | |
747 | uhci->dentry = NULL; | |
748 | ||
749 | err_create_debug_entry: | |
750 | return retval; | |
751 | } | |
752 | ||
753 | static void uhci_stop(struct usb_hcd *hcd) | |
754 | { | |
755 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
756 | ||
1da177e4 | 757 | spin_lock_irq(&uhci->lock); |
a8bed8b6 | 758 | reset_hc(uhci); |
1da177e4 LT |
759 | uhci_scan_schedule(uhci, NULL); |
760 | spin_unlock_irq(&uhci->lock); | |
6c1b445c AS |
761 | |
762 | del_timer_sync(&uhci->stall_timer); | |
1da177e4 LT |
763 | release_uhci(uhci); |
764 | } | |
765 | ||
766 | #ifdef CONFIG_PM | |
a8bed8b6 AS |
767 | static int uhci_rh_suspend(struct usb_hcd *hcd) |
768 | { | |
769 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
770 | ||
771 | spin_lock_irq(&uhci->lock); | |
4daaa87c AS |
772 | if (!uhci->hc_inaccessible) /* Not dead */ |
773 | suspend_rh(uhci, UHCI_RH_SUSPENDED); | |
a8bed8b6 AS |
774 | spin_unlock_irq(&uhci->lock); |
775 | return 0; | |
776 | } | |
777 | ||
778 | static int uhci_rh_resume(struct usb_hcd *hcd) | |
779 | { | |
780 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 781 | int rc = 0; |
a8bed8b6 AS |
782 | |
783 | spin_lock_irq(&uhci->lock); | |
4daaa87c AS |
784 | if (uhci->hc_inaccessible) { |
785 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
786 | dev_warn(uhci_dev(uhci), "HC isn't running!\n"); | |
787 | rc = -ENODEV; | |
788 | } | |
789 | /* Otherwise the HC is dead */ | |
790 | } else | |
791 | wakeup_rh(uhci); | |
a8bed8b6 | 792 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 793 | return rc; |
a8bed8b6 AS |
794 | } |
795 | ||
9a5d3e98 | 796 | static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message) |
1da177e4 LT |
797 | { |
798 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 799 | int rc = 0; |
1da177e4 | 800 | |
a8bed8b6 AS |
801 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
802 | ||
1da177e4 | 803 | spin_lock_irq(&uhci->lock); |
4daaa87c AS |
804 | if (uhci->hc_inaccessible) /* Dead or already suspended */ |
805 | goto done; | |
a8bed8b6 AS |
806 | |
807 | #ifndef CONFIG_USB_SUSPEND | |
808 | /* Otherwise this would never happen */ | |
809 | suspend_rh(uhci, UHCI_RH_SUSPENDED); | |
810 | #endif | |
811 | ||
4daaa87c AS |
812 | if (uhci->rh_state > UHCI_RH_SUSPENDED) { |
813 | dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n"); | |
814 | hcd->state = HC_STATE_RUNNING; | |
815 | rc = -EBUSY; | |
816 | goto done; | |
817 | }; | |
818 | ||
a8bed8b6 AS |
819 | /* All PCI host controllers are required to disable IRQ generation |
820 | * at the source, so we must turn off PIRQ. | |
821 | */ | |
822 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0); | |
823 | uhci->hc_inaccessible = 1; | |
824 | ||
825 | /* FIXME: Enable non-PME# remote wakeup? */ | |
826 | ||
4daaa87c | 827 | done: |
1da177e4 | 828 | spin_unlock_irq(&uhci->lock); |
6c1b445c AS |
829 | if (rc == 0) |
830 | del_timer_sync(&hcd->rh_timer); | |
4daaa87c | 831 | return rc; |
1da177e4 LT |
832 | } |
833 | ||
834 | static int uhci_resume(struct usb_hcd *hcd) | |
835 | { | |
836 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 837 | |
a8bed8b6 AS |
838 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
839 | ||
4daaa87c AS |
840 | if (uhci->rh_state == UHCI_RH_RESET) /* Dead */ |
841 | return 0; | |
1da177e4 | 842 | spin_lock_irq(&uhci->lock); |
1da177e4 | 843 | |
a8bed8b6 AS |
844 | /* FIXME: Disable non-PME# remote wakeup? */ |
845 | ||
846 | uhci->hc_inaccessible = 0; | |
847 | ||
848 | /* The BIOS may have changed the controller settings during a | |
849 | * system wakeup. Check it and reconfigure to avoid problems. | |
850 | */ | |
851 | check_and_reset_hc(uhci); | |
852 | configure_hc(uhci); | |
853 | ||
854 | #ifndef CONFIG_USB_SUSPEND | |
855 | /* Otherwise this would never happen */ | |
856 | wakeup_rh(uhci); | |
857 | #endif | |
858 | if (uhci->rh_state == UHCI_RH_RESET) | |
859 | suspend_rh(uhci, UHCI_RH_SUSPENDED); | |
c8f4fe43 | 860 | |
a8bed8b6 | 861 | spin_unlock_irq(&uhci->lock); |
6c1b445c AS |
862 | |
863 | if (hcd->poll_rh) | |
864 | usb_hcd_poll_rh_status(hcd); | |
1da177e4 LT |
865 | return 0; |
866 | } | |
867 | #endif | |
868 | ||
869 | /* Wait until all the URBs for a particular device/endpoint are gone */ | |
870 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, | |
871 | struct usb_host_endpoint *ep) | |
872 | { | |
873 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
874 | ||
875 | wait_event_interruptible(uhci->waitqh, list_empty(&ep->urb_list)); | |
876 | } | |
877 | ||
878 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
879 | { | |
880 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 881 | unsigned long flags; |
c8f4fe43 AS |
882 | int is_stopped; |
883 | int frame_number; | |
1da177e4 LT |
884 | |
885 | /* Minimize latency by avoiding the spinlock */ | |
886 | local_irq_save(flags); | |
c8f4fe43 AS |
887 | is_stopped = uhci->is_stopped; |
888 | smp_rmb(); | |
889 | frame_number = (is_stopped ? uhci->frame_number : | |
1da177e4 LT |
890 | inw(uhci->io_addr + USBFRNUM)); |
891 | local_irq_restore(flags); | |
892 | return frame_number; | |
893 | } | |
894 | ||
895 | static const char hcd_name[] = "uhci_hcd"; | |
896 | ||
897 | static const struct hc_driver uhci_driver = { | |
898 | .description = hcd_name, | |
899 | .product_desc = "UHCI Host Controller", | |
900 | .hcd_priv_size = sizeof(struct uhci_hcd), | |
901 | ||
902 | /* Generic hardware linkage */ | |
903 | .irq = uhci_irq, | |
904 | .flags = HCD_USB11, | |
905 | ||
906 | /* Basic lifecycle operations */ | |
907 | .reset = uhci_reset, | |
908 | .start = uhci_start, | |
909 | #ifdef CONFIG_PM | |
910 | .suspend = uhci_suspend, | |
911 | .resume = uhci_resume, | |
a8bed8b6 AS |
912 | .hub_suspend = uhci_rh_suspend, |
913 | .hub_resume = uhci_rh_resume, | |
1da177e4 LT |
914 | #endif |
915 | .stop = uhci_stop, | |
916 | ||
917 | .urb_enqueue = uhci_urb_enqueue, | |
918 | .urb_dequeue = uhci_urb_dequeue, | |
919 | ||
920 | .endpoint_disable = uhci_hcd_endpoint_disable, | |
921 | .get_frame_number = uhci_hcd_get_frame_number, | |
922 | ||
923 | .hub_status_data = uhci_hub_status_data, | |
924 | .hub_control = uhci_hub_control, | |
925 | }; | |
926 | ||
927 | static const struct pci_device_id uhci_pci_ids[] = { { | |
928 | /* handle any USB UHCI controller */ | |
929 | PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0), | |
930 | .driver_data = (unsigned long) &uhci_driver, | |
931 | }, { /* end: all zeroes */ } | |
932 | }; | |
933 | ||
934 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | |
935 | ||
936 | static struct pci_driver uhci_pci_driver = { | |
937 | .name = (char *)hcd_name, | |
938 | .id_table = uhci_pci_ids, | |
939 | ||
940 | .probe = usb_hcd_pci_probe, | |
941 | .remove = usb_hcd_pci_remove, | |
942 | ||
943 | #ifdef CONFIG_PM | |
944 | .suspend = usb_hcd_pci_suspend, | |
945 | .resume = usb_hcd_pci_resume, | |
946 | #endif /* PM */ | |
947 | }; | |
948 | ||
949 | static int __init uhci_hcd_init(void) | |
950 | { | |
951 | int retval = -ENOMEM; | |
952 | ||
953 | printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n"); | |
954 | ||
955 | if (usb_disabled()) | |
956 | return -ENODEV; | |
957 | ||
958 | if (debug) { | |
959 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); | |
960 | if (!errbuf) | |
961 | goto errbuf_failed; | |
962 | } | |
963 | ||
964 | uhci_debugfs_root = debugfs_create_dir("uhci", NULL); | |
965 | if (!uhci_debugfs_root) | |
966 | goto debug_failed; | |
967 | ||
968 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", | |
969 | sizeof(struct urb_priv), 0, 0, NULL, NULL); | |
970 | if (!uhci_up_cachep) | |
971 | goto up_failed; | |
972 | ||
973 | retval = pci_register_driver(&uhci_pci_driver); | |
974 | if (retval) | |
975 | goto init_failed; | |
976 | ||
977 | return 0; | |
978 | ||
979 | init_failed: | |
980 | if (kmem_cache_destroy(uhci_up_cachep)) | |
981 | warn("not all urb_priv's were freed!"); | |
982 | ||
983 | up_failed: | |
984 | debugfs_remove(uhci_debugfs_root); | |
985 | ||
986 | debug_failed: | |
1bc3c9e1 | 987 | kfree(errbuf); |
1da177e4 LT |
988 | |
989 | errbuf_failed: | |
990 | ||
991 | return retval; | |
992 | } | |
993 | ||
994 | static void __exit uhci_hcd_cleanup(void) | |
995 | { | |
996 | pci_unregister_driver(&uhci_pci_driver); | |
997 | ||
998 | if (kmem_cache_destroy(uhci_up_cachep)) | |
999 | warn("not all urb_priv's were freed!"); | |
1000 | ||
1001 | debugfs_remove(uhci_debugfs_root); | |
1bc3c9e1 | 1002 | kfree(errbuf); |
1da177e4 LT |
1003 | } |
1004 | ||
1005 | module_init(uhci_hcd_init); | |
1006 | module_exit(uhci_hcd_cleanup); | |
1007 | ||
1008 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
1009 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1010 | MODULE_LICENSE("GPL"); |