Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
c4334726 | 16 | * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | * |
18 | * Intel documents this fairly well, and as far as I know there | |
19 | * are no royalties or anything like that, but even so there are | |
20 | * people who decided that they want to do the same thing in a | |
21 | * completely different way. | |
22 | * | |
1da177e4 LT |
23 | */ |
24 | ||
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/slab.h> | |
1da177e4 LT |
33 | #include <linux/errno.h> |
34 | #include <linux/unistd.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/debugfs.h> | |
38 | #include <linux/pm.h> | |
39 | #include <linux/dmapool.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/usb.h> | |
42 | #include <linux/bitops.h> | |
b62df451 | 43 | #include <linux/dmi.h> |
1da177e4 LT |
44 | |
45 | #include <asm/uaccess.h> | |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | #include <asm/system.h> | |
49 | ||
50 | #include "../core/hcd.h" | |
51 | #include "uhci-hcd.h" | |
75e2df60 | 52 | #include "pci-quirks.h" |
1da177e4 LT |
53 | |
54 | /* | |
55 | * Version Information | |
56 | */ | |
dccf4a48 | 57 | #define DRIVER_VERSION "v3.0" |
1da177e4 LT |
58 | #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ |
59 | Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ | |
60 | Alan Stern" | |
61 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" | |
62 | ||
5f8364b7 AS |
63 | /* for flakey hardware, ignore overcurrent indicators */ |
64 | static int ignore_oc; | |
65 | module_param(ignore_oc, bool, S_IRUGO); | |
66 | MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications"); | |
67 | ||
1da177e4 LT |
68 | /* |
69 | * debug = 0, no debugging messages | |
687f5f34 AS |
70 | * debug = 1, dump failed URBs except for stalls |
71 | * debug = 2, dump all failed URBs (including stalls) | |
1da177e4 | 72 | * show all queues in /debug/uhci/[pci_addr] |
687f5f34 | 73 | * debug = 3, show all TDs in URBs when dumping |
1da177e4 LT |
74 | */ |
75 | #ifdef DEBUG | |
8d402e1a | 76 | #define DEBUG_CONFIGURED 1 |
1da177e4 | 77 | static int debug = 1; |
1da177e4 LT |
78 | module_param(debug, int, S_IRUGO | S_IWUSR); |
79 | MODULE_PARM_DESC(debug, "Debug level"); | |
8d402e1a AS |
80 | |
81 | #else | |
82 | #define DEBUG_CONFIGURED 0 | |
83 | #define debug 0 | |
84 | #endif | |
85 | ||
1da177e4 LT |
86 | static char *errbuf; |
87 | #define ERRBUF_LEN (32 * 1024) | |
88 | ||
e18b890b | 89 | static struct kmem_cache *uhci_up_cachep; /* urb_priv */ |
1da177e4 | 90 | |
6c1b445c AS |
91 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); |
92 | static void wakeup_rh(struct uhci_hcd *uhci); | |
1da177e4 | 93 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); |
1da177e4 | 94 | |
1da177e4 LT |
95 | #include "uhci-debug.c" |
96 | #include "uhci-q.c" | |
1f09df8b | 97 | #include "uhci-hub.c" |
1da177e4 | 98 | |
a8bed8b6 | 99 | /* |
bb200f6e | 100 | * Finish up a host controller reset and update the recorded state. |
a8bed8b6 | 101 | */ |
bb200f6e | 102 | static void finish_reset(struct uhci_hcd *uhci) |
1da177e4 | 103 | { |
c074b416 AS |
104 | int port; |
105 | ||
c074b416 AS |
106 | /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect |
107 | * bits in the port status and control registers. | |
108 | * We have to clear them by hand. | |
109 | */ | |
110 | for (port = 0; port < uhci->rh_numports; ++port) | |
111 | outw(0, uhci->io_addr + USBPORTSC1 + (port * 2)); | |
112 | ||
8e326406 | 113 | uhci->port_c_suspend = uhci->resuming_ports = 0; |
c8f4fe43 | 114 | uhci->rh_state = UHCI_RH_RESET; |
a8bed8b6 AS |
115 | uhci->is_stopped = UHCI_IS_STOPPED; |
116 | uhci_to_hcd(uhci)->state = HC_STATE_HALT; | |
6c1b445c | 117 | uhci_to_hcd(uhci)->poll_rh = 0; |
e323de46 AS |
118 | |
119 | uhci->dead = 0; /* Full reset resurrects the controller */ | |
1da177e4 LT |
120 | } |
121 | ||
4daaa87c AS |
122 | /* |
123 | * Last rites for a defunct/nonfunctional controller | |
02597d2d | 124 | * or one we don't want to use any more. |
4daaa87c | 125 | */ |
e323de46 | 126 | static void uhci_hc_died(struct uhci_hcd *uhci) |
4daaa87c | 127 | { |
e323de46 | 128 | uhci_get_current_frame_number(uhci); |
bb200f6e AS |
129 | uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr); |
130 | finish_reset(uhci); | |
e323de46 AS |
131 | uhci->dead = 1; |
132 | ||
133 | /* The current frame may already be partway finished */ | |
134 | ++uhci->frame_number; | |
4daaa87c AS |
135 | } |
136 | ||
a8bed8b6 | 137 | /* |
be3cbc5f DB |
138 | * Initialize a controller that was newly discovered or has lost power |
139 | * or otherwise been reset while it was suspended. In none of these cases | |
140 | * can we be sure of its previous state. | |
a8bed8b6 AS |
141 | */ |
142 | static void check_and_reset_hc(struct uhci_hcd *uhci) | |
143 | { | |
bb200f6e AS |
144 | if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr)) |
145 | finish_reset(uhci); | |
a8bed8b6 AS |
146 | } |
147 | ||
148 | /* | |
149 | * Store the basic register settings needed by the controller. | |
150 | */ | |
151 | static void configure_hc(struct uhci_hcd *uhci) | |
152 | { | |
153 | /* Set the frame length to the default: 1 ms exactly */ | |
154 | outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); | |
155 | ||
156 | /* Store the frame list base address */ | |
a1d59ce8 | 157 | outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD); |
a8bed8b6 AS |
158 | |
159 | /* Set the current frame number */ | |
c4334726 AS |
160 | outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER, |
161 | uhci->io_addr + USBFRNUM); | |
a8bed8b6 | 162 | |
f37be9b9 AS |
163 | /* Mark controller as not halted before we enable interrupts */ |
164 | uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED; | |
a8bed8b6 AS |
165 | mb(); |
166 | ||
167 | /* Enable PIRQ */ | |
168 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
169 | USBLEGSUP_DEFAULT); | |
170 | } | |
171 | ||
172 | ||
c8f4fe43 | 173 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
1da177e4 | 174 | { |
c8f4fe43 | 175 | int port; |
1da177e4 | 176 | |
5f8364b7 AS |
177 | /* If we have to ignore overcurrent events then almost by definition |
178 | * we can't depend on resume-detect interrupts. */ | |
179 | if (ignore_oc) | |
180 | return 1; | |
181 | ||
c8f4fe43 AS |
182 | switch (to_pci_dev(uhci_dev(uhci))->vendor) { |
183 | default: | |
184 | break; | |
185 | ||
186 | case PCI_VENDOR_ID_GENESYS: | |
187 | /* Genesys Logic's GL880S controllers don't generate | |
188 | * resume-detect interrupts. | |
189 | */ | |
190 | return 1; | |
191 | ||
192 | case PCI_VENDOR_ID_INTEL: | |
193 | /* Some of Intel's USB controllers have a bug that causes | |
194 | * resume-detect interrupts if any port has an over-current | |
195 | * condition. To make matters worse, some motherboards | |
196 | * hardwire unused USB ports' over-current inputs active! | |
197 | * To prevent problems, we will not enable resume-detect | |
198 | * interrupts if any ports are OC. | |
199 | */ | |
200 | for (port = 0; port < uhci->rh_numports; ++port) { | |
201 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | |
202 | USBPORTSC_OC) | |
203 | return 1; | |
204 | } | |
205 | break; | |
206 | } | |
207 | return 0; | |
208 | } | |
209 | ||
b62df451 AS |
210 | static int remote_wakeup_is_broken(struct uhci_hcd *uhci) |
211 | { | |
b62df451 | 212 | int port; |
c80a70d5 AS |
213 | char *sys_info; |
214 | static char bad_Asus_board[] = "A7V8X"; | |
b62df451 AS |
215 | |
216 | /* One of Asus's motherboards has a bug which causes it to | |
217 | * wake up immediately from suspend-to-RAM if any of the ports | |
218 | * are connected. In such cases we will not set EGSM. | |
219 | */ | |
c80a70d5 AS |
220 | sys_info = dmi_get_system_info(DMI_BOARD_NAME); |
221 | if (sys_info && !strcmp(sys_info, bad_Asus_board)) { | |
b62df451 AS |
222 | for (port = 0; port < uhci->rh_numports; ++port) { |
223 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | |
224 | USBPORTSC_CCS) | |
225 | return 1; | |
226 | } | |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
a8bed8b6 | 232 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
c8f4fe43 AS |
233 | __releases(uhci->lock) |
234 | __acquires(uhci->lock) | |
235 | { | |
236 | int auto_stop; | |
b62df451 | 237 | int int_enable, egsm_enable; |
c8f4fe43 AS |
238 | |
239 | auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); | |
be3cbc5f DB |
240 | dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, |
241 | "%s%s\n", __FUNCTION__, | |
c8f4fe43 AS |
242 | (auto_stop ? " (auto-stop)" : "")); |
243 | ||
244 | /* If we get a suspend request when we're already auto-stopped | |
245 | * then there's nothing to do. | |
246 | */ | |
247 | if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) { | |
248 | uhci->rh_state = new_state; | |
249 | return; | |
250 | } | |
251 | ||
252 | /* Enable resume-detect interrupts if they work. | |
b62df451 | 253 | * Then enter Global Suspend mode if _it_ works, still configured. |
c8f4fe43 | 254 | */ |
b62df451 | 255 | egsm_enable = USBCMD_EGSM; |
1f09df8b AS |
256 | uhci->working_RD = 1; |
257 | int_enable = USBINTR_RESUME; | |
b62df451 AS |
258 | if (remote_wakeup_is_broken(uhci)) |
259 | egsm_enable = 0; | |
260 | if (resume_detect_interrupts_are_broken(uhci) || !egsm_enable) | |
1f09df8b | 261 | uhci->working_RD = int_enable = 0; |
b62df451 | 262 | |
c8f4fe43 | 263 | outw(int_enable, uhci->io_addr + USBINTR); |
b62df451 | 264 | outw(egsm_enable | USBCMD_CF, uhci->io_addr + USBCMD); |
a8bed8b6 | 265 | mb(); |
c8f4fe43 AS |
266 | udelay(5); |
267 | ||
268 | /* If we're auto-stopping then no devices have been attached | |
269 | * for a while, so there shouldn't be any active URBs and the | |
270 | * controller should stop after a few microseconds. Otherwise | |
271 | * we will give the controller one frame to stop. | |
272 | */ | |
273 | if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { | |
274 | uhci->rh_state = UHCI_RH_SUSPENDING; | |
275 | spin_unlock_irq(&uhci->lock); | |
276 | msleep(1); | |
277 | spin_lock_irq(&uhci->lock); | |
e323de46 | 278 | if (uhci->dead) |
4daaa87c | 279 | return; |
c8f4fe43 AS |
280 | } |
281 | if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) | |
be3cbc5f DB |
282 | dev_warn(&uhci_to_hcd(uhci)->self.root_hub->dev, |
283 | "Controller not stopped yet!\n"); | |
1da177e4 | 284 | |
1da177e4 | 285 | uhci_get_current_frame_number(uhci); |
c8f4fe43 AS |
286 | |
287 | uhci->rh_state = new_state; | |
1da177e4 | 288 | uhci->is_stopped = UHCI_IS_STOPPED; |
6c1b445c | 289 | uhci_to_hcd(uhci)->poll_rh = !int_enable; |
1da177e4 | 290 | |
7d12e780 | 291 | uhci_scan_schedule(uhci); |
84afddd7 | 292 | uhci_fsbr_off(uhci); |
1da177e4 LT |
293 | } |
294 | ||
a8bed8b6 AS |
295 | static void start_rh(struct uhci_hcd *uhci) |
296 | { | |
f37be9b9 | 297 | uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; |
a8bed8b6 | 298 | uhci->is_stopped = 0; |
a8bed8b6 AS |
299 | |
300 | /* Mark it configured and running with a 64-byte max packet. | |
301 | * All interrupts are enabled, even though RESUME won't do anything. | |
302 | */ | |
303 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); | |
304 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | |
305 | uhci->io_addr + USBINTR); | |
306 | mb(); | |
6c1b445c AS |
307 | uhci->rh_state = UHCI_RH_RUNNING; |
308 | uhci_to_hcd(uhci)->poll_rh = 1; | |
a8bed8b6 AS |
309 | } |
310 | ||
311 | static void wakeup_rh(struct uhci_hcd *uhci) | |
c8f4fe43 AS |
312 | __releases(uhci->lock) |
313 | __acquires(uhci->lock) | |
1da177e4 | 314 | { |
be3cbc5f DB |
315 | dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, |
316 | "%s%s\n", __FUNCTION__, | |
c8f4fe43 AS |
317 | uhci->rh_state == UHCI_RH_AUTO_STOPPED ? |
318 | " (auto-start)" : ""); | |
1da177e4 | 319 | |
c8f4fe43 AS |
320 | /* If we are auto-stopped then no devices are attached so there's |
321 | * no need for wakeup signals. Otherwise we send Global Resume | |
322 | * for 20 ms. | |
323 | */ | |
324 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
325 | uhci->rh_state = UHCI_RH_RESUMING; | |
326 | outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF, | |
327 | uhci->io_addr + USBCMD); | |
328 | spin_unlock_irq(&uhci->lock); | |
329 | msleep(20); | |
330 | spin_lock_irq(&uhci->lock); | |
e323de46 | 331 | if (uhci->dead) |
4daaa87c | 332 | return; |
1da177e4 | 333 | |
c8f4fe43 AS |
334 | /* End Global Resume and wait for EOP to be sent */ |
335 | outw(USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 336 | mb(); |
c8f4fe43 AS |
337 | udelay(4); |
338 | if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) | |
339 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); | |
340 | } | |
1da177e4 | 341 | |
a8bed8b6 | 342 | start_rh(uhci); |
c8f4fe43 | 343 | |
6c1b445c AS |
344 | /* Restart root hub polling */ |
345 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); | |
1da177e4 LT |
346 | } |
347 | ||
7d12e780 | 348 | static irqreturn_t uhci_irq(struct usb_hcd *hcd) |
014e73c9 AS |
349 | { |
350 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
014e73c9 | 351 | unsigned short status; |
4daaa87c | 352 | unsigned long flags; |
1da177e4 LT |
353 | |
354 | /* | |
014e73c9 AS |
355 | * Read the interrupt status, and write it back to clear the |
356 | * interrupt cause. Contrary to the UHCI specification, the | |
357 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 358 | */ |
a8bed8b6 | 359 | status = inw(uhci->io_addr + USBSTS); |
014e73c9 AS |
360 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
361 | return IRQ_NONE; | |
a8bed8b6 | 362 | outw(status, uhci->io_addr + USBSTS); /* Clear it */ |
014e73c9 AS |
363 | |
364 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | |
365 | if (status & USBSTS_HSE) | |
366 | dev_err(uhci_dev(uhci), "host system error, " | |
367 | "PCI problems?\n"); | |
368 | if (status & USBSTS_HCPE) | |
369 | dev_err(uhci_dev(uhci), "host controller process " | |
370 | "error, something bad happened!\n"); | |
4daaa87c AS |
371 | if (status & USBSTS_HCH) { |
372 | spin_lock_irqsave(&uhci->lock, flags); | |
373 | if (uhci->rh_state >= UHCI_RH_RUNNING) { | |
374 | dev_err(uhci_dev(uhci), | |
375 | "host controller halted, " | |
014e73c9 | 376 | "very bad!\n"); |
8d402e1a AS |
377 | if (debug > 1 && errbuf) { |
378 | /* Print the schedule for debugging */ | |
379 | uhci_sprint_schedule(uhci, | |
380 | errbuf, ERRBUF_LEN); | |
381 | lprintk(errbuf); | |
382 | } | |
e323de46 | 383 | uhci_hc_died(uhci); |
1f09df8b AS |
384 | |
385 | /* Force a callback in case there are | |
386 | * pending unlinks */ | |
387 | mod_timer(&hcd->rh_timer, jiffies); | |
4daaa87c AS |
388 | } |
389 | spin_unlock_irqrestore(&uhci->lock, flags); | |
1da177e4 | 390 | } |
1da177e4 LT |
391 | } |
392 | ||
014e73c9 | 393 | if (status & USBSTS_RD) |
6c1b445c | 394 | usb_hcd_poll_rh_status(hcd); |
1f09df8b AS |
395 | else { |
396 | spin_lock_irqsave(&uhci->lock, flags); | |
7d12e780 | 397 | uhci_scan_schedule(uhci); |
1f09df8b AS |
398 | spin_unlock_irqrestore(&uhci->lock, flags); |
399 | } | |
1da177e4 | 400 | |
014e73c9 AS |
401 | return IRQ_HANDLED; |
402 | } | |
1da177e4 | 403 | |
014e73c9 AS |
404 | /* |
405 | * Store the current frame number in uhci->frame_number if the controller | |
c4334726 AS |
406 | * is runnning. Expand from 11 bits (of which we use only 10) to a |
407 | * full-sized integer. | |
408 | * | |
409 | * Like many other parts of the driver, this code relies on being polled | |
410 | * more than once per second as long as the controller is running. | |
014e73c9 AS |
411 | */ |
412 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
413 | { | |
c4334726 AS |
414 | if (!uhci->is_stopped) { |
415 | unsigned delta; | |
416 | ||
417 | delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) & | |
418 | (UHCI_NUMFRAMES - 1); | |
419 | uhci->frame_number += delta; | |
420 | } | |
1da177e4 LT |
421 | } |
422 | ||
423 | /* | |
424 | * De-allocate all resources | |
425 | */ | |
426 | static void release_uhci(struct uhci_hcd *uhci) | |
427 | { | |
428 | int i; | |
429 | ||
8d402e1a AS |
430 | if (DEBUG_CONFIGURED) { |
431 | spin_lock_irq(&uhci->lock); | |
432 | uhci->is_initialized = 0; | |
433 | spin_unlock_irq(&uhci->lock); | |
434 | ||
435 | debugfs_remove(uhci->dentry); | |
436 | } | |
437 | ||
1da177e4 | 438 | for (i = 0; i < UHCI_NUM_SKELQH; i++) |
8b4cd421 | 439 | uhci_free_qh(uhci, uhci->skelqh[i]); |
1da177e4 | 440 | |
8b4cd421 | 441 | uhci_free_td(uhci, uhci->term_td); |
1da177e4 | 442 | |
8b4cd421 | 443 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 | 444 | |
8b4cd421 | 445 | dma_pool_destroy(uhci->td_pool); |
1da177e4 | 446 | |
a1d59ce8 AS |
447 | kfree(uhci->frame_cpu); |
448 | ||
449 | dma_free_coherent(uhci_dev(uhci), | |
450 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
451 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 LT |
452 | } |
453 | ||
be3cbc5f | 454 | static int uhci_init(struct usb_hcd *hcd) |
1da177e4 LT |
455 | { |
456 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c074b416 AS |
457 | unsigned io_size = (unsigned) hcd->rsrc_len; |
458 | int port; | |
1da177e4 LT |
459 | |
460 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | |
461 | ||
c074b416 AS |
462 | /* The UHCI spec says devices must have 2 ports, and goes on to say |
463 | * they may have more but gives no way to determine how many there | |
e07fefa6 | 464 | * are. However according to the UHCI spec, Bit 7 of the port |
c074b416 | 465 | * status and control register is always set to 1. So we try to |
e07fefa6 AS |
466 | * use this to our advantage. Another common failure mode when |
467 | * a nonexistent register is addressed is to return all ones, so | |
468 | * we test for that also. | |
c074b416 AS |
469 | */ |
470 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | |
471 | unsigned int portstatus; | |
472 | ||
473 | portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2)); | |
e07fefa6 | 474 | if (!(portstatus & 0x0080) || portstatus == 0xffff) |
c074b416 AS |
475 | break; |
476 | } | |
477 | if (debug) | |
478 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
479 | ||
e07fefa6 AS |
480 | /* Anything greater than 7 is weird so we'll ignore it. */ |
481 | if (port > UHCI_RH_MAXCHILD) { | |
c074b416 AS |
482 | dev_info(uhci_dev(uhci), "port count misdetected? " |
483 | "forcing to 2 ports\n"); | |
484 | port = 2; | |
485 | } | |
486 | uhci->rh_numports = port; | |
487 | ||
a8bed8b6 AS |
488 | /* Kick BIOS off this hardware and reset if the controller |
489 | * isn't already safely quiescent. | |
1da177e4 | 490 | */ |
a8bed8b6 | 491 | check_and_reset_hc(uhci); |
1da177e4 LT |
492 | return 0; |
493 | } | |
494 | ||
02597d2d AS |
495 | /* Make sure the controller is quiescent and that we're not using it |
496 | * any more. This is mainly for the benefit of programs which, like kexec, | |
497 | * expect the hardware to be idle: not doing DMA or generating IRQs. | |
498 | * | |
499 | * This routine may be called in a damaged or failing kernel. Hence we | |
500 | * do not acquire the spinlock before shutting down the controller. | |
501 | */ | |
502 | static void uhci_shutdown(struct pci_dev *pdev) | |
503 | { | |
504 | struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev); | |
505 | ||
e323de46 | 506 | uhci_hc_died(hcd_to_uhci(hcd)); |
02597d2d AS |
507 | } |
508 | ||
1da177e4 LT |
509 | /* |
510 | * Allocate a frame list, and then setup the skeleton | |
511 | * | |
512 | * The hardware doesn't really know any difference | |
513 | * in the queues, but the order does matter for the | |
514 | * protocols higher up. The order is: | |
515 | * | |
516 | * - any isochronous events handled before any | |
517 | * of the queues. We don't do that here, because | |
518 | * we'll create the actual TD entries on demand. | |
519 | * - The first queue is the interrupt queue. | |
520 | * - The second queue is the control queue, split into low- and full-speed | |
521 | * - The third queue is bulk queue. | |
522 | * - The fourth queue is the bandwidth reclamation queue, which loops back | |
523 | * to the full-speed control queue. | |
524 | */ | |
525 | static int uhci_start(struct usb_hcd *hcd) | |
526 | { | |
527 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
528 | int retval = -EBUSY; | |
c074b416 | 529 | int i; |
1da177e4 LT |
530 | struct dentry *dentry; |
531 | ||
6c1b445c | 532 | hcd->uses_new_polling = 1; |
1da177e4 | 533 | |
1da177e4 | 534 | spin_lock_init(&uhci->lock); |
c5e3b741 AS |
535 | setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout, |
536 | (unsigned long) uhci); | |
dccf4a48 | 537 | INIT_LIST_HEAD(&uhci->idle_qh_list); |
1da177e4 LT |
538 | init_waitqueue_head(&uhci->waitqh); |
539 | ||
8d402e1a AS |
540 | if (DEBUG_CONFIGURED) { |
541 | dentry = debugfs_create_file(hcd->self.bus_name, | |
542 | S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, | |
543 | uhci, &uhci_debug_operations); | |
544 | if (!dentry) { | |
545 | dev_err(uhci_dev(uhci), "couldn't create uhci " | |
546 | "debugfs entry\n"); | |
547 | retval = -ENOMEM; | |
548 | goto err_create_debug_entry; | |
549 | } | |
550 | uhci->dentry = dentry; | |
551 | } | |
552 | ||
a1d59ce8 AS |
553 | uhci->frame = dma_alloc_coherent(uhci_dev(uhci), |
554 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
555 | &uhci->frame_dma_handle, 0); | |
556 | if (!uhci->frame) { | |
1da177e4 LT |
557 | dev_err(uhci_dev(uhci), "unable to allocate " |
558 | "consistent memory for frame list\n"); | |
a1d59ce8 | 559 | goto err_alloc_frame; |
1da177e4 | 560 | } |
a1d59ce8 | 561 | memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); |
1da177e4 | 562 | |
a1d59ce8 AS |
563 | uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), |
564 | GFP_KERNEL); | |
565 | if (!uhci->frame_cpu) { | |
566 | dev_err(uhci_dev(uhci), "unable to allocate " | |
567 | "memory for frame pointers\n"); | |
568 | goto err_alloc_frame_cpu; | |
569 | } | |
1da177e4 LT |
570 | |
571 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
572 | sizeof(struct uhci_td), 16, 0); | |
573 | if (!uhci->td_pool) { | |
574 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
575 | goto err_create_td_pool; | |
576 | } | |
577 | ||
578 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
579 | sizeof(struct uhci_qh), 16, 0); | |
580 | if (!uhci->qh_pool) { | |
581 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
582 | goto err_create_qh_pool; | |
583 | } | |
584 | ||
2532178a | 585 | uhci->term_td = uhci_alloc_td(uhci); |
1da177e4 LT |
586 | if (!uhci->term_td) { |
587 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
588 | goto err_alloc_term_td; | |
589 | } | |
590 | ||
591 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
dccf4a48 | 592 | uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); |
1da177e4 LT |
593 | if (!uhci->skelqh[i]) { |
594 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
595 | goto err_alloc_skelqh; | |
596 | } | |
597 | } | |
598 | ||
599 | /* | |
600 | * 8 Interrupt queues; link all higher int queues to int1, | |
601 | * then link int1 to control and control to bulk | |
602 | */ | |
603 | uhci->skel_int128_qh->link = | |
604 | uhci->skel_int64_qh->link = | |
605 | uhci->skel_int32_qh->link = | |
606 | uhci->skel_int16_qh->link = | |
607 | uhci->skel_int8_qh->link = | |
608 | uhci->skel_int4_qh->link = | |
dccf4a48 AS |
609 | uhci->skel_int2_qh->link = UHCI_PTR_QH | |
610 | cpu_to_le32(uhci->skel_int1_qh->dma_handle); | |
611 | ||
612 | uhci->skel_int1_qh->link = UHCI_PTR_QH | | |
613 | cpu_to_le32(uhci->skel_ls_control_qh->dma_handle); | |
614 | uhci->skel_ls_control_qh->link = UHCI_PTR_QH | | |
615 | cpu_to_le32(uhci->skel_fs_control_qh->dma_handle); | |
616 | uhci->skel_fs_control_qh->link = UHCI_PTR_QH | | |
617 | cpu_to_le32(uhci->skel_bulk_qh->dma_handle); | |
618 | uhci->skel_bulk_qh->link = UHCI_PTR_QH | | |
619 | cpu_to_le32(uhci->skel_term_qh->dma_handle); | |
1da177e4 LT |
620 | |
621 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
fa346568 | 622 | uhci_fill_td(uhci->term_td, 0, uhci_explen(0) | |
1da177e4 LT |
623 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); |
624 | uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle); | |
625 | ||
626 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
627 | uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle); | |
628 | ||
629 | /* | |
630 | * Fill the frame list: make all entries point to the proper | |
631 | * interrupt queue. | |
632 | * | |
633 | * The interrupt queues will be interleaved as evenly as possible. | |
634 | * There's not much to be done about period-1 interrupts; they have | |
635 | * to occur in every frame. But we can schedule period-2 interrupts | |
636 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
637 | * to 2 (mod 4), and so on. This way each frame only has two | |
638 | * interrupt QHs, which will help spread out bandwidth utilization. | |
639 | */ | |
640 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
641 | int irq; | |
642 | ||
643 | /* | |
644 | * ffs (Find First bit Set) does exactly what we need: | |
dccf4a48 AS |
645 | * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[8], |
646 | * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[7], etc. | |
647 | * ffs >= 7 => not on any high-period queue, so use | |
648 | * skel_int1_qh = skelqh[9]. | |
1da177e4 LT |
649 | * Add UHCI_NUMFRAMES to insure at least one bit is set. |
650 | */ | |
dccf4a48 AS |
651 | irq = 8 - (int) __ffs(i + UHCI_NUMFRAMES); |
652 | if (irq <= 1) | |
653 | irq = 9; | |
1da177e4 LT |
654 | |
655 | /* Only place we don't use the frame list routines */ | |
a1d59ce8 | 656 | uhci->frame[i] = UHCI_PTR_QH | |
1da177e4 LT |
657 | cpu_to_le32(uhci->skelqh[irq]->dma_handle); |
658 | } | |
659 | ||
660 | /* | |
661 | * Some architectures require a full mb() to enforce completion of | |
a8bed8b6 | 662 | * the memory writes above before the I/O transfers in configure_hc(). |
1da177e4 LT |
663 | */ |
664 | mb(); | |
a8bed8b6 AS |
665 | |
666 | configure_hc(uhci); | |
8d402e1a | 667 | uhci->is_initialized = 1; |
a8bed8b6 | 668 | start_rh(uhci); |
1da177e4 LT |
669 | return 0; |
670 | ||
671 | /* | |
672 | * error exits: | |
673 | */ | |
1da177e4 | 674 | err_alloc_skelqh: |
8b4cd421 AS |
675 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { |
676 | if (uhci->skelqh[i]) | |
1da177e4 | 677 | uhci_free_qh(uhci, uhci->skelqh[i]); |
8b4cd421 | 678 | } |
1da177e4 LT |
679 | |
680 | uhci_free_td(uhci, uhci->term_td); | |
1da177e4 LT |
681 | |
682 | err_alloc_term_td: | |
1da177e4 | 683 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 LT |
684 | |
685 | err_create_qh_pool: | |
686 | dma_pool_destroy(uhci->td_pool); | |
1da177e4 LT |
687 | |
688 | err_create_td_pool: | |
a1d59ce8 AS |
689 | kfree(uhci->frame_cpu); |
690 | ||
691 | err_alloc_frame_cpu: | |
692 | dma_free_coherent(uhci_dev(uhci), | |
693 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
694 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 | 695 | |
a1d59ce8 | 696 | err_alloc_frame: |
1da177e4 | 697 | debugfs_remove(uhci->dentry); |
1da177e4 LT |
698 | |
699 | err_create_debug_entry: | |
700 | return retval; | |
701 | } | |
702 | ||
703 | static void uhci_stop(struct usb_hcd *hcd) | |
704 | { | |
705 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
706 | ||
1da177e4 | 707 | spin_lock_irq(&uhci->lock); |
e323de46 AS |
708 | if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && !uhci->dead) |
709 | uhci_hc_died(uhci); | |
7d12e780 | 710 | uhci_scan_schedule(uhci); |
1da177e4 | 711 | spin_unlock_irq(&uhci->lock); |
6c1b445c | 712 | |
c5e3b741 | 713 | del_timer_sync(&uhci->fsbr_timer); |
1da177e4 LT |
714 | release_uhci(uhci); |
715 | } | |
716 | ||
717 | #ifdef CONFIG_PM | |
a8bed8b6 AS |
718 | static int uhci_rh_suspend(struct usb_hcd *hcd) |
719 | { | |
720 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
be3cbc5f | 721 | int rc = 0; |
a8bed8b6 AS |
722 | |
723 | spin_lock_irq(&uhci->lock); | |
be3cbc5f DB |
724 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) |
725 | rc = -ESHUTDOWN; | |
e323de46 | 726 | else if (!uhci->dead) |
4daaa87c | 727 | suspend_rh(uhci, UHCI_RH_SUSPENDED); |
a8bed8b6 | 728 | spin_unlock_irq(&uhci->lock); |
be3cbc5f | 729 | return rc; |
a8bed8b6 AS |
730 | } |
731 | ||
732 | static int uhci_rh_resume(struct usb_hcd *hcd) | |
733 | { | |
734 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 735 | int rc = 0; |
a8bed8b6 AS |
736 | |
737 | spin_lock_irq(&uhci->lock); | |
be3cbc5f DB |
738 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
739 | dev_warn(&hcd->self.root_hub->dev, "HC isn't running!\n"); | |
740 | rc = -ESHUTDOWN; | |
e323de46 | 741 | } else if (!uhci->dead) |
4daaa87c | 742 | wakeup_rh(uhci); |
a8bed8b6 | 743 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 744 | return rc; |
a8bed8b6 AS |
745 | } |
746 | ||
9a5d3e98 | 747 | static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message) |
1da177e4 LT |
748 | { |
749 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 750 | int rc = 0; |
1da177e4 | 751 | |
a8bed8b6 AS |
752 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
753 | ||
1da177e4 | 754 | spin_lock_irq(&uhci->lock); |
e323de46 AS |
755 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) || uhci->dead) |
756 | goto done_okay; /* Already suspended or dead */ | |
a8bed8b6 | 757 | |
4daaa87c AS |
758 | if (uhci->rh_state > UHCI_RH_SUSPENDED) { |
759 | dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n"); | |
4daaa87c AS |
760 | rc = -EBUSY; |
761 | goto done; | |
762 | }; | |
763 | ||
a8bed8b6 AS |
764 | /* All PCI host controllers are required to disable IRQ generation |
765 | * at the source, so we must turn off PIRQ. | |
766 | */ | |
767 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0); | |
42245e65 | 768 | mb(); |
1f09df8b | 769 | hcd->poll_rh = 0; |
a8bed8b6 AS |
770 | |
771 | /* FIXME: Enable non-PME# remote wakeup? */ | |
772 | ||
18584999 DB |
773 | /* make sure snapshot being resumed re-enumerates everything */ |
774 | if (message.event == PM_EVENT_PRETHAW) | |
775 | uhci_hc_died(uhci); | |
776 | ||
e323de46 AS |
777 | done_okay: |
778 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
4daaa87c | 779 | done: |
1da177e4 | 780 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 781 | return rc; |
1da177e4 LT |
782 | } |
783 | ||
784 | static int uhci_resume(struct usb_hcd *hcd) | |
785 | { | |
786 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 787 | |
a8bed8b6 AS |
788 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
789 | ||
687f5f34 | 790 | /* Since we aren't in D3 any more, it's safe to set this flag |
e323de46 | 791 | * even if the controller was dead. |
8de98402 BH |
792 | */ |
793 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
42245e65 | 794 | mb(); |
8de98402 | 795 | |
1da177e4 | 796 | spin_lock_irq(&uhci->lock); |
1da177e4 | 797 | |
a8bed8b6 AS |
798 | /* FIXME: Disable non-PME# remote wakeup? */ |
799 | ||
e323de46 AS |
800 | /* The firmware or a boot kernel may have changed the controller |
801 | * settings during a system wakeup. Check it and reconfigure | |
802 | * to avoid problems. | |
a8bed8b6 AS |
803 | */ |
804 | check_and_reset_hc(uhci); | |
e323de46 AS |
805 | |
806 | /* If the controller was dead before, it's back alive now */ | |
a8bed8b6 AS |
807 | configure_hc(uhci); |
808 | ||
1c50c317 AS |
809 | if (uhci->rh_state == UHCI_RH_RESET) { |
810 | ||
811 | /* The controller had to be reset */ | |
812 | usb_root_hub_lost_power(hcd->self.root_hub); | |
a8bed8b6 | 813 | suspend_rh(uhci, UHCI_RH_SUSPENDED); |
1c50c317 | 814 | } |
c8f4fe43 | 815 | |
a8bed8b6 | 816 | spin_unlock_irq(&uhci->lock); |
6c1b445c | 817 | |
1f09df8b AS |
818 | if (!uhci->working_RD) { |
819 | /* Suspended root hub needs to be polled */ | |
820 | hcd->poll_rh = 1; | |
6c1b445c | 821 | usb_hcd_poll_rh_status(hcd); |
1f09df8b | 822 | } |
1da177e4 LT |
823 | return 0; |
824 | } | |
825 | #endif | |
826 | ||
dccf4a48 | 827 | /* Wait until a particular device/endpoint's QH is idle, and free it */ |
1da177e4 | 828 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, |
dccf4a48 | 829 | struct usb_host_endpoint *hep) |
1da177e4 LT |
830 | { |
831 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
dccf4a48 AS |
832 | struct uhci_qh *qh; |
833 | ||
834 | spin_lock_irq(&uhci->lock); | |
835 | qh = (struct uhci_qh *) hep->hcpriv; | |
836 | if (qh == NULL) | |
837 | goto done; | |
1da177e4 | 838 | |
dccf4a48 AS |
839 | while (qh->state != QH_STATE_IDLE) { |
840 | ++uhci->num_waiting; | |
841 | spin_unlock_irq(&uhci->lock); | |
842 | wait_event_interruptible(uhci->waitqh, | |
843 | qh->state == QH_STATE_IDLE); | |
844 | spin_lock_irq(&uhci->lock); | |
845 | --uhci->num_waiting; | |
846 | } | |
847 | ||
848 | uhci_free_qh(uhci, qh); | |
849 | done: | |
850 | spin_unlock_irq(&uhci->lock); | |
1da177e4 LT |
851 | } |
852 | ||
853 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
854 | { | |
855 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c4334726 AS |
856 | unsigned frame_number; |
857 | unsigned delta; | |
1da177e4 LT |
858 | |
859 | /* Minimize latency by avoiding the spinlock */ | |
c4334726 AS |
860 | frame_number = uhci->frame_number; |
861 | barrier(); | |
862 | delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) & | |
863 | (UHCI_NUMFRAMES - 1); | |
864 | return frame_number + delta; | |
1da177e4 LT |
865 | } |
866 | ||
867 | static const char hcd_name[] = "uhci_hcd"; | |
868 | ||
869 | static const struct hc_driver uhci_driver = { | |
870 | .description = hcd_name, | |
871 | .product_desc = "UHCI Host Controller", | |
872 | .hcd_priv_size = sizeof(struct uhci_hcd), | |
873 | ||
874 | /* Generic hardware linkage */ | |
875 | .irq = uhci_irq, | |
876 | .flags = HCD_USB11, | |
877 | ||
878 | /* Basic lifecycle operations */ | |
be3cbc5f | 879 | .reset = uhci_init, |
1da177e4 LT |
880 | .start = uhci_start, |
881 | #ifdef CONFIG_PM | |
882 | .suspend = uhci_suspend, | |
883 | .resume = uhci_resume, | |
0c0382e3 AS |
884 | .bus_suspend = uhci_rh_suspend, |
885 | .bus_resume = uhci_rh_resume, | |
1da177e4 LT |
886 | #endif |
887 | .stop = uhci_stop, | |
888 | ||
889 | .urb_enqueue = uhci_urb_enqueue, | |
890 | .urb_dequeue = uhci_urb_dequeue, | |
891 | ||
892 | .endpoint_disable = uhci_hcd_endpoint_disable, | |
893 | .get_frame_number = uhci_hcd_get_frame_number, | |
894 | ||
895 | .hub_status_data = uhci_hub_status_data, | |
896 | .hub_control = uhci_hub_control, | |
897 | }; | |
898 | ||
899 | static const struct pci_device_id uhci_pci_ids[] = { { | |
900 | /* handle any USB UHCI controller */ | |
c67808ee | 901 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0), |
1da177e4 LT |
902 | .driver_data = (unsigned long) &uhci_driver, |
903 | }, { /* end: all zeroes */ } | |
904 | }; | |
905 | ||
906 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | |
907 | ||
908 | static struct pci_driver uhci_pci_driver = { | |
909 | .name = (char *)hcd_name, | |
910 | .id_table = uhci_pci_ids, | |
911 | ||
912 | .probe = usb_hcd_pci_probe, | |
913 | .remove = usb_hcd_pci_remove, | |
02597d2d | 914 | .shutdown = uhci_shutdown, |
1da177e4 LT |
915 | |
916 | #ifdef CONFIG_PM | |
917 | .suspend = usb_hcd_pci_suspend, | |
918 | .resume = usb_hcd_pci_resume, | |
919 | #endif /* PM */ | |
920 | }; | |
921 | ||
922 | static int __init uhci_hcd_init(void) | |
923 | { | |
924 | int retval = -ENOMEM; | |
925 | ||
5f8364b7 AS |
926 | printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "%s\n", |
927 | ignore_oc ? ", overcurrent ignored" : ""); | |
1da177e4 LT |
928 | |
929 | if (usb_disabled()) | |
930 | return -ENODEV; | |
931 | ||
8d402e1a | 932 | if (DEBUG_CONFIGURED) { |
1da177e4 LT |
933 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); |
934 | if (!errbuf) | |
935 | goto errbuf_failed; | |
8d402e1a AS |
936 | uhci_debugfs_root = debugfs_create_dir("uhci", NULL); |
937 | if (!uhci_debugfs_root) | |
938 | goto debug_failed; | |
1da177e4 LT |
939 | } |
940 | ||
1da177e4 LT |
941 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", |
942 | sizeof(struct urb_priv), 0, 0, NULL, NULL); | |
943 | if (!uhci_up_cachep) | |
944 | goto up_failed; | |
945 | ||
946 | retval = pci_register_driver(&uhci_pci_driver); | |
947 | if (retval) | |
948 | goto init_failed; | |
949 | ||
950 | return 0; | |
951 | ||
952 | init_failed: | |
1a1d92c1 | 953 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 LT |
954 | |
955 | up_failed: | |
956 | debugfs_remove(uhci_debugfs_root); | |
957 | ||
958 | debug_failed: | |
1bc3c9e1 | 959 | kfree(errbuf); |
1da177e4 LT |
960 | |
961 | errbuf_failed: | |
962 | ||
963 | return retval; | |
964 | } | |
965 | ||
966 | static void __exit uhci_hcd_cleanup(void) | |
967 | { | |
968 | pci_unregister_driver(&uhci_pci_driver); | |
1a1d92c1 | 969 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 | 970 | debugfs_remove(uhci_debugfs_root); |
1bc3c9e1 | 971 | kfree(errbuf); |
1da177e4 LT |
972 | } |
973 | ||
974 | module_init(uhci_hcd_init); | |
975 | module_exit(uhci_hcd_cleanup); | |
976 | ||
977 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
978 | MODULE_DESCRIPTION(DRIVER_DESC); | |
979 | MODULE_LICENSE("GPL"); |