Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
b761d9d8 | 16 | * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | */ |
18 | ||
1da177e4 LT |
19 | |
20 | /* | |
21 | * Technically, updating td->status here is a race, but it's not really a | |
22 | * problem. The worst that can happen is that we set the IOC bit again | |
23 | * generating a spurious interrupt. We could fix this by creating another | |
24 | * QH and leaving the IOC bit always set, but then we would have to play | |
25 | * games with the FSBR code to make sure we get the correct order in all | |
26 | * the cases. I don't think it's worth the effort | |
27 | */ | |
dccf4a48 | 28 | static void uhci_set_next_interrupt(struct uhci_hcd *uhci) |
1da177e4 | 29 | { |
6c1b445c | 30 | if (uhci->is_stopped) |
1f09df8b | 31 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); |
1da177e4 LT |
32 | uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC); |
33 | } | |
34 | ||
35 | static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci) | |
36 | { | |
37 | uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC); | |
38 | } | |
39 | ||
84afddd7 AS |
40 | |
41 | /* | |
42 | * Full-Speed Bandwidth Reclamation (FSBR). | |
43 | * We turn on FSBR whenever a queue that wants it is advancing, | |
44 | * and leave it on for a short time thereafter. | |
45 | */ | |
46 | static void uhci_fsbr_on(struct uhci_hcd *uhci) | |
47 | { | |
48 | uhci->fsbr_is_on = 1; | |
49 | uhci->skel_term_qh->link = cpu_to_le32( | |
50 | uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH; | |
51 | } | |
52 | ||
53 | static void uhci_fsbr_off(struct uhci_hcd *uhci) | |
54 | { | |
55 | uhci->fsbr_is_on = 0; | |
56 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
57 | } | |
58 | ||
59 | static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb) | |
60 | { | |
61 | struct urb_priv *urbp = urb->hcpriv; | |
62 | ||
63 | if (!(urb->transfer_flags & URB_NO_FSBR)) | |
64 | urbp->fsbr = 1; | |
65 | } | |
66 | ||
c5e3b741 | 67 | static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp) |
84afddd7 | 68 | { |
84afddd7 | 69 | if (urbp->fsbr) { |
c5e3b741 | 70 | uhci->fsbr_is_wanted = 1; |
84afddd7 AS |
71 | if (!uhci->fsbr_is_on) |
72 | uhci_fsbr_on(uhci); | |
c5e3b741 AS |
73 | else if (uhci->fsbr_expiring) { |
74 | uhci->fsbr_expiring = 0; | |
75 | del_timer(&uhci->fsbr_timer); | |
76 | } | |
77 | } | |
78 | } | |
79 | ||
80 | static void uhci_fsbr_timeout(unsigned long _uhci) | |
81 | { | |
82 | struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci; | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&uhci->lock, flags); | |
86 | if (uhci->fsbr_expiring) { | |
87 | uhci->fsbr_expiring = 0; | |
88 | uhci_fsbr_off(uhci); | |
84afddd7 | 89 | } |
c5e3b741 | 90 | spin_unlock_irqrestore(&uhci->lock, flags); |
84afddd7 AS |
91 | } |
92 | ||
93 | ||
2532178a | 94 | static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci) |
1da177e4 LT |
95 | { |
96 | dma_addr_t dma_handle; | |
97 | struct uhci_td *td; | |
98 | ||
99 | td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle); | |
100 | if (!td) | |
101 | return NULL; | |
102 | ||
103 | td->dma_handle = dma_handle; | |
1da177e4 | 104 | td->frame = -1; |
1da177e4 LT |
105 | |
106 | INIT_LIST_HEAD(&td->list); | |
1da177e4 LT |
107 | INIT_LIST_HEAD(&td->fl_list); |
108 | ||
1da177e4 LT |
109 | return td; |
110 | } | |
111 | ||
dccf4a48 AS |
112 | static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td) |
113 | { | |
114 | if (!list_empty(&td->list)) | |
115 | dev_warn(uhci_dev(uhci), "td %p still in list!\n", td); | |
dccf4a48 AS |
116 | if (!list_empty(&td->fl_list)) |
117 | dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td); | |
118 | ||
119 | dma_pool_free(uhci->td_pool, td, td->dma_handle); | |
120 | } | |
121 | ||
1da177e4 LT |
122 | static inline void uhci_fill_td(struct uhci_td *td, u32 status, |
123 | u32 token, u32 buffer) | |
124 | { | |
125 | td->status = cpu_to_le32(status); | |
126 | td->token = cpu_to_le32(token); | |
127 | td->buffer = cpu_to_le32(buffer); | |
128 | } | |
129 | ||
04538a25 AS |
130 | static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp) |
131 | { | |
132 | list_add_tail(&td->list, &urbp->td_list); | |
133 | } | |
134 | ||
135 | static void uhci_remove_td_from_urbp(struct uhci_td *td) | |
136 | { | |
137 | list_del_init(&td->list); | |
138 | } | |
139 | ||
1da177e4 | 140 | /* |
687f5f34 | 141 | * We insert Isochronous URBs directly into the frame list at the beginning |
1da177e4 | 142 | */ |
dccf4a48 AS |
143 | static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci, |
144 | struct uhci_td *td, unsigned framenum) | |
1da177e4 LT |
145 | { |
146 | framenum &= (UHCI_NUMFRAMES - 1); | |
147 | ||
148 | td->frame = framenum; | |
149 | ||
150 | /* Is there a TD already mapped there? */ | |
a1d59ce8 | 151 | if (uhci->frame_cpu[framenum]) { |
1da177e4 LT |
152 | struct uhci_td *ftd, *ltd; |
153 | ||
a1d59ce8 | 154 | ftd = uhci->frame_cpu[framenum]; |
1da177e4 LT |
155 | ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list); |
156 | ||
157 | list_add_tail(&td->fl_list, &ftd->fl_list); | |
158 | ||
159 | td->link = ltd->link; | |
160 | wmb(); | |
161 | ltd->link = cpu_to_le32(td->dma_handle); | |
162 | } else { | |
a1d59ce8 | 163 | td->link = uhci->frame[framenum]; |
1da177e4 | 164 | wmb(); |
a1d59ce8 AS |
165 | uhci->frame[framenum] = cpu_to_le32(td->dma_handle); |
166 | uhci->frame_cpu[framenum] = td; | |
1da177e4 LT |
167 | } |
168 | } | |
169 | ||
dccf4a48 | 170 | static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci, |
b81d3436 | 171 | struct uhci_td *td) |
1da177e4 LT |
172 | { |
173 | /* If it's not inserted, don't remove it */ | |
b81d3436 AS |
174 | if (td->frame == -1) { |
175 | WARN_ON(!list_empty(&td->fl_list)); | |
1da177e4 | 176 | return; |
b81d3436 | 177 | } |
1da177e4 | 178 | |
b81d3436 | 179 | if (uhci->frame_cpu[td->frame] == td) { |
1da177e4 | 180 | if (list_empty(&td->fl_list)) { |
a1d59ce8 AS |
181 | uhci->frame[td->frame] = td->link; |
182 | uhci->frame_cpu[td->frame] = NULL; | |
1da177e4 LT |
183 | } else { |
184 | struct uhci_td *ntd; | |
185 | ||
186 | ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list); | |
a1d59ce8 AS |
187 | uhci->frame[td->frame] = cpu_to_le32(ntd->dma_handle); |
188 | uhci->frame_cpu[td->frame] = ntd; | |
1da177e4 LT |
189 | } |
190 | } else { | |
191 | struct uhci_td *ptd; | |
192 | ||
193 | ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list); | |
194 | ptd->link = td->link; | |
195 | } | |
196 | ||
1da177e4 LT |
197 | list_del_init(&td->fl_list); |
198 | td->frame = -1; | |
199 | } | |
200 | ||
c8155cc5 AS |
201 | static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci, |
202 | unsigned int framenum) | |
203 | { | |
204 | struct uhci_td *ftd, *ltd; | |
205 | ||
206 | framenum &= (UHCI_NUMFRAMES - 1); | |
207 | ||
208 | ftd = uhci->frame_cpu[framenum]; | |
209 | if (ftd) { | |
210 | ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list); | |
211 | uhci->frame[framenum] = ltd->link; | |
212 | uhci->frame_cpu[framenum] = NULL; | |
213 | ||
214 | while (!list_empty(&ftd->fl_list)) | |
215 | list_del_init(ftd->fl_list.prev); | |
216 | } | |
217 | } | |
218 | ||
dccf4a48 AS |
219 | /* |
220 | * Remove all the TDs for an Isochronous URB from the frame list | |
221 | */ | |
222 | static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb) | |
b81d3436 AS |
223 | { |
224 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; | |
225 | struct uhci_td *td; | |
226 | ||
227 | list_for_each_entry(td, &urbp->td_list, list) | |
dccf4a48 | 228 | uhci_remove_td_from_frame_list(uhci, td); |
b81d3436 AS |
229 | } |
230 | ||
dccf4a48 AS |
231 | static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci, |
232 | struct usb_device *udev, struct usb_host_endpoint *hep) | |
1da177e4 LT |
233 | { |
234 | dma_addr_t dma_handle; | |
235 | struct uhci_qh *qh; | |
236 | ||
237 | qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle); | |
238 | if (!qh) | |
239 | return NULL; | |
240 | ||
59e29ed9 | 241 | memset(qh, 0, sizeof(*qh)); |
1da177e4 LT |
242 | qh->dma_handle = dma_handle; |
243 | ||
244 | qh->element = UHCI_PTR_TERM; | |
245 | qh->link = UHCI_PTR_TERM; | |
246 | ||
dccf4a48 AS |
247 | INIT_LIST_HEAD(&qh->queue); |
248 | INIT_LIST_HEAD(&qh->node); | |
1da177e4 | 249 | |
dccf4a48 | 250 | if (udev) { /* Normal QH */ |
af0bb599 AS |
251 | qh->dummy_td = uhci_alloc_td(uhci); |
252 | if (!qh->dummy_td) { | |
253 | dma_pool_free(uhci->qh_pool, qh, dma_handle); | |
254 | return NULL; | |
255 | } | |
dccf4a48 AS |
256 | qh->state = QH_STATE_IDLE; |
257 | qh->hep = hep; | |
258 | qh->udev = udev; | |
259 | hep->hcpriv = qh; | |
4de7d2c2 | 260 | qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
1da177e4 | 261 | |
dccf4a48 AS |
262 | } else { /* Skeleton QH */ |
263 | qh->state = QH_STATE_ACTIVE; | |
4de7d2c2 | 264 | qh->type = -1; |
dccf4a48 | 265 | } |
1da177e4 LT |
266 | return qh; |
267 | } | |
268 | ||
269 | static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
270 | { | |
dccf4a48 AS |
271 | WARN_ON(qh->state != QH_STATE_IDLE && qh->udev); |
272 | if (!list_empty(&qh->queue)) | |
1da177e4 | 273 | dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh); |
1da177e4 | 274 | |
dccf4a48 AS |
275 | list_del(&qh->node); |
276 | if (qh->udev) { | |
277 | qh->hep->hcpriv = NULL; | |
af0bb599 | 278 | uhci_free_td(uhci, qh->dummy_td); |
dccf4a48 | 279 | } |
1da177e4 LT |
280 | dma_pool_free(uhci->qh_pool, qh, qh->dma_handle); |
281 | } | |
282 | ||
0ed8fee1 | 283 | /* |
a0b458b6 AS |
284 | * When a queue is stopped and a dequeued URB is given back, adjust |
285 | * the previous TD link (if the URB isn't first on the queue) or | |
286 | * save its toggle value (if it is first and is currently executing). | |
10b8e47d AS |
287 | * |
288 | * Returns 0 if the URB should not yet be given back, 1 otherwise. | |
0ed8fee1 | 289 | */ |
10b8e47d | 290 | static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh, |
a0b458b6 | 291 | struct urb *urb) |
0ed8fee1 | 292 | { |
a0b458b6 | 293 | struct urb_priv *urbp = urb->hcpriv; |
0ed8fee1 | 294 | struct uhci_td *td; |
10b8e47d | 295 | int ret = 1; |
0ed8fee1 | 296 | |
a0b458b6 | 297 | /* Isochronous pipes don't use toggles and their TD link pointers |
10b8e47d AS |
298 | * get adjusted during uhci_urb_dequeue(). But since their queues |
299 | * cannot truly be stopped, we have to watch out for dequeues | |
300 | * occurring after the nominal unlink frame. */ | |
301 | if (qh->type == USB_ENDPOINT_XFER_ISOC) { | |
302 | ret = (uhci->frame_number + uhci->is_stopped != | |
303 | qh->unlink_frame); | |
c5e3b741 | 304 | goto done; |
10b8e47d | 305 | } |
a0b458b6 AS |
306 | |
307 | /* If the URB isn't first on its queue, adjust the link pointer | |
308 | * of the last TD in the previous URB. The toggle doesn't need | |
309 | * to be saved since this URB can't be executing yet. */ | |
310 | if (qh->queue.next != &urbp->node) { | |
311 | struct urb_priv *purbp; | |
312 | struct uhci_td *ptd; | |
313 | ||
314 | purbp = list_entry(urbp->node.prev, struct urb_priv, node); | |
315 | WARN_ON(list_empty(&purbp->td_list)); | |
316 | ptd = list_entry(purbp->td_list.prev, struct uhci_td, | |
317 | list); | |
318 | td = list_entry(urbp->td_list.prev, struct uhci_td, | |
319 | list); | |
320 | ptd->link = td->link; | |
c5e3b741 | 321 | goto done; |
a0b458b6 AS |
322 | } |
323 | ||
0ed8fee1 AS |
324 | /* If the QH element pointer is UHCI_PTR_TERM then then currently |
325 | * executing URB has already been unlinked, so this one isn't it. */ | |
a0b458b6 | 326 | if (qh_element(qh) == UHCI_PTR_TERM) |
c5e3b741 | 327 | goto done; |
0ed8fee1 AS |
328 | qh->element = UHCI_PTR_TERM; |
329 | ||
a0b458b6 AS |
330 | /* Control pipes have to worry about toggles */ |
331 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) | |
c5e3b741 | 332 | goto done; |
0ed8fee1 | 333 | |
a0b458b6 | 334 | /* Save the next toggle value */ |
59e29ed9 AS |
335 | WARN_ON(list_empty(&urbp->td_list)); |
336 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
337 | qh->needs_fixup = 1; | |
338 | qh->initial_toggle = uhci_toggle(td_token(td)); | |
c5e3b741 AS |
339 | |
340 | done: | |
10b8e47d | 341 | return ret; |
0ed8fee1 AS |
342 | } |
343 | ||
344 | /* | |
345 | * Fix up the data toggles for URBs in a queue, when one of them | |
346 | * terminates early (short transfer, error, or dequeued). | |
347 | */ | |
348 | static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first) | |
349 | { | |
350 | struct urb_priv *urbp = NULL; | |
351 | struct uhci_td *td; | |
352 | unsigned int toggle = qh->initial_toggle; | |
353 | unsigned int pipe; | |
354 | ||
355 | /* Fixups for a short transfer start with the second URB in the | |
356 | * queue (the short URB is the first). */ | |
357 | if (skip_first) | |
358 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
359 | ||
360 | /* When starting with the first URB, if the QH element pointer is | |
361 | * still valid then we know the URB's toggles are okay. */ | |
362 | else if (qh_element(qh) != UHCI_PTR_TERM) | |
363 | toggle = 2; | |
364 | ||
365 | /* Fix up the toggle for the URBs in the queue. Normally this | |
366 | * loop won't run more than once: When an error or short transfer | |
367 | * occurs, the queue usually gets emptied. */ | |
1393adb2 | 368 | urbp = list_prepare_entry(urbp, &qh->queue, node); |
0ed8fee1 AS |
369 | list_for_each_entry_continue(urbp, &qh->queue, node) { |
370 | ||
371 | /* If the first TD has the right toggle value, we don't | |
372 | * need to change any toggles in this URB */ | |
373 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
374 | if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) { | |
375 | td = list_entry(urbp->td_list.next, struct uhci_td, | |
376 | list); | |
377 | toggle = uhci_toggle(td_token(td)) ^ 1; | |
378 | ||
379 | /* Otherwise all the toggles in the URB have to be switched */ | |
380 | } else { | |
381 | list_for_each_entry(td, &urbp->td_list, list) { | |
382 | td->token ^= __constant_cpu_to_le32( | |
383 | TD_TOKEN_TOGGLE); | |
384 | toggle ^= 1; | |
385 | } | |
386 | } | |
387 | } | |
388 | ||
389 | wmb(); | |
390 | pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe; | |
391 | usb_settoggle(qh->udev, usb_pipeendpoint(pipe), | |
392 | usb_pipeout(pipe), toggle); | |
393 | qh->needs_fixup = 0; | |
394 | } | |
395 | ||
1da177e4 | 396 | /* |
dccf4a48 | 397 | * Put a QH on the schedule in both hardware and software |
1da177e4 | 398 | */ |
dccf4a48 | 399 | static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) |
1da177e4 | 400 | { |
dccf4a48 | 401 | struct uhci_qh *pqh; |
1da177e4 | 402 | |
dccf4a48 | 403 | WARN_ON(list_empty(&qh->queue)); |
1da177e4 | 404 | |
dccf4a48 AS |
405 | /* Set the element pointer if it isn't set already. |
406 | * This isn't needed for Isochronous queues, but it doesn't hurt. */ | |
407 | if (qh_element(qh) == UHCI_PTR_TERM) { | |
408 | struct urb_priv *urbp = list_entry(qh->queue.next, | |
409 | struct urb_priv, node); | |
410 | struct uhci_td *td = list_entry(urbp->td_list.next, | |
411 | struct uhci_td, list); | |
1da177e4 | 412 | |
dccf4a48 | 413 | qh->element = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
414 | } |
415 | ||
84afddd7 AS |
416 | /* Treat the queue as if it has just advanced */ |
417 | qh->wait_expired = 0; | |
418 | qh->advance_jiffies = jiffies; | |
419 | ||
dccf4a48 AS |
420 | if (qh->state == QH_STATE_ACTIVE) |
421 | return; | |
422 | qh->state = QH_STATE_ACTIVE; | |
423 | ||
424 | /* Move the QH from its old list to the end of the appropriate | |
425 | * skeleton's list */ | |
0ed8fee1 AS |
426 | if (qh == uhci->next_qh) |
427 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
428 | node); | |
dccf4a48 AS |
429 | list_move_tail(&qh->node, &qh->skel->node); |
430 | ||
431 | /* Link it into the schedule */ | |
432 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | |
433 | qh->link = pqh->link; | |
434 | wmb(); | |
435 | pqh->link = UHCI_PTR_QH | cpu_to_le32(qh->dma_handle); | |
1da177e4 LT |
436 | } |
437 | ||
438 | /* | |
dccf4a48 | 439 | * Take a QH off the hardware schedule |
1da177e4 | 440 | */ |
dccf4a48 | 441 | static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) |
1da177e4 LT |
442 | { |
443 | struct uhci_qh *pqh; | |
1da177e4 | 444 | |
dccf4a48 | 445 | if (qh->state == QH_STATE_UNLINKING) |
1da177e4 | 446 | return; |
dccf4a48 AS |
447 | WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev); |
448 | qh->state = QH_STATE_UNLINKING; | |
1da177e4 | 449 | |
dccf4a48 AS |
450 | /* Unlink the QH from the schedule and record when we did it */ |
451 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | |
452 | pqh->link = qh->link; | |
453 | mb(); | |
1da177e4 LT |
454 | |
455 | uhci_get_current_frame_number(uhci); | |
dccf4a48 | 456 | qh->unlink_frame = uhci->frame_number; |
1da177e4 | 457 | |
dccf4a48 AS |
458 | /* Force an interrupt so we know when the QH is fully unlinked */ |
459 | if (list_empty(&uhci->skel_unlink_qh->node)) | |
1da177e4 LT |
460 | uhci_set_next_interrupt(uhci); |
461 | ||
dccf4a48 | 462 | /* Move the QH from its old list to the end of the unlinking list */ |
0ed8fee1 AS |
463 | if (qh == uhci->next_qh) |
464 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
465 | node); | |
dccf4a48 | 466 | list_move_tail(&qh->node, &uhci->skel_unlink_qh->node); |
1da177e4 LT |
467 | } |
468 | ||
dccf4a48 AS |
469 | /* |
470 | * When we and the controller are through with a QH, it becomes IDLE. | |
471 | * This happens when a QH has been off the schedule (on the unlinking | |
472 | * list) for more than one frame, or when an error occurs while adding | |
473 | * the first URB onto a new QH. | |
474 | */ | |
475 | static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
1da177e4 | 476 | { |
dccf4a48 | 477 | WARN_ON(qh->state == QH_STATE_ACTIVE); |
1da177e4 | 478 | |
0ed8fee1 AS |
479 | if (qh == uhci->next_qh) |
480 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
481 | node); | |
dccf4a48 AS |
482 | list_move(&qh->node, &uhci->idle_qh_list); |
483 | qh->state = QH_STATE_IDLE; | |
1da177e4 | 484 | |
59e29ed9 AS |
485 | /* Now that the QH is idle, its post_td isn't being used */ |
486 | if (qh->post_td) { | |
487 | uhci_free_td(uhci, qh->post_td); | |
488 | qh->post_td = NULL; | |
489 | } | |
490 | ||
dccf4a48 AS |
491 | /* If anyone is waiting for a QH to become idle, wake them up */ |
492 | if (uhci->num_waiting) | |
493 | wake_up_all(&uhci->waitqh); | |
1da177e4 LT |
494 | } |
495 | ||
dccf4a48 AS |
496 | static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci, |
497 | struct urb *urb) | |
1da177e4 LT |
498 | { |
499 | struct urb_priv *urbp; | |
500 | ||
501 | urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC); | |
502 | if (!urbp) | |
503 | return NULL; | |
504 | ||
505 | memset((void *)urbp, 0, sizeof(*urbp)); | |
506 | ||
1da177e4 | 507 | urbp->urb = urb; |
dccf4a48 | 508 | urb->hcpriv = urbp; |
1da177e4 | 509 | |
dccf4a48 | 510 | INIT_LIST_HEAD(&urbp->node); |
1da177e4 | 511 | INIT_LIST_HEAD(&urbp->td_list); |
1da177e4 | 512 | |
1da177e4 LT |
513 | return urbp; |
514 | } | |
515 | ||
dccf4a48 AS |
516 | static void uhci_free_urb_priv(struct uhci_hcd *uhci, |
517 | struct urb_priv *urbp) | |
1da177e4 LT |
518 | { |
519 | struct uhci_td *td, *tmp; | |
1da177e4 | 520 | |
dccf4a48 AS |
521 | if (!list_empty(&urbp->node)) |
522 | dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n", | |
523 | urbp->urb); | |
1da177e4 | 524 | |
1da177e4 | 525 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
04538a25 AS |
526 | uhci_remove_td_from_urbp(td); |
527 | uhci_free_td(uhci, td); | |
1da177e4 LT |
528 | } |
529 | ||
dccf4a48 | 530 | urbp->urb->hcpriv = NULL; |
1da177e4 LT |
531 | kmem_cache_free(uhci_up_cachep, urbp); |
532 | } | |
533 | ||
1da177e4 LT |
534 | /* |
535 | * Map status to standard result codes | |
536 | * | |
537 | * <status> is (td_status(td) & 0xF60000), a.k.a. | |
538 | * uhci_status_bits(td_status(td)). | |
539 | * Note: <status> does not include the TD_CTRL_NAK bit. | |
540 | * <dir_out> is True for output TDs and False for input TDs. | |
541 | */ | |
542 | static int uhci_map_status(int status, int dir_out) | |
543 | { | |
544 | if (!status) | |
545 | return 0; | |
546 | if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */ | |
547 | return -EPROTO; | |
548 | if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */ | |
549 | if (dir_out) | |
550 | return -EPROTO; | |
551 | else | |
552 | return -EILSEQ; | |
553 | } | |
554 | if (status & TD_CTRL_BABBLE) /* Babble */ | |
555 | return -EOVERFLOW; | |
556 | if (status & TD_CTRL_DBUFERR) /* Buffer error */ | |
557 | return -ENOSR; | |
558 | if (status & TD_CTRL_STALLED) /* Stalled */ | |
559 | return -EPIPE; | |
1da177e4 LT |
560 | return 0; |
561 | } | |
562 | ||
563 | /* | |
564 | * Control transfers | |
565 | */ | |
dccf4a48 AS |
566 | static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, |
567 | struct uhci_qh *qh) | |
1da177e4 | 568 | { |
1da177e4 | 569 | struct uhci_td *td; |
1da177e4 | 570 | unsigned long destination, status; |
dccf4a48 | 571 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
1da177e4 LT |
572 | int len = urb->transfer_buffer_length; |
573 | dma_addr_t data = urb->transfer_dma; | |
dccf4a48 | 574 | __le32 *plink; |
04538a25 | 575 | struct urb_priv *urbp = urb->hcpriv; |
1da177e4 LT |
576 | |
577 | /* The "pipe" thing contains the destination in bits 8--18 */ | |
578 | destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; | |
579 | ||
af0bb599 AS |
580 | /* 3 errors, dummy TD remains inactive */ |
581 | status = uhci_maxerr(3); | |
1da177e4 LT |
582 | if (urb->dev->speed == USB_SPEED_LOW) |
583 | status |= TD_CTRL_LS; | |
584 | ||
585 | /* | |
586 | * Build the TD for the control request setup packet | |
587 | */ | |
af0bb599 | 588 | td = qh->dummy_td; |
04538a25 | 589 | uhci_add_td_to_urbp(td, urbp); |
fa346568 | 590 | uhci_fill_td(td, status, destination | uhci_explen(8), |
dccf4a48 AS |
591 | urb->setup_dma); |
592 | plink = &td->link; | |
af0bb599 | 593 | status |= TD_CTRL_ACTIVE; |
1da177e4 LT |
594 | |
595 | /* | |
596 | * If direction is "send", change the packet ID from SETUP (0x2D) | |
597 | * to OUT (0xE1). Else change it from SETUP to IN (0x69) and | |
598 | * set Short Packet Detect (SPD) for all data packets. | |
599 | */ | |
600 | if (usb_pipeout(urb->pipe)) | |
601 | destination ^= (USB_PID_SETUP ^ USB_PID_OUT); | |
602 | else { | |
603 | destination ^= (USB_PID_SETUP ^ USB_PID_IN); | |
604 | status |= TD_CTRL_SPD; | |
605 | } | |
606 | ||
607 | /* | |
687f5f34 | 608 | * Build the DATA TDs |
1da177e4 LT |
609 | */ |
610 | while (len > 0) { | |
dccf4a48 | 611 | int pktsze = min(len, maxsze); |
1da177e4 | 612 | |
2532178a | 613 | td = uhci_alloc_td(uhci); |
1da177e4 | 614 | if (!td) |
af0bb599 | 615 | goto nomem; |
dccf4a48 | 616 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
617 | |
618 | /* Alternate Data0/1 (start with Data1) */ | |
619 | destination ^= TD_TOKEN_TOGGLE; | |
620 | ||
04538a25 | 621 | uhci_add_td_to_urbp(td, urbp); |
fa346568 | 622 | uhci_fill_td(td, status, destination | uhci_explen(pktsze), |
dccf4a48 AS |
623 | data); |
624 | plink = &td->link; | |
1da177e4 LT |
625 | |
626 | data += pktsze; | |
627 | len -= pktsze; | |
628 | } | |
629 | ||
630 | /* | |
631 | * Build the final TD for control status | |
632 | */ | |
2532178a | 633 | td = uhci_alloc_td(uhci); |
1da177e4 | 634 | if (!td) |
af0bb599 | 635 | goto nomem; |
dccf4a48 | 636 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
637 | |
638 | /* | |
639 | * It's IN if the pipe is an output pipe or we're not expecting | |
640 | * data back. | |
641 | */ | |
642 | destination &= ~TD_TOKEN_PID_MASK; | |
643 | if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length) | |
644 | destination |= USB_PID_IN; | |
645 | else | |
646 | destination |= USB_PID_OUT; | |
647 | ||
648 | destination |= TD_TOKEN_TOGGLE; /* End in Data1 */ | |
649 | ||
650 | status &= ~TD_CTRL_SPD; | |
651 | ||
04538a25 | 652 | uhci_add_td_to_urbp(td, urbp); |
1da177e4 | 653 | uhci_fill_td(td, status | TD_CTRL_IOC, |
dccf4a48 | 654 | destination | uhci_explen(0), 0); |
af0bb599 AS |
655 | plink = &td->link; |
656 | ||
657 | /* | |
658 | * Build the new dummy TD and activate the old one | |
659 | */ | |
660 | td = uhci_alloc_td(uhci); | |
661 | if (!td) | |
662 | goto nomem; | |
663 | *plink = cpu_to_le32(td->dma_handle); | |
664 | ||
665 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | |
666 | wmb(); | |
667 | qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE); | |
668 | qh->dummy_td = td; | |
1da177e4 LT |
669 | |
670 | /* Low-speed transfers get a different queue, and won't hog the bus. | |
671 | * Also, some devices enumerate better without FSBR; the easiest way | |
672 | * to do that is to put URBs on the low-speed queue while the device | |
630aa3cf | 673 | * isn't in the CONFIGURED state. */ |
1da177e4 | 674 | if (urb->dev->speed == USB_SPEED_LOW || |
630aa3cf | 675 | urb->dev->state != USB_STATE_CONFIGURED) |
dccf4a48 | 676 | qh->skel = uhci->skel_ls_control_qh; |
1da177e4 | 677 | else { |
dccf4a48 | 678 | qh->skel = uhci->skel_fs_control_qh; |
84afddd7 | 679 | uhci_add_fsbr(uhci, urb); |
1da177e4 | 680 | } |
59e29ed9 AS |
681 | |
682 | urb->actual_length = -8; /* Account for the SETUP packet */ | |
dccf4a48 | 683 | return 0; |
af0bb599 AS |
684 | |
685 | nomem: | |
686 | /* Remove the dummy TD from the td_list so it doesn't get freed */ | |
04538a25 | 687 | uhci_remove_td_from_urbp(qh->dummy_td); |
af0bb599 | 688 | return -ENOMEM; |
1da177e4 LT |
689 | } |
690 | ||
1da177e4 LT |
691 | /* |
692 | * Common submit for bulk and interrupt | |
693 | */ | |
dccf4a48 AS |
694 | static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, |
695 | struct uhci_qh *qh) | |
1da177e4 LT |
696 | { |
697 | struct uhci_td *td; | |
1da177e4 | 698 | unsigned long destination, status; |
dccf4a48 | 699 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
1da177e4 | 700 | int len = urb->transfer_buffer_length; |
1da177e4 | 701 | dma_addr_t data = urb->transfer_dma; |
af0bb599 | 702 | __le32 *plink; |
04538a25 | 703 | struct urb_priv *urbp = urb->hcpriv; |
af0bb599 | 704 | unsigned int toggle; |
1da177e4 LT |
705 | |
706 | if (len < 0) | |
707 | return -EINVAL; | |
708 | ||
709 | /* The "pipe" thing contains the destination in bits 8--18 */ | |
710 | destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe); | |
af0bb599 AS |
711 | toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), |
712 | usb_pipeout(urb->pipe)); | |
1da177e4 | 713 | |
af0bb599 AS |
714 | /* 3 errors, dummy TD remains inactive */ |
715 | status = uhci_maxerr(3); | |
1da177e4 LT |
716 | if (urb->dev->speed == USB_SPEED_LOW) |
717 | status |= TD_CTRL_LS; | |
718 | if (usb_pipein(urb->pipe)) | |
719 | status |= TD_CTRL_SPD; | |
720 | ||
721 | /* | |
687f5f34 | 722 | * Build the DATA TDs |
1da177e4 | 723 | */ |
af0bb599 AS |
724 | plink = NULL; |
725 | td = qh->dummy_td; | |
1da177e4 LT |
726 | do { /* Allow zero length packets */ |
727 | int pktsze = maxsze; | |
728 | ||
dccf4a48 | 729 | if (len <= pktsze) { /* The last packet */ |
1da177e4 LT |
730 | pktsze = len; |
731 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
732 | status &= ~TD_CTRL_SPD; | |
733 | } | |
734 | ||
af0bb599 AS |
735 | if (plink) { |
736 | td = uhci_alloc_td(uhci); | |
737 | if (!td) | |
738 | goto nomem; | |
739 | *plink = cpu_to_le32(td->dma_handle); | |
740 | } | |
04538a25 | 741 | uhci_add_td_to_urbp(td, urbp); |
dccf4a48 | 742 | uhci_fill_td(td, status, |
af0bb599 AS |
743 | destination | uhci_explen(pktsze) | |
744 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | |
745 | data); | |
dccf4a48 | 746 | plink = &td->link; |
af0bb599 | 747 | status |= TD_CTRL_ACTIVE; |
1da177e4 LT |
748 | |
749 | data += pktsze; | |
750 | len -= maxsze; | |
af0bb599 | 751 | toggle ^= 1; |
1da177e4 LT |
752 | } while (len > 0); |
753 | ||
754 | /* | |
755 | * URB_ZERO_PACKET means adding a 0-length packet, if direction | |
756 | * is OUT and the transfer_length was an exact multiple of maxsze, | |
757 | * hence (len = transfer_length - N * maxsze) == 0 | |
758 | * however, if transfer_length == 0, the zero packet was already | |
759 | * prepared above. | |
760 | */ | |
dccf4a48 AS |
761 | if ((urb->transfer_flags & URB_ZERO_PACKET) && |
762 | usb_pipeout(urb->pipe) && len == 0 && | |
763 | urb->transfer_buffer_length > 0) { | |
2532178a | 764 | td = uhci_alloc_td(uhci); |
1da177e4 | 765 | if (!td) |
af0bb599 | 766 | goto nomem; |
dccf4a48 | 767 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 | 768 | |
04538a25 | 769 | uhci_add_td_to_urbp(td, urbp); |
af0bb599 AS |
770 | uhci_fill_td(td, status, |
771 | destination | uhci_explen(0) | | |
772 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | |
773 | data); | |
774 | plink = &td->link; | |
1da177e4 | 775 | |
af0bb599 | 776 | toggle ^= 1; |
1da177e4 LT |
777 | } |
778 | ||
779 | /* Set the interrupt-on-completion flag on the last packet. | |
780 | * A more-or-less typical 4 KB URB (= size of one memory page) | |
781 | * will require about 3 ms to transfer; that's a little on the | |
782 | * fast side but not enough to justify delaying an interrupt | |
783 | * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT | |
784 | * flag setting. */ | |
dccf4a48 | 785 | td->status |= __constant_cpu_to_le32(TD_CTRL_IOC); |
1da177e4 | 786 | |
af0bb599 AS |
787 | /* |
788 | * Build the new dummy TD and activate the old one | |
789 | */ | |
790 | td = uhci_alloc_td(uhci); | |
791 | if (!td) | |
792 | goto nomem; | |
793 | *plink = cpu_to_le32(td->dma_handle); | |
794 | ||
795 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | |
796 | wmb(); | |
797 | qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE); | |
798 | qh->dummy_td = td; | |
caf3827a | 799 | qh->period = urb->interval; |
af0bb599 AS |
800 | |
801 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | |
802 | usb_pipeout(urb->pipe), toggle); | |
dccf4a48 | 803 | return 0; |
af0bb599 AS |
804 | |
805 | nomem: | |
806 | /* Remove the dummy TD from the td_list so it doesn't get freed */ | |
04538a25 | 807 | uhci_remove_td_from_urbp(qh->dummy_td); |
af0bb599 | 808 | return -ENOMEM; |
1da177e4 LT |
809 | } |
810 | ||
dccf4a48 AS |
811 | static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb, |
812 | struct uhci_qh *qh) | |
1da177e4 LT |
813 | { |
814 | int ret; | |
815 | ||
816 | /* Can't have low-speed bulk transfers */ | |
817 | if (urb->dev->speed == USB_SPEED_LOW) | |
818 | return -EINVAL; | |
819 | ||
dccf4a48 AS |
820 | qh->skel = uhci->skel_bulk_qh; |
821 | ret = uhci_submit_common(uhci, urb, qh); | |
822 | if (ret == 0) | |
84afddd7 | 823 | uhci_add_fsbr(uhci, urb); |
1da177e4 LT |
824 | return ret; |
825 | } | |
826 | ||
caf3827a | 827 | static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb, |
dccf4a48 | 828 | struct uhci_qh *qh) |
1da177e4 | 829 | { |
caf3827a AS |
830 | int exponent; |
831 | ||
dccf4a48 AS |
832 | /* USB 1.1 interrupt transfers only involve one packet per interval. |
833 | * Drivers can submit URBs of any length, but longer ones will need | |
834 | * multiple intervals to complete. | |
1da177e4 | 835 | */ |
caf3827a AS |
836 | |
837 | /* Figure out which power-of-two queue to use */ | |
838 | for (exponent = 7; exponent >= 0; --exponent) { | |
839 | if ((1 << exponent) <= urb->interval) | |
840 | break; | |
841 | } | |
842 | if (exponent < 0) | |
843 | return -EINVAL; | |
844 | urb->interval = 1 << exponent; | |
845 | ||
846 | if (qh->period == 0) | |
847 | qh->skel = uhci->skelqh[UHCI_SKEL_INDEX(exponent)]; | |
848 | else if (qh->period != urb->interval) | |
849 | return -EINVAL; /* Can't change the period */ | |
850 | ||
dccf4a48 | 851 | return uhci_submit_common(uhci, urb, qh); |
1da177e4 LT |
852 | } |
853 | ||
b1869000 AS |
854 | /* |
855 | * Fix up the data structures following a short transfer | |
856 | */ | |
857 | static int uhci_fixup_short_transfer(struct uhci_hcd *uhci, | |
59e29ed9 | 858 | struct uhci_qh *qh, struct urb_priv *urbp) |
b1869000 AS |
859 | { |
860 | struct uhci_td *td; | |
59e29ed9 AS |
861 | struct list_head *tmp; |
862 | int ret; | |
b1869000 AS |
863 | |
864 | td = list_entry(urbp->td_list.prev, struct uhci_td, list); | |
865 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { | |
b1869000 AS |
866 | |
867 | /* When a control transfer is short, we have to restart | |
868 | * the queue at the status stage transaction, which is | |
869 | * the last TD. */ | |
59e29ed9 | 870 | WARN_ON(list_empty(&urbp->td_list)); |
b1869000 | 871 | qh->element = cpu_to_le32(td->dma_handle); |
59e29ed9 | 872 | tmp = td->list.prev; |
b1869000 AS |
873 | ret = -EINPROGRESS; |
874 | ||
59e29ed9 | 875 | } else { |
b1869000 AS |
876 | |
877 | /* When a bulk/interrupt transfer is short, we have to | |
878 | * fix up the toggles of the following URBs on the queue | |
879 | * before restarting the queue at the next URB. */ | |
59e29ed9 | 880 | qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1; |
b1869000 AS |
881 | uhci_fixup_toggles(qh, 1); |
882 | ||
59e29ed9 AS |
883 | if (list_empty(&urbp->td_list)) |
884 | td = qh->post_td; | |
b1869000 | 885 | qh->element = td->link; |
59e29ed9 AS |
886 | tmp = urbp->td_list.prev; |
887 | ret = 0; | |
b1869000 AS |
888 | } |
889 | ||
59e29ed9 AS |
890 | /* Remove all the TDs we skipped over, from tmp back to the start */ |
891 | while (tmp != &urbp->td_list) { | |
892 | td = list_entry(tmp, struct uhci_td, list); | |
893 | tmp = tmp->prev; | |
894 | ||
04538a25 AS |
895 | uhci_remove_td_from_urbp(td); |
896 | uhci_free_td(uhci, td); | |
59e29ed9 | 897 | } |
b1869000 AS |
898 | return ret; |
899 | } | |
900 | ||
901 | /* | |
902 | * Common result for control, bulk, and interrupt | |
903 | */ | |
904 | static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb) | |
905 | { | |
906 | struct urb_priv *urbp = urb->hcpriv; | |
907 | struct uhci_qh *qh = urbp->qh; | |
59e29ed9 | 908 | struct uhci_td *td, *tmp; |
b1869000 AS |
909 | unsigned status; |
910 | int ret = 0; | |
911 | ||
59e29ed9 | 912 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
b1869000 AS |
913 | unsigned int ctrlstat; |
914 | int len; | |
915 | ||
b1869000 AS |
916 | ctrlstat = td_status(td); |
917 | status = uhci_status_bits(ctrlstat); | |
918 | if (status & TD_CTRL_ACTIVE) | |
919 | return -EINPROGRESS; | |
920 | ||
921 | len = uhci_actual_length(ctrlstat); | |
922 | urb->actual_length += len; | |
923 | ||
924 | if (status) { | |
925 | ret = uhci_map_status(status, | |
926 | uhci_packetout(td_token(td))); | |
927 | if ((debug == 1 && ret != -EPIPE) || debug > 1) { | |
928 | /* Some debugging code */ | |
be3cbc5f | 929 | dev_dbg(&urb->dev->dev, |
b1869000 AS |
930 | "%s: failed with status %x\n", |
931 | __FUNCTION__, status); | |
932 | ||
933 | if (debug > 1 && errbuf) { | |
934 | /* Print the chain for debugging */ | |
935 | uhci_show_qh(urbp->qh, errbuf, | |
936 | ERRBUF_LEN, 0); | |
937 | lprintk(errbuf); | |
938 | } | |
939 | } | |
940 | ||
941 | } else if (len < uhci_expected_length(td_token(td))) { | |
942 | ||
943 | /* We received a short packet */ | |
944 | if (urb->transfer_flags & URB_SHORT_NOT_OK) | |
945 | ret = -EREMOTEIO; | |
946 | else if (ctrlstat & TD_CTRL_SPD) | |
947 | ret = 1; | |
948 | } | |
949 | ||
04538a25 | 950 | uhci_remove_td_from_urbp(td); |
59e29ed9 | 951 | if (qh->post_td) |
04538a25 | 952 | uhci_free_td(uhci, qh->post_td); |
59e29ed9 AS |
953 | qh->post_td = td; |
954 | ||
b1869000 AS |
955 | if (ret != 0) |
956 | goto err; | |
957 | } | |
958 | return ret; | |
959 | ||
960 | err: | |
961 | if (ret < 0) { | |
962 | /* In case a control transfer gets an error | |
963 | * during the setup stage */ | |
964 | urb->actual_length = max(urb->actual_length, 0); | |
965 | ||
966 | /* Note that the queue has stopped and save | |
967 | * the next toggle value */ | |
968 | qh->element = UHCI_PTR_TERM; | |
969 | qh->is_stopped = 1; | |
970 | qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL); | |
971 | qh->initial_toggle = uhci_toggle(td_token(td)) ^ | |
972 | (ret == -EREMOTEIO); | |
973 | ||
974 | } else /* Short packet received */ | |
59e29ed9 | 975 | ret = uhci_fixup_short_transfer(uhci, qh, urbp); |
b1869000 AS |
976 | return ret; |
977 | } | |
978 | ||
1da177e4 LT |
979 | /* |
980 | * Isochronous transfers | |
981 | */ | |
0ed8fee1 AS |
982 | static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb, |
983 | struct uhci_qh *qh) | |
1da177e4 | 984 | { |
0ed8fee1 AS |
985 | struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */ |
986 | int i, frame; | |
987 | unsigned long destination, status; | |
988 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; | |
1da177e4 | 989 | |
caf3827a AS |
990 | /* Values must not be too big (could overflow below) */ |
991 | if (urb->interval >= UHCI_NUMFRAMES || | |
992 | urb->number_of_packets >= UHCI_NUMFRAMES) | |
1da177e4 LT |
993 | return -EFBIG; |
994 | ||
caf3827a | 995 | /* Check the period and figure out the starting frame number */ |
caf3827a AS |
996 | if (qh->period == 0) { |
997 | if (urb->transfer_flags & URB_ISO_ASAP) { | |
c8155cc5 | 998 | uhci_get_current_frame_number(uhci); |
caf3827a AS |
999 | urb->start_frame = uhci->frame_number + 10; |
1000 | } else { | |
c8155cc5 | 1001 | i = urb->start_frame - uhci->last_iso_frame; |
caf3827a AS |
1002 | if (i <= 0 || i >= UHCI_NUMFRAMES) |
1003 | return -EINVAL; | |
1004 | } | |
1005 | } else if (qh->period != urb->interval) { | |
1006 | return -EINVAL; /* Can't change the period */ | |
1da177e4 | 1007 | |
caf3827a | 1008 | } else { /* Pick up where the last URB leaves off */ |
0ed8fee1 | 1009 | if (list_empty(&qh->queue)) { |
c8155cc5 | 1010 | frame = qh->iso_frame; |
caf3827a AS |
1011 | } else { |
1012 | struct urb *lurb; | |
0ed8fee1 | 1013 | |
caf3827a | 1014 | lurb = list_entry(qh->queue.prev, |
0ed8fee1 | 1015 | struct urb_priv, node)->urb; |
caf3827a AS |
1016 | frame = lurb->start_frame + |
1017 | lurb->number_of_packets * | |
1018 | lurb->interval; | |
0ed8fee1 | 1019 | } |
caf3827a AS |
1020 | if (urb->transfer_flags & URB_ISO_ASAP) |
1021 | urb->start_frame = frame; | |
c8155cc5 AS |
1022 | else if (urb->start_frame != frame) |
1023 | return -EINVAL; | |
1da177e4 | 1024 | } |
1da177e4 | 1025 | |
caf3827a | 1026 | /* Make sure we won't have to go too far into the future */ |
c8155cc5 | 1027 | if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES, |
caf3827a AS |
1028 | urb->start_frame + urb->number_of_packets * |
1029 | urb->interval)) | |
1030 | return -EFBIG; | |
1031 | ||
1032 | status = TD_CTRL_ACTIVE | TD_CTRL_IOS; | |
1033 | destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe); | |
1034 | ||
b81d3436 | 1035 | for (i = 0; i < urb->number_of_packets; i++) { |
2532178a | 1036 | td = uhci_alloc_td(uhci); |
1da177e4 LT |
1037 | if (!td) |
1038 | return -ENOMEM; | |
1039 | ||
04538a25 | 1040 | uhci_add_td_to_urbp(td, urbp); |
dccf4a48 AS |
1041 | uhci_fill_td(td, status, destination | |
1042 | uhci_explen(urb->iso_frame_desc[i].length), | |
1043 | urb->transfer_dma + | |
1044 | urb->iso_frame_desc[i].offset); | |
b81d3436 | 1045 | } |
1da177e4 | 1046 | |
dccf4a48 AS |
1047 | /* Set the interrupt-on-completion flag on the last packet. */ |
1048 | td->status |= __constant_cpu_to_le32(TD_CTRL_IOC); | |
1049 | ||
1050 | qh->skel = uhci->skel_iso_qh; | |
caf3827a | 1051 | qh->period = urb->interval; |
dccf4a48 AS |
1052 | |
1053 | /* Add the TDs to the frame list */ | |
b81d3436 AS |
1054 | frame = urb->start_frame; |
1055 | list_for_each_entry(td, &urbp->td_list, list) { | |
dccf4a48 | 1056 | uhci_insert_td_in_frame_list(uhci, td, frame); |
c8155cc5 AS |
1057 | frame += qh->period; |
1058 | } | |
1059 | ||
1060 | if (list_empty(&qh->queue)) { | |
1061 | qh->iso_packet_desc = &urb->iso_frame_desc[0]; | |
1062 | qh->iso_frame = urb->start_frame; | |
1063 | qh->iso_status = 0; | |
1da177e4 LT |
1064 | } |
1065 | ||
dccf4a48 | 1066 | return 0; |
1da177e4 LT |
1067 | } |
1068 | ||
1069 | static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb) | |
1070 | { | |
c8155cc5 AS |
1071 | struct uhci_td *td, *tmp; |
1072 | struct urb_priv *urbp = urb->hcpriv; | |
1073 | struct uhci_qh *qh = urbp->qh; | |
1da177e4 | 1074 | |
c8155cc5 AS |
1075 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
1076 | unsigned int ctrlstat; | |
1077 | int status; | |
1da177e4 | 1078 | int actlength; |
1da177e4 | 1079 | |
c8155cc5 | 1080 | if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame)) |
1da177e4 LT |
1081 | return -EINPROGRESS; |
1082 | ||
c8155cc5 AS |
1083 | uhci_remove_tds_from_frame(uhci, qh->iso_frame); |
1084 | ||
1085 | ctrlstat = td_status(td); | |
1086 | if (ctrlstat & TD_CTRL_ACTIVE) { | |
1087 | status = -EXDEV; /* TD was added too late? */ | |
1088 | } else { | |
1089 | status = uhci_map_status(uhci_status_bits(ctrlstat), | |
1090 | usb_pipeout(urb->pipe)); | |
1091 | actlength = uhci_actual_length(ctrlstat); | |
1092 | ||
1093 | urb->actual_length += actlength; | |
1094 | qh->iso_packet_desc->actual_length = actlength; | |
1095 | qh->iso_packet_desc->status = status; | |
1096 | } | |
1da177e4 | 1097 | |
1da177e4 LT |
1098 | if (status) { |
1099 | urb->error_count++; | |
c8155cc5 | 1100 | qh->iso_status = status; |
1da177e4 LT |
1101 | } |
1102 | ||
c8155cc5 AS |
1103 | uhci_remove_td_from_urbp(td); |
1104 | uhci_free_td(uhci, td); | |
1105 | qh->iso_frame += qh->period; | |
1106 | ++qh->iso_packet_desc; | |
1da177e4 | 1107 | } |
c8155cc5 | 1108 | return qh->iso_status; |
1da177e4 LT |
1109 | } |
1110 | ||
1da177e4 | 1111 | static int uhci_urb_enqueue(struct usb_hcd *hcd, |
dccf4a48 | 1112 | struct usb_host_endpoint *hep, |
55016f10 | 1113 | struct urb *urb, gfp_t mem_flags) |
1da177e4 LT |
1114 | { |
1115 | int ret; | |
1116 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1117 | unsigned long flags; | |
dccf4a48 AS |
1118 | struct urb_priv *urbp; |
1119 | struct uhci_qh *qh; | |
1da177e4 LT |
1120 | int bustime; |
1121 | ||
1122 | spin_lock_irqsave(&uhci->lock, flags); | |
1123 | ||
1124 | ret = urb->status; | |
1125 | if (ret != -EINPROGRESS) /* URB already unlinked! */ | |
dccf4a48 | 1126 | goto done; |
1da177e4 | 1127 | |
dccf4a48 AS |
1128 | ret = -ENOMEM; |
1129 | urbp = uhci_alloc_urb_priv(uhci, urb); | |
1130 | if (!urbp) | |
1131 | goto done; | |
1da177e4 | 1132 | |
dccf4a48 AS |
1133 | if (hep->hcpriv) |
1134 | qh = (struct uhci_qh *) hep->hcpriv; | |
1135 | else { | |
1136 | qh = uhci_alloc_qh(uhci, urb->dev, hep); | |
1137 | if (!qh) | |
1138 | goto err_no_qh; | |
1da177e4 | 1139 | } |
dccf4a48 | 1140 | urbp->qh = qh; |
1da177e4 | 1141 | |
4de7d2c2 AS |
1142 | switch (qh->type) { |
1143 | case USB_ENDPOINT_XFER_CONTROL: | |
dccf4a48 AS |
1144 | ret = uhci_submit_control(uhci, urb, qh); |
1145 | break; | |
4de7d2c2 | 1146 | case USB_ENDPOINT_XFER_BULK: |
dccf4a48 | 1147 | ret = uhci_submit_bulk(uhci, urb, qh); |
1da177e4 | 1148 | break; |
4de7d2c2 | 1149 | case USB_ENDPOINT_XFER_INT: |
dccf4a48 | 1150 | if (list_empty(&qh->queue)) { |
1da177e4 LT |
1151 | bustime = usb_check_bandwidth(urb->dev, urb); |
1152 | if (bustime < 0) | |
1153 | ret = bustime; | |
1154 | else { | |
dccf4a48 AS |
1155 | ret = uhci_submit_interrupt(uhci, urb, qh); |
1156 | if (ret == 0) | |
1da177e4 LT |
1157 | usb_claim_bandwidth(urb->dev, urb, bustime, 0); |
1158 | } | |
1159 | } else { /* inherit from parent */ | |
dccf4a48 AS |
1160 | struct urb_priv *eurbp; |
1161 | ||
1162 | eurbp = list_entry(qh->queue.prev, struct urb_priv, | |
1163 | node); | |
1164 | urb->bandwidth = eurbp->urb->bandwidth; | |
1165 | ret = uhci_submit_interrupt(uhci, urb, qh); | |
1da177e4 LT |
1166 | } |
1167 | break; | |
4de7d2c2 | 1168 | case USB_ENDPOINT_XFER_ISOC: |
c8155cc5 | 1169 | urb->error_count = 0; |
1da177e4 LT |
1170 | bustime = usb_check_bandwidth(urb->dev, urb); |
1171 | if (bustime < 0) { | |
1172 | ret = bustime; | |
1173 | break; | |
1174 | } | |
1175 | ||
dccf4a48 AS |
1176 | ret = uhci_submit_isochronous(uhci, urb, qh); |
1177 | if (ret == 0) | |
1da177e4 LT |
1178 | usb_claim_bandwidth(urb->dev, urb, bustime, 1); |
1179 | break; | |
1180 | } | |
dccf4a48 AS |
1181 | if (ret != 0) |
1182 | goto err_submit_failed; | |
1da177e4 | 1183 | |
dccf4a48 AS |
1184 | /* Add this URB to the QH */ |
1185 | urbp->qh = qh; | |
1186 | list_add_tail(&urbp->node, &qh->queue); | |
1da177e4 | 1187 | |
dccf4a48 AS |
1188 | /* If the new URB is the first and only one on this QH then either |
1189 | * the QH is new and idle or else it's unlinked and waiting to | |
2775562a AS |
1190 | * become idle, so we can activate it right away. But only if the |
1191 | * queue isn't stopped. */ | |
84afddd7 | 1192 | if (qh->queue.next == &urbp->node && !qh->is_stopped) { |
dccf4a48 | 1193 | uhci_activate_qh(uhci, qh); |
c5e3b741 | 1194 | uhci_urbp_wants_fsbr(uhci, urbp); |
84afddd7 | 1195 | } |
dccf4a48 AS |
1196 | goto done; |
1197 | ||
1198 | err_submit_failed: | |
1199 | if (qh->state == QH_STATE_IDLE) | |
1200 | uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */ | |
1da177e4 | 1201 | |
dccf4a48 AS |
1202 | err_no_qh: |
1203 | uhci_free_urb_priv(uhci, urbp); | |
1204 | ||
1205 | done: | |
1da177e4 LT |
1206 | spin_unlock_irqrestore(&uhci->lock, flags); |
1207 | return ret; | |
1208 | } | |
1209 | ||
0ed8fee1 AS |
1210 | static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) |
1211 | { | |
1212 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1213 | unsigned long flags; | |
1214 | struct urb_priv *urbp; | |
10b8e47d | 1215 | struct uhci_qh *qh; |
0ed8fee1 AS |
1216 | |
1217 | spin_lock_irqsave(&uhci->lock, flags); | |
1218 | urbp = urb->hcpriv; | |
1219 | if (!urbp) /* URB was never linked! */ | |
1220 | goto done; | |
10b8e47d | 1221 | qh = urbp->qh; |
0ed8fee1 AS |
1222 | |
1223 | /* Remove Isochronous TDs from the frame list ASAP */ | |
10b8e47d | 1224 | if (qh->type == USB_ENDPOINT_XFER_ISOC) { |
0ed8fee1 | 1225 | uhci_unlink_isochronous_tds(uhci, urb); |
10b8e47d AS |
1226 | mb(); |
1227 | ||
1228 | /* If the URB has already started, update the QH unlink time */ | |
1229 | uhci_get_current_frame_number(uhci); | |
1230 | if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number)) | |
1231 | qh->unlink_frame = uhci->frame_number; | |
1232 | } | |
1233 | ||
1234 | uhci_unlink_qh(uhci, qh); | |
0ed8fee1 AS |
1235 | |
1236 | done: | |
1237 | spin_unlock_irqrestore(&uhci->lock, flags); | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1da177e4 | 1241 | /* |
0ed8fee1 | 1242 | * Finish unlinking an URB and give it back |
1da177e4 | 1243 | */ |
0ed8fee1 AS |
1244 | static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh, |
1245 | struct urb *urb, struct pt_regs *regs) | |
1246 | __releases(uhci->lock) | |
1247 | __acquires(uhci->lock) | |
1da177e4 | 1248 | { |
dccf4a48 | 1249 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; |
1da177e4 | 1250 | |
c8155cc5 AS |
1251 | /* When giving back the first URB in an Isochronous queue, |
1252 | * reinitialize the QH's iso-related members for the next URB. */ | |
1253 | if (qh->type == USB_ENDPOINT_XFER_ISOC && | |
1254 | urbp->node.prev == &qh->queue && | |
1255 | urbp->node.next != &qh->queue) { | |
1256 | struct urb *nurb = list_entry(urbp->node.next, | |
1257 | struct urb_priv, node)->urb; | |
1258 | ||
1259 | qh->iso_packet_desc = &nurb->iso_frame_desc[0]; | |
1260 | qh->iso_frame = nurb->start_frame; | |
1261 | qh->iso_status = 0; | |
1262 | } | |
1da177e4 | 1263 | |
0ed8fee1 AS |
1264 | /* Take the URB off the QH's queue. If the queue is now empty, |
1265 | * this is a perfect time for a toggle fixup. */ | |
1266 | list_del_init(&urbp->node); | |
1267 | if (list_empty(&qh->queue) && qh->needs_fixup) { | |
1268 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | |
1269 | usb_pipeout(urb->pipe), qh->initial_toggle); | |
1270 | qh->needs_fixup = 0; | |
1271 | } | |
1272 | ||
0ed8fee1 | 1273 | uhci_free_urb_priv(uhci, urbp); |
1da177e4 | 1274 | |
4de7d2c2 AS |
1275 | switch (qh->type) { |
1276 | case USB_ENDPOINT_XFER_ISOC: | |
1da177e4 LT |
1277 | /* Release bandwidth for Interrupt or Isoc. transfers */ |
1278 | if (urb->bandwidth) | |
1279 | usb_release_bandwidth(urb->dev, urb, 1); | |
1da177e4 | 1280 | break; |
4de7d2c2 | 1281 | case USB_ENDPOINT_XFER_INT: |
1da177e4 LT |
1282 | /* Release bandwidth for Interrupt or Isoc. transfers */ |
1283 | /* Make sure we don't release if we have a queued URB */ | |
0ed8fee1 | 1284 | if (list_empty(&qh->queue) && urb->bandwidth) |
1da177e4 LT |
1285 | usb_release_bandwidth(urb->dev, urb, 0); |
1286 | else | |
1287 | /* bandwidth was passed on to queued URB, */ | |
1288 | /* so don't let usb_unlink_urb() release it */ | |
1289 | urb->bandwidth = 0; | |
1da177e4 | 1290 | break; |
1da177e4 LT |
1291 | } |
1292 | ||
0ed8fee1 AS |
1293 | spin_unlock(&uhci->lock); |
1294 | usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, regs); | |
1295 | spin_lock(&uhci->lock); | |
1da177e4 | 1296 | |
0ed8fee1 AS |
1297 | /* If the queue is now empty, we can unlink the QH and give up its |
1298 | * reserved bandwidth. */ | |
1299 | if (list_empty(&qh->queue)) { | |
1300 | uhci_unlink_qh(uhci, qh); | |
1da177e4 | 1301 | |
0ed8fee1 | 1302 | /* Bandwidth stuff not yet implemented */ |
caf3827a | 1303 | qh->period = 0; |
0ed8fee1 | 1304 | } |
dccf4a48 | 1305 | } |
1da177e4 | 1306 | |
dccf4a48 | 1307 | /* |
0ed8fee1 | 1308 | * Scan the URBs in a QH's queue |
dccf4a48 | 1309 | */ |
0ed8fee1 AS |
1310 | #define QH_FINISHED_UNLINKING(qh) \ |
1311 | (qh->state == QH_STATE_UNLINKING && \ | |
1312 | uhci->frame_number + uhci->is_stopped != qh->unlink_frame) | |
1da177e4 | 1313 | |
0ed8fee1 AS |
1314 | static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh, |
1315 | struct pt_regs *regs) | |
1da177e4 | 1316 | { |
1da177e4 | 1317 | struct urb_priv *urbp; |
0ed8fee1 AS |
1318 | struct urb *urb; |
1319 | int status; | |
1da177e4 | 1320 | |
0ed8fee1 AS |
1321 | while (!list_empty(&qh->queue)) { |
1322 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1323 | urb = urbp->urb; | |
1da177e4 | 1324 | |
b1869000 | 1325 | if (qh->type == USB_ENDPOINT_XFER_ISOC) |
0ed8fee1 | 1326 | status = uhci_result_isochronous(uhci, urb); |
b1869000 | 1327 | else |
0ed8fee1 | 1328 | status = uhci_result_common(uhci, urb); |
0ed8fee1 AS |
1329 | if (status == -EINPROGRESS) |
1330 | break; | |
1da177e4 | 1331 | |
0ed8fee1 AS |
1332 | spin_lock(&urb->lock); |
1333 | if (urb->status == -EINPROGRESS) /* Not dequeued */ | |
1334 | urb->status = status; | |
1335 | else | |
2775562a | 1336 | status = ECONNRESET; /* Not -ECONNRESET */ |
0ed8fee1 | 1337 | spin_unlock(&urb->lock); |
1da177e4 | 1338 | |
0ed8fee1 AS |
1339 | /* Dequeued but completed URBs can't be given back unless |
1340 | * the QH is stopped or has finished unlinking. */ | |
2775562a AS |
1341 | if (status == ECONNRESET) { |
1342 | if (QH_FINISHED_UNLINKING(qh)) | |
1343 | qh->is_stopped = 1; | |
1344 | else if (!qh->is_stopped) | |
1345 | return; | |
1346 | } | |
1da177e4 | 1347 | |
0ed8fee1 | 1348 | uhci_giveback_urb(uhci, qh, urb, regs); |
2775562a | 1349 | if (status < 0) |
0ed8fee1 AS |
1350 | break; |
1351 | } | |
1da177e4 | 1352 | |
0ed8fee1 AS |
1353 | /* If the QH is neither stopped nor finished unlinking (normal case), |
1354 | * our work here is done. */ | |
2775562a AS |
1355 | if (QH_FINISHED_UNLINKING(qh)) |
1356 | qh->is_stopped = 1; | |
1357 | else if (!qh->is_stopped) | |
0ed8fee1 | 1358 | return; |
1da177e4 | 1359 | |
0ed8fee1 | 1360 | /* Otherwise give back each of the dequeued URBs */ |
2775562a | 1361 | restart: |
0ed8fee1 AS |
1362 | list_for_each_entry(urbp, &qh->queue, node) { |
1363 | urb = urbp->urb; | |
1364 | if (urb->status != -EINPROGRESS) { | |
10b8e47d AS |
1365 | |
1366 | /* Fix up the TD links and save the toggles for | |
1367 | * non-Isochronous queues. For Isochronous queues, | |
1368 | * test for too-recent dequeues. */ | |
1369 | if (!uhci_cleanup_queue(uhci, qh, urb)) { | |
1370 | qh->is_stopped = 0; | |
1371 | return; | |
1372 | } | |
0ed8fee1 AS |
1373 | uhci_giveback_urb(uhci, qh, urb, regs); |
1374 | goto restart; | |
1375 | } | |
1376 | } | |
1377 | qh->is_stopped = 0; | |
1da177e4 | 1378 | |
0ed8fee1 AS |
1379 | /* There are no more dequeued URBs. If there are still URBs on the |
1380 | * queue, the QH can now be re-activated. */ | |
1381 | if (!list_empty(&qh->queue)) { | |
1382 | if (qh->needs_fixup) | |
1383 | uhci_fixup_toggles(qh, 0); | |
84afddd7 AS |
1384 | |
1385 | /* If the first URB on the queue wants FSBR but its time | |
1386 | * limit has expired, set the next TD to interrupt on | |
1387 | * completion before reactivating the QH. */ | |
1388 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1389 | if (urbp->fsbr && qh->wait_expired) { | |
1390 | struct uhci_td *td = list_entry(urbp->td_list.next, | |
1391 | struct uhci_td, list); | |
1392 | ||
1393 | td->status |= __cpu_to_le32(TD_CTRL_IOC); | |
1394 | } | |
1395 | ||
0ed8fee1 | 1396 | uhci_activate_qh(uhci, qh); |
1da177e4 LT |
1397 | } |
1398 | ||
0ed8fee1 AS |
1399 | /* The queue is empty. The QH can become idle if it is fully |
1400 | * unlinked. */ | |
1401 | else if (QH_FINISHED_UNLINKING(qh)) | |
1402 | uhci_make_qh_idle(uhci, qh); | |
1da177e4 LT |
1403 | } |
1404 | ||
84afddd7 AS |
1405 | /* |
1406 | * Check for queues that have made some forward progress. | |
1407 | * Returns 0 if the queue is not Isochronous, is ACTIVE, and | |
1408 | * has not advanced since last examined; 1 otherwise. | |
b761d9d8 AS |
1409 | * |
1410 | * Early Intel controllers have a bug which causes qh->element sometimes | |
1411 | * not to advance when a TD completes successfully. The queue remains | |
1412 | * stuck on the inactive completed TD. We detect such cases and advance | |
1413 | * the element pointer by hand. | |
84afddd7 AS |
1414 | */ |
1415 | static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
1416 | { | |
1417 | struct urb_priv *urbp = NULL; | |
1418 | struct uhci_td *td; | |
1419 | int ret = 1; | |
1420 | unsigned status; | |
1421 | ||
1422 | if (qh->type == USB_ENDPOINT_XFER_ISOC) | |
c5e3b741 | 1423 | goto done; |
84afddd7 AS |
1424 | |
1425 | /* Treat an UNLINKING queue as though it hasn't advanced. | |
1426 | * This is okay because reactivation will treat it as though | |
1427 | * it has advanced, and if it is going to become IDLE then | |
1428 | * this doesn't matter anyway. Furthermore it's possible | |
1429 | * for an UNLINKING queue not to have any URBs at all, or | |
1430 | * for its first URB not to have any TDs (if it was dequeued | |
1431 | * just as it completed). So it's not easy in any case to | |
1432 | * test whether such queues have advanced. */ | |
1433 | if (qh->state != QH_STATE_ACTIVE) { | |
1434 | urbp = NULL; | |
1435 | status = 0; | |
1436 | ||
1437 | } else { | |
1438 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1439 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
1440 | status = td_status(td); | |
1441 | if (!(status & TD_CTRL_ACTIVE)) { | |
1442 | ||
1443 | /* We're okay, the queue has advanced */ | |
1444 | qh->wait_expired = 0; | |
1445 | qh->advance_jiffies = jiffies; | |
c5e3b741 | 1446 | goto done; |
84afddd7 AS |
1447 | } |
1448 | ret = 0; | |
1449 | } | |
1450 | ||
1451 | /* The queue hasn't advanced; check for timeout */ | |
c5e3b741 AS |
1452 | if (qh->wait_expired) |
1453 | goto done; | |
1454 | ||
1455 | if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) { | |
b761d9d8 AS |
1456 | |
1457 | /* Detect the Intel bug and work around it */ | |
1458 | if (qh->post_td && qh_element(qh) == | |
1459 | cpu_to_le32(qh->post_td->dma_handle)) { | |
1460 | qh->element = qh->post_td->link; | |
1461 | qh->advance_jiffies = jiffies; | |
c5e3b741 AS |
1462 | ret = 1; |
1463 | goto done; | |
b761d9d8 AS |
1464 | } |
1465 | ||
84afddd7 AS |
1466 | qh->wait_expired = 1; |
1467 | ||
1468 | /* If the current URB wants FSBR, unlink it temporarily | |
1469 | * so that we can safely set the next TD to interrupt on | |
1470 | * completion. That way we'll know as soon as the queue | |
1471 | * starts moving again. */ | |
1472 | if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC)) | |
1473 | uhci_unlink_qh(uhci, qh); | |
c5e3b741 AS |
1474 | |
1475 | } else { | |
1476 | /* Unmoving but not-yet-expired queues keep FSBR alive */ | |
1477 | if (urbp) | |
1478 | uhci_urbp_wants_fsbr(uhci, urbp); | |
84afddd7 | 1479 | } |
c5e3b741 AS |
1480 | |
1481 | done: | |
84afddd7 AS |
1482 | return ret; |
1483 | } | |
1484 | ||
0ed8fee1 AS |
1485 | /* |
1486 | * Process events in the schedule, but only in one thread at a time | |
1487 | */ | |
1da177e4 LT |
1488 | static void uhci_scan_schedule(struct uhci_hcd *uhci, struct pt_regs *regs) |
1489 | { | |
0ed8fee1 AS |
1490 | int i; |
1491 | struct uhci_qh *qh; | |
1da177e4 LT |
1492 | |
1493 | /* Don't allow re-entrant calls */ | |
1494 | if (uhci->scan_in_progress) { | |
1495 | uhci->need_rescan = 1; | |
1496 | return; | |
1497 | } | |
1498 | uhci->scan_in_progress = 1; | |
84afddd7 | 1499 | rescan: |
1da177e4 | 1500 | uhci->need_rescan = 0; |
c5e3b741 | 1501 | uhci->fsbr_is_wanted = 0; |
1da177e4 | 1502 | |
6c1b445c | 1503 | uhci_clear_next_interrupt(uhci); |
1da177e4 | 1504 | uhci_get_current_frame_number(uhci); |
c8155cc5 | 1505 | uhci->cur_iso_frame = uhci->frame_number; |
1da177e4 | 1506 | |
0ed8fee1 AS |
1507 | /* Go through all the QH queues and process the URBs in each one */ |
1508 | for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) { | |
1509 | uhci->next_qh = list_entry(uhci->skelqh[i]->node.next, | |
1510 | struct uhci_qh, node); | |
1511 | while ((qh = uhci->next_qh) != uhci->skelqh[i]) { | |
1512 | uhci->next_qh = list_entry(qh->node.next, | |
1513 | struct uhci_qh, node); | |
84afddd7 AS |
1514 | |
1515 | if (uhci_advance_check(uhci, qh)) { | |
1516 | uhci_scan_qh(uhci, qh, regs); | |
c5e3b741 AS |
1517 | if (qh->state == QH_STATE_ACTIVE) { |
1518 | uhci_urbp_wants_fsbr(uhci, | |
1519 | list_entry(qh->queue.next, struct urb_priv, node)); | |
1520 | } | |
84afddd7 | 1521 | } |
0ed8fee1 | 1522 | } |
1da177e4 | 1523 | } |
1da177e4 | 1524 | |
c8155cc5 | 1525 | uhci->last_iso_frame = uhci->cur_iso_frame; |
1da177e4 LT |
1526 | if (uhci->need_rescan) |
1527 | goto rescan; | |
1528 | uhci->scan_in_progress = 0; | |
1529 | ||
c5e3b741 AS |
1530 | if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted && |
1531 | !uhci->fsbr_expiring) { | |
1532 | uhci->fsbr_expiring = 1; | |
1533 | mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY); | |
1534 | } | |
84afddd7 | 1535 | |
04538a25 | 1536 | if (list_empty(&uhci->skel_unlink_qh->node)) |
1da177e4 LT |
1537 | uhci_clear_next_interrupt(uhci); |
1538 | else | |
1539 | uhci_set_next_interrupt(uhci); | |
1da177e4 | 1540 | } |