Commit | Line | Data |
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0f2a7930 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <asm/unaligned.h> | |
24 | ||
25 | #include "xhci.h" | |
26 | ||
9777e3ce AX |
27 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
28 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ | |
29 | PORT_RC | PORT_PLC | PORT_PE) | |
30 | ||
4bbb0ace SS |
31 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, |
32 | struct usb_hub_descriptor *desc, int ports) | |
0f2a7930 | 33 | { |
0f2a7930 SS |
34 | u16 temp; |
35 | ||
0f2a7930 SS |
36 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
37 | desc->bHubContrCurrent = 0; | |
38 | ||
39 | desc->bNbrPorts = ports; | |
0f2a7930 SS |
40 | /* Ugh, these should be #defines, FIXME */ |
41 | /* Using table 11-13 in USB 2.0 spec. */ | |
42 | temp = 0; | |
43 | /* Bits 1:0 - support port power switching, or power always on */ | |
44 | if (HCC_PPC(xhci->hcc_params)) | |
45 | temp |= 0x0001; | |
46 | else | |
47 | temp |= 0x0002; | |
48 | /* Bit 2 - root hubs are not part of a compound device */ | |
49 | /* Bits 4:3 - individual port over current protection */ | |
50 | temp |= 0x0008; | |
51 | /* Bits 6:5 - no TTs in root ports */ | |
52 | /* Bit 7 - no port indicators */ | |
28ccd296 | 53 | desc->wHubCharacteristics = cpu_to_le16(temp); |
0f2a7930 SS |
54 | } |
55 | ||
4bbb0ace SS |
56 | /* Fill in the USB 2.0 roothub descriptor */ |
57 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
58 | struct usb_hub_descriptor *desc) | |
59 | { | |
60 | int ports; | |
61 | u16 temp; | |
62 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | |
63 | u32 portsc; | |
64 | unsigned int i; | |
65 | ||
66 | ports = xhci->num_usb2_ports; | |
67 | ||
68 | xhci_common_hub_descriptor(xhci, desc, ports); | |
69 | desc->bDescriptorType = 0x29; | |
70 | temp = 1 + (ports / 8); | |
71 | desc->bDescLength = 7 + 2 * temp; | |
72 | ||
73 | /* The Device Removable bits are reported on a byte granularity. | |
74 | * If the port doesn't exist within that byte, the bit is set to 0. | |
75 | */ | |
76 | memset(port_removable, 0, sizeof(port_removable)); | |
77 | for (i = 0; i < ports; i++) { | |
78 | portsc = xhci_readl(xhci, xhci->usb3_ports[i]); | |
79 | /* If a device is removable, PORTSC reports a 0, same as in the | |
80 | * hub descriptor DeviceRemovable bits. | |
81 | */ | |
82 | if (portsc & PORT_DEV_REMOVE) | |
83 | /* This math is hairy because bit 0 of DeviceRemovable | |
84 | * is reserved, and bit 1 is for port 1, etc. | |
85 | */ | |
86 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | |
87 | } | |
88 | ||
89 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | |
90 | * ports on it. The USB 2.0 specification says that there are two | |
91 | * variable length fields at the end of the hub descriptor: | |
92 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | |
93 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | |
94 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | |
95 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | |
96 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | |
97 | * set of ports that actually exist. | |
98 | */ | |
99 | memset(desc->u.hs.DeviceRemovable, 0xff, | |
100 | sizeof(desc->u.hs.DeviceRemovable)); | |
101 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | |
102 | sizeof(desc->u.hs.PortPwrCtrlMask)); | |
103 | ||
104 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | |
105 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | |
106 | sizeof(__u8)); | |
107 | } | |
108 | ||
109 | /* Fill in the USB 3.0 roothub descriptor */ | |
110 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
111 | struct usb_hub_descriptor *desc) | |
112 | { | |
113 | int ports; | |
114 | u16 port_removable; | |
115 | u32 portsc; | |
116 | unsigned int i; | |
117 | ||
118 | ports = xhci->num_usb3_ports; | |
119 | xhci_common_hub_descriptor(xhci, desc, ports); | |
120 | desc->bDescriptorType = 0x2a; | |
121 | desc->bDescLength = 12; | |
122 | ||
123 | /* header decode latency should be zero for roothubs, | |
124 | * see section 4.23.5.2. | |
125 | */ | |
126 | desc->u.ss.bHubHdrDecLat = 0; | |
127 | desc->u.ss.wHubDelay = 0; | |
128 | ||
129 | port_removable = 0; | |
130 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | |
131 | for (i = 0; i < ports; i++) { | |
132 | portsc = xhci_readl(xhci, xhci->usb3_ports[i]); | |
133 | if (portsc & PORT_DEV_REMOVE) | |
134 | port_removable |= 1 << (i + 1); | |
135 | } | |
136 | memset(&desc->u.ss.DeviceRemovable, | |
137 | (__force __u16) cpu_to_le16(port_removable), | |
138 | sizeof(__u16)); | |
139 | } | |
140 | ||
141 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
142 | struct usb_hub_descriptor *desc) | |
143 | { | |
144 | ||
145 | if (hcd->speed == HCD_USB3) | |
146 | xhci_usb3_hub_descriptor(hcd, xhci, desc); | |
147 | else | |
148 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | |
149 | ||
150 | } | |
151 | ||
0f2a7930 SS |
152 | static unsigned int xhci_port_speed(unsigned int port_status) |
153 | { | |
154 | if (DEV_LOWSPEED(port_status)) | |
288ead45 | 155 | return USB_PORT_STAT_LOW_SPEED; |
0f2a7930 | 156 | if (DEV_HIGHSPEED(port_status)) |
288ead45 | 157 | return USB_PORT_STAT_HIGH_SPEED; |
0f2a7930 SS |
158 | /* |
159 | * FIXME: Yes, we should check for full speed, but the core uses that as | |
160 | * a default in portspeed() in usb/core/hub.c (which is the only place | |
288ead45 | 161 | * USB_PORT_STAT_*_SPEED is used). |
0f2a7930 SS |
162 | */ |
163 | return 0; | |
164 | } | |
165 | ||
166 | /* | |
167 | * These bits are Read Only (RO) and should be saved and written to the | |
168 | * registers: 0, 3, 10:13, 30 | |
169 | * connect status, over-current status, port speed, and device removable. | |
170 | * connect status and port speed are also sticky - meaning they're in | |
171 | * the AUX well and they aren't changed by a hot, warm, or cold reset. | |
172 | */ | |
173 | #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) | |
174 | /* | |
175 | * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: | |
176 | * bits 5:8, 9, 14:15, 25:27 | |
177 | * link state, port power, port indicator state, "wake on" enable state | |
178 | */ | |
179 | #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) | |
180 | /* | |
181 | * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: | |
182 | * bit 4 (port reset) | |
183 | */ | |
184 | #define XHCI_PORT_RW1S ((1<<4)) | |
185 | /* | |
186 | * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: | |
187 | * bits 1, 17, 18, 19, 20, 21, 22, 23 | |
188 | * port enable/disable, and | |
189 | * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), | |
190 | * over-current, reset, link state, and L1 change | |
191 | */ | |
192 | #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) | |
193 | /* | |
194 | * Bit 16 is RW, and writing a '1' to it causes the link state control to be | |
195 | * latched in | |
196 | */ | |
197 | #define XHCI_PORT_RW ((1<<16)) | |
198 | /* | |
199 | * These bits are Reserved Zero (RsvdZ) and zero should be written to them: | |
200 | * bits 2, 24, 28:31 | |
201 | */ | |
202 | #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) | |
203 | ||
204 | /* | |
205 | * Given a port state, this function returns a value that would result in the | |
206 | * port being in the same state, if the value was written to the port status | |
207 | * control register. | |
208 | * Save Read Only (RO) bits and save read/write bits where | |
209 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
210 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
211 | */ | |
56192531 | 212 | u32 xhci_port_state_to_neutral(u32 state) |
0f2a7930 SS |
213 | { |
214 | /* Save read-only status and port state */ | |
215 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
216 | } | |
217 | ||
be88fe4f AX |
218 | /* |
219 | * find slot id based on port number. | |
f6ff0ac8 | 220 | * @port: The one-based port number from one of the two split roothubs. |
be88fe4f | 221 | */ |
5233630f SS |
222 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
223 | u16 port) | |
be88fe4f AX |
224 | { |
225 | int slot_id; | |
226 | int i; | |
f6ff0ac8 | 227 | enum usb_device_speed speed; |
be88fe4f AX |
228 | |
229 | slot_id = 0; | |
230 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
231 | if (!xhci->devs[i]) | |
232 | continue; | |
f6ff0ac8 SS |
233 | speed = xhci->devs[i]->udev->speed; |
234 | if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) | |
235 | && xhci->devs[i]->port == port) { | |
be88fe4f AX |
236 | slot_id = i; |
237 | break; | |
238 | } | |
239 | } | |
240 | ||
241 | return slot_id; | |
242 | } | |
243 | ||
244 | /* | |
245 | * Stop device | |
246 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | |
247 | * to complete. | |
248 | * suspend will set to 1, if suspend bit need to set in command. | |
249 | */ | |
250 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |
251 | { | |
252 | struct xhci_virt_device *virt_dev; | |
253 | struct xhci_command *cmd; | |
254 | unsigned long flags; | |
255 | int timeleft; | |
256 | int ret; | |
257 | int i; | |
258 | ||
259 | ret = 0; | |
260 | virt_dev = xhci->devs[slot_id]; | |
261 | cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
262 | if (!cmd) { | |
263 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
264 | return -ENOMEM; | |
265 | } | |
266 | ||
267 | spin_lock_irqsave(&xhci->lock, flags); | |
268 | for (i = LAST_EP_INDEX; i > 0; i--) { | |
269 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) | |
270 | xhci_queue_stop_endpoint(xhci, slot_id, i, suspend); | |
271 | } | |
272 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
273 | list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list); | |
274 | xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend); | |
275 | xhci_ring_cmd_db(xhci); | |
276 | spin_unlock_irqrestore(&xhci->lock, flags); | |
277 | ||
278 | /* Wait for last stop endpoint command to finish */ | |
279 | timeleft = wait_for_completion_interruptible_timeout( | |
280 | cmd->completion, | |
281 | USB_CTRL_SET_TIMEOUT); | |
282 | if (timeleft <= 0) { | |
283 | xhci_warn(xhci, "%s while waiting for stop endpoint command\n", | |
284 | timeleft == 0 ? "Timeout" : "Signal"); | |
285 | spin_lock_irqsave(&xhci->lock, flags); | |
286 | /* The timeout might have raced with the event ring handler, so | |
287 | * only delete from the list if the item isn't poisoned. | |
288 | */ | |
289 | if (cmd->cmd_list.next != LIST_POISON1) | |
290 | list_del(&cmd->cmd_list); | |
291 | spin_unlock_irqrestore(&xhci->lock, flags); | |
292 | ret = -ETIME; | |
293 | goto command_cleanup; | |
294 | } | |
295 | ||
296 | command_cleanup: | |
297 | xhci_free_command(xhci, cmd); | |
298 | return ret; | |
299 | } | |
300 | ||
301 | /* | |
302 | * Ring device, it rings the all doorbells unconditionally. | |
303 | */ | |
56192531 | 304 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) |
be88fe4f AX |
305 | { |
306 | int i; | |
307 | ||
308 | for (i = 0; i < LAST_EP_INDEX + 1; i++) | |
309 | if (xhci->devs[slot_id]->eps[i].ring && | |
310 | xhci->devs[slot_id]->eps[i].ring->dequeue) | |
311 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); | |
312 | ||
313 | return; | |
314 | } | |
315 | ||
f6ff0ac8 | 316 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
28ccd296 | 317 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
6219c047 | 318 | { |
6dd0a3a7 | 319 | /* Don't allow the USB core to disable SuperSpeed ports. */ |
f6ff0ac8 | 320 | if (hcd->speed == HCD_USB3) { |
6dd0a3a7 SS |
321 | xhci_dbg(xhci, "Ignoring request to disable " |
322 | "SuperSpeed port.\n"); | |
323 | return; | |
324 | } | |
325 | ||
6219c047 SS |
326 | /* Write 1 to disable the port */ |
327 | xhci_writel(xhci, port_status | PORT_PE, addr); | |
328 | port_status = xhci_readl(xhci, addr); | |
329 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", | |
330 | wIndex, port_status); | |
331 | } | |
332 | ||
34fb562a | 333 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
28ccd296 | 334 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
34fb562a SS |
335 | { |
336 | char *port_change_bit; | |
337 | u32 status; | |
338 | ||
339 | switch (wValue) { | |
340 | case USB_PORT_FEAT_C_RESET: | |
341 | status = PORT_RC; | |
342 | port_change_bit = "reset"; | |
343 | break; | |
a11496eb AX |
344 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
345 | status = PORT_WRC; | |
346 | port_change_bit = "warm(BH) reset"; | |
347 | break; | |
34fb562a SS |
348 | case USB_PORT_FEAT_C_CONNECTION: |
349 | status = PORT_CSC; | |
350 | port_change_bit = "connect"; | |
351 | break; | |
352 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
353 | status = PORT_OCC; | |
354 | port_change_bit = "over-current"; | |
355 | break; | |
6219c047 SS |
356 | case USB_PORT_FEAT_C_ENABLE: |
357 | status = PORT_PEC; | |
358 | port_change_bit = "enable/disable"; | |
359 | break; | |
be88fe4f AX |
360 | case USB_PORT_FEAT_C_SUSPEND: |
361 | status = PORT_PLC; | |
362 | port_change_bit = "suspend/resume"; | |
363 | break; | |
85387c0e AX |
364 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
365 | status = PORT_PLC; | |
366 | port_change_bit = "link state"; | |
367 | break; | |
34fb562a SS |
368 | default: |
369 | /* Should never happen */ | |
370 | return; | |
371 | } | |
372 | /* Change bits are all write 1 to clear */ | |
373 | xhci_writel(xhci, port_status | status, addr); | |
374 | port_status = xhci_readl(xhci, addr); | |
375 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", | |
376 | port_change_bit, wIndex, port_status); | |
377 | } | |
378 | ||
0f2a7930 SS |
379 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
380 | u16 wIndex, char *buf, u16 wLength) | |
381 | { | |
382 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
383 | int ports; | |
384 | unsigned long flags; | |
56192531 | 385 | u32 temp, temp1, status; |
0f2a7930 | 386 | int retval = 0; |
28ccd296 | 387 | __le32 __iomem **port_array; |
be88fe4f | 388 | int slot_id; |
20b67cf5 | 389 | struct xhci_bus_state *bus_state; |
2c441780 | 390 | u16 link_state = 0; |
0f2a7930 | 391 | |
f6ff0ac8 SS |
392 | if (hcd->speed == HCD_USB3) { |
393 | ports = xhci->num_usb3_ports; | |
394 | port_array = xhci->usb3_ports; | |
395 | } else { | |
396 | ports = xhci->num_usb2_ports; | |
397 | port_array = xhci->usb2_ports; | |
5308a91b | 398 | } |
20b67cf5 | 399 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
400 | |
401 | spin_lock_irqsave(&xhci->lock, flags); | |
402 | switch (typeReq) { | |
403 | case GetHubStatus: | |
404 | /* No power source, over-current reported per port */ | |
405 | memset(buf, 0, 4); | |
406 | break; | |
407 | case GetHubDescriptor: | |
4bbb0ace SS |
408 | /* Check to make sure userspace is asking for the USB 3.0 hub |
409 | * descriptor for the USB 3.0 roothub. If not, we stall the | |
410 | * endpoint, like external hubs do. | |
411 | */ | |
412 | if (hcd->speed == HCD_USB3 && | |
413 | (wLength < USB_DT_SS_HUB_SIZE || | |
414 | wValue != (USB_DT_SS_HUB << 8))) { | |
415 | xhci_dbg(xhci, "Wrong hub descriptor type for " | |
416 | "USB 3.0 roothub.\n"); | |
417 | goto error; | |
418 | } | |
f6ff0ac8 SS |
419 | xhci_hub_descriptor(hcd, xhci, |
420 | (struct usb_hub_descriptor *) buf); | |
0f2a7930 SS |
421 | break; |
422 | case GetPortStatus: | |
423 | if (!wIndex || wIndex > ports) | |
424 | goto error; | |
425 | wIndex--; | |
426 | status = 0; | |
5308a91b | 427 | temp = xhci_readl(xhci, port_array[wIndex]); |
f9de8151 SS |
428 | if (temp == 0xffffffff) { |
429 | retval = -ENODEV; | |
430 | break; | |
431 | } | |
0f2a7930 SS |
432 | xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); |
433 | ||
434 | /* wPortChange bits */ | |
435 | if (temp & PORT_CSC) | |
749da5f8 | 436 | status |= USB_PORT_STAT_C_CONNECTION << 16; |
0f2a7930 | 437 | if (temp & PORT_PEC) |
749da5f8 | 438 | status |= USB_PORT_STAT_C_ENABLE << 16; |
0f2a7930 | 439 | if ((temp & PORT_OCC)) |
749da5f8 | 440 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; |
0ed9a57e AX |
441 | if ((temp & PORT_RC)) |
442 | status |= USB_PORT_STAT_C_RESET << 16; | |
443 | /* USB3.0 only */ | |
444 | if (hcd->speed == HCD_USB3) { | |
445 | if ((temp & PORT_PLC)) | |
446 | status |= USB_PORT_STAT_C_LINK_STATE << 16; | |
447 | if ((temp & PORT_WRC)) | |
448 | status |= USB_PORT_STAT_C_BH_RESET << 16; | |
449 | } | |
450 | ||
451 | if (hcd->speed != HCD_USB3) { | |
452 | if ((temp & PORT_PLS_MASK) == XDEV_U3 | |
453 | && (temp & PORT_POWER)) | |
454 | status |= USB_PORT_STAT_SUSPEND; | |
455 | } | |
56192531 AX |
456 | if ((temp & PORT_PLS_MASK) == XDEV_RESUME) { |
457 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) | |
458 | goto error; | |
459 | if (!DEV_SUPERSPEED(temp) && time_after_eq(jiffies, | |
20b67cf5 | 460 | bus_state->resume_done[wIndex])) { |
56192531 AX |
461 | xhci_dbg(xhci, "Resume USB2 port %d\n", |
462 | wIndex + 1); | |
20b67cf5 | 463 | bus_state->resume_done[wIndex] = 0; |
56192531 AX |
464 | temp1 = xhci_port_state_to_neutral(temp); |
465 | temp1 &= ~PORT_PLS_MASK; | |
466 | temp1 |= PORT_LINK_STROBE | XDEV_U0; | |
5308a91b | 467 | xhci_writel(xhci, temp1, port_array[wIndex]); |
56192531 AX |
468 | |
469 | xhci_dbg(xhci, "set port %d resume\n", | |
470 | wIndex + 1); | |
5233630f | 471 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
56192531 AX |
472 | wIndex + 1); |
473 | if (!slot_id) { | |
474 | xhci_dbg(xhci, "slot_id is zero\n"); | |
475 | goto error; | |
476 | } | |
477 | xhci_ring_device(xhci, slot_id); | |
20b67cf5 SS |
478 | bus_state->port_c_suspend |= 1 << wIndex; |
479 | bus_state->suspended_ports &= ~(1 << wIndex); | |
56192531 AX |
480 | } |
481 | } | |
be88fe4f AX |
482 | if ((temp & PORT_PLS_MASK) == XDEV_U0 |
483 | && (temp & PORT_POWER) | |
20b67cf5 SS |
484 | && (bus_state->suspended_ports & (1 << wIndex))) { |
485 | bus_state->suspended_ports &= ~(1 << wIndex); | |
486 | bus_state->port_c_suspend |= 1 << wIndex; | |
be88fe4f | 487 | } |
0f2a7930 | 488 | if (temp & PORT_CONNECT) { |
749da5f8 | 489 | status |= USB_PORT_STAT_CONNECTION; |
0f2a7930 SS |
490 | status |= xhci_port_speed(temp); |
491 | } | |
492 | if (temp & PORT_PE) | |
749da5f8 | 493 | status |= USB_PORT_STAT_ENABLE; |
0f2a7930 | 494 | if (temp & PORT_OC) |
749da5f8 | 495 | status |= USB_PORT_STAT_OVERCURRENT; |
0f2a7930 | 496 | if (temp & PORT_RESET) |
749da5f8 | 497 | status |= USB_PORT_STAT_RESET; |
0ed9a57e AX |
498 | if (temp & PORT_POWER) { |
499 | if (hcd->speed == HCD_USB3) | |
500 | status |= USB_SS_PORT_STAT_POWER; | |
501 | else | |
502 | status |= USB_PORT_STAT_POWER; | |
503 | } | |
504 | /* Port Link State */ | |
505 | if (hcd->speed == HCD_USB3) { | |
506 | /* resume state is a xHCI internal state. | |
507 | * Do not report it to usb core. | |
508 | */ | |
509 | if ((temp & PORT_PLS_MASK) != XDEV_RESUME) | |
510 | status |= (temp & PORT_PLS_MASK); | |
511 | } | |
20b67cf5 | 512 | if (bus_state->port_c_suspend & (1 << wIndex)) |
be88fe4f | 513 | status |= 1 << USB_PORT_FEAT_C_SUSPEND; |
0f2a7930 SS |
514 | xhci_dbg(xhci, "Get port status returned 0x%x\n", status); |
515 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | |
516 | break; | |
517 | case SetPortFeature: | |
2c441780 AX |
518 | if (wValue == USB_PORT_FEAT_LINK_STATE) |
519 | link_state = (wIndex & 0xff00) >> 3; | |
0f2a7930 SS |
520 | wIndex &= 0xff; |
521 | if (!wIndex || wIndex > ports) | |
522 | goto error; | |
523 | wIndex--; | |
5308a91b | 524 | temp = xhci_readl(xhci, port_array[wIndex]); |
f9de8151 SS |
525 | if (temp == 0xffffffff) { |
526 | retval = -ENODEV; | |
527 | break; | |
528 | } | |
0f2a7930 | 529 | temp = xhci_port_state_to_neutral(temp); |
4bbb0ace | 530 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 | 531 | switch (wValue) { |
be88fe4f | 532 | case USB_PORT_FEAT_SUSPEND: |
5308a91b | 533 | temp = xhci_readl(xhci, port_array[wIndex]); |
be88fe4f AX |
534 | /* In spec software should not attempt to suspend |
535 | * a port unless the port reports that it is in the | |
536 | * enabled (PED = ‘1’,PLS < ‘3’) state. | |
537 | */ | |
538 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) | |
539 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | |
540 | xhci_warn(xhci, "USB core suspending device " | |
541 | "not in U0/U1/U2.\n"); | |
542 | goto error; | |
543 | } | |
544 | ||
5233630f SS |
545 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
546 | wIndex + 1); | |
be88fe4f AX |
547 | if (!slot_id) { |
548 | xhci_warn(xhci, "slot_id is zero\n"); | |
549 | goto error; | |
550 | } | |
551 | /* unlock to execute stop endpoint commands */ | |
552 | spin_unlock_irqrestore(&xhci->lock, flags); | |
553 | xhci_stop_device(xhci, slot_id, 1); | |
554 | spin_lock_irqsave(&xhci->lock, flags); | |
555 | ||
556 | temp = xhci_port_state_to_neutral(temp); | |
557 | temp &= ~PORT_PLS_MASK; | |
558 | temp |= PORT_LINK_STROBE | XDEV_U3; | |
5308a91b | 559 | xhci_writel(xhci, temp, port_array[wIndex]); |
be88fe4f AX |
560 | |
561 | spin_unlock_irqrestore(&xhci->lock, flags); | |
562 | msleep(10); /* wait device to enter */ | |
563 | spin_lock_irqsave(&xhci->lock, flags); | |
564 | ||
5308a91b | 565 | temp = xhci_readl(xhci, port_array[wIndex]); |
20b67cf5 | 566 | bus_state->suspended_ports |= 1 << wIndex; |
be88fe4f | 567 | break; |
2c441780 AX |
568 | case USB_PORT_FEAT_LINK_STATE: |
569 | temp = xhci_readl(xhci, port_array[wIndex]); | |
570 | /* Software should not attempt to set | |
571 | * port link state above '5' (Rx.Detect) and the port | |
572 | * must be enabled. | |
573 | */ | |
574 | if ((temp & PORT_PE) == 0 || | |
575 | (link_state > USB_SS_PORT_LS_RX_DETECT)) { | |
576 | xhci_warn(xhci, "Cannot set link state.\n"); | |
577 | goto error; | |
578 | } | |
579 | ||
580 | if (link_state == USB_SS_PORT_LS_U3) { | |
581 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
582 | wIndex + 1); | |
583 | if (slot_id) { | |
584 | /* unlock to execute stop endpoint | |
585 | * commands */ | |
586 | spin_unlock_irqrestore(&xhci->lock, | |
587 | flags); | |
588 | xhci_stop_device(xhci, slot_id, 1); | |
589 | spin_lock_irqsave(&xhci->lock, flags); | |
590 | } | |
591 | } | |
592 | ||
593 | temp = xhci_port_state_to_neutral(temp); | |
594 | temp &= ~PORT_PLS_MASK; | |
595 | temp |= PORT_LINK_STROBE | link_state; | |
596 | xhci_writel(xhci, temp, port_array[wIndex]); | |
597 | ||
598 | spin_unlock_irqrestore(&xhci->lock, flags); | |
599 | msleep(20); /* wait device to enter */ | |
600 | spin_lock_irqsave(&xhci->lock, flags); | |
601 | ||
602 | temp = xhci_readl(xhci, port_array[wIndex]); | |
603 | if (link_state == USB_SS_PORT_LS_U3) | |
604 | bus_state->suspended_ports |= 1 << wIndex; | |
605 | break; | |
0f2a7930 SS |
606 | case USB_PORT_FEAT_POWER: |
607 | /* | |
608 | * Turn on ports, even if there isn't per-port switching. | |
609 | * HC will report connect events even before this is set. | |
610 | * However, khubd will ignore the roothub events until | |
611 | * the roothub is registered. | |
612 | */ | |
5308a91b SS |
613 | xhci_writel(xhci, temp | PORT_POWER, |
614 | port_array[wIndex]); | |
0f2a7930 | 615 | |
5308a91b | 616 | temp = xhci_readl(xhci, port_array[wIndex]); |
0f2a7930 SS |
617 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); |
618 | break; | |
619 | case USB_PORT_FEAT_RESET: | |
620 | temp = (temp | PORT_RESET); | |
5308a91b | 621 | xhci_writel(xhci, temp, port_array[wIndex]); |
0f2a7930 | 622 | |
5308a91b | 623 | temp = xhci_readl(xhci, port_array[wIndex]); |
0f2a7930 SS |
624 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
625 | break; | |
a11496eb AX |
626 | case USB_PORT_FEAT_BH_PORT_RESET: |
627 | temp |= PORT_WR; | |
628 | xhci_writel(xhci, temp, port_array[wIndex]); | |
629 | ||
630 | temp = xhci_readl(xhci, port_array[wIndex]); | |
631 | break; | |
0f2a7930 SS |
632 | default: |
633 | goto error; | |
634 | } | |
5308a91b SS |
635 | /* unblock any posted writes */ |
636 | temp = xhci_readl(xhci, port_array[wIndex]); | |
0f2a7930 SS |
637 | break; |
638 | case ClearPortFeature: | |
639 | if (!wIndex || wIndex > ports) | |
640 | goto error; | |
641 | wIndex--; | |
5308a91b | 642 | temp = xhci_readl(xhci, port_array[wIndex]); |
f9de8151 SS |
643 | if (temp == 0xffffffff) { |
644 | retval = -ENODEV; | |
645 | break; | |
646 | } | |
4bbb0ace | 647 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 SS |
648 | temp = xhci_port_state_to_neutral(temp); |
649 | switch (wValue) { | |
be88fe4f | 650 | case USB_PORT_FEAT_SUSPEND: |
5308a91b | 651 | temp = xhci_readl(xhci, port_array[wIndex]); |
be88fe4f AX |
652 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
653 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | |
654 | if (temp & PORT_RESET) | |
655 | goto error; | |
656 | if (temp & XDEV_U3) { | |
657 | if ((temp & PORT_PE) == 0) | |
658 | goto error; | |
659 | if (DEV_SUPERSPEED(temp)) { | |
660 | temp = xhci_port_state_to_neutral(temp); | |
661 | temp &= ~PORT_PLS_MASK; | |
662 | temp |= PORT_LINK_STROBE | XDEV_U0; | |
5308a91b SS |
663 | xhci_writel(xhci, temp, |
664 | port_array[wIndex]); | |
665 | xhci_readl(xhci, port_array[wIndex]); | |
be88fe4f AX |
666 | } else { |
667 | temp = xhci_port_state_to_neutral(temp); | |
668 | temp &= ~PORT_PLS_MASK; | |
669 | temp |= PORT_LINK_STROBE | XDEV_RESUME; | |
5308a91b SS |
670 | xhci_writel(xhci, temp, |
671 | port_array[wIndex]); | |
be88fe4f AX |
672 | |
673 | spin_unlock_irqrestore(&xhci->lock, | |
674 | flags); | |
675 | msleep(20); | |
676 | spin_lock_irqsave(&xhci->lock, flags); | |
677 | ||
5308a91b SS |
678 | temp = xhci_readl(xhci, |
679 | port_array[wIndex]); | |
be88fe4f AX |
680 | temp = xhci_port_state_to_neutral(temp); |
681 | temp &= ~PORT_PLS_MASK; | |
682 | temp |= PORT_LINK_STROBE | XDEV_U0; | |
5308a91b SS |
683 | xhci_writel(xhci, temp, |
684 | port_array[wIndex]); | |
be88fe4f | 685 | } |
20b67cf5 | 686 | bus_state->port_c_suspend |= 1 << wIndex; |
be88fe4f AX |
687 | } |
688 | ||
5233630f SS |
689 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
690 | wIndex + 1); | |
be88fe4f AX |
691 | if (!slot_id) { |
692 | xhci_dbg(xhci, "slot_id is zero\n"); | |
693 | goto error; | |
694 | } | |
695 | xhci_ring_device(xhci, slot_id); | |
696 | break; | |
697 | case USB_PORT_FEAT_C_SUSPEND: | |
20b67cf5 | 698 | bus_state->port_c_suspend &= ~(1 << wIndex); |
0f2a7930 | 699 | case USB_PORT_FEAT_C_RESET: |
a11496eb | 700 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
0f2a7930 | 701 | case USB_PORT_FEAT_C_CONNECTION: |
0f2a7930 | 702 | case USB_PORT_FEAT_C_OVER_CURRENT: |
6219c047 | 703 | case USB_PORT_FEAT_C_ENABLE: |
85387c0e | 704 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
34fb562a | 705 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
5308a91b | 706 | port_array[wIndex], temp); |
0f2a7930 | 707 | break; |
6219c047 | 708 | case USB_PORT_FEAT_ENABLE: |
f6ff0ac8 | 709 | xhci_disable_port(hcd, xhci, wIndex, |
5308a91b | 710 | port_array[wIndex], temp); |
6219c047 | 711 | break; |
0f2a7930 SS |
712 | default: |
713 | goto error; | |
714 | } | |
0f2a7930 SS |
715 | break; |
716 | default: | |
717 | error: | |
718 | /* "stall" on error */ | |
719 | retval = -EPIPE; | |
720 | } | |
721 | spin_unlock_irqrestore(&xhci->lock, flags); | |
722 | return retval; | |
723 | } | |
724 | ||
725 | /* | |
726 | * Returns 0 if the status hasn't changed, or the number of bytes in buf. | |
727 | * Ports are 0-indexed from the HCD point of view, | |
728 | * and 1-indexed from the USB core pointer of view. | |
0f2a7930 SS |
729 | * |
730 | * Note that the status change bits will be cleared as soon as a port status | |
731 | * change event is generated, so we use the saved status from that event. | |
732 | */ | |
733 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |
734 | { | |
735 | unsigned long flags; | |
736 | u32 temp, status; | |
56192531 | 737 | u32 mask; |
0f2a7930 SS |
738 | int i, retval; |
739 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
740 | int ports; | |
28ccd296 | 741 | __le32 __iomem **port_array; |
20b67cf5 | 742 | struct xhci_bus_state *bus_state; |
0f2a7930 | 743 | |
f6ff0ac8 SS |
744 | if (hcd->speed == HCD_USB3) { |
745 | ports = xhci->num_usb3_ports; | |
746 | port_array = xhci->usb3_ports; | |
747 | } else { | |
748 | ports = xhci->num_usb2_ports; | |
749 | port_array = xhci->usb2_ports; | |
5308a91b | 750 | } |
20b67cf5 | 751 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
752 | |
753 | /* Initial status is no changes */ | |
419a8e81 WG |
754 | retval = (ports + 8) / 8; |
755 | memset(buf, 0, retval); | |
0f2a7930 | 756 | status = 0; |
0f2a7930 | 757 | |
56192531 AX |
758 | mask = PORT_CSC | PORT_PEC | PORT_OCC; |
759 | ||
0f2a7930 SS |
760 | spin_lock_irqsave(&xhci->lock, flags); |
761 | /* For each port, did anything change? If so, set that bit in buf. */ | |
762 | for (i = 0; i < ports; i++) { | |
5308a91b | 763 | temp = xhci_readl(xhci, port_array[i]); |
f9de8151 SS |
764 | if (temp == 0xffffffff) { |
765 | retval = -ENODEV; | |
766 | break; | |
767 | } | |
56192531 | 768 | if ((temp & mask) != 0 || |
20b67cf5 SS |
769 | (bus_state->port_c_suspend & 1 << i) || |
770 | (bus_state->resume_done[i] && time_after_eq( | |
771 | jiffies, bus_state->resume_done[i]))) { | |
419a8e81 | 772 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
0f2a7930 SS |
773 | status = 1; |
774 | } | |
775 | } | |
776 | spin_unlock_irqrestore(&xhci->lock, flags); | |
777 | return status ? retval : 0; | |
778 | } | |
9777e3ce AX |
779 | |
780 | #ifdef CONFIG_PM | |
781 | ||
782 | int xhci_bus_suspend(struct usb_hcd *hcd) | |
783 | { | |
784 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 785 | int max_ports, port_index; |
28ccd296 | 786 | __le32 __iomem **port_array; |
20b67cf5 | 787 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
788 | unsigned long flags; |
789 | ||
f6ff0ac8 SS |
790 | if (hcd->speed == HCD_USB3) { |
791 | max_ports = xhci->num_usb3_ports; | |
792 | port_array = xhci->usb3_ports; | |
793 | xhci_dbg(xhci, "suspend USB 3.0 root hub\n"); | |
794 | } else { | |
795 | max_ports = xhci->num_usb2_ports; | |
796 | port_array = xhci->usb2_ports; | |
797 | xhci_dbg(xhci, "suspend USB 2.0 root hub\n"); | |
5308a91b | 798 | } |
20b67cf5 | 799 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce AX |
800 | |
801 | spin_lock_irqsave(&xhci->lock, flags); | |
802 | ||
803 | if (hcd->self.root_hub->do_remote_wakeup) { | |
518e848e SS |
804 | port_index = max_ports; |
805 | while (port_index--) { | |
20b67cf5 | 806 | if (bus_state->resume_done[port_index] != 0) { |
9777e3ce AX |
807 | spin_unlock_irqrestore(&xhci->lock, flags); |
808 | xhci_dbg(xhci, "suspend failed because " | |
809 | "port %d is resuming\n", | |
518e848e | 810 | port_index + 1); |
9777e3ce AX |
811 | return -EBUSY; |
812 | } | |
813 | } | |
814 | } | |
815 | ||
518e848e | 816 | port_index = max_ports; |
20b67cf5 | 817 | bus_state->bus_suspended = 0; |
518e848e | 818 | while (port_index--) { |
9777e3ce | 819 | /* suspend the port if the port is not suspended */ |
9777e3ce AX |
820 | u32 t1, t2; |
821 | int slot_id; | |
822 | ||
5308a91b | 823 | t1 = xhci_readl(xhci, port_array[port_index]); |
9777e3ce AX |
824 | t2 = xhci_port_state_to_neutral(t1); |
825 | ||
826 | if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { | |
518e848e | 827 | xhci_dbg(xhci, "port %d not suspended\n", port_index); |
5233630f | 828 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
518e848e | 829 | port_index + 1); |
9777e3ce AX |
830 | if (slot_id) { |
831 | spin_unlock_irqrestore(&xhci->lock, flags); | |
832 | xhci_stop_device(xhci, slot_id, 1); | |
833 | spin_lock_irqsave(&xhci->lock, flags); | |
834 | } | |
835 | t2 &= ~PORT_PLS_MASK; | |
836 | t2 |= PORT_LINK_STROBE | XDEV_U3; | |
20b67cf5 | 837 | set_bit(port_index, &bus_state->bus_suspended); |
9777e3ce AX |
838 | } |
839 | if (hcd->self.root_hub->do_remote_wakeup) { | |
840 | if (t1 & PORT_CONNECT) { | |
841 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | |
842 | t2 &= ~PORT_WKCONN_E; | |
843 | } else { | |
844 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | |
845 | t2 &= ~PORT_WKDISC_E; | |
846 | } | |
847 | } else | |
848 | t2 &= ~PORT_WAKE_BITS; | |
849 | ||
850 | t1 = xhci_port_state_to_neutral(t1); | |
851 | if (t1 != t2) | |
5308a91b | 852 | xhci_writel(xhci, t2, port_array[port_index]); |
9777e3ce AX |
853 | |
854 | if (DEV_HIGHSPEED(t1)) { | |
855 | /* enable remote wake up for USB 2.0 */ | |
28ccd296 | 856 | __le32 __iomem *addr; |
9777e3ce AX |
857 | u32 tmp; |
858 | ||
5308a91b SS |
859 | /* Add one to the port status register address to get |
860 | * the port power control register address. | |
861 | */ | |
862 | addr = port_array[port_index] + 1; | |
9777e3ce AX |
863 | tmp = xhci_readl(xhci, addr); |
864 | tmp |= PORT_RWE; | |
865 | xhci_writel(xhci, tmp, addr); | |
866 | } | |
867 | } | |
868 | hcd->state = HC_STATE_SUSPENDED; | |
20b67cf5 | 869 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
9777e3ce AX |
870 | spin_unlock_irqrestore(&xhci->lock, flags); |
871 | return 0; | |
872 | } | |
873 | ||
874 | int xhci_bus_resume(struct usb_hcd *hcd) | |
875 | { | |
876 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 877 | int max_ports, port_index; |
28ccd296 | 878 | __le32 __iomem **port_array; |
20b67cf5 | 879 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
880 | u32 temp; |
881 | unsigned long flags; | |
882 | ||
f6ff0ac8 SS |
883 | if (hcd->speed == HCD_USB3) { |
884 | max_ports = xhci->num_usb3_ports; | |
885 | port_array = xhci->usb3_ports; | |
886 | xhci_dbg(xhci, "resume USB 3.0 root hub\n"); | |
887 | } else { | |
888 | max_ports = xhci->num_usb2_ports; | |
889 | port_array = xhci->usb2_ports; | |
890 | xhci_dbg(xhci, "resume USB 2.0 root hub\n"); | |
5308a91b | 891 | } |
20b67cf5 | 892 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce | 893 | |
20b67cf5 | 894 | if (time_before(jiffies, bus_state->next_statechange)) |
9777e3ce AX |
895 | msleep(5); |
896 | ||
897 | spin_lock_irqsave(&xhci->lock, flags); | |
898 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
899 | spin_unlock_irqrestore(&xhci->lock, flags); | |
900 | return -ESHUTDOWN; | |
901 | } | |
902 | ||
903 | /* delay the irqs */ | |
904 | temp = xhci_readl(xhci, &xhci->op_regs->command); | |
905 | temp &= ~CMD_EIE; | |
906 | xhci_writel(xhci, temp, &xhci->op_regs->command); | |
907 | ||
518e848e SS |
908 | port_index = max_ports; |
909 | while (port_index--) { | |
9777e3ce AX |
910 | /* Check whether need resume ports. If needed |
911 | resume port and disable remote wakeup */ | |
9777e3ce AX |
912 | u32 temp; |
913 | int slot_id; | |
914 | ||
5308a91b | 915 | temp = xhci_readl(xhci, port_array[port_index]); |
9777e3ce AX |
916 | if (DEV_SUPERSPEED(temp)) |
917 | temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
918 | else | |
919 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
20b67cf5 | 920 | if (test_bit(port_index, &bus_state->bus_suspended) && |
9777e3ce AX |
921 | (temp & PORT_PLS_MASK)) { |
922 | if (DEV_SUPERSPEED(temp)) { | |
923 | temp = xhci_port_state_to_neutral(temp); | |
924 | temp &= ~PORT_PLS_MASK; | |
925 | temp |= PORT_LINK_STROBE | XDEV_U0; | |
5308a91b | 926 | xhci_writel(xhci, temp, port_array[port_index]); |
9777e3ce AX |
927 | } else { |
928 | temp = xhci_port_state_to_neutral(temp); | |
929 | temp &= ~PORT_PLS_MASK; | |
930 | temp |= PORT_LINK_STROBE | XDEV_RESUME; | |
5308a91b | 931 | xhci_writel(xhci, temp, port_array[port_index]); |
9777e3ce AX |
932 | |
933 | spin_unlock_irqrestore(&xhci->lock, flags); | |
934 | msleep(20); | |
935 | spin_lock_irqsave(&xhci->lock, flags); | |
936 | ||
5308a91b | 937 | temp = xhci_readl(xhci, port_array[port_index]); |
9777e3ce AX |
938 | temp = xhci_port_state_to_neutral(temp); |
939 | temp &= ~PORT_PLS_MASK; | |
940 | temp |= PORT_LINK_STROBE | XDEV_U0; | |
5308a91b | 941 | xhci_writel(xhci, temp, port_array[port_index]); |
9777e3ce | 942 | } |
5233630f SS |
943 | slot_id = xhci_find_slot_id_by_port(hcd, |
944 | xhci, port_index + 1); | |
9777e3ce AX |
945 | if (slot_id) |
946 | xhci_ring_device(xhci, slot_id); | |
947 | } else | |
5308a91b | 948 | xhci_writel(xhci, temp, port_array[port_index]); |
9777e3ce AX |
949 | |
950 | if (DEV_HIGHSPEED(temp)) { | |
951 | /* disable remote wake up for USB 2.0 */ | |
28ccd296 | 952 | __le32 __iomem *addr; |
9777e3ce AX |
953 | u32 tmp; |
954 | ||
5308a91b SS |
955 | /* Add one to the port status register address to get |
956 | * the port power control register address. | |
957 | */ | |
958 | addr = port_array[port_index] + 1; | |
9777e3ce AX |
959 | tmp = xhci_readl(xhci, addr); |
960 | tmp &= ~PORT_RWE; | |
961 | xhci_writel(xhci, tmp, addr); | |
962 | } | |
963 | } | |
964 | ||
965 | (void) xhci_readl(xhci, &xhci->op_regs->command); | |
966 | ||
20b67cf5 | 967 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
9777e3ce AX |
968 | /* re-enable irqs */ |
969 | temp = xhci_readl(xhci, &xhci->op_regs->command); | |
970 | temp |= CMD_EIE; | |
971 | xhci_writel(xhci, temp, &xhci->op_regs->command); | |
972 | temp = xhci_readl(xhci, &xhci->op_regs->command); | |
973 | ||
974 | spin_unlock_irqrestore(&xhci->lock, flags); | |
975 | return 0; | |
976 | } | |
977 | ||
436a3890 | 978 | #endif /* CONFIG_PM */ |