[deliverable/linux.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>

#include "xhci.h"
#include "xhci-trace.h"

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_ASROCK_P67	0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31

static const char hcd_name[] = "xhci_hcd";

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;
	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	    (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI ||
	     pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) {
		/* Workaround for occasional spurious wakeups from S5 (or
		 * any other sleep) on Haswell machines with LPT and LPT-LP
		 * with the new Intel BIOS
		 */
		/* Limit the quirk to only known vendors, as this triggers
		 * yet another BIOS bug on some other machines
		 * https://bugzilla.kernel.org/show_bug.cgi?id=66171
		 */
		if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)
			xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
}

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	xhci = hcd_to_xhci(hcd);
	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	kfree(xhci);
	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;
	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		return retval;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	 * is called by usb_add_hcd().
	 */
	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	/* We know the LPM timeout algorithms for this host, let the USB core
	 * enable and disable LPM for devices under the USB 3.0 roothub.
	 */
	if (xhci->quirks & XHCI_LPM_SUPPORT)
		hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);

	kfree(xhci);
}

#ifdef CONFIG_PM
static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci_compliance_mode_recovery_timer_quirk_check())
		pdev->no_d3cold = true;

	return xhci_suspend(xhci);
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

static const struct hc_driver xhci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"xHCI Host Controller",
	.hcd_priv_size =	sizeof(struct xhci_hcd *),

	/*
	 * generic hardware linkage
	 */
	.irq =			xhci_irq,
	.flags =		HCD_MEMORY | HCD_USB3 | HCD_SHARED,

	/*
	 * basic lifecycle operations
	 */
	.reset =		xhci_pci_setup,
	.start =		xhci_run,
#ifdef CONFIG_PM
	.pci_suspend =          xhci_pci_suspend,
	.pci_resume =           xhci_pci_resume,
#endif
	.stop =			xhci_stop,
	.shutdown =		xhci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		xhci_urb_enqueue,
	.urb_dequeue =		xhci_urb_dequeue,
	.alloc_dev =		xhci_alloc_dev,
	.free_dev =		xhci_free_dev,
	.alloc_streams =	xhci_alloc_streams,
	.free_streams =		xhci_free_streams,
	.add_endpoint =		xhci_add_endpoint,
	.drop_endpoint =	xhci_drop_endpoint,
	.endpoint_reset =	xhci_endpoint_reset,
	.check_bandwidth =	xhci_check_bandwidth,
	.reset_bandwidth =	xhci_reset_bandwidth,
	.address_device =	xhci_address_device,
	.enable_device =	xhci_enable_device,
	.update_hub_device =	xhci_update_hub_device,
	.reset_device =		xhci_discover_or_reset_device,

	/*
	 * scheduling support
	 */
	.get_frame_number =	xhci_get_frame,

	/* Root hub support */
	.hub_control =		xhci_hub_control,
	.hub_status_data =	xhci_hub_status_data,
	.bus_suspend =		xhci_bus_suspend,
	.bus_resume =		xhci_bus_resume,
	/*
	 * call back when device connected and addressed
	 */
	.update_device =        xhci_update_device,
	.set_usb2_hw_lpm =	xhci_set_usb2_hardware_lpm,
	.enable_usb3_lpm_timeout =	xhci_enable_usb3_lpm_timeout,
	.disable_usb3_lpm_timeout =	xhci_disable_usb3_lpm_timeout,
	.find_raw_port_number =	xhci_find_raw_port_number,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

int __init xhci_register_pci(void)
{
	return pci_register_driver(&xhci_pci_driver);
}

void xhci_unregister_pci(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
66d4eadd SS	26
66d4eadd SS	27	#include "xhci.h"
4bdfe4c3	28	#include "xhci-trace.h"
66d4eadd	29
ac9d8fe7 SS	30	/* Device for a quirk */
	31	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	32	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33	33	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	34
c877b3b2 ML	35	#define PCI_VENDOR_ID_ETRON 0x1b6f
	36	#define PCI_DEVICE_ID_ASROCK_P67 0x7023
	37
638298dc TI	38	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
	39	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
	40
66d4eadd SS	41	static const char hcd_name[] = "xhci_hcd";
	42
	43	/* called after powerup, by probe or system-pm "wakeup" */
	44	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	45	{
	46	/*
	47	* TODO: Implement finding debug ports later.
	48	* TODO: see if there are any quirks that need to be added to handle
	49	* new extended capabilities.
	50	*/
	51
	52	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	53	if (!pci_set_mwi(pdev))
	54	xhci_dbg(xhci, "MWI active\n");
	55
	56	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	57	return 0;
	58	}
	59
da3c9c4f SAS	60	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	61	{
	62	struct pci_dev *pdev = to_pci_dev(dev);
	63
ac9d8fe7 SS	64	/* Look for vendor-specific quirks */
ac9d8fe7 SS	65	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	66	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	67	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	68	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	69	pdev->revision == 0x0) {
ac9d8fe7	70	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	71	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	72	"QUIRK: Fresco Logic xHC needs configure"
	73	" endpoint cmd after reset endpoint");
f5182b41	74	}
455f5892 ON	75	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	76	pdev->revision == 0x4) {
	77	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	78	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	79	"QUIRK: Fresco Logic xHC revision %u"
	80	"must be suspended extra slowly",
	81	pdev->revision);
	82	}
f5182b41 SS	83	/* Fresco Logic confirms: all revisions of this chip do not
	84	* support MSI, even though some of them claim to in their PCI
	85	* capabilities.
	86	*/
	87	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	88	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	89	"QUIRK: Fresco Logic revision %u "
	90	"has broken MSI implementation",
f5182b41	91	pdev->revision);
1530bbc6	92	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	93	}
f5182b41	94
0238634d SS	95	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	96	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	97
7e393a83 AX	98	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	99	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	100
c41136b0 AX	101	/* AMD PLL quirk */
	102	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	103	xhci->quirks \|= XHCI_AMD_PLL_FIX;
e3567d2c SS	104	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	105	xhci->quirks \|= XHCI_LPM_SUPPORT;
	106	xhci->quirks \|= XHCI_INTEL_HOST;
	107	}
ad808333 SS	108	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	109	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	110	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	111	xhci->limit_active_eps = 64;
86cc558e	112	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	113	/*
	114	* PPT desktop boards DH77EB and DH77DF will power back on after
	115	* a few seconds of being shutdown. The fix for this is to
	116	* switch the ports from xHCI to EHCI on shutdown. We can't use
	117	* DMI information to find those particular boards (since each
	118	* vendor will change the board name), so we have to key off all
	119	* PPT chipsets.
	120	*/
	121	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
80fab3b2	122	xhci->quirks \|= XHCI_AVOID_BEI;
ad808333	123	}
638298dc TI	124	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	125	(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI \|\|
	126	pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) {
	127	/* Workaround for occasional spurious wakeups from S5 (or
	128	* any other sleep) on Haswell machines with LPT and LPT-LP
	129	* with the new Intel BIOS
	130	*/
6962d914 TI	131	/* Limit the quirk to only known vendors, as this triggers
	132	* yet another BIOS bug on some other machines
	133	* https://bugzilla.kernel.org/show_bug.cgi?id=66171
	134	*/
	135	if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)
	136	xhci->quirks \|= XHCI_SPURIOUS_WAKEUP;
638298dc	137	}
c877b3b2 ML	138	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
	139	pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
	140	xhci->quirks \|= XHCI_RESET_ON_RESUME;
4bdfe4c3 XR	141	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4bdfe4c3 XR	142	"QUIRK: Resetting on resume");
5cb7df2b	143	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
c877b3b2	144	}
457a4f61 EF	145	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	146	xhci->quirks \|= XHCI_RESET_ON_RESUME;
da3c9c4f	147	}
c41136b0	148
da3c9c4f SAS	149	/* called during probe() after chip reset completes */
	150	static int xhci_pci_setup(struct usb_hcd *hcd)
	151	{
	152	struct xhci_hcd *xhci;
	153	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	154	int retval;
66d4eadd	155
da3c9c4f	156	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	157	if (retval)
da3c9c4f	158	return retval;
006d5820	159
da3c9c4f SAS	160	xhci = hcd_to_xhci(hcd);
	161	if (!usb_hcd_is_primary_hcd(hcd))
	162	return 0;
66d4eadd SS	163
	164	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	165	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	166
	167	/* Find any debug ports */
b02d0ed6 SS	168	retval = xhci_pci_reinit(xhci, pdev);
	169	if (!retval)
	170	return retval;
	171
b02d0ed6 SS	172	kfree(xhci);
	173	return retval;
	174	}
	175
f6ff0ac8 SS	176	/*
	177	* We need to register our own PCI probe function (instead of the USB core's
	178	* function) in order to create a second roothub under xHCI.
	179	*/
	180	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	181	{
	182	int retval;
	183	struct xhci_hcd *xhci;
	184	struct hc_driver *driver;
	185	struct usb_hcd *hcd;
	186
	187	driver = (struct hc_driver *)id->driver_data;
	188	/* Register the USB 2.0 roothub.
	189	* FIXME: USB core must know to register the USB 2.0 roothub first.
	190	* This is sort of silly, because we could just set the HCD driver flags
	191	* to say USB 2.0, but I'm not sure what the implications would be in
	192	* the other parts of the HCD code.
	193	*/
	194	retval = usb_hcd_pci_probe(dev, id);
	195
	196	if (retval)
	197	return retval;
	198
	199	/* USB 2.0 roothub is stored in the PCI device now. */
	200	hcd = dev_get_drvdata(&dev->dev);
	201	xhci = hcd_to_xhci(hcd);
	202	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	203	pci_name(dev), hcd);
	204	if (!xhci->shared_hcd) {
	205	retval = -ENOMEM;
	206	goto dealloc_usb2_hcd;
	207	}
	208
	209	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	210	* is called by usb_add_hcd().
	211	*/
	212	((struct xhci_hcd *) xhci->shared_hcd->hcd_priv) = xhci;
	213
	214	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	215	IRQF_SHARED);
f6ff0ac8 SS	216	if (retval)
	217	goto put_usb3_hcd;
	218	/* Roothub already marked as USB 3.0 speed */
3b3db026 SS	219
	220	/* We know the LPM timeout algorithms for this host, let the USB core
	221	* enable and disable LPM for devices under the USB 3.0 roothub.
	222	*/
	223	if (xhci->quirks & XHCI_LPM_SUPPORT)
	224	hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
	225
f6ff0ac8 SS	226	return 0;
	227
	228	put_usb3_hcd:
	229	usb_put_hcd(xhci->shared_hcd);
	230	dealloc_usb2_hcd:
	231	usb_hcd_pci_remove(dev);
	232	return retval;
	233	}
	234
b02d0ed6 SS	235	static void xhci_pci_remove(struct pci_dev *dev)
	236	{
	237	struct xhci_hcd *xhci;
	238
	239	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	240	if (xhci->shared_hcd) {
	241	usb_remove_hcd(xhci->shared_hcd);
	242	usb_put_hcd(xhci->shared_hcd);
	243	}
b02d0ed6	244	usb_hcd_pci_remove(dev);
638298dc TI	245
	246	/* Workaround for spurious wakeups at shutdown with HSW */
	247	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	248	pci_set_power_state(dev, PCI_D3hot);
	249
b02d0ed6	250	kfree(xhci);
66d4eadd SS	251	}
66d4eadd SS	252
5535b1d5 AX	253	#ifdef CONFIG_PM
	254	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	255	{
	256	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5 SS	257	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	258
	259	/*
	260	* Systems with the TI redriver that loses port status change events
	261	* need to have the registers polled during D3, so avoid D3cold.
	262	*/
	263	if (xhci_compliance_mode_recovery_timer_quirk_check())
	264	pdev->no_d3cold = true;
5535b1d5	265
77b84767	266	return xhci_suspend(xhci);
5535b1d5 AX	267	}
	268
	269	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	270	{
	271	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	272	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	273	int retval = 0;
5535b1d5 AX	274
69e848c2 SS	275	/* The BIOS on systems with the Intel Panther Point chipset may or may
	276	* not support xHCI natively. That means that during system resume, it
	277	* may switch the ports back to EHCI so that users can use their
	278	* keyboard to select a kernel from GRUB after resume from hibernate.
	279	*
	280	* The BIOS is supposed to remember whether the OS had xHCI ports
	281	* enabled before resume, and switch the ports back to xHCI when the
	282	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	283	* writers.
	284	*
	285	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	286	* It should not matter whether the EHCI or xHCI controller is
	287	* resumed first. It's enough to do the switchover in xHCI because
	288	* USB core won't notice anything as the hub driver doesn't start
	289	* running again until after all the devices (including both EHCI and
	290	* xHCI host controllers) have been resumed.
69e848c2	291	*/
26b76798 MN	292
	293	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	294	usb_enable_intel_xhci_ports(pdev);
69e848c2	295
5535b1d5 AX	296	retval = xhci_resume(xhci, hibernated);
	297	return retval;
	298	}
	299	#endif /* CONFIG_PM */
	300
66d4eadd SS	301	static const struct hc_driver xhci_pci_hc_driver = {
	302	.description = hcd_name,
	303	.product_desc = "xHCI Host Controller",
b02d0ed6	304	.hcd_priv_size = sizeof(struct xhci_hcd *),
66d4eadd SS	305
	306	/*
	307	* generic hardware linkage
	308	*/
7f84eef0	309	.irq = xhci_irq,
f6ff0ac8	310	.flags = HCD_MEMORY \| HCD_USB3 \| HCD_SHARED,
66d4eadd SS	311
	312	/*
	313	* basic lifecycle operations
	314	*/
	315	.reset = xhci_pci_setup,
	316	.start = xhci_run,
5535b1d5 AX	317	#ifdef CONFIG_PM
	318	.pci_suspend = xhci_pci_suspend,
	319	.pci_resume = xhci_pci_resume,
	320	#endif
66d4eadd SS	321	.stop = xhci_stop,
	322	.shutdown = xhci_shutdown,
	323
3ffbba95 SS	324	/*
	325	* managing i/o requests and associated device resources
	326	*/
d0e96f5a SS	327	.urb_enqueue = xhci_urb_enqueue,
d0e96f5a SS	328	.urb_dequeue = xhci_urb_dequeue,
3ffbba95 SS	329	.alloc_dev = xhci_alloc_dev,
3ffbba95 SS	330	.free_dev = xhci_free_dev,
eab1cafc SS	331	.alloc_streams = xhci_alloc_streams,
eab1cafc SS	332	.free_streams = xhci_free_streams,
f94e0186 SS	333	.add_endpoint = xhci_add_endpoint,
f94e0186 SS	334	.drop_endpoint = xhci_drop_endpoint,
a1587d97	335	.endpoint_reset = xhci_endpoint_reset,
f94e0186 SS	336	.check_bandwidth = xhci_check_bandwidth,
f94e0186 SS	337	.reset_bandwidth = xhci_reset_bandwidth,
3ffbba95	338	.address_device = xhci_address_device,
48fc7dbd	339	.enable_device = xhci_enable_device,
b356b7c7	340	.update_hub_device = xhci_update_hub_device,
f0615c45	341	.reset_device = xhci_discover_or_reset_device,
3ffbba95	342
66d4eadd SS	343	/*
	344	* scheduling support
	345	*/
	346	.get_frame_number = xhci_get_frame,
	347
0f2a7930 SS	348	/* Root hub support */
	349	.hub_control = xhci_hub_control,
	350	.hub_status_data = xhci_hub_status_data,
9777e3ce AX	351	.bus_suspend = xhci_bus_suspend,
9777e3ce AX	352	.bus_resume = xhci_bus_resume,
9574323c AX	353	/*
	354	* call back when device connected and addressed
	355	*/
	356	.update_device = xhci_update_device,
65580b43	357	.set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
3b3db026 SS	358	.enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
3b3db026 SS	359	.disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
3f5eb141	360	.find_raw_port_number = xhci_find_raw_port_number,
66d4eadd SS	361	};
	362
	363	/-------------------------------------------------------------------------/
	364
	365	/* PCI driver selection metadata; PCI hotplugging uses this */
	366	static const struct pci_device_id pci_ids[] = { {
	367	/* handle any USB 3.0 xHCI controller */
	368	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	369	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	370	},
	371	{ /* end: all zeroes */ }
	372	};
	373	MODULE_DEVICE_TABLE(pci, pci_ids);
	374
	375	/* pci driver glue; this is a "new style" PCI driver module */
	376	static struct pci_driver xhci_pci_driver = {
	377	.name = (char *) hcd_name,
	378	.id_table = pci_ids,
	379
f6ff0ac8	380	.probe = xhci_pci_probe,
b02d0ed6	381	.remove = xhci_pci_remove,
66d4eadd SS	382	/* suspend and resume implemented later */
	383
	384	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	385	#ifdef CONFIG_PM
5535b1d5 AX	386	.driver = {
	387	.pm = &usb_hcd_pci_pm_ops
	388	},
	389	#endif
66d4eadd SS	390	};
66d4eadd SS	391
0cc47d54	392	int __init xhci_register_pci(void)
66d4eadd SS	393	{
	394	return pci_register_driver(&xhci_pci_driver);
	395	}
	396
a46c46a1	397	void xhci_unregister_pci(void)
66d4eadd SS	398	{
	399	pci_unregister_driver(&xhci_pci_driver);
	400	}