Commit | Line | Data |
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eb83092c AKG |
1 | /* |
2 | * Texas Instruments AM35x "glue layer" | |
3 | * | |
4 | * Copyright (c) 2010, by Texas Instruments | |
5 | * | |
6 | * Based on the DA8xx "glue layer" code. | |
7 | * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com> | |
8 | * | |
9 | * This file is part of the Inventra Controller Driver for Linux. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is free software; you | |
12 | * can redistribute it and/or modify it under the terms of the GNU | |
13 | * General Public License version 2 as published by the Free Software | |
14 | * Foundation. | |
15 | * | |
16 | * The Inventra Controller Driver for Linux is distributed in | |
17 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
18 | * without even the implied warranty of MERCHANTABILITY or | |
19 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
20 | * License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with The Inventra Controller Driver for Linux ; if not, | |
24 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
25 | * Suite 330, Boston, MA 02111-1307 USA | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
ab570da2 | 30 | #include <linux/module.h> |
eb83092c AKG |
31 | #include <linux/clk.h> |
32 | #include <linux/io.h> | |
ce40c576 FB |
33 | #include <linux/platform_device.h> |
34 | #include <linux/dma-mapping.h> | |
eb83092c | 35 | |
eb83092c AKG |
36 | #include <plat/usb.h> |
37 | ||
38 | #include "musb_core.h" | |
39 | ||
40 | /* | |
41 | * AM35x specific definitions | |
42 | */ | |
43 | /* USB 2.0 OTG module registers */ | |
44 | #define USB_REVISION_REG 0x00 | |
45 | #define USB_CTRL_REG 0x04 | |
46 | #define USB_STAT_REG 0x08 | |
47 | #define USB_EMULATION_REG 0x0c | |
48 | /* 0x10 Reserved */ | |
49 | #define USB_AUTOREQ_REG 0x14 | |
50 | #define USB_SRP_FIX_TIME_REG 0x18 | |
51 | #define USB_TEARDOWN_REG 0x1c | |
52 | #define EP_INTR_SRC_REG 0x20 | |
53 | #define EP_INTR_SRC_SET_REG 0x24 | |
54 | #define EP_INTR_SRC_CLEAR_REG 0x28 | |
55 | #define EP_INTR_MASK_REG 0x2c | |
56 | #define EP_INTR_MASK_SET_REG 0x30 | |
57 | #define EP_INTR_MASK_CLEAR_REG 0x34 | |
58 | #define EP_INTR_SRC_MASKED_REG 0x38 | |
59 | #define CORE_INTR_SRC_REG 0x40 | |
60 | #define CORE_INTR_SRC_SET_REG 0x44 | |
61 | #define CORE_INTR_SRC_CLEAR_REG 0x48 | |
62 | #define CORE_INTR_MASK_REG 0x4c | |
63 | #define CORE_INTR_MASK_SET_REG 0x50 | |
64 | #define CORE_INTR_MASK_CLEAR_REG 0x54 | |
65 | #define CORE_INTR_SRC_MASKED_REG 0x58 | |
66 | /* 0x5c Reserved */ | |
67 | #define USB_END_OF_INTR_REG 0x60 | |
68 | ||
69 | /* Control register bits */ | |
70 | #define AM35X_SOFT_RESET_MASK 1 | |
71 | ||
72 | /* USB interrupt register bits */ | |
73 | #define AM35X_INTR_USB_SHIFT 16 | |
74 | #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) | |
75 | #define AM35X_INTR_DRVVBUS 0x100 | |
76 | #define AM35X_INTR_RX_SHIFT 16 | |
77 | #define AM35X_INTR_TX_SHIFT 0 | |
78 | #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ | |
79 | #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ | |
80 | #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) | |
81 | #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) | |
82 | ||
83 | #define USB_MENTOR_CORE_OFFSET 0x400 | |
84 | ||
0919dfc1 FB |
85 | struct am35x_glue { |
86 | struct device *dev; | |
87 | struct platform_device *musb; | |
03491761 FB |
88 | struct clk *phy_clk; |
89 | struct clk *clk; | |
0919dfc1 | 90 | }; |
6f783e28 | 91 | #define glue_to_musb(g) platform_get_drvdata(g->musb) |
0919dfc1 | 92 | |
eb83092c | 93 | /* |
743411b3 | 94 | * am35x_musb_enable - enable interrupts |
eb83092c | 95 | */ |
743411b3 | 96 | static void am35x_musb_enable(struct musb *musb) |
eb83092c AKG |
97 | { |
98 | void __iomem *reg_base = musb->ctrl_base; | |
99 | u32 epmask; | |
100 | ||
101 | /* Workaround: setup IRQs through both register sets. */ | |
102 | epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | | |
103 | ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); | |
104 | ||
105 | musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); | |
106 | musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); | |
107 | ||
108 | /* Force the DRVVBUS IRQ so we can start polling for ID change. */ | |
109 | if (is_otg_enabled(musb)) | |
110 | musb_writel(reg_base, CORE_INTR_SRC_SET_REG, | |
111 | AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); | |
112 | } | |
113 | ||
114 | /* | |
743411b3 | 115 | * am35x_musb_disable - disable HDRC and flush interrupts |
eb83092c | 116 | */ |
743411b3 | 117 | static void am35x_musb_disable(struct musb *musb) |
eb83092c AKG |
118 | { |
119 | void __iomem *reg_base = musb->ctrl_base; | |
120 | ||
121 | musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); | |
122 | musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, | |
123 | AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); | |
124 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
125 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
126 | } | |
127 | ||
eb83092c | 128 | #define portstate(stmt) stmt |
eb83092c | 129 | |
743411b3 | 130 | static void am35x_musb_set_vbus(struct musb *musb, int is_on) |
eb83092c AKG |
131 | { |
132 | WARN_ON(is_on && is_peripheral_active(musb)); | |
133 | } | |
134 | ||
135 | #define POLL_SECONDS 2 | |
136 | ||
137 | static struct timer_list otg_workaround; | |
138 | ||
139 | static void otg_timer(unsigned long _musb) | |
140 | { | |
141 | struct musb *musb = (void *)_musb; | |
142 | void __iomem *mregs = musb->mregs; | |
143 | u8 devctl; | |
144 | unsigned long flags; | |
145 | ||
146 | /* | |
147 | * We poll because AM35x's won't expose several OTG-critical | |
148 | * status change events (from the transceiver) otherwise. | |
149 | */ | |
150 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 151 | dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, |
3df00453 | 152 | otg_state_string(musb->xceiv->state)); |
eb83092c AKG |
153 | |
154 | spin_lock_irqsave(&musb->lock, flags); | |
155 | switch (musb->xceiv->state) { | |
156 | case OTG_STATE_A_WAIT_BCON: | |
157 | devctl &= ~MUSB_DEVCTL_SESSION; | |
158 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
159 | ||
160 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
161 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
162 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
163 | MUSB_DEV_MODE(musb); | |
164 | } else { | |
165 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
166 | MUSB_HST_MODE(musb); | |
167 | } | |
168 | break; | |
169 | case OTG_STATE_A_WAIT_VFALL: | |
170 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; | |
171 | musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, | |
172 | MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); | |
173 | break; | |
174 | case OTG_STATE_B_IDLE: | |
175 | if (!is_peripheral_enabled(musb)) | |
176 | break; | |
177 | ||
178 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
179 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
180 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
181 | else | |
182 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
183 | break; | |
184 | default: | |
185 | break; | |
186 | } | |
187 | spin_unlock_irqrestore(&musb->lock, flags); | |
188 | } | |
189 | ||
743411b3 | 190 | static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) |
eb83092c AKG |
191 | { |
192 | static unsigned long last_timer; | |
193 | ||
194 | if (!is_otg_enabled(musb)) | |
195 | return; | |
196 | ||
197 | if (timeout == 0) | |
198 | timeout = jiffies + msecs_to_jiffies(3); | |
199 | ||
200 | /* Never idle if active, or when VBUS timeout is not set as host */ | |
201 | if (musb->is_active || (musb->a_wait_bcon == 0 && | |
202 | musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { | |
5c8a86e1 | 203 | dev_dbg(musb->controller, "%s active, deleting timer\n", |
3df00453 | 204 | otg_state_string(musb->xceiv->state)); |
eb83092c AKG |
205 | del_timer(&otg_workaround); |
206 | last_timer = jiffies; | |
207 | return; | |
208 | } | |
209 | ||
210 | if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { | |
5c8a86e1 | 211 | dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); |
eb83092c AKG |
212 | return; |
213 | } | |
214 | last_timer = timeout; | |
215 | ||
5c8a86e1 | 216 | dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", |
3df00453 AG |
217 | otg_state_string(musb->xceiv->state), |
218 | jiffies_to_msecs(timeout - jiffies)); | |
eb83092c AKG |
219 | mod_timer(&otg_workaround, timeout); |
220 | } | |
221 | ||
743411b3 | 222 | static irqreturn_t am35x_musb_interrupt(int irq, void *hci) |
eb83092c AKG |
223 | { |
224 | struct musb *musb = hci; | |
225 | void __iomem *reg_base = musb->ctrl_base; | |
a9c03783 AKG |
226 | struct device *dev = musb->controller; |
227 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
228 | struct omap_musb_board_data *data = plat->board_data; | |
d445b6da | 229 | struct usb_otg *otg = musb->xceiv->otg; |
eb83092c AKG |
230 | unsigned long flags; |
231 | irqreturn_t ret = IRQ_NONE; | |
a9c03783 | 232 | u32 epintr, usbintr; |
eb83092c AKG |
233 | |
234 | spin_lock_irqsave(&musb->lock, flags); | |
235 | ||
236 | /* Get endpoint interrupts */ | |
237 | epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); | |
238 | ||
239 | if (epintr) { | |
240 | musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); | |
241 | ||
242 | musb->int_rx = | |
243 | (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; | |
244 | musb->int_tx = | |
245 | (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; | |
246 | } | |
247 | ||
248 | /* Get usb core interrupts */ | |
249 | usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); | |
250 | if (!usbintr && !epintr) | |
251 | goto eoi; | |
252 | ||
253 | if (usbintr) { | |
254 | musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); | |
255 | ||
256 | musb->int_usb = | |
257 | (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; | |
258 | } | |
259 | /* | |
260 | * DRVVBUS IRQs are the only proxy we have (a very poor one!) for | |
261 | * AM35x's missing ID change IRQ. We need an ID change IRQ to | |
262 | * switch appropriately between halves of the OTG state machine. | |
263 | * Managing DEVCTL.SESSION per Mentor docs requires that we know its | |
264 | * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
265 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
266 | */ | |
267 | if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { | |
268 | int drvvbus = musb_readl(reg_base, USB_STAT_REG); | |
269 | void __iomem *mregs = musb->mregs; | |
270 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
271 | int err; | |
272 | ||
273 | err = is_host_enabled(musb) && (musb->int_usb & | |
274 | MUSB_INTR_VBUSERROR); | |
275 | if (err) { | |
276 | /* | |
277 | * The Mentor core doesn't debounce VBUS as needed | |
278 | * to cope with device connect current spikes. This | |
279 | * means it's not uncommon for bus-powered devices | |
280 | * to get VBUS errors during enumeration. | |
281 | * | |
282 | * This is a workaround, but newer RTL from Mentor | |
283 | * seems to allow a better one: "re"-starting sessions | |
284 | * without waiting for VBUS to stop registering in | |
285 | * devctl. | |
286 | */ | |
287 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
288 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; | |
289 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
290 | WARNING("VBUS error workaround (delay coming)\n"); | |
291 | } else if (is_host_enabled(musb) && drvvbus) { | |
292 | MUSB_HST_MODE(musb); | |
d445b6da | 293 | otg->default_a = 1; |
eb83092c AKG |
294 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
295 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); | |
296 | del_timer(&otg_workaround); | |
297 | } else { | |
298 | musb->is_active = 0; | |
299 | MUSB_DEV_MODE(musb); | |
d445b6da | 300 | otg->default_a = 0; |
eb83092c AKG |
301 | musb->xceiv->state = OTG_STATE_B_IDLE; |
302 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); | |
303 | } | |
304 | ||
305 | /* NOTE: this must complete power-on within 100 ms. */ | |
5c8a86e1 | 306 | dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", |
eb83092c | 307 | drvvbus ? "on" : "off", |
3df00453 | 308 | otg_state_string(musb->xceiv->state), |
eb83092c AKG |
309 | err ? " ERROR" : "", |
310 | devctl); | |
311 | ret = IRQ_HANDLED; | |
312 | } | |
313 | ||
314 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
315 | ret |= musb_interrupt(musb); | |
316 | ||
317 | eoi: | |
318 | /* EOI needs to be written for the IRQ to be re-asserted. */ | |
319 | if (ret == IRQ_HANDLED || epintr || usbintr) { | |
320 | /* clear level interrupt */ | |
a9c03783 AKG |
321 | if (data->clear_irq) |
322 | data->clear_irq(); | |
eb83092c AKG |
323 | /* write EOI */ |
324 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
325 | } | |
326 | ||
327 | /* Poll for ID change */ | |
328 | if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) | |
329 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
330 | ||
331 | spin_unlock_irqrestore(&musb->lock, flags); | |
332 | ||
333 | return ret; | |
334 | } | |
335 | ||
743411b3 | 336 | static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) |
eb83092c | 337 | { |
a9c03783 AKG |
338 | struct device *dev = musb->controller; |
339 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
340 | struct omap_musb_board_data *data = plat->board_data; | |
341 | int retval = 0; | |
eb83092c | 342 | |
a9c03783 AKG |
343 | if (data->set_mode) |
344 | data->set_mode(musb_mode); | |
345 | else | |
346 | retval = -EIO; | |
eb83092c | 347 | |
a9c03783 | 348 | return retval; |
eb83092c AKG |
349 | } |
350 | ||
743411b3 | 351 | static int am35x_musb_init(struct musb *musb) |
eb83092c | 352 | { |
a9c03783 AKG |
353 | struct device *dev = musb->controller; |
354 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
355 | struct omap_musb_board_data *data = plat->board_data; | |
eb83092c | 356 | void __iomem *reg_base = musb->ctrl_base; |
a9c03783 | 357 | u32 rev; |
eb83092c AKG |
358 | |
359 | musb->mregs += USB_MENTOR_CORE_OFFSET; | |
360 | ||
eb83092c AKG |
361 | /* Returns zero if e.g. not clocked */ |
362 | rev = musb_readl(reg_base, USB_REVISION_REG); | |
03491761 FB |
363 | if (!rev) |
364 | return -ENODEV; | |
eb83092c AKG |
365 | |
366 | usb_nop_xceiv_register(); | |
721002ec | 367 | musb->xceiv = usb_get_phy(); |
03491761 FB |
368 | if (!musb->xceiv) |
369 | return -ENODEV; | |
eb83092c AKG |
370 | |
371 | if (is_host_enabled(musb)) | |
372 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); | |
373 | ||
a9c03783 AKG |
374 | /* Reset the musb */ |
375 | if (data->reset) | |
376 | data->reset(); | |
eb83092c AKG |
377 | |
378 | /* Reset the controller */ | |
379 | musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); | |
380 | ||
381 | /* Start the on-chip PHY and its PLL. */ | |
a9c03783 AKG |
382 | if (data->set_phy_power) |
383 | data->set_phy_power(1); | |
eb83092c AKG |
384 | |
385 | msleep(5); | |
386 | ||
743411b3 | 387 | musb->isr = am35x_musb_interrupt; |
eb83092c AKG |
388 | |
389 | /* clear level interrupt */ | |
a9c03783 AKG |
390 | if (data->clear_irq) |
391 | data->clear_irq(); | |
03491761 | 392 | |
eb83092c | 393 | return 0; |
eb83092c AKG |
394 | } |
395 | ||
743411b3 | 396 | static int am35x_musb_exit(struct musb *musb) |
eb83092c | 397 | { |
a9c03783 AKG |
398 | struct device *dev = musb->controller; |
399 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
400 | struct omap_musb_board_data *data = plat->board_data; | |
401 | ||
eb83092c AKG |
402 | if (is_host_enabled(musb)) |
403 | del_timer_sync(&otg_workaround); | |
404 | ||
a9c03783 AKG |
405 | /* Shutdown the on-chip PHY and its PLL. */ |
406 | if (data->set_phy_power) | |
407 | data->set_phy_power(0); | |
eb83092c | 408 | |
721002ec | 409 | usb_put_phy(musb->xceiv); |
eb83092c AKG |
410 | usb_nop_xceiv_unregister(); |
411 | ||
eb83092c AKG |
412 | return 0; |
413 | } | |
414 | ||
843bb1d0 AKG |
415 | /* AM35x supports only 32bit read operation */ |
416 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
417 | { | |
418 | void __iomem *fifo = hw_ep->fifo; | |
419 | u32 val; | |
420 | int i; | |
421 | ||
422 | /* Read for 32bit-aligned destination address */ | |
423 | if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { | |
424 | readsl(fifo, dst, len >> 2); | |
425 | dst += len & ~0x03; | |
426 | len &= 0x03; | |
427 | } | |
428 | /* | |
429 | * Now read the remaining 1 to 3 byte or complete length if | |
430 | * unaligned address. | |
431 | */ | |
432 | if (len > 4) { | |
433 | for (i = 0; i < (len >> 2); i++) { | |
434 | *(u32 *) dst = musb_readl(fifo, 0); | |
435 | dst += 4; | |
436 | } | |
437 | len &= 0x03; | |
438 | } | |
439 | if (len > 0) { | |
440 | val = musb_readl(fifo, 0); | |
441 | memcpy(dst, &val, len); | |
442 | } | |
443 | } | |
743411b3 | 444 | |
f7ec9437 | 445 | static const struct musb_platform_ops am35x_ops = { |
743411b3 FB |
446 | .init = am35x_musb_init, |
447 | .exit = am35x_musb_exit, | |
448 | ||
449 | .enable = am35x_musb_enable, | |
450 | .disable = am35x_musb_disable, | |
451 | ||
452 | .set_mode = am35x_musb_set_mode, | |
453 | .try_idle = am35x_musb_try_idle, | |
454 | ||
455 | .set_vbus = am35x_musb_set_vbus, | |
456 | }; | |
ce40c576 FB |
457 | |
458 | static u64 am35x_dmamask = DMA_BIT_MASK(32); | |
459 | ||
e9e8c85e | 460 | static int __devinit am35x_probe(struct platform_device *pdev) |
ce40c576 FB |
461 | { |
462 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
463 | struct platform_device *musb; | |
0919dfc1 | 464 | struct am35x_glue *glue; |
ce40c576 | 465 | |
03491761 FB |
466 | struct clk *phy_clk; |
467 | struct clk *clk; | |
468 | ||
ce40c576 FB |
469 | int ret = -ENOMEM; |
470 | ||
0919dfc1 FB |
471 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
472 | if (!glue) { | |
473 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
474 | goto err0; | |
475 | } | |
476 | ||
ce40c576 FB |
477 | musb = platform_device_alloc("musb-hdrc", -1); |
478 | if (!musb) { | |
479 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
0919dfc1 | 480 | goto err1; |
ce40c576 FB |
481 | } |
482 | ||
03491761 FB |
483 | phy_clk = clk_get(&pdev->dev, "fck"); |
484 | if (IS_ERR(phy_clk)) { | |
485 | dev_err(&pdev->dev, "failed to get PHY clock\n"); | |
486 | ret = PTR_ERR(phy_clk); | |
487 | goto err2; | |
488 | } | |
489 | ||
490 | clk = clk_get(&pdev->dev, "ick"); | |
491 | if (IS_ERR(clk)) { | |
492 | dev_err(&pdev->dev, "failed to get clock\n"); | |
493 | ret = PTR_ERR(clk); | |
494 | goto err3; | |
495 | } | |
496 | ||
497 | ret = clk_enable(phy_clk); | |
498 | if (ret) { | |
499 | dev_err(&pdev->dev, "failed to enable PHY clock\n"); | |
500 | goto err4; | |
501 | } | |
502 | ||
503 | ret = clk_enable(clk); | |
504 | if (ret) { | |
505 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
506 | goto err5; | |
507 | } | |
508 | ||
ce40c576 FB |
509 | musb->dev.parent = &pdev->dev; |
510 | musb->dev.dma_mask = &am35x_dmamask; | |
511 | musb->dev.coherent_dma_mask = am35x_dmamask; | |
512 | ||
0919dfc1 FB |
513 | glue->dev = &pdev->dev; |
514 | glue->musb = musb; | |
03491761 FB |
515 | glue->phy_clk = phy_clk; |
516 | glue->clk = clk; | |
0919dfc1 | 517 | |
f7ec9437 FB |
518 | pdata->platform_ops = &am35x_ops; |
519 | ||
0919dfc1 | 520 | platform_set_drvdata(pdev, glue); |
ce40c576 FB |
521 | |
522 | ret = platform_device_add_resources(musb, pdev->resource, | |
523 | pdev->num_resources); | |
524 | if (ret) { | |
525 | dev_err(&pdev->dev, "failed to add resources\n"); | |
03491761 | 526 | goto err6; |
ce40c576 FB |
527 | } |
528 | ||
529 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
530 | if (ret) { | |
531 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
03491761 | 532 | goto err6; |
ce40c576 FB |
533 | } |
534 | ||
535 | ret = platform_device_add(musb); | |
536 | if (ret) { | |
537 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
03491761 | 538 | goto err6; |
ce40c576 FB |
539 | } |
540 | ||
541 | return 0; | |
542 | ||
03491761 FB |
543 | err6: |
544 | clk_disable(clk); | |
545 | ||
546 | err5: | |
547 | clk_disable(phy_clk); | |
548 | ||
549 | err4: | |
550 | clk_put(clk); | |
551 | ||
552 | err3: | |
553 | clk_put(phy_clk); | |
554 | ||
0919dfc1 | 555 | err2: |
ce40c576 FB |
556 | platform_device_put(musb); |
557 | ||
0919dfc1 FB |
558 | err1: |
559 | kfree(glue); | |
560 | ||
ce40c576 FB |
561 | err0: |
562 | return ret; | |
563 | } | |
564 | ||
e9e8c85e | 565 | static int __devexit am35x_remove(struct platform_device *pdev) |
ce40c576 | 566 | { |
0919dfc1 | 567 | struct am35x_glue *glue = platform_get_drvdata(pdev); |
ce40c576 | 568 | |
0919dfc1 FB |
569 | platform_device_del(glue->musb); |
570 | platform_device_put(glue->musb); | |
03491761 FB |
571 | clk_disable(glue->clk); |
572 | clk_disable(glue->phy_clk); | |
573 | clk_put(glue->clk); | |
574 | clk_put(glue->phy_clk); | |
0919dfc1 | 575 | kfree(glue); |
ce40c576 FB |
576 | |
577 | return 0; | |
578 | } | |
579 | ||
6f783e28 FB |
580 | #ifdef CONFIG_PM |
581 | static int am35x_suspend(struct device *dev) | |
582 | { | |
583 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
a9c03783 AKG |
584 | struct musb_hdrc_platform_data *plat = dev->platform_data; |
585 | struct omap_musb_board_data *data = plat->board_data; | |
586 | ||
587 | /* Shutdown the on-chip PHY and its PLL. */ | |
588 | if (data->set_phy_power) | |
589 | data->set_phy_power(0); | |
6f783e28 | 590 | |
6f783e28 FB |
591 | clk_disable(glue->phy_clk); |
592 | clk_disable(glue->clk); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static int am35x_resume(struct device *dev) | |
598 | { | |
599 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
a9c03783 AKG |
600 | struct musb_hdrc_platform_data *plat = dev->platform_data; |
601 | struct omap_musb_board_data *data = plat->board_data; | |
6f783e28 FB |
602 | int ret; |
603 | ||
a9c03783 AKG |
604 | /* Start the on-chip PHY and its PLL. */ |
605 | if (data->set_phy_power) | |
606 | data->set_phy_power(1); | |
607 | ||
6f783e28 FB |
608 | ret = clk_enable(glue->phy_clk); |
609 | if (ret) { | |
610 | dev_err(dev, "failed to enable PHY clock\n"); | |
611 | return ret; | |
612 | } | |
613 | ||
614 | ret = clk_enable(glue->clk); | |
615 | if (ret) { | |
616 | dev_err(dev, "failed to enable clock\n"); | |
617 | return ret; | |
618 | } | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
623 | static struct dev_pm_ops am35x_pm_ops = { | |
624 | .suspend = am35x_suspend, | |
625 | .resume = am35x_resume, | |
626 | }; | |
627 | ||
628 | #define DEV_PM_OPS &am35x_pm_ops | |
629 | #else | |
630 | #define DEV_PM_OPS NULL | |
631 | #endif | |
632 | ||
ce40c576 | 633 | static struct platform_driver am35x_driver = { |
e9e8c85e FB |
634 | .probe = am35x_probe, |
635 | .remove = __devexit_p(am35x_remove), | |
ce40c576 FB |
636 | .driver = { |
637 | .name = "musb-am35x", | |
6f783e28 | 638 | .pm = DEV_PM_OPS, |
ce40c576 FB |
639 | }, |
640 | }; | |
641 | ||
642 | MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); | |
643 | MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); | |
644 | MODULE_LICENSE("GPL v2"); | |
645 | ||
646 | static int __init am35x_init(void) | |
647 | { | |
e9e8c85e | 648 | return platform_driver_register(&am35x_driver); |
ce40c576 | 649 | } |
e9e8c85e | 650 | module_init(am35x_init); |
ce40c576 FB |
651 | |
652 | static void __exit am35x_exit(void) | |
653 | { | |
654 | platform_driver_unregister(&am35x_driver); | |
655 | } | |
656 | module_exit(am35x_exit); |