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usb: musb: fix incorrect usage of resource pointer
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375
FB		 85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
9303961f 99#include <linux/prefetch.h>
550a7375
FB		 100#include <linux/platform_device.h>
101#include <linux/io.h>
65b3d52d 102#include <linux/idr.h>
8d2421e6 103#include <linux/dma-mapping.h>
550a7375 104
550a7375
FB		 105#include "musb_core.h"
106
f7f9d63e 107#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 108
109
550a7375
FB		 110#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112
e8164f64 113#define MUSB_VERSION "6.0"
550a7375
FB		 114
115#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116
05ac10dd 117#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 118const char musb_driver_name[] = MUSB_DRIVER_NAME;
119
120MODULE_DESCRIPTION(DRIVER_INFO);
121MODULE_AUTHOR(DRIVER_AUTHOR);
122MODULE_LICENSE("GPL");
123MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124
125
126/*-------------------------------------------------------------------------*/
127
128static inline struct musb *dev_to_musb(struct device *dev)
129{
550a7375 130 return dev_get_drvdata(dev);
550a7375
FB		 131}
132
133/*-------------------------------------------------------------------------*/
134
ffb865b1 135#ifndef CONFIG_BLACKFIN
b96d3b08 136static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
ffb865b1 137{
b96d3b08 138 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 139 int i = 0;
140 u8 r;
141 u8 power;
bf070bc1
GI		 142 int ret;
143
144 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 145
146 /* Make sure the transceiver is not in low power mode */
147 power = musb_readb(addr, MUSB_POWER);
148 power &= ~MUSB_POWER_SUSPENDM;
149 musb_writeb(addr, MUSB_POWER, power);
150
151 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
152 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 */
154
155 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
156 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
157 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
158
159 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
160 & MUSB_ULPI_REG_CMPLT)) {
161 i++;
bf070bc1
GI		 162 if (i == 10000) {
163 ret = -ETIMEDOUT;
164 goto out;
165 }
ffb865b1
HK		 166
167 }
168 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
169 r &= ~MUSB_ULPI_REG_CMPLT;
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
171
bf070bc1
GI		 172 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173
174out:
175 pm_runtime_put(phy->io_dev);
176
177 return ret;
ffb865b1
HK		 178}
179
b96d3b08 180static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
ffb865b1 181{
b96d3b08 182 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 183 int i = 0;
184 u8 r = 0;
185 u8 power;
bf070bc1
GI		 186 int ret = 0;
187
188 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 189
190 /* Make sure the transceiver is not in low power mode */
191 power = musb_readb(addr, MUSB_POWER);
192 power &= ~MUSB_POWER_SUSPENDM;
193 musb_writeb(addr, MUSB_POWER, power);
194
195 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
196 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
197 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198
199 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
200 & MUSB_ULPI_REG_CMPLT)) {
201 i++;
bf070bc1
GI		 202 if (i == 10000) {
203 ret = -ETIMEDOUT;
204 goto out;
205 }
ffb865b1
HK		 206 }
207
208 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
209 r &= ~MUSB_ULPI_REG_CMPLT;
210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
211
bf070bc1
GI		 212out:
213 pm_runtime_put(phy->io_dev);
214
215 return ret;
ffb865b1
HK		 216}
217#else
f2263db7
MF		 218#define musb_ulpi_read NULL
219#define musb_ulpi_write NULL
ffb865b1
HK		 220#endif
221
b96d3b08 222static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 223 .read = musb_ulpi_read,
224 .write = musb_ulpi_write,
225};
226
227/*-------------------------------------------------------------------------*/
228
7c925546 229#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
c6cf8b00 230
550a7375
FB		 231/*
232 * Load an endpoint's FIFO
233 */
234void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
235{
5c8a86e1 236 struct musb *musb = hw_ep->musb;
550a7375
FB		 237 void __iomem *fifo = hw_ep->fifo;
238
603fe2b2
AKG		 239 if (unlikely(len == 0))
240 return;
241
550a7375
FB		 242 prefetch((u8 *)src);
243
5c8a86e1 244 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 245 'T', hw_ep->epnum, fifo, len, src);
246
247 /* we can't assume unaligned reads work */
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251 /* best case is 32bit-aligned source address */
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
2bf0a8f6 254 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
2bf0a8f6 263 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270 /* byte aligned */
2bf0a8f6 271 iowrite8_rep(fifo, src, len);
550a7375
FB		 272 }
273}
274
843bb1d0 275#if !defined(CONFIG_USB_MUSB_AM35X)
550a7375
FB		 276/*
277 * Unload an endpoint's FIFO
278 */
279void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
280{
5c8a86e1 281 struct musb *musb = hw_ep->musb;
550a7375
FB		 282 void __iomem *fifo = hw_ep->fifo;
283
603fe2b2
AKG		 284 if (unlikely(len == 0))
285 return;
286
5c8a86e1 287 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 288 'R', hw_ep->epnum, fifo, len, dst);
289
290 /* we can't assume unaligned writes work */
291 if (likely((0x01 & (unsigned long) dst) == 0)) {
292 u16 index = 0;
293
294 /* best case is 32bit-aligned destination address */
295 if ((0x02 & (unsigned long) dst) == 0) {
296 if (len >= 4) {
2bf0a8f6 297 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 298 index = len & ~0x03;
299 }
300 if (len & 0x02) {
301 *(u16 *)&dst[index] = musb_readw(fifo, 0);
302 index += 2;
303 }
304 } else {
305 if (len >= 2) {
2bf0a8f6 306 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 307 index = len & ~0x01;
308 }
309 }
310 if (len & 0x01)
311 dst[index] = musb_readb(fifo, 0);
312 } else {
313 /* byte aligned */
2bf0a8f6 314 ioread8_rep(fifo, dst, len);
550a7375
FB		 315 }
316}
843bb1d0 317#endif
550a7375
FB		 318
319#endif /* normal PIO */
320
321
322/*-------------------------------------------------------------------------*/
323
324/* for high speed test mode; see USB 2.0 spec 7.1.20 */
325static const u8 musb_test_packet[53] = {
326 /* implicit SYNC then DATA0 to start */
327
328 /* JKJKJKJK x9 */
329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
330 /* JJKKJJKK x8 */
331 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
332 /* JJJJKKKK x8 */
333 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
334 /* JJJJJJJKKKKKKK x8 */
335 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
336 /* JJJJJJJK x8 */
337 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
338 /* JKKKKKKK x10, JK */
339 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
340
341 /* implicit CRC16 then EOP to end */
342};
343
344void musb_load_testpacket(struct musb *musb)
345{
346 void __iomem *regs = musb->endpoints[0].regs;
347
348 musb_ep_select(musb->mregs, 0);
349 musb_write_fifo(musb->control_ep,
350 sizeof(musb_test_packet), musb_test_packet);
351 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
352}
353
354/*-------------------------------------------------------------------------*/
355
550a7375
FB		 356/*
357 * Handles OTG hnp timeouts, such as b_ase0_brst
358 */
a156544b 359static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 360{
361 struct musb *musb = (struct musb *)data;
362 unsigned long flags;
363
364 spin_lock_irqsave(&musb->lock, flags);
84e250ff 365 switch (musb->xceiv->state) {
550a7375 366 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 367 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 368 musb_g_disconnect(musb);
84e250ff 369 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 370 musb->is_active = 0;
371 break;
ab983f2a 372 case OTG_STATE_A_SUSPEND:
550a7375 373 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 374 dev_dbg(musb->controller, "HNP: %s timeout\n",
42c0bf1c 375 usb_otg_state_string(musb->xceiv->state));
743411b3 376 musb_platform_set_vbus(musb, 0);
ab983f2a 377 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 378 break;
379 default:
5c8a86e1 380 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
42c0bf1c 381 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 382 }
383 musb->ignore_disconnect = 0;
384 spin_unlock_irqrestore(&musb->lock, flags);
385}
386
550a7375 387/*
f7f9d63e 388 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 389 */
390void musb_hnp_stop(struct musb *musb)
391{
392 struct usb_hcd *hcd = musb_to_hcd(musb);
393 void __iomem *mbase = musb->mregs;
394 u8 reg;
395
42c0bf1c
FB		 396 dev_dbg(musb->controller, "HNP: stop from %s\n",
397 usb_otg_state_string(musb->xceiv->state));
ab983f2a 398
84e250ff 399 switch (musb->xceiv->state) {
550a7375 400 case OTG_STATE_A_PERIPHERAL:
550a7375 401 musb_g_disconnect(musb);
5c8a86e1 402 dev_dbg(musb->controller, "HNP: back to %s\n",
42c0bf1c 403 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 404 break;
405 case OTG_STATE_B_HOST:
5c8a86e1 406 dev_dbg(musb->controller, "HNP: Disabling HR\n");
550a7375 407 hcd->self.is_b_host = 0;
84e250ff 408 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 409 MUSB_DEV_MODE(musb);
410 reg = musb_readb(mbase, MUSB_POWER);
411 reg |= MUSB_POWER_SUSPENDM;
412 musb_writeb(mbase, MUSB_POWER, reg);
413 /* REVISIT: Start SESSION_REQUEST here? */
414 break;
415 default:
5c8a86e1 416 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
42c0bf1c 417 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 418 }
419
420 /*
421 * When returning to A state after HNP, avoid hub_port_rebounce(),
422 * which cause occasional OPT A "Did not receive reset after connect"
423 * errors.
424 */
749da5f8 425 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 426}
427
550a7375
FB		 428/*
429 * Interrupt Service Routine to record USB "global" interrupts.
430 * Since these do not happen often and signify things of
431 * paramount importance, it seems OK to check them individually;
432 * the order of the tests is specified in the manual
433 *
434 * @param musb instance pointer
435 * @param int_usb register contents
436 * @param devctl
437 * @param power
438 */
439
550a7375 440static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 441 u8 devctl)
550a7375 442{
d445b6da 443 struct usb_otg *otg = musb->xceiv->otg;
550a7375 444 irqreturn_t handled = IRQ_NONE;
550a7375 445
b11e94d0 446 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 447 int_usb);
448
449 /* in host mode, the peripheral may issue remote wakeup.
450 * in peripheral mode, the host may resume the link.
451 * spurious RESUME irqs happen too, paired with SUSPEND.
452 */
453 if (int_usb & MUSB_INTR_RESUME) {
454 handled = IRQ_HANDLED;
42c0bf1c 455 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 456
457 if (devctl & MUSB_DEVCTL_HM) {
aa471456 458 void __iomem *mbase = musb->mregs;
b11e94d0 459 u8 power;
aa471456 460
84e250ff 461 switch (musb->xceiv->state) {
550a7375
FB		 462 case OTG_STATE_A_SUSPEND:
463 /* remote wakeup? later, GetPortStatus
464 * will stop RESUME signaling
465 */
466
b11e94d0 467 power = musb_readb(musb->mregs, MUSB_POWER);
550a7375
FB		 468 if (power & MUSB_POWER_SUSPENDM) {
469 /* spurious */
470 musb->int_usb &= ~MUSB_INTR_SUSPEND;
5c8a86e1 471 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
550a7375
FB		 472 break;
473 }
474
475 power &= ~MUSB_POWER_SUSPENDM;
476 musb_writeb(mbase, MUSB_POWER,
477 power | MUSB_POWER_RESUME);
478
479 musb->port1_status |=
480 (USB_PORT_STAT_C_SUSPEND << 16)
481 | MUSB_PORT_STAT_RESUME;
482 musb->rh_timer = jiffies
483 + msecs_to_jiffies(20);
484
84e250ff 485 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 486 musb->is_active = 1;
487 usb_hcd_resume_root_hub(musb_to_hcd(musb));
488 break;
489 case OTG_STATE_B_WAIT_ACON:
84e250ff 490 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 491 musb->is_active = 1;
492 MUSB_DEV_MODE(musb);
493 break;
494 default:
495 WARNING("bogus %s RESUME (%s)\n",
496 "host",
42c0bf1c 497 usb_otg_state_string(musb->xceiv->state));
550a7375 498 }
550a7375 499 } else {
84e250ff 500 switch (musb->xceiv->state) {
550a7375
FB		 501 case OTG_STATE_A_SUSPEND:
502 /* possibly DISCONNECT is upcoming */
84e250ff 503 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 504 usb_hcd_resume_root_hub(musb_to_hcd(musb));
505 break;
550a7375
FB		 506 case OTG_STATE_B_WAIT_ACON:
507 case OTG_STATE_B_PERIPHERAL:
508 /* disconnect while suspended? we may
509 * not get a disconnect irq...
510 */
511 if ((devctl & MUSB_DEVCTL_VBUS)
512 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
513 ) {
514 musb->int_usb |= MUSB_INTR_DISCONNECT;
515 musb->int_usb &= ~MUSB_INTR_SUSPEND;
516 break;
517 }
518 musb_g_resume(musb);
519 break;
520 case OTG_STATE_B_IDLE:
521 musb->int_usb &= ~MUSB_INTR_SUSPEND;
522 break;
550a7375
FB		 523 default:
524 WARNING("bogus %s RESUME (%s)\n",
525 "peripheral",
42c0bf1c 526 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 527 }
528 }
529 }
530
550a7375
FB		 531 /* see manual for the order of the tests */
532 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 533 void __iomem *mbase = musb->mregs;
534
19aab56c
HK		 535 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
536 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 537 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 538 return IRQ_HANDLED;
539 }
540
5c8a86e1 541 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
42c0bf1c 542 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 543
544 /* IRQ arrives from ID pin sense or (later, if VBUS power
545 * is removed) SRP. responses are time critical:
546 * - turn on VBUS (with silicon-specific mechanism)
547 * - go through A_WAIT_VRISE
548 * - ... to A_WAIT_BCON.
549 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
550 */
551 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
552 musb->ep0_stage = MUSB_EP0_START;
84e250ff 553 musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 554 MUSB_HST_MODE(musb);
743411b3 555 musb_platform_set_vbus(musb, 1);
550a7375
FB		 556
557 handled = IRQ_HANDLED;
558 }
559
560 if (int_usb & MUSB_INTR_VBUSERROR) {
561 int ignore = 0;
562
563 /* During connection as an A-Device, we may see a short
564 * current spikes causing voltage drop, because of cable
565 * and peripheral capacitance combined with vbus draw.
566 * (So: less common with truly self-powered devices, where
567 * vbus doesn't act like a power supply.)
568 *
569 * Such spikes are short; usually less than ~500 usec, max
570 * of ~2 msec. That is, they're not sustained overcurrent
571 * errors, though they're reported using VBUSERROR irqs.
572 *
573 * Workarounds: (a) hardware: use self powered devices.
574 * (b) software: ignore non-repeated VBUS errors.
575 *
576 * REVISIT: do delays from lots of DEBUG_KERNEL checks
577 * make trouble here, keeping VBUS < 4.4V ?
578 */
84e250ff 579 switch (musb->xceiv->state) {
550a7375
FB		 580 case OTG_STATE_A_HOST:
581 /* recovery is dicey once we've gotten past the
582 * initial stages of enumeration, but if VBUS
583 * stayed ok at the other end of the link, and
584 * another reset is due (at least for high speed,
585 * to redo the chirp etc), it might work OK...
586 */
587 case OTG_STATE_A_WAIT_BCON:
588 case OTG_STATE_A_WAIT_VRISE:
589 if (musb->vbuserr_retry) {
aa471456
FB		 590 void __iomem *mbase = musb->mregs;
591
550a7375
FB		 592 musb->vbuserr_retry--;
593 ignore = 1;
594 devctl |= MUSB_DEVCTL_SESSION;
595 musb_writeb(mbase, MUSB_DEVCTL, devctl);
596 } else {
597 musb->port1_status |=
749da5f8
AS		 598 USB_PORT_STAT_OVERCURRENT
599 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 600 }
601 break;
602 default:
603 break;
604 }
605
54485116
GI		 606 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
607 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
42c0bf1c 608 usb_otg_state_string(musb->xceiv->state),
550a7375
FB		 609 devctl,
610 ({ char *s;
611 switch (devctl & MUSB_DEVCTL_VBUS) {
612 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
613 s = "<SessEnd"; break;
614 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
615 s = "<AValid"; break;
616 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
617 s = "<VBusValid"; break;
618 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
619 default:
620 s = "VALID"; break;
621 }; s; }),
622 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
623 musb->port1_status);
624
625 /* go through A_WAIT_VFALL then start a new session */
626 if (!ignore)
743411b3 627 musb_platform_set_vbus(musb, 0);
550a7375
FB		 628 handled = IRQ_HANDLED;
629 }
630
1c25fda4 631 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0 632 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
42c0bf1c 633 usb_otg_state_string(musb->xceiv->state), devctl);
1c25fda4
AM		 634 handled = IRQ_HANDLED;
635
636 switch (musb->xceiv->state) {
1c25fda4
AM		 637 case OTG_STATE_A_PERIPHERAL:
638 /* We also come here if the cable is removed, since
639 * this silicon doesn't report ID-no-longer-grounded.
640 *
641 * We depend on T(a_wait_bcon) to shut us down, and
642 * hope users don't do anything dicey during this
643 * undesired detour through A_WAIT_BCON.
644 */
645 musb_hnp_stop(musb);
646 usb_hcd_resume_root_hub(musb_to_hcd(musb));
647 musb_root_disconnect(musb);
648 musb_platform_try_idle(musb, jiffies
649 + msecs_to_jiffies(musb->a_wait_bcon
650 ? : OTG_TIME_A_WAIT_BCON));
651
652 break;
1c25fda4
AM		 653 case OTG_STATE_B_IDLE:
654 if (!musb->is_active)
655 break;
656 case OTG_STATE_B_PERIPHERAL:
657 musb_g_suspend(musb);
032ec49f 658 musb->is_active = otg->gadget->b_hnp_enable;
1c25fda4 659 if (musb->is_active) {
1c25fda4 660 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 661 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 662 mod_timer(&musb->otg_timer, jiffies
663 + msecs_to_jiffies(
664 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 665 }
666 break;
667 case OTG_STATE_A_WAIT_BCON:
668 if (musb->a_wait_bcon != 0)
669 musb_platform_try_idle(musb, jiffies
670 + msecs_to_jiffies(musb->a_wait_bcon));
671 break;
672 case OTG_STATE_A_HOST:
673 musb->xceiv->state = OTG_STATE_A_SUSPEND;
032ec49f 674 musb->is_active = otg->host->b_hnp_enable;
1c25fda4
AM		 675 break;
676 case OTG_STATE_B_HOST:
677 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 678 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 679 break;
680 default:
681 /* "should not happen" */
682 musb->is_active = 0;
683 break;
684 }
685 }
686
550a7375
FB		 687 if (int_usb & MUSB_INTR_CONNECT) {
688 struct usb_hcd *hcd = musb_to_hcd(musb);
689
690 handled = IRQ_HANDLED;
691 musb->is_active = 1;
550a7375
FB		 692
693 musb->ep0_stage = MUSB_EP0_START;
694
550a7375
FB		 695 /* flush endpoints when transitioning from Device Mode */
696 if (is_peripheral_active(musb)) {
697 /* REVISIT HNP; just force disconnect */
698 }
b18d26f6
SAS		 699 musb->intrtxe = musb->epmask;
700 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 701 musb->intrrxe = musb->epmask & 0xfffe;
702 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 703 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 704 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
705 |USB_PORT_STAT_HIGH_SPEED
706 |USB_PORT_STAT_ENABLE
707 );
708 musb->port1_status |= USB_PORT_STAT_CONNECTION
709 |(USB_PORT_STAT_C_CONNECTION << 16);
710
711 /* high vs full speed is just a guess until after reset */
712 if (devctl & MUSB_DEVCTL_LSDEV)
713 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
714
550a7375 715 /* indicate new connection to OTG machine */
84e250ff 716 switch (musb->xceiv->state) {
550a7375
FB		 717 case OTG_STATE_B_PERIPHERAL:
718 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 719 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 720 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 721 goto b_host;
550a7375 722 } else
5c8a86e1 723 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 724 break;
725 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 726 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 727b_host:
84e250ff 728 musb->xceiv->state = OTG_STATE_B_HOST;
550a7375 729 hcd->self.is_b_host = 1;
1de00dae
DB		 730 musb->ignore_disconnect = 0;
731 del_timer(&musb->otg_timer);
550a7375
FB		 732 break;
733 default:
734 if ((devctl & MUSB_DEVCTL_VBUS)
735 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
84e250ff 736 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 737 hcd->self.is_b_host = 0;
738 }
739 break;
740 }
1de00dae
DB		 741
742 /* poke the root hub */
743 MUSB_HST_MODE(musb);
744 if (hcd->status_urb)
745 usb_hcd_poll_rh_status(hcd);
746 else
747 usb_hcd_resume_root_hub(hcd);
748
5c8a86e1 749 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
42c0bf1c 750 usb_otg_state_string(musb->xceiv->state), devctl);
550a7375 751 }
550a7375 752
1c25fda4 753 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
5c8a86e1 754 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
42c0bf1c 755 usb_otg_state_string(musb->xceiv->state),
1c25fda4
AM		 756 MUSB_MODE(musb), devctl);
757 handled = IRQ_HANDLED;
758
759 switch (musb->xceiv->state) {
1c25fda4
AM		 760 case OTG_STATE_A_HOST:
761 case OTG_STATE_A_SUSPEND:
762 usb_hcd_resume_root_hub(musb_to_hcd(musb));
763 musb_root_disconnect(musb);
032ec49f 764 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 765 musb_platform_try_idle(musb, jiffies
766 + msecs_to_jiffies(musb->a_wait_bcon));
767 break;
1c25fda4
AM		 768 case OTG_STATE_B_HOST:
769 /* REVISIT this behaves for "real disconnect"
770 * cases; make sure the other transitions from
771 * from B_HOST act right too. The B_HOST code
772 * in hnp_stop() is currently not used...
773 */
774 musb_root_disconnect(musb);
775 musb_to_hcd(musb)->self.is_b_host = 0;
776 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
777 MUSB_DEV_MODE(musb);
778 musb_g_disconnect(musb);
779 break;
780 case OTG_STATE_A_PERIPHERAL:
781 musb_hnp_stop(musb);
782 musb_root_disconnect(musb);
783 /* FALLTHROUGH */
784 case OTG_STATE_B_WAIT_ACON:
785 /* FALLTHROUGH */
1c25fda4
AM		 786 case OTG_STATE_B_PERIPHERAL:
787 case OTG_STATE_B_IDLE:
788 musb_g_disconnect(musb);
789 break;
1c25fda4
AM		 790 default:
791 WARNING("unhandled DISCONNECT transition (%s)\n",
42c0bf1c 792 usb_otg_state_string(musb->xceiv->state));
1c25fda4
AM		 793 break;
794 }
795 }
796
550a7375
FB		 797 /* mentor saves a bit: bus reset and babble share the same irq.
798 * only host sees babble; only peripheral sees bus reset.
799 */
800 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 801 handled = IRQ_HANDLED;
a04d46d0 802 if ((devctl & MUSB_DEVCTL_HM) != 0) {
550a7375
FB		 803 /*
804 * Looks like non-HS BABBLE can be ignored, but
805 * HS BABBLE is an error condition. For HS the solution
806 * is to avoid babble in the first place and fix what
807 * caused BABBLE. When HS BABBLE happens we can only
808 * stop the session.
809 */
810 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
5c8a86e1 811 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
550a7375
FB		 812 else {
813 ERR("Stopping host session -- babble\n");
1c25fda4 814 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 815 }
a04d46d0 816 } else {
5c8a86e1 817 dev_dbg(musb->controller, "BUS RESET as %s\n",
42c0bf1c 818 usb_otg_state_string(musb->xceiv->state));
84e250ff 819 switch (musb->xceiv->state) {
550a7375
FB		 820 case OTG_STATE_A_SUSPEND:
821 /* We need to ignore disconnect on suspend
822 * otherwise tusb 2.0 won't reconnect after a
823 * power cycle, which breaks otg compliance.
824 */
825 musb->ignore_disconnect = 1;
826 musb_g_reset(musb);
827 /* FALLTHROUGH */
828 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 829 /* never use invalid T(a_wait_bcon) */
5c8a86e1 830 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
42c0bf1c 831 usb_otg_state_string(musb->xceiv->state),
3df00453 832 TA_WAIT_BCON(musb));
f7f9d63e
DB		 833 mod_timer(&musb->otg_timer, jiffies
834 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 835 break;
836 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 837 musb->ignore_disconnect = 0;
838 del_timer(&musb->otg_timer);
839 musb_g_reset(musb);
550a7375
FB		 840 break;
841 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 842 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
42c0bf1c 843 usb_otg_state_string(musb->xceiv->state));
84e250ff 844 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 845 musb_g_reset(musb);
846 break;
550a7375 847 case OTG_STATE_B_IDLE:
84e250ff 848 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 849 /* FALLTHROUGH */
850 case OTG_STATE_B_PERIPHERAL:
851 musb_g_reset(musb);
852 break;
853 default:
5c8a86e1 854 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
42c0bf1c 855 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 856 }
857 }
550a7375 858 }
550a7375
FB		 859
860#if 0
861/* REVISIT ... this would be for multiplexing periodic endpoints, or
862 * supporting transfer phasing to prevent exceeding ISO bandwidth
863 * limits of a given frame or microframe.
864 *
865 * It's not needed for peripheral side, which dedicates endpoints;
866 * though it _might_ use SOF irqs for other purposes.
867 *
868 * And it's not currently needed for host side, which also dedicates
869 * endpoints, relies on TX/RX interval registers, and isn't claimed
870 * to support ISO transfers yet.
871 */
872 if (int_usb & MUSB_INTR_SOF) {
873 void __iomem *mbase = musb->mregs;
874 struct musb_hw_ep *ep;
875 u8 epnum;
876 u16 frame;
877
5c8a86e1 878 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 879 handled = IRQ_HANDLED;
880
881 /* start any periodic Tx transfers waiting for current frame */
882 frame = musb_readw(mbase, MUSB_FRAME);
883 ep = musb->endpoints;
884 for (epnum = 1; (epnum < musb->nr_endpoints)
885 && (musb->epmask >= (1 << epnum));
886 epnum++, ep++) {
887 /*
888 * FIXME handle framecounter wraps (12 bits)
889 * eliminate duplicated StartUrb logic
890 */
891 if (ep->dwWaitFrame >= frame) {
892 ep->dwWaitFrame = 0;
893 pr_debug("SOF --> periodic TX%s on %d\n",
894 ep->tx_channel ? " DMA" : "",
895 epnum);
896 if (!ep->tx_channel)
897 musb_h_tx_start(musb, epnum);
898 else
899 cppi_hostdma_start(musb, epnum);
900 }
901 } /* end of for loop */
902 }
903#endif
904
1c25fda4 905 schedule_work(&musb->irq_work);
550a7375
FB		 906
907 return handled;
908}
909
910/*-------------------------------------------------------------------------*/
911
912/*
913* Program the HDRC to start (enable interrupts, dma, etc.).
914*/
915void musb_start(struct musb *musb)
916{
917 void __iomem *regs = musb->mregs;
918 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
919
5c8a86e1 920 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
550a7375
FB		 921
922 /* Set INT enable registers, enable interrupts */
b18d26f6
SAS		 923 musb->intrtxe = musb->epmask;
924 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 925 musb->intrrxe = musb->epmask & 0xfffe;
926 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
550a7375
FB		 927 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
928
929 musb_writeb(regs, MUSB_TESTMODE, 0);
930
931 /* put into basic highspeed mode and start session */
932 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
550a7375
FB		 933 | MUSB_POWER_HSENAB
934 /* ENSUSPEND wedges tusb */
935 /* | MUSB_POWER_ENSUSPEND */
936 );
937
938 musb->is_active = 0;
939 devctl = musb_readb(regs, MUSB_DEVCTL);
940 devctl &= ~MUSB_DEVCTL_SESSION;
941
032ec49f
FB		 942 /* session started after:
943 * (a) ID-grounded irq, host mode;
944 * (b) vbus present/connect IRQ, peripheral mode;
945 * (c) peripheral initiates, using SRP
946 */
947 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
948 musb->is_active = 1;
949 else
550a7375
FB		 950 devctl |= MUSB_DEVCTL_SESSION;
951
550a7375
FB		 952 musb_platform_enable(musb);
953 musb_writeb(regs, MUSB_DEVCTL, devctl);
954}
955
956
957static void musb_generic_disable(struct musb *musb)
958{
959 void __iomem *mbase = musb->mregs;
960 u16 temp;
961
962 /* disable interrupts */
963 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 964 musb->intrtxe = 0;
550a7375 965 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 966 musb->intrrxe = 0;
550a7375
FB		 967 musb_writew(mbase, MUSB_INTRRXE, 0);
968
969 /* off */
970 musb_writeb(mbase, MUSB_DEVCTL, 0);
971
972 /* flush pending interrupts */
973 temp = musb_readb(mbase, MUSB_INTRUSB);
974 temp = musb_readw(mbase, MUSB_INTRTX);
975 temp = musb_readw(mbase, MUSB_INTRRX);
976
977}
978
979/*
980 * Make the HDRC stop (disable interrupts, etc.);
981 * reversible by musb_start
982 * called on gadget driver unregister
983 * with controller locked, irqs blocked
984 * acts as a NOP unless some role activated the hardware
985 */
986void musb_stop(struct musb *musb)
987{
988 /* stop IRQs, timers, ... */
989 musb_platform_disable(musb);
990 musb_generic_disable(musb);
5c8a86e1 991 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 992
993 /* FIXME
994 * - mark host and/or peripheral drivers unusable/inactive
995 * - disable DMA (and enable it in HdrcStart)
996 * - make sure we can musb_start() after musb_stop(); with
997 * OTG mode, gadget driver module rmmod/modprobe cycles that
998 * - ...
999 */
1000 musb_platform_try_idle(musb, 0);
1001}
1002
1003static void musb_shutdown(struct platform_device *pdev)
1004{
1005 struct musb *musb = dev_to_musb(&pdev->dev);
1006 unsigned long flags;
1007
4f9edd2d 1008 pm_runtime_get_sync(musb->controller);
24307cae
GI		 1009
1010 musb_gadget_cleanup(musb);
1011
550a7375
FB		 1012 spin_lock_irqsave(&musb->lock, flags);
1013 musb_platform_disable(musb);
1014 musb_generic_disable(musb);
550a7375
FB		 1015 spin_unlock_irqrestore(&musb->lock, flags);
1016
120d074c
GI		 1017 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1018 musb_platform_exit(musb);
120d074c 1019
4f9edd2d 1020 pm_runtime_put(musb->controller);
550a7375
FB		 1021 /* FIXME power down */
1022}
1023
1024
1025/*-------------------------------------------------------------------------*/
1026
1027/*
1028 * The silicon either has hard-wired endpoint configurations, or else
1029 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1030 * writing only the dynamic sizing is very well tested. Since we switched
1031 * away from compile-time hardware parameters, we can no longer rely on
1032 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1033 *
1034 * We don't currently use dynamic fifo setup capability to do anything
1035 * more than selecting one of a bunch of predefined configurations.
1036 */
ee34e51a
FB		 1037#if defined(CONFIG_USB_MUSB_TUSB6010) \
1038 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1039 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1040 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1041 || defined(CONFIG_USB_MUSB_AM35X) \
9ecb8875
AKG		 1042 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1043 || defined(CONFIG_USB_MUSB_DSPS) \
1044 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
d3608b6d 1045static ushort fifo_mode = 4;
ee34e51a
FB		 1046#elif defined(CONFIG_USB_MUSB_UX500) \
1047 || defined(CONFIG_USB_MUSB_UX500_MODULE)
d3608b6d 1048static ushort fifo_mode = 5;
550a7375 1049#else
d3608b6d 1050static ushort fifo_mode = 2;
550a7375
FB		 1051#endif
1052
1053/* "modprobe ... fifo_mode=1" etc */
1054module_param(fifo_mode, ushort, 0);
1055MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1056
550a7375
FB		 1057/*
1058 * tables defining fifo_mode values. define more if you like.
1059 * for host side, make sure both halves of ep1 are set up.
1060 */
1061
1062/* mode 0 - fits in 2KB */
d3608b6d 1063static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1064{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1065{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1066{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1067{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1068{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1069};
1070
1071/* mode 1 - fits in 4KB */
d3608b6d 1072static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1073{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1074{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1075{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1076{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1077{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1078};
1079
1080/* mode 2 - fits in 4KB */
d3608b6d 1081static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1082{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1083{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1084{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1085{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1086{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1087{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1088};
1089
1090/* mode 3 - fits in 4KB */
d3608b6d 1091static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1092{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1093{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1094{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1095{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1096{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1097{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1098};
1099
1100/* mode 4 - fits in 16KB */
d3608b6d 1101static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1102{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1103{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1104{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1105{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1106{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1107{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1108{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1109{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1110{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1111{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1112{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1113{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1114{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1115{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1116{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1117{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1118{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1119{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1120{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1121{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1122{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1123{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1124{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1125{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1126{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1127{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1128{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1129};
1130
3b151526 1131/* mode 5 - fits in 8KB */
d3608b6d 1132static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1133{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1134{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1135{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1136{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1137{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1138{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1139{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1140{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1141{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1142{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1143{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1144{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1145{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1146{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1147{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1148{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1149{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1150{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1151{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1152{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1153{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1154{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1155{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1156{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1157{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1158{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1159{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1160};
550a7375
FB		 1161
1162/*
1163 * configure a fifo; for non-shared endpoints, this may be called
1164 * once for a tx fifo and once for an rx fifo.
1165 *
1166 * returns negative errno or offset for next fifo.
1167 */
41ac7b3a 1168static int
550a7375 1169fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1170 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1171{
1172 void __iomem *mbase = musb->mregs;
1173 int size = 0;
1174 u16 maxpacket = cfg->maxpacket;
1175 u16 c_off = offset >> 3;
1176 u8 c_size;
1177
1178 /* expect hw_ep has already been zero-initialized */
1179
1180 size = ffs(max(maxpacket, (u16) 8)) - 1;
1181 maxpacket = 1 << size;
1182
1183 c_size = size - 3;
1184 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1185 if ((offset + (maxpacket << 1)) >
1186 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1187 return -EMSGSIZE;
1188 c_size |= MUSB_FIFOSZ_DPB;
1189 } else {
ca6d1b13 1190 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1191 return -EMSGSIZE;
1192 }
1193
1194 /* configure the FIFO */
1195 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1196
550a7375
FB		 1197 /* EP0 reserved endpoint for control, bidirectional;
1198 * EP1 reserved for bulk, two unidirection halves.
1199 */
1200 if (hw_ep->epnum == 1)
1201 musb->bulk_ep = hw_ep;
1202 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1203 switch (cfg->style) {
1204 case FIFO_TX:
c6cf8b00
BW		 1205 musb_write_txfifosz(mbase, c_size);
1206 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1207 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1208 hw_ep->max_packet_sz_tx = maxpacket;
1209 break;
1210 case FIFO_RX:
c6cf8b00
BW		 1211 musb_write_rxfifosz(mbase, c_size);
1212 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1213 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1214 hw_ep->max_packet_sz_rx = maxpacket;
1215 break;
1216 case FIFO_RXTX:
c6cf8b00
BW		 1217 musb_write_txfifosz(mbase, c_size);
1218 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1219 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1220 hw_ep->max_packet_sz_rx = maxpacket;
1221
c6cf8b00
BW		 1222 musb_write_rxfifosz(mbase, c_size);
1223 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1224 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1225 hw_ep->max_packet_sz_tx = maxpacket;
1226
1227 hw_ep->is_shared_fifo = true;
1228 break;
1229 }
1230
1231 /* NOTE rx and tx endpoint irqs aren't managed separately,
1232 * which happens to be ok
1233 */
1234 musb->epmask |= (1 << hw_ep->epnum);
1235
1236 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1237}
1238
d3608b6d 1239static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1240 .style = FIFO_RXTX, .maxpacket = 64,
1241};
1242
41ac7b3a 1243static int ep_config_from_table(struct musb *musb)
550a7375 1244{
e6c213b2 1245 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1246 unsigned i, n;
1247 int offset;
1248 struct musb_hw_ep *hw_ep = musb->endpoints;
1249
e6c213b2
FB		 1250 if (musb->config->fifo_cfg) {
1251 cfg = musb->config->fifo_cfg;
1252 n = musb->config->fifo_cfg_size;
1253 goto done;
1254 }
1255
550a7375
FB		 1256 switch (fifo_mode) {
1257 default:
1258 fifo_mode = 0;
1259 /* FALLTHROUGH */
1260 case 0:
1261 cfg = mode_0_cfg;
1262 n = ARRAY_SIZE(mode_0_cfg);
1263 break;
1264 case 1:
1265 cfg = mode_1_cfg;
1266 n = ARRAY_SIZE(mode_1_cfg);
1267 break;
1268 case 2:
1269 cfg = mode_2_cfg;
1270 n = ARRAY_SIZE(mode_2_cfg);
1271 break;
1272 case 3:
1273 cfg = mode_3_cfg;
1274 n = ARRAY_SIZE(mode_3_cfg);
1275 break;
1276 case 4:
1277 cfg = mode_4_cfg;
1278 n = ARRAY_SIZE(mode_4_cfg);
1279 break;
3b151526
AKG		 1280 case 5:
1281 cfg = mode_5_cfg;
1282 n = ARRAY_SIZE(mode_5_cfg);
1283 break;
550a7375
FB		 1284 }
1285
1286 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1287 musb_driver_name, fifo_mode);
1288
1289
e6c213b2 1290done:
550a7375
FB		 1291 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1292 /* assert(offset > 0) */
1293
1294 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1295 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1296 */
1297
1298 for (i = 0; i < n; i++) {
1299 u8 epn = cfg->hw_ep_num;
1300
ca6d1b13 1301 if (epn >= musb->config->num_eps) {
550a7375
FB		 1302 pr_debug("%s: invalid ep %d\n",
1303 musb_driver_name, epn);
bb1c9ef1 1304 return -EINVAL;
550a7375
FB		 1305 }
1306 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1307 if (offset < 0) {
1308 pr_debug("%s: mem overrun, ep %d\n",
1309 musb_driver_name, epn);
f69dfa1f 1310 return offset;
550a7375
FB		 1311 }
1312 epn++;
1313 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1314 }
1315
1316 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1317 musb_driver_name,
ca6d1b13
FB		 1318 n + 1, musb->config->num_eps * 2 - 1,
1319 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1320
550a7375
FB		 1321 if (!musb->bulk_ep) {
1322 pr_debug("%s: missing bulk\n", musb_driver_name);
1323 return -EINVAL;
1324 }
550a7375
FB		 1325
1326 return 0;
1327}
1328
1329
1330/*
1331 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1332 * @param musb the controller
1333 */
41ac7b3a 1334static int ep_config_from_hw(struct musb *musb)
550a7375 1335{
c6cf8b00 1336 u8 epnum = 0;
550a7375 1337 struct musb_hw_ep *hw_ep;
a156544b 1338 void __iomem *mbase = musb->mregs;
c6cf8b00 1339 int ret = 0;
550a7375 1340
5c8a86e1 1341 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1342
1343 /* FIXME pick up ep0 maxpacket size */
1344
ca6d1b13 1345 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1346 musb_ep_select(mbase, epnum);
1347 hw_ep = musb->endpoints + epnum;
1348
c6cf8b00
BW		 1349 ret = musb_read_fifosize(musb, hw_ep, epnum);
1350 if (ret < 0)
550a7375 1351 break;
550a7375
FB		 1352
1353 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1354
550a7375
FB		 1355 /* pick an RX/TX endpoint for bulk */
1356 if (hw_ep->max_packet_sz_tx < 512
1357 || hw_ep->max_packet_sz_rx < 512)
1358 continue;
1359
1360 /* REVISIT: this algorithm is lazy, we should at least
1361 * try to pick a double buffered endpoint.
1362 */
1363 if (musb->bulk_ep)
1364 continue;
1365 musb->bulk_ep = hw_ep;
550a7375
FB		 1366 }
1367
550a7375
FB		 1368 if (!musb->bulk_ep) {
1369 pr_debug("%s: missing bulk\n", musb_driver_name);
1370 return -EINVAL;
1371 }
550a7375
FB		 1372
1373 return 0;
1374}
1375
1376enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1377
1378/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1379 * configure endpoints, or take their config from silicon
1380 */
41ac7b3a 1381static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1382{
550a7375
FB		 1383 u8 reg;
1384 char *type;
0ea52ff4 1385 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1386 void __iomem *mbase = musb->mregs;
1387 int status = 0;
1388 int i;
1389
1390 /* log core options (read using indexed model) */
c6cf8b00 1391 reg = musb_read_configdata(mbase);
550a7375
FB		 1392
1393 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1394 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1395 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1396 musb->dyn_fifo = true;
1397 }
550a7375
FB		 1398 if (reg & MUSB_CONFIGDATA_MPRXE) {
1399 strcat(aInfo, ", bulk combine");
550a7375 1400 musb->bulk_combine = true;
550a7375
FB		 1401 }
1402 if (reg & MUSB_CONFIGDATA_MPTXE) {
1403 strcat(aInfo, ", bulk split");
550a7375 1404 musb->bulk_split = true;
550a7375
FB		 1405 }
1406 if (reg & MUSB_CONFIGDATA_HBRXE) {
1407 strcat(aInfo, ", HB-ISO Rx");
a483d706 1408 musb->hb_iso_rx = true;
550a7375
FB		 1409 }
1410 if (reg & MUSB_CONFIGDATA_HBTXE) {
1411 strcat(aInfo, ", HB-ISO Tx");
a483d706 1412 musb->hb_iso_tx = true;
550a7375
FB		 1413 }
1414 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1415 strcat(aInfo, ", SoftConn");
1416
1417 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1418 musb_driver_name, reg, aInfo);
1419
550a7375 1420 aDate[0] = 0;
550a7375
FB		 1421 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1422 musb->is_multipoint = 1;
1423 type = "M";
1424 } else {
1425 musb->is_multipoint = 0;
1426 type = "";
550a7375
FB		 1427#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1428 printk(KERN_ERR
1429 "%s: kernel must blacklist external hubs\n",
1430 musb_driver_name);
550a7375
FB		 1431#endif
1432 }
1433
1434 /* log release info */
32c3b94e
AG		 1435 musb->hwvers = musb_read_hwvers(mbase);
1436 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1437 MUSB_HWVERS_MINOR(musb->hwvers),
1438 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1439 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1440 musb_driver_name, type, aRevision, aDate);
1441
1442 /* configure ep0 */
c6cf8b00 1443 musb_configure_ep0(musb);
550a7375
FB		 1444
1445 /* discover endpoint configuration */
1446 musb->nr_endpoints = 1;
1447 musb->epmask = 1;
1448
ad517e9e
FB		 1449 if (musb->dyn_fifo)
1450 status = ep_config_from_table(musb);
1451 else
1452 status = ep_config_from_hw(musb);
550a7375
FB		 1453
1454 if (status < 0)
1455 return status;
1456
1457 /* finish init, and print endpoint config */
1458 for (i = 0; i < musb->nr_endpoints; i++) {
1459 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1460
1461 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
9a35f876 1462#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
550a7375
FB		 1463 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1464 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1465 hw_ep->fifo_sync_va =
1466 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1467
1468 if (i == 0)
1469 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1470 else
1471 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1472#endif
1473
1474 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
c6cf8b00 1475 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1476 hw_ep->rx_reinit = 1;
1477 hw_ep->tx_reinit = 1;
550a7375
FB		 1478
1479 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1480 dev_dbg(musb->controller,
550a7375
FB		 1481 "%s: hw_ep %d%s, %smax %d\n",
1482 musb_driver_name, i,
1483 hw_ep->is_shared_fifo ? "shared" : "tx",
1484 hw_ep->tx_double_buffered
1485 ? "doublebuffer, " : "",
1486 hw_ep->max_packet_sz_tx);
1487 }
1488 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1489 dev_dbg(musb->controller,
550a7375
FB		 1490 "%s: hw_ep %d%s, %smax %d\n",
1491 musb_driver_name, i,
1492 "rx",
1493 hw_ep->rx_double_buffered
1494 ? "doublebuffer, " : "",
1495 hw_ep->max_packet_sz_rx);
1496 }
1497 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1498 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1499 }
1500
1501 return 0;
1502}
1503
1504/*-------------------------------------------------------------------------*/
1505
550a7375
FB		 1506/*
1507 * handle all the irqs defined by the HDRC core. for now we expect: other
1508 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1509 * will be assigned, and the irq will already have been acked.
1510 *
1511 * called in irq context with spinlock held, irqs blocked
1512 */
1513irqreturn_t musb_interrupt(struct musb *musb)
1514{
1515 irqreturn_t retval = IRQ_NONE;
b11e94d0 1516 u8 devctl;
550a7375
FB		 1517 int ep_num;
1518 u32 reg;
1519
1520 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1521
5c8a86e1 1522 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
550a7375
FB		 1523 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1524 musb->int_usb, musb->int_tx, musb->int_rx);
1525
1526 /* the core can interrupt us for multiple reasons; docs have
1527 * a generic interrupt flowchart to follow
1528 */
7d9645fd 1529 if (musb->int_usb)
550a7375 1530 retval |= musb_stage0_irq(musb, musb->int_usb,
b11e94d0 1531 devctl);
550a7375
FB		 1532
1533 /* "stage 1" is handling endpoint irqs */
1534
1535 /* handle endpoint 0 first */
1536 if (musb->int_tx & 1) {
1537 if (devctl & MUSB_DEVCTL_HM)
1538 retval |= musb_h_ep0_irq(musb);
1539 else
1540 retval |= musb_g_ep0_irq(musb);
1541 }
1542
1543 /* RX on endpoints 1-15 */
1544 reg = musb->int_rx >> 1;
1545 ep_num = 1;
1546 while (reg) {
1547 if (reg & 1) {
1548 /* musb_ep_select(musb->mregs, ep_num); */
1549 /* REVISIT just retval = ep->rx_irq(...) */
1550 retval = IRQ_HANDLED;
a04d46d0
FB		 1551 if (devctl & MUSB_DEVCTL_HM)
1552 musb_host_rx(musb, ep_num);
1553 else
1554 musb_g_rx(musb, ep_num);
550a7375
FB		 1555 }
1556
1557 reg >>= 1;
1558 ep_num++;
1559 }
1560
1561 /* TX on endpoints 1-15 */
1562 reg = musb->int_tx >> 1;
1563 ep_num = 1;
1564 while (reg) {
1565 if (reg & 1) {
1566 /* musb_ep_select(musb->mregs, ep_num); */
1567 /* REVISIT just retval |= ep->tx_irq(...) */
1568 retval = IRQ_HANDLED;
a04d46d0
FB		 1569 if (devctl & MUSB_DEVCTL_HM)
1570 musb_host_tx(musb, ep_num);
1571 else
1572 musb_g_tx(musb, ep_num);
550a7375
FB		 1573 }
1574 reg >>= 1;
1575 ep_num++;
1576 }
1577
550a7375
FB		 1578 return retval;
1579}
981430a1 1580EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1581
1582#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1583static bool use_dma = 1;
550a7375
FB		 1584
1585/* "modprobe ... use_dma=0" etc */
1586module_param(use_dma, bool, 0);
1587MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1588
1589void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1590{
1591 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1592
1593 /* called with controller lock already held */
1594
1595 if (!epnum) {
1596#ifndef CONFIG_USB_TUSB_OMAP_DMA
1597 if (!is_cppi_enabled()) {
1598 /* endpoint 0 */
1599 if (devctl & MUSB_DEVCTL_HM)
1600 musb_h_ep0_irq(musb);
1601 else
1602 musb_g_ep0_irq(musb);
1603 }
1604#endif
1605 } else {
1606 /* endpoints 1..15 */
1607 if (transmit) {
a04d46d0
FB		 1608 if (devctl & MUSB_DEVCTL_HM)
1609 musb_host_tx(musb, epnum);
1610 else
1611 musb_g_tx(musb, epnum);
550a7375
FB		 1612 } else {
1613 /* receive */
a04d46d0
FB		 1614 if (devctl & MUSB_DEVCTL_HM)
1615 musb_host_rx(musb, epnum);
1616 else
1617 musb_g_rx(musb, epnum);
550a7375
FB		 1618 }
1619 }
1620}
9a35f876 1621EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1622
1623#else
1624#define use_dma 0
1625#endif
1626
1627/*-------------------------------------------------------------------------*/
1628
550a7375
FB		 1629static ssize_t
1630musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1631{
1632 struct musb *musb = dev_to_musb(dev);
1633 unsigned long flags;
1634 int ret = -EINVAL;
1635
1636 spin_lock_irqsave(&musb->lock, flags);
42c0bf1c 1637 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 1638 spin_unlock_irqrestore(&musb->lock, flags);
1639
1640 return ret;
1641}
1642
1643static ssize_t
1644musb_mode_store(struct device *dev, struct device_attribute *attr,
1645 const char *buf, size_t n)
1646{
1647 struct musb *musb = dev_to_musb(dev);
1648 unsigned long flags;
96a274d1 1649 int status;
550a7375
FB		 1650
1651 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1652 if (sysfs_streq(buf, "host"))
1653 status = musb_platform_set_mode(musb, MUSB_HOST);
1654 else if (sysfs_streq(buf, "peripheral"))
1655 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1656 else if (sysfs_streq(buf, "otg"))
1657 status = musb_platform_set_mode(musb, MUSB_OTG);
1658 else
1659 status = -EINVAL;
550a7375
FB		 1660 spin_unlock_irqrestore(&musb->lock, flags);
1661
96a274d1 1662 return (status == 0) ? n : status;
550a7375
FB		 1663}
1664static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1665
1666static ssize_t
1667musb_vbus_store(struct device *dev, struct device_attribute *attr,
1668 const char *buf, size_t n)
1669{
1670 struct musb *musb = dev_to_musb(dev);
1671 unsigned long flags;
1672 unsigned long val;
1673
1674 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1675 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1676 return -EINVAL;
1677 }
1678
1679 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1680 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1681 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
84e250ff 1682 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1683 musb->is_active = 0;
1684 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1685 spin_unlock_irqrestore(&musb->lock, flags);
1686
1687 return n;
1688}
1689
1690static ssize_t
1691musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1692{
1693 struct musb *musb = dev_to_musb(dev);
1694 unsigned long flags;
1695 unsigned long val;
1696 int vbus;
1697
1698 spin_lock_irqsave(&musb->lock, flags);
1699 val = musb->a_wait_bcon;
f7f9d63e
DB		 1700 /* FIXME get_vbus_status() is normally #defined as false...
1701 * and is effectively TUSB-specific.
1702 */
550a7375
FB		 1703 vbus = musb_platform_get_vbus_status(musb);
1704 spin_unlock_irqrestore(&musb->lock, flags);
1705
f7f9d63e 1706 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1707 vbus ? "on" : "off", val);
1708}
1709static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1710
550a7375
FB		 1711/* Gadget drivers can't know that a host is connected so they might want
1712 * to start SRP, but users can. This allows userspace to trigger SRP.
1713 */
1714static ssize_t
1715musb_srp_store(struct device *dev, struct device_attribute *attr,
1716 const char *buf, size_t n)
1717{
1718 struct musb *musb = dev_to_musb(dev);
1719 unsigned short srp;
1720
1721 if (sscanf(buf, "%hu", &srp) != 1
1722 || (srp != 1)) {
b3b1cc3b 1723 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1724 return -EINVAL;
1725 }
1726
1727 if (srp == 1)
1728 musb_g_wakeup(musb);
1729
1730 return n;
1731}
1732static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1733
94375751
FB		 1734static struct attribute *musb_attributes[] = {
1735 &dev_attr_mode.attr,
1736 &dev_attr_vbus.attr,
94375751 1737 &dev_attr_srp.attr,
94375751
FB		 1738 NULL
1739};
1740
1741static const struct attribute_group musb_attr_group = {
1742 .attrs = musb_attributes,
1743};
1744
550a7375
FB		 1745/* Only used to provide driver mode change events */
1746static void musb_irq_work(struct work_struct *data)
1747{
1748 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1749
8d2421e6
AKG		 1750 if (musb->xceiv->state != musb->xceiv_old_state) {
1751 musb->xceiv_old_state = musb->xceiv->state;
550a7375
FB		 1752 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1753 }
1754}
1755
1756/* --------------------------------------------------------------------------
1757 * Init support
1758 */
1759
41ac7b3a 1760static struct musb *allocate_instance(struct device *dev,
ca6d1b13 1761 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1762{
1763 struct musb *musb;
1764 struct musb_hw_ep *ep;
1765 int epnum;
550a7375
FB		 1766 struct usb_hcd *hcd;
1767
427c4f33 1768 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
550a7375
FB		 1769 if (!hcd)
1770 return NULL;
1771 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1772
1773 musb = hcd_to_musb(hcd);
1774 INIT_LIST_HEAD(&musb->control);
1775 INIT_LIST_HEAD(&musb->in_bulk);
1776 INIT_LIST_HEAD(&musb->out_bulk);
1777
1778 hcd->uses_new_polling = 1;
ec95d35a 1779 hcd->has_tt = 1;
550a7375
FB		 1780
1781 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1782 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
456bb169 1783 dev_set_drvdata(dev, musb);
550a7375
FB		 1784 musb->mregs = mbase;
1785 musb->ctrl_base = mbase;
1786 musb->nIrq = -ENODEV;
ca6d1b13 1787 musb->config = config;
02582b92 1788 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1789 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1790 epnum < musb->config->num_eps;
550a7375 1791 epnum++, ep++) {
550a7375
FB		 1792 ep->musb = musb;
1793 ep->epnum = epnum;
1794 }
1795
1796 musb->controller = dev;
743411b3 1797
550a7375
FB		 1798 return musb;
1799}
1800
1801static void musb_free(struct musb *musb)
1802{
1803 /* this has multiple entry modes. it handles fault cleanup after
1804 * probe(), where things may be partially set up, as well as rmmod
1805 * cleanup after everything's been de-activated.
1806 */
1807
1808#ifdef CONFIG_SYSFS
94375751 1809 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1810#endif
1811
97a39896
AKG		 1812 if (musb->nIrq >= 0) {
1813 if (musb->irq_wake)
1814 disable_irq_wake(musb->nIrq);
550a7375
FB		 1815 free_irq(musb->nIrq, musb);
1816 }
1817 if (is_dma_capable() && musb->dma_controller) {
1818 struct dma_controller *c = musb->dma_controller;
1819
1820 (void) c->stop(c);
1821 dma_controller_destroy(c);
1822 }
1823
decadacb 1824 usb_put_hcd(musb_to_hcd(musb));
550a7375
FB		 1825}
1826
1827/*
1828 * Perform generic per-controller initialization.
1829 *
28dd924a
SS		 1830 * @dev: the controller (already clocked, etc)
1831 * @nIrq: IRQ number
1832 * @ctrl: virtual address of controller registers,
550a7375
FB		 1833 * not yet corrected for platform-specific offsets
1834 */
41ac7b3a 1835static int
550a7375
FB		 1836musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1837{
1838 int status;
1839 struct musb *musb;
1840 struct musb_hdrc_platform_data *plat = dev->platform_data;
032ec49f 1841 struct usb_hcd *hcd;
550a7375
FB		 1842
1843 /* The driver might handle more features than the board; OK.
1844 * Fail when the board needs a feature that's not enabled.
1845 */
1846 if (!plat) {
1847 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 1848 status = -ENODEV;
1849 goto fail0;
550a7375 1850 }
34e2beb2 1851
550a7375 1852 /* allocate */
ca6d1b13 1853 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 1854 if (!musb) {
1855 status = -ENOMEM;
1856 goto fail0;
1857 }
550a7375 1858
7acc6197
HH		 1859 pm_runtime_use_autosuspend(musb->controller);
1860 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1861 pm_runtime_enable(musb->controller);
1862
550a7375 1863 spin_lock_init(&musb->lock);
550a7375 1864 musb->board_set_power = plat->set_power;
550a7375 1865 musb->min_power = plat->min_power;
f7ec9437 1866 musb->ops = plat->platform_ops;
550a7375 1867
84e250ff 1868 /* The musb_platform_init() call:
baef653a
PDS		 1869 * - adjusts musb->mregs
1870 * - sets the musb->isr
84e250ff 1871 * - may initialize an integrated tranceiver
721002ec 1872 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 1873 * - stops powering VBUS
84e250ff 1874 *
7c9d440e 1875 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 1876 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1877 * external/discrete ones in various flavors (twl4030 family,
1878 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 1879 */
ea65df57 1880 status = musb_platform_init(musb);
550a7375 1881 if (status < 0)
03491761 1882 goto fail1;
34e2beb2 1883
550a7375
FB		 1884 if (!musb->isr) {
1885 status = -ENODEV;
c04352a5 1886 goto fail2;
550a7375
FB		 1887 }
1888
ffb865b1 1889 if (!musb->xceiv->io_ops) {
bf070bc1 1890 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 1891 musb->xceiv->io_priv = musb->mregs;
1892 musb->xceiv->io_ops = &musb_ulpi_access;
1893 }
1894
c04352a5
GI		 1895 pm_runtime_get_sync(musb->controller);
1896
550a7375
FB		 1897#ifndef CONFIG_MUSB_PIO_ONLY
1898 if (use_dma && dev->dma_mask) {
1899 struct dma_controller *c;
1900
1901 c = dma_controller_create(musb, musb->mregs);
1902 musb->dma_controller = c;
1903 if (c)
1904 (void) c->start(c);
1905 }
1906#endif
1907 /* ideally this would be abstracted in platform setup */
1908 if (!is_dma_capable() || !musb->dma_controller)
1909 dev->dma_mask = NULL;
1910
1911 /* be sure interrupts are disabled before connecting ISR */
1912 musb_platform_disable(musb);
1913 musb_generic_disable(musb);
1914
1915 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 1916 status = musb_core_init(plat->config->multipoint
550a7375
FB		 1917 ? MUSB_CONTROLLER_MHDRC
1918 : MUSB_CONTROLLER_HDRC, musb);
1919 if (status < 0)
34e2beb2 1920 goto fail3;
550a7375 1921
f7f9d63e 1922 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 1923
550a7375
FB		 1924 /* Init IRQ workqueue before request_irq */
1925 INIT_WORK(&musb->irq_work, musb_irq_work);
1926
1927 /* attach to the IRQ */
427c4f33 1928 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 1929 dev_err(dev, "request_irq %d failed!\n", nIrq);
1930 status = -ENODEV;
34e2beb2 1931 goto fail3;
550a7375
FB		 1932 }
1933 musb->nIrq = nIrq;
032ec49f 1934 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 1935 if (enable_irq_wake(nIrq) == 0) {
1936 musb->irq_wake = 1;
550a7375 1937 device_init_wakeup(dev, 1);
c48a5155
FB		 1938 } else {
1939 musb->irq_wake = 0;
1940 }
550a7375 1941
84e250ff 1942 /* host side needs more setup */
032ec49f
FB		 1943 hcd = musb_to_hcd(musb);
1944 otg_set_host(musb->xceiv->otg, &hcd->self);
1945 hcd->self.otg_port = 1;
1946 musb->xceiv->otg->host = &hcd->self;
1947 hcd->power_budget = 2 * (plat->power ? : 250);
1948
1949 /* program PHY to use external vBus if required */
1950 if (plat->extvbus) {
1951 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1952 busctl |= MUSB_ULPI_USE_EXTVBUS;
1953 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 1954 }
550a7375 1955
e5615112
GI		 1956 if (musb->xceiv->otg->default_a) {
1957 MUSB_HST_MODE(musb);
1958 musb->xceiv->state = OTG_STATE_A_IDLE;
1959 } else {
1960 MUSB_DEV_MODE(musb);
1961 musb->xceiv->state = OTG_STATE_B_IDLE;
1962 }
550a7375 1963
032ec49f 1964 status = musb_gadget_setup(musb);
550a7375 1965
461972d8 1966 if (status < 0)
34e2beb2 1967 goto fail3;
550a7375 1968
7f7f9e2a
FB		 1969 status = musb_init_debugfs(musb);
1970 if (status < 0)
b0f9da7e 1971 goto fail4;
7f7f9e2a 1972
94375751 1973 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 1974 if (status)
b0f9da7e 1975 goto fail5;
550a7375 1976
c04352a5
GI		 1977 pm_runtime_put(musb->controller);
1978
28c2c51c 1979 return 0;
550a7375 1980
b0f9da7e
FB		 1981fail5:
1982 musb_exit_debugfs(musb);
1983
34e2beb2 1984fail4:
032ec49f 1985 musb_gadget_cleanup(musb);
34e2beb2
SS		 1986
1987fail3:
c04352a5
GI		 1988 pm_runtime_put_sync(musb->controller);
1989
1990fail2:
34e2beb2
SS		 1991 if (musb->irq_wake)
1992 device_init_wakeup(dev, 0);
550a7375 1993 musb_platform_exit(musb);
28c2c51c 1994
34e2beb2 1995fail1:
681d1e87 1996 pm_runtime_disable(musb->controller);
34e2beb2
SS		 1997 dev_err(musb->controller,
1998 "musb_init_controller failed with status %d\n", status);
1999
28c2c51c
FB		 2000 musb_free(musb);
2001
34e2beb2
SS		 2002fail0:
2003
28c2c51c
FB		 2004 return status;
2005
550a7375
FB		 2006}
2007
2008/*-------------------------------------------------------------------------*/
2009
2010/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2011 * bridge to a platform device; this driver then suffices.
2012 */
41ac7b3a 2013static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2014{
2015 struct device *dev = &pdev->dev;
fcf173e4 2016 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2017 struct resource *iomem;
2018 void __iomem *base;
2019
2020 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
541079de 2021 if (!iomem || irq <= 0)
550a7375
FB		 2022 return -ENODEV;
2023
b42f7f30
FB		 2024 base = devm_ioremap_resource(dev, iomem);
2025 if (IS_ERR(base))
2026 return PTR_ERR(base);
550a7375 2027
b42f7f30 2028 return musb_init_controller(dev, irq, base);
550a7375
FB		 2029}
2030
fb4e98ab 2031static int musb_remove(struct platform_device *pdev)
550a7375 2032{
8d2421e6
AKG		 2033 struct device *dev = &pdev->dev;
2034 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2035
2036 /* this gets called on rmmod.
2037 * - Host mode: host may still be active
2038 * - Peripheral mode: peripheral is deactivated (or never-activated)
2039 * - OTG mode: both roles are deactivated (or never-activated)
2040 */
7f7f9e2a 2041 musb_exit_debugfs(musb);
550a7375 2042 musb_shutdown(pdev);
461972d8 2043
550a7375 2044 musb_free(musb);
8d2421e6 2045 device_init_wakeup(dev, 0);
550a7375 2046#ifndef CONFIG_MUSB_PIO_ONLY
8d2421e6 2047 dma_set_mask(dev, *dev->parent->dma_mask);
550a7375
FB		 2048#endif
2049 return 0;
2050}
2051
2052#ifdef CONFIG_PM
2053
3c8a5fcc 2054static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2055{
2056 int i;
2057 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2058 void __iomem *epio;
4f712e01 2059
032ec49f
FB		 2060 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2061 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2062 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2063 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2064 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2065 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2066 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2067
ae9b2ad2 2068 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2069 struct musb_hw_ep *hw_ep;
2070
2071 hw_ep = &musb->endpoints[i];
2072 if (!hw_ep)
2073 continue;
2074
2075 epio = hw_ep->regs;
2076 if (!epio)
2077 continue;
2078
ea737554 2079 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2080 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2081 musb_readw(epio, MUSB_TXMAXP);
7421107b 2082 musb->context.index_regs[i].txcsr =
ae9b2ad2 2083 musb_readw(epio, MUSB_TXCSR);
7421107b 2084 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2085 musb_readw(epio, MUSB_RXMAXP);
7421107b 2086 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2087 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2088
2089 if (musb->dyn_fifo) {
7421107b 2090 musb->context.index_regs[i].txfifoadd =
4f712e01 2091 musb_read_txfifoadd(musb_base);
7421107b 2092 musb->context.index_regs[i].rxfifoadd =
4f712e01 2093 musb_read_rxfifoadd(musb_base);
7421107b 2094 musb->context.index_regs[i].txfifosz =
4f712e01 2095 musb_read_txfifosz(musb_base);
7421107b 2096 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2097 musb_read_rxfifosz(musb_base);
2098 }
032ec49f
FB		 2099
2100 musb->context.index_regs[i].txtype =
2101 musb_readb(epio, MUSB_TXTYPE);
2102 musb->context.index_regs[i].txinterval =
2103 musb_readb(epio, MUSB_TXINTERVAL);
2104 musb->context.index_regs[i].rxtype =
2105 musb_readb(epio, MUSB_RXTYPE);
2106 musb->context.index_regs[i].rxinterval =
2107 musb_readb(epio, MUSB_RXINTERVAL);
2108
2109 musb->context.index_regs[i].txfunaddr =
2110 musb_read_txfunaddr(musb_base, i);
2111 musb->context.index_regs[i].txhubaddr =
2112 musb_read_txhubaddr(musb_base, i);
2113 musb->context.index_regs[i].txhubport =
2114 musb_read_txhubport(musb_base, i);
2115
2116 musb->context.index_regs[i].rxfunaddr =
2117 musb_read_rxfunaddr(musb_base, i);
2118 musb->context.index_regs[i].rxhubaddr =
2119 musb_read_rxhubaddr(musb_base, i);
2120 musb->context.index_regs[i].rxhubport =
2121 musb_read_rxhubport(musb_base, i);
4f712e01 2122 }
4f712e01
AKG		 2123}
2124
3c8a5fcc 2125static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2126{
2127 int i;
2128 void __iomem *musb_base = musb->mregs;
2129 void __iomem *ep_target_regs;
ae9b2ad2 2130 void __iomem *epio;
4f712e01 2131
032ec49f
FB		 2132 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2133 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2134 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
7421107b 2135 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
b18d26f6 2136 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2137 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b
FB		 2138 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2139 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2140
ae9b2ad2 2141 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2142 struct musb_hw_ep *hw_ep;
2143
2144 hw_ep = &musb->endpoints[i];
2145 if (!hw_ep)
2146 continue;
2147
2148 epio = hw_ep->regs;
2149 if (!epio)
2150 continue;
2151
ea737554 2152 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2153 musb_writew(epio, MUSB_TXMAXP,
7421107b 2154 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2155 musb_writew(epio, MUSB_TXCSR,
7421107b 2156 musb->context.index_regs[i].txcsr);
ae9b2ad2 2157 musb_writew(epio, MUSB_RXMAXP,
7421107b 2158 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2159 musb_writew(epio, MUSB_RXCSR,
7421107b 2160 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2161
2162 if (musb->dyn_fifo) {
2163 musb_write_txfifosz(musb_base,
7421107b 2164 musb->context.index_regs[i].txfifosz);
4f712e01 2165 musb_write_rxfifosz(musb_base,
7421107b 2166 musb->context.index_regs[i].rxfifosz);
4f712e01 2167 musb_write_txfifoadd(musb_base,
7421107b 2168 musb->context.index_regs[i].txfifoadd);
4f712e01 2169 musb_write_rxfifoadd(musb_base,
7421107b 2170 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2171 }
2172
032ec49f 2173 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2174 musb->context.index_regs[i].txtype);
032ec49f 2175 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2176 musb->context.index_regs[i].txinterval);
032ec49f 2177 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2178 musb->context.index_regs[i].rxtype);
032ec49f 2179 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2180
032ec49f
FB		 2181 musb->context.index_regs[i].rxinterval);
2182 musb_write_txfunaddr(musb_base, i,
7421107b 2183 musb->context.index_regs[i].txfunaddr);
032ec49f 2184 musb_write_txhubaddr(musb_base, i,
7421107b 2185 musb->context.index_regs[i].txhubaddr);
032ec49f 2186 musb_write_txhubport(musb_base, i,
7421107b 2187 musb->context.index_regs[i].txhubport);
4f712e01 2188
032ec49f
FB		 2189 ep_target_regs =
2190 musb_read_target_reg_base(i, musb_base);
4f712e01 2191
032ec49f 2192 musb_write_rxfunaddr(ep_target_regs,
7421107b 2193 musb->context.index_regs[i].rxfunaddr);
032ec49f 2194 musb_write_rxhubaddr(ep_target_regs,
7421107b 2195 musb->context.index_regs[i].rxhubaddr);
032ec49f 2196 musb_write_rxhubport(ep_target_regs,
7421107b 2197 musb->context.index_regs[i].rxhubport);
4f712e01 2198 }
3c5fec75 2199 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2200}
2201
48fea965 2202static int musb_suspend(struct device *dev)
550a7375 2203{
8220796d 2204 struct musb *musb = dev_to_musb(dev);
550a7375 2205 unsigned long flags;
550a7375 2206
550a7375
FB		 2207 spin_lock_irqsave(&musb->lock, flags);
2208
2209 if (is_peripheral_active(musb)) {
2210 /* FIXME force disconnect unless we know USB will wake
2211 * the system up quickly enough to respond ...
2212 */
2213 } else if (is_host_active(musb)) {
2214 /* we know all the children are suspended; sometimes
2215 * they will even be wakeup-enabled.
2216 */
2217 }
2218
550a7375
FB		 2219 spin_unlock_irqrestore(&musb->lock, flags);
2220 return 0;
2221}
2222
48fea965 2223static int musb_resume_noirq(struct device *dev)
550a7375 2224{
550a7375 2225 /* for static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2226 * unless for some reason the whole soc powered down or the USB
2227 * module got reset through the PSC (vs just being disabled).
550a7375 2228 */
550a7375
FB		 2229 return 0;
2230}
2231
7acc6197
HH		 2232static int musb_runtime_suspend(struct device *dev)
2233{
2234 struct musb *musb = dev_to_musb(dev);
2235
2236 musb_save_context(musb);
2237
2238 return 0;
2239}
2240
2241static int musb_runtime_resume(struct device *dev)
2242{
2243 struct musb *musb = dev_to_musb(dev);
2244 static int first = 1;
2245
2246 /*
2247 * When pm_runtime_get_sync called for the first time in driver
2248 * init, some of the structure is still not initialized which is
2249 * used in restore function. But clock needs to be
2250 * enabled before any register access, so
2251 * pm_runtime_get_sync has to be called.
2252 * Also context restore without save does not make
2253 * any sense
2254 */
2255 if (!first)
2256 musb_restore_context(musb);
2257 first = 0;
2258
2259 return 0;
2260}
2261
47145210 2262static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965
MD		 2263 .suspend = musb_suspend,
2264 .resume_noirq = musb_resume_noirq,
7acc6197
HH		 2265 .runtime_suspend = musb_runtime_suspend,
2266 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2267};
2268
2269#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2270#else
48fea965 2271#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2272#endif
2273
2274static struct platform_driver musb_driver = {
2275 .driver = {
2276 .name = (char *)musb_driver_name,
2277 .bus = &platform_bus_type,
2278 .owner = THIS_MODULE,
48fea965 2279 .pm = MUSB_DEV_PM_OPS,
550a7375 2280 },
e9e8c85e 2281 .probe = musb_probe,
7690417d 2282 .remove = musb_remove,
550a7375 2283 .shutdown = musb_shutdown,
550a7375
FB		 2284};
2285
2286/*-------------------------------------------------------------------------*/
2287
2288static int __init musb_init(void)
2289{
550a7375
FB		 2290 if (usb_disabled())
2291 return 0;
550a7375 2292
e9e8c85e 2293 return platform_driver_register(&musb_driver);
550a7375 2294}
e9e8c85e 2295module_init(musb_init);
550a7375
FB		 2296
2297static void __exit musb_cleanup(void)
2298{
2299 platform_driver_unregister(&musb_driver);
2300}
2301module_exit(musb_cleanup);
Linux kernel - Deliverables
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