Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 FB |
85 | * - platform_device for addressing, irq, and platform_data |
86 | * - platform_data is mostly for board-specific informarion | |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
9303961f | 99 | #include <linux/prefetch.h> |
550a7375 FB |
100 | #include <linux/platform_device.h> |
101 | #include <linux/io.h> | |
65b3d52d | 102 | #include <linux/idr.h> |
8d2421e6 | 103 | #include <linux/dma-mapping.h> |
550a7375 | 104 | |
550a7375 FB |
105 | #include "musb_core.h" |
106 | ||
f7f9d63e | 107 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
108 | |
109 | ||
550a7375 FB |
110 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
111 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
112 | ||
e8164f64 | 113 | #define MUSB_VERSION "6.0" |
550a7375 FB |
114 | |
115 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
116 | ||
05ac10dd | 117 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
118 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
119 | ||
120 | MODULE_DESCRIPTION(DRIVER_INFO); | |
121 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
122 | MODULE_LICENSE("GPL"); | |
123 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
124 | ||
125 | ||
126 | /*-------------------------------------------------------------------------*/ | |
127 | ||
128 | static inline struct musb *dev_to_musb(struct device *dev) | |
129 | { | |
550a7375 | 130 | return dev_get_drvdata(dev); |
550a7375 FB |
131 | } |
132 | ||
133 | /*-------------------------------------------------------------------------*/ | |
134 | ||
ffb865b1 | 135 | #ifndef CONFIG_BLACKFIN |
b96d3b08 | 136 | static int musb_ulpi_read(struct usb_phy *phy, u32 offset) |
ffb865b1 | 137 | { |
b96d3b08 | 138 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
139 | int i = 0; |
140 | u8 r; | |
141 | u8 power; | |
bf070bc1 GI |
142 | int ret; |
143 | ||
144 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
145 | |
146 | /* Make sure the transceiver is not in low power mode */ | |
147 | power = musb_readb(addr, MUSB_POWER); | |
148 | power &= ~MUSB_POWER_SUSPENDM; | |
149 | musb_writeb(addr, MUSB_POWER, power); | |
150 | ||
151 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
152 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
153 | */ | |
154 | ||
155 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
156 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
157 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
158 | ||
159 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
160 | & MUSB_ULPI_REG_CMPLT)) { | |
161 | i++; | |
bf070bc1 GI |
162 | if (i == 10000) { |
163 | ret = -ETIMEDOUT; | |
164 | goto out; | |
165 | } | |
ffb865b1 HK |
166 | |
167 | } | |
168 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
169 | r &= ~MUSB_ULPI_REG_CMPLT; | |
170 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
171 | ||
bf070bc1 GI |
172 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
173 | ||
174 | out: | |
175 | pm_runtime_put(phy->io_dev); | |
176 | ||
177 | return ret; | |
ffb865b1 HK |
178 | } |
179 | ||
b96d3b08 | 180 | static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) |
ffb865b1 | 181 | { |
b96d3b08 | 182 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
183 | int i = 0; |
184 | u8 r = 0; | |
185 | u8 power; | |
bf070bc1 GI |
186 | int ret = 0; |
187 | ||
188 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
189 | |
190 | /* Make sure the transceiver is not in low power mode */ | |
191 | power = musb_readb(addr, MUSB_POWER); | |
192 | power &= ~MUSB_POWER_SUSPENDM; | |
193 | musb_writeb(addr, MUSB_POWER, power); | |
194 | ||
195 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
196 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
197 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
198 | ||
199 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
200 | & MUSB_ULPI_REG_CMPLT)) { | |
201 | i++; | |
bf070bc1 GI |
202 | if (i == 10000) { |
203 | ret = -ETIMEDOUT; | |
204 | goto out; | |
205 | } | |
ffb865b1 HK |
206 | } |
207 | ||
208 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
209 | r &= ~MUSB_ULPI_REG_CMPLT; | |
210 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
211 | ||
bf070bc1 GI |
212 | out: |
213 | pm_runtime_put(phy->io_dev); | |
214 | ||
215 | return ret; | |
ffb865b1 HK |
216 | } |
217 | #else | |
f2263db7 MF |
218 | #define musb_ulpi_read NULL |
219 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
220 | #endif |
221 | ||
b96d3b08 | 222 | static struct usb_phy_io_ops musb_ulpi_access = { |
ffb865b1 HK |
223 | .read = musb_ulpi_read, |
224 | .write = musb_ulpi_write, | |
225 | }; | |
226 | ||
227 | /*-------------------------------------------------------------------------*/ | |
228 | ||
7c925546 | 229 | #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) |
c6cf8b00 | 230 | |
550a7375 FB |
231 | /* |
232 | * Load an endpoint's FIFO | |
233 | */ | |
234 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
235 | { | |
5c8a86e1 | 236 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
237 | void __iomem *fifo = hw_ep->fifo; |
238 | ||
603fe2b2 AKG |
239 | if (unlikely(len == 0)) |
240 | return; | |
241 | ||
550a7375 FB |
242 | prefetch((u8 *)src); |
243 | ||
5c8a86e1 | 244 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
245 | 'T', hw_ep->epnum, fifo, len, src); |
246 | ||
247 | /* we can't assume unaligned reads work */ | |
248 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
249 | u16 index = 0; | |
250 | ||
251 | /* best case is 32bit-aligned source address */ | |
252 | if ((0x02 & (unsigned long) src) == 0) { | |
253 | if (len >= 4) { | |
254 | writesl(fifo, src + index, len >> 2); | |
255 | index += len & ~0x03; | |
256 | } | |
257 | if (len & 0x02) { | |
258 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
259 | index += 2; | |
260 | } | |
261 | } else { | |
262 | if (len >= 2) { | |
263 | writesw(fifo, src + index, len >> 1); | |
264 | index += len & ~0x01; | |
265 | } | |
266 | } | |
267 | if (len & 0x01) | |
268 | musb_writeb(fifo, 0, src[index]); | |
269 | } else { | |
270 | /* byte aligned */ | |
271 | writesb(fifo, src, len); | |
272 | } | |
273 | } | |
274 | ||
843bb1d0 | 275 | #if !defined(CONFIG_USB_MUSB_AM35X) |
550a7375 FB |
276 | /* |
277 | * Unload an endpoint's FIFO | |
278 | */ | |
279 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
280 | { | |
5c8a86e1 | 281 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
282 | void __iomem *fifo = hw_ep->fifo; |
283 | ||
603fe2b2 AKG |
284 | if (unlikely(len == 0)) |
285 | return; | |
286 | ||
5c8a86e1 | 287 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
288 | 'R', hw_ep->epnum, fifo, len, dst); |
289 | ||
290 | /* we can't assume unaligned writes work */ | |
291 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
292 | u16 index = 0; | |
293 | ||
294 | /* best case is 32bit-aligned destination address */ | |
295 | if ((0x02 & (unsigned long) dst) == 0) { | |
296 | if (len >= 4) { | |
297 | readsl(fifo, dst, len >> 2); | |
298 | index = len & ~0x03; | |
299 | } | |
300 | if (len & 0x02) { | |
301 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
302 | index += 2; | |
303 | } | |
304 | } else { | |
305 | if (len >= 2) { | |
306 | readsw(fifo, dst, len >> 1); | |
307 | index = len & ~0x01; | |
308 | } | |
309 | } | |
310 | if (len & 0x01) | |
311 | dst[index] = musb_readb(fifo, 0); | |
312 | } else { | |
313 | /* byte aligned */ | |
314 | readsb(fifo, dst, len); | |
315 | } | |
316 | } | |
843bb1d0 | 317 | #endif |
550a7375 FB |
318 | |
319 | #endif /* normal PIO */ | |
320 | ||
321 | ||
322 | /*-------------------------------------------------------------------------*/ | |
323 | ||
324 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
325 | static const u8 musb_test_packet[53] = { | |
326 | /* implicit SYNC then DATA0 to start */ | |
327 | ||
328 | /* JKJKJKJK x9 */ | |
329 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
330 | /* JJKKJJKK x8 */ | |
331 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
332 | /* JJJJKKKK x8 */ | |
333 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
334 | /* JJJJJJJKKKKKKK x8 */ | |
335 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
336 | /* JJJJJJJK x8 */ | |
337 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
338 | /* JKKKKKKK x10, JK */ | |
339 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
340 | ||
341 | /* implicit CRC16 then EOP to end */ | |
342 | }; | |
343 | ||
344 | void musb_load_testpacket(struct musb *musb) | |
345 | { | |
346 | void __iomem *regs = musb->endpoints[0].regs; | |
347 | ||
348 | musb_ep_select(musb->mregs, 0); | |
349 | musb_write_fifo(musb->control_ep, | |
350 | sizeof(musb_test_packet), musb_test_packet); | |
351 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
352 | } | |
353 | ||
354 | /*-------------------------------------------------------------------------*/ | |
355 | ||
550a7375 FB |
356 | /* |
357 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
358 | */ | |
a156544b | 359 | static void musb_otg_timer_func(unsigned long data) |
550a7375 FB |
360 | { |
361 | struct musb *musb = (struct musb *)data; | |
362 | unsigned long flags; | |
363 | ||
364 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 365 | switch (musb->xceiv->state) { |
550a7375 | 366 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 367 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 368 | musb_g_disconnect(musb); |
84e250ff | 369 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
370 | musb->is_active = 0; |
371 | break; | |
ab983f2a | 372 | case OTG_STATE_A_SUSPEND: |
550a7375 | 373 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 374 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
3df00453 | 375 | otg_state_string(musb->xceiv->state)); |
743411b3 | 376 | musb_platform_set_vbus(musb, 0); |
ab983f2a | 377 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
378 | break; |
379 | default: | |
5c8a86e1 | 380 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
3df00453 | 381 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
382 | } |
383 | musb->ignore_disconnect = 0; | |
384 | spin_unlock_irqrestore(&musb->lock, flags); | |
385 | } | |
386 | ||
550a7375 | 387 | /* |
f7f9d63e | 388 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
389 | */ |
390 | void musb_hnp_stop(struct musb *musb) | |
391 | { | |
392 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
393 | void __iomem *mbase = musb->mregs; | |
394 | u8 reg; | |
395 | ||
5c8a86e1 | 396 | dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); |
ab983f2a | 397 | |
84e250ff | 398 | switch (musb->xceiv->state) { |
550a7375 | 399 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 400 | musb_g_disconnect(musb); |
5c8a86e1 | 401 | dev_dbg(musb->controller, "HNP: back to %s\n", |
3df00453 | 402 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
403 | break; |
404 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 405 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
550a7375 | 406 | hcd->self.is_b_host = 0; |
84e250ff | 407 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
408 | MUSB_DEV_MODE(musb); |
409 | reg = musb_readb(mbase, MUSB_POWER); | |
410 | reg |= MUSB_POWER_SUSPENDM; | |
411 | musb_writeb(mbase, MUSB_POWER, reg); | |
412 | /* REVISIT: Start SESSION_REQUEST here? */ | |
413 | break; | |
414 | default: | |
5c8a86e1 | 415 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
3df00453 | 416 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
417 | } |
418 | ||
419 | /* | |
420 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
421 | * which cause occasional OPT A "Did not receive reset after connect" | |
422 | * errors. | |
423 | */ | |
749da5f8 | 424 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
425 | } |
426 | ||
550a7375 FB |
427 | /* |
428 | * Interrupt Service Routine to record USB "global" interrupts. | |
429 | * Since these do not happen often and signify things of | |
430 | * paramount importance, it seems OK to check them individually; | |
431 | * the order of the tests is specified in the manual | |
432 | * | |
433 | * @param musb instance pointer | |
434 | * @param int_usb register contents | |
435 | * @param devctl | |
436 | * @param power | |
437 | */ | |
438 | ||
550a7375 | 439 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
b11e94d0 | 440 | u8 devctl) |
550a7375 | 441 | { |
d445b6da | 442 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 443 | irqreturn_t handled = IRQ_NONE; |
550a7375 | 444 | |
b11e94d0 | 445 | dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl, |
550a7375 FB |
446 | int_usb); |
447 | ||
448 | /* in host mode, the peripheral may issue remote wakeup. | |
449 | * in peripheral mode, the host may resume the link. | |
450 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
451 | */ | |
452 | if (int_usb & MUSB_INTR_RESUME) { | |
453 | handled = IRQ_HANDLED; | |
5c8a86e1 | 454 | dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
455 | |
456 | if (devctl & MUSB_DEVCTL_HM) { | |
aa471456 | 457 | void __iomem *mbase = musb->mregs; |
b11e94d0 | 458 | u8 power; |
aa471456 | 459 | |
84e250ff | 460 | switch (musb->xceiv->state) { |
550a7375 FB |
461 | case OTG_STATE_A_SUSPEND: |
462 | /* remote wakeup? later, GetPortStatus | |
463 | * will stop RESUME signaling | |
464 | */ | |
465 | ||
b11e94d0 | 466 | power = musb_readb(musb->mregs, MUSB_POWER); |
550a7375 FB |
467 | if (power & MUSB_POWER_SUSPENDM) { |
468 | /* spurious */ | |
469 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
5c8a86e1 | 470 | dev_dbg(musb->controller, "Spurious SUSPENDM\n"); |
550a7375 FB |
471 | break; |
472 | } | |
473 | ||
474 | power &= ~MUSB_POWER_SUSPENDM; | |
475 | musb_writeb(mbase, MUSB_POWER, | |
476 | power | MUSB_POWER_RESUME); | |
477 | ||
478 | musb->port1_status |= | |
479 | (USB_PORT_STAT_C_SUSPEND << 16) | |
480 | | MUSB_PORT_STAT_RESUME; | |
481 | musb->rh_timer = jiffies | |
482 | + msecs_to_jiffies(20); | |
483 | ||
84e250ff | 484 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
485 | musb->is_active = 1; |
486 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
487 | break; | |
488 | case OTG_STATE_B_WAIT_ACON: | |
84e250ff | 489 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
490 | musb->is_active = 1; |
491 | MUSB_DEV_MODE(musb); | |
492 | break; | |
493 | default: | |
494 | WARNING("bogus %s RESUME (%s)\n", | |
495 | "host", | |
3df00453 | 496 | otg_state_string(musb->xceiv->state)); |
550a7375 | 497 | } |
550a7375 | 498 | } else { |
84e250ff | 499 | switch (musb->xceiv->state) { |
550a7375 FB |
500 | case OTG_STATE_A_SUSPEND: |
501 | /* possibly DISCONNECT is upcoming */ | |
84e250ff | 502 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
503 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); |
504 | break; | |
550a7375 FB |
505 | case OTG_STATE_B_WAIT_ACON: |
506 | case OTG_STATE_B_PERIPHERAL: | |
507 | /* disconnect while suspended? we may | |
508 | * not get a disconnect irq... | |
509 | */ | |
510 | if ((devctl & MUSB_DEVCTL_VBUS) | |
511 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
512 | ) { | |
513 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
514 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
515 | break; | |
516 | } | |
517 | musb_g_resume(musb); | |
518 | break; | |
519 | case OTG_STATE_B_IDLE: | |
520 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
521 | break; | |
550a7375 FB |
522 | default: |
523 | WARNING("bogus %s RESUME (%s)\n", | |
524 | "peripheral", | |
3df00453 | 525 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
526 | } |
527 | } | |
528 | } | |
529 | ||
550a7375 FB |
530 | /* see manual for the order of the tests */ |
531 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
532 | void __iomem *mbase = musb->mregs; |
533 | ||
19aab56c HK |
534 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
535 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 536 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
537 | return IRQ_HANDLED; |
538 | } | |
539 | ||
5c8a86e1 | 540 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
3df00453 | 541 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
542 | |
543 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
544 | * is removed) SRP. responses are time critical: | |
545 | * - turn on VBUS (with silicon-specific mechanism) | |
546 | * - go through A_WAIT_VRISE | |
547 | * - ... to A_WAIT_BCON. | |
548 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
549 | */ | |
550 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
551 | musb->ep0_stage = MUSB_EP0_START; | |
84e250ff | 552 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 553 | MUSB_HST_MODE(musb); |
743411b3 | 554 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
555 | |
556 | handled = IRQ_HANDLED; | |
557 | } | |
558 | ||
559 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
560 | int ignore = 0; | |
561 | ||
562 | /* During connection as an A-Device, we may see a short | |
563 | * current spikes causing voltage drop, because of cable | |
564 | * and peripheral capacitance combined with vbus draw. | |
565 | * (So: less common with truly self-powered devices, where | |
566 | * vbus doesn't act like a power supply.) | |
567 | * | |
568 | * Such spikes are short; usually less than ~500 usec, max | |
569 | * of ~2 msec. That is, they're not sustained overcurrent | |
570 | * errors, though they're reported using VBUSERROR irqs. | |
571 | * | |
572 | * Workarounds: (a) hardware: use self powered devices. | |
573 | * (b) software: ignore non-repeated VBUS errors. | |
574 | * | |
575 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
576 | * make trouble here, keeping VBUS < 4.4V ? | |
577 | */ | |
84e250ff | 578 | switch (musb->xceiv->state) { |
550a7375 FB |
579 | case OTG_STATE_A_HOST: |
580 | /* recovery is dicey once we've gotten past the | |
581 | * initial stages of enumeration, but if VBUS | |
582 | * stayed ok at the other end of the link, and | |
583 | * another reset is due (at least for high speed, | |
584 | * to redo the chirp etc), it might work OK... | |
585 | */ | |
586 | case OTG_STATE_A_WAIT_BCON: | |
587 | case OTG_STATE_A_WAIT_VRISE: | |
588 | if (musb->vbuserr_retry) { | |
aa471456 FB |
589 | void __iomem *mbase = musb->mregs; |
590 | ||
550a7375 FB |
591 | musb->vbuserr_retry--; |
592 | ignore = 1; | |
593 | devctl |= MUSB_DEVCTL_SESSION; | |
594 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
595 | } else { | |
596 | musb->port1_status |= | |
749da5f8 AS |
597 | USB_PORT_STAT_OVERCURRENT |
598 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
599 | } |
600 | break; | |
601 | default: | |
602 | break; | |
603 | } | |
604 | ||
5c8a86e1 | 605 | dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", |
3df00453 | 606 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
607 | devctl, |
608 | ({ char *s; | |
609 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
610 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
611 | s = "<SessEnd"; break; | |
612 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
613 | s = "<AValid"; break; | |
614 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
615 | s = "<VBusValid"; break; | |
616 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
617 | default: | |
618 | s = "VALID"; break; | |
619 | }; s; }), | |
620 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
621 | musb->port1_status); | |
622 | ||
623 | /* go through A_WAIT_VFALL then start a new session */ | |
624 | if (!ignore) | |
743411b3 | 625 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
626 | handled = IRQ_HANDLED; |
627 | } | |
628 | ||
1c25fda4 | 629 | if (int_usb & MUSB_INTR_SUSPEND) { |
b11e94d0 SAS |
630 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n", |
631 | otg_state_string(musb->xceiv->state), devctl); | |
1c25fda4 AM |
632 | handled = IRQ_HANDLED; |
633 | ||
634 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
635 | case OTG_STATE_A_PERIPHERAL: |
636 | /* We also come here if the cable is removed, since | |
637 | * this silicon doesn't report ID-no-longer-grounded. | |
638 | * | |
639 | * We depend on T(a_wait_bcon) to shut us down, and | |
640 | * hope users don't do anything dicey during this | |
641 | * undesired detour through A_WAIT_BCON. | |
642 | */ | |
643 | musb_hnp_stop(musb); | |
644 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
645 | musb_root_disconnect(musb); | |
646 | musb_platform_try_idle(musb, jiffies | |
647 | + msecs_to_jiffies(musb->a_wait_bcon | |
648 | ? : OTG_TIME_A_WAIT_BCON)); | |
649 | ||
650 | break; | |
1c25fda4 AM |
651 | case OTG_STATE_B_IDLE: |
652 | if (!musb->is_active) | |
653 | break; | |
654 | case OTG_STATE_B_PERIPHERAL: | |
655 | musb_g_suspend(musb); | |
032ec49f | 656 | musb->is_active = otg->gadget->b_hnp_enable; |
1c25fda4 | 657 | if (musb->is_active) { |
1c25fda4 | 658 | musb->xceiv->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 659 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
660 | mod_timer(&musb->otg_timer, jiffies |
661 | + msecs_to_jiffies( | |
662 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
663 | } |
664 | break; | |
665 | case OTG_STATE_A_WAIT_BCON: | |
666 | if (musb->a_wait_bcon != 0) | |
667 | musb_platform_try_idle(musb, jiffies | |
668 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
669 | break; | |
670 | case OTG_STATE_A_HOST: | |
671 | musb->xceiv->state = OTG_STATE_A_SUSPEND; | |
032ec49f | 672 | musb->is_active = otg->host->b_hnp_enable; |
1c25fda4 AM |
673 | break; |
674 | case OTG_STATE_B_HOST: | |
675 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 676 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
677 | break; |
678 | default: | |
679 | /* "should not happen" */ | |
680 | musb->is_active = 0; | |
681 | break; | |
682 | } | |
683 | } | |
684 | ||
550a7375 FB |
685 | if (int_usb & MUSB_INTR_CONNECT) { |
686 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
687 | ||
688 | handled = IRQ_HANDLED; | |
689 | musb->is_active = 1; | |
550a7375 FB |
690 | |
691 | musb->ep0_stage = MUSB_EP0_START; | |
692 | ||
550a7375 FB |
693 | /* flush endpoints when transitioning from Device Mode */ |
694 | if (is_peripheral_active(musb)) { | |
695 | /* REVISIT HNP; just force disconnect */ | |
696 | } | |
b18d26f6 SAS |
697 | musb->intrtxe = musb->epmask; |
698 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); | |
af5ec14d SAS |
699 | musb->intrrxe = musb->epmask & 0xfffe; |
700 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); | |
d709d22e | 701 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); |
550a7375 FB |
702 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
703 | |USB_PORT_STAT_HIGH_SPEED | |
704 | |USB_PORT_STAT_ENABLE | |
705 | ); | |
706 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
707 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
708 | ||
709 | /* high vs full speed is just a guess until after reset */ | |
710 | if (devctl & MUSB_DEVCTL_LSDEV) | |
711 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
712 | ||
550a7375 | 713 | /* indicate new connection to OTG machine */ |
84e250ff | 714 | switch (musb->xceiv->state) { |
550a7375 FB |
715 | case OTG_STATE_B_PERIPHERAL: |
716 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 717 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 718 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 719 | goto b_host; |
550a7375 | 720 | } else |
5c8a86e1 | 721 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
722 | break; |
723 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 724 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 725 | b_host: |
84e250ff | 726 | musb->xceiv->state = OTG_STATE_B_HOST; |
550a7375 | 727 | hcd->self.is_b_host = 1; |
1de00dae DB |
728 | musb->ignore_disconnect = 0; |
729 | del_timer(&musb->otg_timer); | |
550a7375 FB |
730 | break; |
731 | default: | |
732 | if ((devctl & MUSB_DEVCTL_VBUS) | |
733 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
84e250ff | 734 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
735 | hcd->self.is_b_host = 0; |
736 | } | |
737 | break; | |
738 | } | |
1de00dae DB |
739 | |
740 | /* poke the root hub */ | |
741 | MUSB_HST_MODE(musb); | |
742 | if (hcd->status_urb) | |
743 | usb_hcd_poll_rh_status(hcd); | |
744 | else | |
745 | usb_hcd_resume_root_hub(hcd); | |
746 | ||
5c8a86e1 | 747 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
3df00453 | 748 | otg_state_string(musb->xceiv->state), devctl); |
550a7375 | 749 | } |
550a7375 | 750 | |
1c25fda4 | 751 | if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { |
5c8a86e1 | 752 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
3df00453 | 753 | otg_state_string(musb->xceiv->state), |
1c25fda4 AM |
754 | MUSB_MODE(musb), devctl); |
755 | handled = IRQ_HANDLED; | |
756 | ||
757 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
758 | case OTG_STATE_A_HOST: |
759 | case OTG_STATE_A_SUSPEND: | |
760 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
761 | musb_root_disconnect(musb); | |
032ec49f | 762 | if (musb->a_wait_bcon != 0) |
1c25fda4 AM |
763 | musb_platform_try_idle(musb, jiffies |
764 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
765 | break; | |
1c25fda4 AM |
766 | case OTG_STATE_B_HOST: |
767 | /* REVISIT this behaves for "real disconnect" | |
768 | * cases; make sure the other transitions from | |
769 | * from B_HOST act right too. The B_HOST code | |
770 | * in hnp_stop() is currently not used... | |
771 | */ | |
772 | musb_root_disconnect(musb); | |
773 | musb_to_hcd(musb)->self.is_b_host = 0; | |
774 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; | |
775 | MUSB_DEV_MODE(musb); | |
776 | musb_g_disconnect(musb); | |
777 | break; | |
778 | case OTG_STATE_A_PERIPHERAL: | |
779 | musb_hnp_stop(musb); | |
780 | musb_root_disconnect(musb); | |
781 | /* FALLTHROUGH */ | |
782 | case OTG_STATE_B_WAIT_ACON: | |
783 | /* FALLTHROUGH */ | |
1c25fda4 AM |
784 | case OTG_STATE_B_PERIPHERAL: |
785 | case OTG_STATE_B_IDLE: | |
786 | musb_g_disconnect(musb); | |
787 | break; | |
1c25fda4 AM |
788 | default: |
789 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
3df00453 | 790 | otg_state_string(musb->xceiv->state)); |
1c25fda4 AM |
791 | break; |
792 | } | |
793 | } | |
794 | ||
550a7375 FB |
795 | /* mentor saves a bit: bus reset and babble share the same irq. |
796 | * only host sees babble; only peripheral sees bus reset. | |
797 | */ | |
798 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 799 | handled = IRQ_HANDLED; |
a04d46d0 | 800 | if ((devctl & MUSB_DEVCTL_HM) != 0) { |
550a7375 FB |
801 | /* |
802 | * Looks like non-HS BABBLE can be ignored, but | |
803 | * HS BABBLE is an error condition. For HS the solution | |
804 | * is to avoid babble in the first place and fix what | |
805 | * caused BABBLE. When HS BABBLE happens we can only | |
806 | * stop the session. | |
807 | */ | |
808 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
5c8a86e1 | 809 | dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); |
550a7375 FB |
810 | else { |
811 | ERR("Stopping host session -- babble\n"); | |
1c25fda4 | 812 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
550a7375 | 813 | } |
a04d46d0 | 814 | } else { |
5c8a86e1 | 815 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
3df00453 | 816 | otg_state_string(musb->xceiv->state)); |
84e250ff | 817 | switch (musb->xceiv->state) { |
550a7375 FB |
818 | case OTG_STATE_A_SUSPEND: |
819 | /* We need to ignore disconnect on suspend | |
820 | * otherwise tusb 2.0 won't reconnect after a | |
821 | * power cycle, which breaks otg compliance. | |
822 | */ | |
823 | musb->ignore_disconnect = 1; | |
824 | musb_g_reset(musb); | |
825 | /* FALLTHROUGH */ | |
826 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 827 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 828 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
3df00453 AG |
829 | otg_state_string(musb->xceiv->state), |
830 | TA_WAIT_BCON(musb)); | |
f7f9d63e DB |
831 | mod_timer(&musb->otg_timer, jiffies |
832 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
833 | break; |
834 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
835 | musb->ignore_disconnect = 0; |
836 | del_timer(&musb->otg_timer); | |
837 | musb_g_reset(musb); | |
550a7375 FB |
838 | break; |
839 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 840 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
3df00453 | 841 | otg_state_string(musb->xceiv->state)); |
84e250ff | 842 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
843 | musb_g_reset(musb); |
844 | break; | |
550a7375 | 845 | case OTG_STATE_B_IDLE: |
84e250ff | 846 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
847 | /* FALLTHROUGH */ |
848 | case OTG_STATE_B_PERIPHERAL: | |
849 | musb_g_reset(musb); | |
850 | break; | |
851 | default: | |
5c8a86e1 | 852 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
3df00453 | 853 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
854 | } |
855 | } | |
550a7375 | 856 | } |
550a7375 FB |
857 | |
858 | #if 0 | |
859 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
860 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
861 | * limits of a given frame or microframe. | |
862 | * | |
863 | * It's not needed for peripheral side, which dedicates endpoints; | |
864 | * though it _might_ use SOF irqs for other purposes. | |
865 | * | |
866 | * And it's not currently needed for host side, which also dedicates | |
867 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
868 | * to support ISO transfers yet. | |
869 | */ | |
870 | if (int_usb & MUSB_INTR_SOF) { | |
871 | void __iomem *mbase = musb->mregs; | |
872 | struct musb_hw_ep *ep; | |
873 | u8 epnum; | |
874 | u16 frame; | |
875 | ||
5c8a86e1 | 876 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
877 | handled = IRQ_HANDLED; |
878 | ||
879 | /* start any periodic Tx transfers waiting for current frame */ | |
880 | frame = musb_readw(mbase, MUSB_FRAME); | |
881 | ep = musb->endpoints; | |
882 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
883 | && (musb->epmask >= (1 << epnum)); | |
884 | epnum++, ep++) { | |
885 | /* | |
886 | * FIXME handle framecounter wraps (12 bits) | |
887 | * eliminate duplicated StartUrb logic | |
888 | */ | |
889 | if (ep->dwWaitFrame >= frame) { | |
890 | ep->dwWaitFrame = 0; | |
891 | pr_debug("SOF --> periodic TX%s on %d\n", | |
892 | ep->tx_channel ? " DMA" : "", | |
893 | epnum); | |
894 | if (!ep->tx_channel) | |
895 | musb_h_tx_start(musb, epnum); | |
896 | else | |
897 | cppi_hostdma_start(musb, epnum); | |
898 | } | |
899 | } /* end of for loop */ | |
900 | } | |
901 | #endif | |
902 | ||
1c25fda4 | 903 | schedule_work(&musb->irq_work); |
550a7375 FB |
904 | |
905 | return handled; | |
906 | } | |
907 | ||
908 | /*-------------------------------------------------------------------------*/ | |
909 | ||
910 | /* | |
911 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
912 | */ | |
913 | void musb_start(struct musb *musb) | |
914 | { | |
915 | void __iomem *regs = musb->mregs; | |
916 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
917 | ||
5c8a86e1 | 918 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); |
550a7375 FB |
919 | |
920 | /* Set INT enable registers, enable interrupts */ | |
b18d26f6 SAS |
921 | musb->intrtxe = musb->epmask; |
922 | musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); | |
af5ec14d SAS |
923 | musb->intrrxe = musb->epmask & 0xfffe; |
924 | musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); | |
550a7375 FB |
925 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); |
926 | ||
927 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
928 | ||
929 | /* put into basic highspeed mode and start session */ | |
930 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
550a7375 FB |
931 | | MUSB_POWER_HSENAB |
932 | /* ENSUSPEND wedges tusb */ | |
933 | /* | MUSB_POWER_ENSUSPEND */ | |
934 | ); | |
935 | ||
936 | musb->is_active = 0; | |
937 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
938 | devctl &= ~MUSB_DEVCTL_SESSION; | |
939 | ||
032ec49f FB |
940 | /* session started after: |
941 | * (a) ID-grounded irq, host mode; | |
942 | * (b) vbus present/connect IRQ, peripheral mode; | |
943 | * (c) peripheral initiates, using SRP | |
944 | */ | |
945 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
946 | musb->is_active = 1; | |
947 | else | |
550a7375 FB |
948 | devctl |= MUSB_DEVCTL_SESSION; |
949 | ||
550a7375 FB |
950 | musb_platform_enable(musb); |
951 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
952 | } | |
953 | ||
954 | ||
955 | static void musb_generic_disable(struct musb *musb) | |
956 | { | |
957 | void __iomem *mbase = musb->mregs; | |
958 | u16 temp; | |
959 | ||
960 | /* disable interrupts */ | |
961 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
b18d26f6 | 962 | musb->intrtxe = 0; |
550a7375 | 963 | musb_writew(mbase, MUSB_INTRTXE, 0); |
af5ec14d | 964 | musb->intrrxe = 0; |
550a7375 FB |
965 | musb_writew(mbase, MUSB_INTRRXE, 0); |
966 | ||
967 | /* off */ | |
968 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
969 | ||
970 | /* flush pending interrupts */ | |
971 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
972 | temp = musb_readw(mbase, MUSB_INTRTX); | |
973 | temp = musb_readw(mbase, MUSB_INTRRX); | |
974 | ||
975 | } | |
976 | ||
977 | /* | |
978 | * Make the HDRC stop (disable interrupts, etc.); | |
979 | * reversible by musb_start | |
980 | * called on gadget driver unregister | |
981 | * with controller locked, irqs blocked | |
982 | * acts as a NOP unless some role activated the hardware | |
983 | */ | |
984 | void musb_stop(struct musb *musb) | |
985 | { | |
986 | /* stop IRQs, timers, ... */ | |
987 | musb_platform_disable(musb); | |
988 | musb_generic_disable(musb); | |
5c8a86e1 | 989 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
990 | |
991 | /* FIXME | |
992 | * - mark host and/or peripheral drivers unusable/inactive | |
993 | * - disable DMA (and enable it in HdrcStart) | |
994 | * - make sure we can musb_start() after musb_stop(); with | |
995 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
996 | * - ... | |
997 | */ | |
998 | musb_platform_try_idle(musb, 0); | |
999 | } | |
1000 | ||
1001 | static void musb_shutdown(struct platform_device *pdev) | |
1002 | { | |
1003 | struct musb *musb = dev_to_musb(&pdev->dev); | |
1004 | unsigned long flags; | |
1005 | ||
4f9edd2d | 1006 | pm_runtime_get_sync(musb->controller); |
24307cae GI |
1007 | |
1008 | musb_gadget_cleanup(musb); | |
1009 | ||
550a7375 FB |
1010 | spin_lock_irqsave(&musb->lock, flags); |
1011 | musb_platform_disable(musb); | |
1012 | musb_generic_disable(musb); | |
550a7375 FB |
1013 | spin_unlock_irqrestore(&musb->lock, flags); |
1014 | ||
120d074c GI |
1015 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
1016 | musb_platform_exit(musb); | |
120d074c | 1017 | |
4f9edd2d | 1018 | pm_runtime_put(musb->controller); |
550a7375 FB |
1019 | /* FIXME power down */ |
1020 | } | |
1021 | ||
1022 | ||
1023 | /*-------------------------------------------------------------------------*/ | |
1024 | ||
1025 | /* | |
1026 | * The silicon either has hard-wired endpoint configurations, or else | |
1027 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1028 | * writing only the dynamic sizing is very well tested. Since we switched |
1029 | * away from compile-time hardware parameters, we can no longer rely on | |
1030 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1031 | * |
1032 | * We don't currently use dynamic fifo setup capability to do anything | |
1033 | * more than selecting one of a bunch of predefined configurations. | |
1034 | */ | |
ee34e51a FB |
1035 | #if defined(CONFIG_USB_MUSB_TUSB6010) \ |
1036 | || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ | |
1037 | || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ | |
1038 | || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ | |
1039 | || defined(CONFIG_USB_MUSB_AM35X) \ | |
9ecb8875 AKG |
1040 | || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ |
1041 | || defined(CONFIG_USB_MUSB_DSPS) \ | |
1042 | || defined(CONFIG_USB_MUSB_DSPS_MODULE) | |
e9e8c85e | 1043 | static ushort __devinitdata fifo_mode = 4; |
ee34e51a FB |
1044 | #elif defined(CONFIG_USB_MUSB_UX500) \ |
1045 | || defined(CONFIG_USB_MUSB_UX500_MODULE) | |
e9e8c85e | 1046 | static ushort __devinitdata fifo_mode = 5; |
550a7375 | 1047 | #else |
e9e8c85e | 1048 | static ushort __devinitdata fifo_mode = 2; |
550a7375 FB |
1049 | #endif |
1050 | ||
1051 | /* "modprobe ... fifo_mode=1" etc */ | |
1052 | module_param(fifo_mode, ushort, 0); | |
1053 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1054 | ||
550a7375 FB |
1055 | /* |
1056 | * tables defining fifo_mode values. define more if you like. | |
1057 | * for host side, make sure both halves of ep1 are set up. | |
1058 | */ | |
1059 | ||
1060 | /* mode 0 - fits in 2KB */ | |
e9e8c85e | 1061 | static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { |
550a7375 FB |
1062 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1063 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1064 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1065 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1066 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1067 | }; | |
1068 | ||
1069 | /* mode 1 - fits in 4KB */ | |
e9e8c85e | 1070 | static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { |
550a7375 FB |
1071 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1072 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1073 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1074 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1075 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1076 | }; | |
1077 | ||
1078 | /* mode 2 - fits in 4KB */ | |
e9e8c85e | 1079 | static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { |
550a7375 FB |
1080 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1081 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1082 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1083 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1084 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1085 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1086 | }; | |
1087 | ||
1088 | /* mode 3 - fits in 4KB */ | |
e9e8c85e | 1089 | static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { |
550a7375 FB |
1090 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1091 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1092 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1093 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1094 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1095 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1096 | }; | |
1097 | ||
1098 | /* mode 4 - fits in 16KB */ | |
e9e8c85e | 1099 | static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { |
550a7375 FB |
1100 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1101 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1102 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1103 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1104 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1105 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1106 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1107 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1108 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1109 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1110 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1111 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1112 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1113 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1114 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1115 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1116 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1117 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1118 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1119 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1120 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1121 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1122 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1123 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1124 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1125 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1126 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1127 | }; | |
1128 | ||
3b151526 | 1129 | /* mode 5 - fits in 8KB */ |
e9e8c85e | 1130 | static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { |
3b151526 AKG |
1131 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1132 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1133 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1134 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1135 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1136 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1137 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1138 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1139 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1140 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1141 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1142 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1143 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1144 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1145 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1146 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1147 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1148 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1149 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1150 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1151 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1152 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1153 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1154 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1155 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1156 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1157 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1158 | }; | |
550a7375 FB |
1159 | |
1160 | /* | |
1161 | * configure a fifo; for non-shared endpoints, this may be called | |
1162 | * once for a tx fifo and once for an rx fifo. | |
1163 | * | |
1164 | * returns negative errno or offset for next fifo. | |
1165 | */ | |
41ac7b3a | 1166 | static int |
550a7375 | 1167 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
e6c213b2 | 1168 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1169 | { |
1170 | void __iomem *mbase = musb->mregs; | |
1171 | int size = 0; | |
1172 | u16 maxpacket = cfg->maxpacket; | |
1173 | u16 c_off = offset >> 3; | |
1174 | u8 c_size; | |
1175 | ||
1176 | /* expect hw_ep has already been zero-initialized */ | |
1177 | ||
1178 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1179 | maxpacket = 1 << size; | |
1180 | ||
1181 | c_size = size - 3; | |
1182 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1183 | if ((offset + (maxpacket << 1)) > |
1184 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1185 | return -EMSGSIZE; |
1186 | c_size |= MUSB_FIFOSZ_DPB; | |
1187 | } else { | |
ca6d1b13 | 1188 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1189 | return -EMSGSIZE; |
1190 | } | |
1191 | ||
1192 | /* configure the FIFO */ | |
1193 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1194 | ||
550a7375 FB |
1195 | /* EP0 reserved endpoint for control, bidirectional; |
1196 | * EP1 reserved for bulk, two unidirection halves. | |
1197 | */ | |
1198 | if (hw_ep->epnum == 1) | |
1199 | musb->bulk_ep = hw_ep; | |
1200 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1201 | switch (cfg->style) { |
1202 | case FIFO_TX: | |
c6cf8b00 BW |
1203 | musb_write_txfifosz(mbase, c_size); |
1204 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1205 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1206 | hw_ep->max_packet_sz_tx = maxpacket; | |
1207 | break; | |
1208 | case FIFO_RX: | |
c6cf8b00 BW |
1209 | musb_write_rxfifosz(mbase, c_size); |
1210 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1211 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1212 | hw_ep->max_packet_sz_rx = maxpacket; | |
1213 | break; | |
1214 | case FIFO_RXTX: | |
c6cf8b00 BW |
1215 | musb_write_txfifosz(mbase, c_size); |
1216 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1217 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1218 | hw_ep->max_packet_sz_rx = maxpacket; | |
1219 | ||
c6cf8b00 BW |
1220 | musb_write_rxfifosz(mbase, c_size); |
1221 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1222 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1223 | hw_ep->max_packet_sz_tx = maxpacket; | |
1224 | ||
1225 | hw_ep->is_shared_fifo = true; | |
1226 | break; | |
1227 | } | |
1228 | ||
1229 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1230 | * which happens to be ok | |
1231 | */ | |
1232 | musb->epmask |= (1 << hw_ep->epnum); | |
1233 | ||
1234 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1235 | } | |
1236 | ||
e9e8c85e | 1237 | static struct musb_fifo_cfg __devinitdata ep0_cfg = { |
550a7375 FB |
1238 | .style = FIFO_RXTX, .maxpacket = 64, |
1239 | }; | |
1240 | ||
41ac7b3a | 1241 | static int ep_config_from_table(struct musb *musb) |
550a7375 | 1242 | { |
e6c213b2 | 1243 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1244 | unsigned i, n; |
1245 | int offset; | |
1246 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1247 | ||
e6c213b2 FB |
1248 | if (musb->config->fifo_cfg) { |
1249 | cfg = musb->config->fifo_cfg; | |
1250 | n = musb->config->fifo_cfg_size; | |
1251 | goto done; | |
1252 | } | |
1253 | ||
550a7375 FB |
1254 | switch (fifo_mode) { |
1255 | default: | |
1256 | fifo_mode = 0; | |
1257 | /* FALLTHROUGH */ | |
1258 | case 0: | |
1259 | cfg = mode_0_cfg; | |
1260 | n = ARRAY_SIZE(mode_0_cfg); | |
1261 | break; | |
1262 | case 1: | |
1263 | cfg = mode_1_cfg; | |
1264 | n = ARRAY_SIZE(mode_1_cfg); | |
1265 | break; | |
1266 | case 2: | |
1267 | cfg = mode_2_cfg; | |
1268 | n = ARRAY_SIZE(mode_2_cfg); | |
1269 | break; | |
1270 | case 3: | |
1271 | cfg = mode_3_cfg; | |
1272 | n = ARRAY_SIZE(mode_3_cfg); | |
1273 | break; | |
1274 | case 4: | |
1275 | cfg = mode_4_cfg; | |
1276 | n = ARRAY_SIZE(mode_4_cfg); | |
1277 | break; | |
3b151526 AKG |
1278 | case 5: |
1279 | cfg = mode_5_cfg; | |
1280 | n = ARRAY_SIZE(mode_5_cfg); | |
1281 | break; | |
550a7375 FB |
1282 | } |
1283 | ||
1284 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1285 | musb_driver_name, fifo_mode); | |
1286 | ||
1287 | ||
e6c213b2 | 1288 | done: |
550a7375 FB |
1289 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1290 | /* assert(offset > 0) */ | |
1291 | ||
1292 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1293 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1294 | */ |
1295 | ||
1296 | for (i = 0; i < n; i++) { | |
1297 | u8 epn = cfg->hw_ep_num; | |
1298 | ||
ca6d1b13 | 1299 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1300 | pr_debug("%s: invalid ep %d\n", |
1301 | musb_driver_name, epn); | |
bb1c9ef1 | 1302 | return -EINVAL; |
550a7375 FB |
1303 | } |
1304 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1305 | if (offset < 0) { | |
1306 | pr_debug("%s: mem overrun, ep %d\n", | |
1307 | musb_driver_name, epn); | |
f69dfa1f | 1308 | return offset; |
550a7375 FB |
1309 | } |
1310 | epn++; | |
1311 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1312 | } | |
1313 | ||
1314 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1315 | musb_driver_name, | |
ca6d1b13 FB |
1316 | n + 1, musb->config->num_eps * 2 - 1, |
1317 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1318 | |
550a7375 FB |
1319 | if (!musb->bulk_ep) { |
1320 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1321 | return -EINVAL; | |
1322 | } | |
550a7375 FB |
1323 | |
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | ||
1328 | /* | |
1329 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1330 | * @param musb the controller | |
1331 | */ | |
41ac7b3a | 1332 | static int ep_config_from_hw(struct musb *musb) |
550a7375 | 1333 | { |
c6cf8b00 | 1334 | u8 epnum = 0; |
550a7375 | 1335 | struct musb_hw_ep *hw_ep; |
a156544b | 1336 | void __iomem *mbase = musb->mregs; |
c6cf8b00 | 1337 | int ret = 0; |
550a7375 | 1338 | |
5c8a86e1 | 1339 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1340 | |
1341 | /* FIXME pick up ep0 maxpacket size */ | |
1342 | ||
ca6d1b13 | 1343 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1344 | musb_ep_select(mbase, epnum); |
1345 | hw_ep = musb->endpoints + epnum; | |
1346 | ||
c6cf8b00 BW |
1347 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1348 | if (ret < 0) | |
550a7375 | 1349 | break; |
550a7375 FB |
1350 | |
1351 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1352 | ||
550a7375 FB |
1353 | /* pick an RX/TX endpoint for bulk */ |
1354 | if (hw_ep->max_packet_sz_tx < 512 | |
1355 | || hw_ep->max_packet_sz_rx < 512) | |
1356 | continue; | |
1357 | ||
1358 | /* REVISIT: this algorithm is lazy, we should at least | |
1359 | * try to pick a double buffered endpoint. | |
1360 | */ | |
1361 | if (musb->bulk_ep) | |
1362 | continue; | |
1363 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1364 | } |
1365 | ||
550a7375 FB |
1366 | if (!musb->bulk_ep) { |
1367 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1368 | return -EINVAL; | |
1369 | } | |
550a7375 FB |
1370 | |
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1375 | ||
1376 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1377 | * configure endpoints, or take their config from silicon | |
1378 | */ | |
41ac7b3a | 1379 | static int musb_core_init(u16 musb_type, struct musb *musb) |
550a7375 | 1380 | { |
550a7375 FB |
1381 | u8 reg; |
1382 | char *type; | |
0ea52ff4 | 1383 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1384 | void __iomem *mbase = musb->mregs; |
1385 | int status = 0; | |
1386 | int i; | |
1387 | ||
1388 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1389 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1390 | |
1391 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1392 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1393 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1394 | musb->dyn_fifo = true; |
1395 | } | |
550a7375 FB |
1396 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1397 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1398 | musb->bulk_combine = true; |
550a7375 FB |
1399 | } |
1400 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1401 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1402 | musb->bulk_split = true; |
550a7375 FB |
1403 | } |
1404 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1405 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1406 | musb->hb_iso_rx = true; |
550a7375 FB |
1407 | } |
1408 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1409 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1410 | musb->hb_iso_tx = true; |
550a7375 FB |
1411 | } |
1412 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1413 | strcat(aInfo, ", SoftConn"); | |
1414 | ||
1415 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1416 | musb_driver_name, reg, aInfo); | |
1417 | ||
550a7375 | 1418 | aDate[0] = 0; |
550a7375 FB |
1419 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1420 | musb->is_multipoint = 1; | |
1421 | type = "M"; | |
1422 | } else { | |
1423 | musb->is_multipoint = 0; | |
1424 | type = ""; | |
550a7375 FB |
1425 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1426 | printk(KERN_ERR | |
1427 | "%s: kernel must blacklist external hubs\n", | |
1428 | musb_driver_name); | |
550a7375 FB |
1429 | #endif |
1430 | } | |
1431 | ||
1432 | /* log release info */ | |
32c3b94e AG |
1433 | musb->hwvers = musb_read_hwvers(mbase); |
1434 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1435 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1436 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1437 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1438 | musb_driver_name, type, aRevision, aDate); | |
1439 | ||
1440 | /* configure ep0 */ | |
c6cf8b00 | 1441 | musb_configure_ep0(musb); |
550a7375 FB |
1442 | |
1443 | /* discover endpoint configuration */ | |
1444 | musb->nr_endpoints = 1; | |
1445 | musb->epmask = 1; | |
1446 | ||
ad517e9e FB |
1447 | if (musb->dyn_fifo) |
1448 | status = ep_config_from_table(musb); | |
1449 | else | |
1450 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1451 | |
1452 | if (status < 0) | |
1453 | return status; | |
1454 | ||
1455 | /* finish init, and print endpoint config */ | |
1456 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1457 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1458 | ||
1459 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
9a35f876 | 1460 | #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) |
550a7375 FB |
1461 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); |
1462 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1463 | hw_ep->fifo_sync_va = | |
1464 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1465 | ||
1466 | if (i == 0) | |
1467 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1468 | else | |
1469 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1470 | #endif | |
1471 | ||
1472 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
c6cf8b00 | 1473 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1474 | hw_ep->rx_reinit = 1; |
1475 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1476 | |
1477 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1478 | dev_dbg(musb->controller, |
550a7375 FB |
1479 | "%s: hw_ep %d%s, %smax %d\n", |
1480 | musb_driver_name, i, | |
1481 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1482 | hw_ep->tx_double_buffered | |
1483 | ? "doublebuffer, " : "", | |
1484 | hw_ep->max_packet_sz_tx); | |
1485 | } | |
1486 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1487 | dev_dbg(musb->controller, |
550a7375 FB |
1488 | "%s: hw_ep %d%s, %smax %d\n", |
1489 | musb_driver_name, i, | |
1490 | "rx", | |
1491 | hw_ep->rx_double_buffered | |
1492 | ? "doublebuffer, " : "", | |
1493 | hw_ep->max_packet_sz_rx); | |
1494 | } | |
1495 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1496 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1497 | } |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
1502 | /*-------------------------------------------------------------------------*/ | |
1503 | ||
550a7375 FB |
1504 | /* |
1505 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1506 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1507 | * will be assigned, and the irq will already have been acked. | |
1508 | * | |
1509 | * called in irq context with spinlock held, irqs blocked | |
1510 | */ | |
1511 | irqreturn_t musb_interrupt(struct musb *musb) | |
1512 | { | |
1513 | irqreturn_t retval = IRQ_NONE; | |
b11e94d0 | 1514 | u8 devctl; |
550a7375 FB |
1515 | int ep_num; |
1516 | u32 reg; | |
1517 | ||
1518 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
550a7375 | 1519 | |
5c8a86e1 | 1520 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
550a7375 FB |
1521 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", |
1522 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1523 | ||
1524 | /* the core can interrupt us for multiple reasons; docs have | |
1525 | * a generic interrupt flowchart to follow | |
1526 | */ | |
7d9645fd | 1527 | if (musb->int_usb) |
550a7375 | 1528 | retval |= musb_stage0_irq(musb, musb->int_usb, |
b11e94d0 | 1529 | devctl); |
550a7375 FB |
1530 | |
1531 | /* "stage 1" is handling endpoint irqs */ | |
1532 | ||
1533 | /* handle endpoint 0 first */ | |
1534 | if (musb->int_tx & 1) { | |
1535 | if (devctl & MUSB_DEVCTL_HM) | |
1536 | retval |= musb_h_ep0_irq(musb); | |
1537 | else | |
1538 | retval |= musb_g_ep0_irq(musb); | |
1539 | } | |
1540 | ||
1541 | /* RX on endpoints 1-15 */ | |
1542 | reg = musb->int_rx >> 1; | |
1543 | ep_num = 1; | |
1544 | while (reg) { | |
1545 | if (reg & 1) { | |
1546 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1547 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1548 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1549 | if (devctl & MUSB_DEVCTL_HM) |
1550 | musb_host_rx(musb, ep_num); | |
1551 | else | |
1552 | musb_g_rx(musb, ep_num); | |
550a7375 FB |
1553 | } |
1554 | ||
1555 | reg >>= 1; | |
1556 | ep_num++; | |
1557 | } | |
1558 | ||
1559 | /* TX on endpoints 1-15 */ | |
1560 | reg = musb->int_tx >> 1; | |
1561 | ep_num = 1; | |
1562 | while (reg) { | |
1563 | if (reg & 1) { | |
1564 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1565 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1566 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1567 | if (devctl & MUSB_DEVCTL_HM) |
1568 | musb_host_tx(musb, ep_num); | |
1569 | else | |
1570 | musb_g_tx(musb, ep_num); | |
550a7375 FB |
1571 | } |
1572 | reg >>= 1; | |
1573 | ep_num++; | |
1574 | } | |
1575 | ||
550a7375 FB |
1576 | return retval; |
1577 | } | |
981430a1 | 1578 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1579 | |
1580 | #ifndef CONFIG_MUSB_PIO_ONLY | |
e9e8c85e | 1581 | static bool __devinitdata use_dma = 1; |
550a7375 FB |
1582 | |
1583 | /* "modprobe ... use_dma=0" etc */ | |
1584 | module_param(use_dma, bool, 0); | |
1585 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1586 | ||
1587 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1588 | { | |
1589 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1590 | ||
1591 | /* called with controller lock already held */ | |
1592 | ||
1593 | if (!epnum) { | |
1594 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1595 | if (!is_cppi_enabled()) { | |
1596 | /* endpoint 0 */ | |
1597 | if (devctl & MUSB_DEVCTL_HM) | |
1598 | musb_h_ep0_irq(musb); | |
1599 | else | |
1600 | musb_g_ep0_irq(musb); | |
1601 | } | |
1602 | #endif | |
1603 | } else { | |
1604 | /* endpoints 1..15 */ | |
1605 | if (transmit) { | |
a04d46d0 FB |
1606 | if (devctl & MUSB_DEVCTL_HM) |
1607 | musb_host_tx(musb, epnum); | |
1608 | else | |
1609 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1610 | } else { |
1611 | /* receive */ | |
a04d46d0 FB |
1612 | if (devctl & MUSB_DEVCTL_HM) |
1613 | musb_host_rx(musb, epnum); | |
1614 | else | |
1615 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1616 | } |
1617 | } | |
1618 | } | |
9a35f876 | 1619 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1620 | |
1621 | #else | |
1622 | #define use_dma 0 | |
1623 | #endif | |
1624 | ||
1625 | /*-------------------------------------------------------------------------*/ | |
1626 | ||
1627 | #ifdef CONFIG_SYSFS | |
1628 | ||
1629 | static ssize_t | |
1630 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1631 | { | |
1632 | struct musb *musb = dev_to_musb(dev); | |
1633 | unsigned long flags; | |
1634 | int ret = -EINVAL; | |
1635 | ||
1636 | spin_lock_irqsave(&musb->lock, flags); | |
3df00453 | 1637 | ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1638 | spin_unlock_irqrestore(&musb->lock, flags); |
1639 | ||
1640 | return ret; | |
1641 | } | |
1642 | ||
1643 | static ssize_t | |
1644 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1645 | const char *buf, size_t n) | |
1646 | { | |
1647 | struct musb *musb = dev_to_musb(dev); | |
1648 | unsigned long flags; | |
96a274d1 | 1649 | int status; |
550a7375 FB |
1650 | |
1651 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1652 | if (sysfs_streq(buf, "host")) |
1653 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1654 | else if (sysfs_streq(buf, "peripheral")) | |
1655 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1656 | else if (sysfs_streq(buf, "otg")) | |
1657 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1658 | else | |
1659 | status = -EINVAL; | |
550a7375 FB |
1660 | spin_unlock_irqrestore(&musb->lock, flags); |
1661 | ||
96a274d1 | 1662 | return (status == 0) ? n : status; |
550a7375 FB |
1663 | } |
1664 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1665 | ||
1666 | static ssize_t | |
1667 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1668 | const char *buf, size_t n) | |
1669 | { | |
1670 | struct musb *musb = dev_to_musb(dev); | |
1671 | unsigned long flags; | |
1672 | unsigned long val; | |
1673 | ||
1674 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1675 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1676 | return -EINVAL; |
1677 | } | |
1678 | ||
1679 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1680 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1681 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
84e250ff | 1682 | if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1683 | musb->is_active = 0; |
1684 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1685 | spin_unlock_irqrestore(&musb->lock, flags); | |
1686 | ||
1687 | return n; | |
1688 | } | |
1689 | ||
1690 | static ssize_t | |
1691 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1692 | { | |
1693 | struct musb *musb = dev_to_musb(dev); | |
1694 | unsigned long flags; | |
1695 | unsigned long val; | |
1696 | int vbus; | |
1697 | ||
1698 | spin_lock_irqsave(&musb->lock, flags); | |
1699 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1700 | /* FIXME get_vbus_status() is normally #defined as false... |
1701 | * and is effectively TUSB-specific. | |
1702 | */ | |
550a7375 FB |
1703 | vbus = musb_platform_get_vbus_status(musb); |
1704 | spin_unlock_irqrestore(&musb->lock, flags); | |
1705 | ||
f7f9d63e | 1706 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1707 | vbus ? "on" : "off", val); |
1708 | } | |
1709 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1710 | ||
550a7375 FB |
1711 | /* Gadget drivers can't know that a host is connected so they might want |
1712 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1713 | */ | |
1714 | static ssize_t | |
1715 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1716 | const char *buf, size_t n) | |
1717 | { | |
1718 | struct musb *musb = dev_to_musb(dev); | |
1719 | unsigned short srp; | |
1720 | ||
1721 | if (sscanf(buf, "%hu", &srp) != 1 | |
1722 | || (srp != 1)) { | |
b3b1cc3b | 1723 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1724 | return -EINVAL; |
1725 | } | |
1726 | ||
1727 | if (srp == 1) | |
1728 | musb_g_wakeup(musb); | |
1729 | ||
1730 | return n; | |
1731 | } | |
1732 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1733 | ||
94375751 FB |
1734 | static struct attribute *musb_attributes[] = { |
1735 | &dev_attr_mode.attr, | |
1736 | &dev_attr_vbus.attr, | |
94375751 | 1737 | &dev_attr_srp.attr, |
94375751 FB |
1738 | NULL |
1739 | }; | |
1740 | ||
1741 | static const struct attribute_group musb_attr_group = { | |
1742 | .attrs = musb_attributes, | |
1743 | }; | |
1744 | ||
550a7375 FB |
1745 | #endif /* sysfs */ |
1746 | ||
1747 | /* Only used to provide driver mode change events */ | |
1748 | static void musb_irq_work(struct work_struct *data) | |
1749 | { | |
1750 | struct musb *musb = container_of(data, struct musb, irq_work); | |
550a7375 | 1751 | |
8d2421e6 AKG |
1752 | if (musb->xceiv->state != musb->xceiv_old_state) { |
1753 | musb->xceiv_old_state = musb->xceiv->state; | |
550a7375 FB |
1754 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1755 | } | |
1756 | } | |
1757 | ||
1758 | /* -------------------------------------------------------------------------- | |
1759 | * Init support | |
1760 | */ | |
1761 | ||
41ac7b3a | 1762 | static struct musb *allocate_instance(struct device *dev, |
ca6d1b13 | 1763 | struct musb_hdrc_config *config, void __iomem *mbase) |
550a7375 FB |
1764 | { |
1765 | struct musb *musb; | |
1766 | struct musb_hw_ep *ep; | |
1767 | int epnum; | |
550a7375 FB |
1768 | struct usb_hcd *hcd; |
1769 | ||
427c4f33 | 1770 | hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); |
550a7375 FB |
1771 | if (!hcd) |
1772 | return NULL; | |
1773 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
1774 | ||
1775 | musb = hcd_to_musb(hcd); | |
1776 | INIT_LIST_HEAD(&musb->control); | |
1777 | INIT_LIST_HEAD(&musb->in_bulk); | |
1778 | INIT_LIST_HEAD(&musb->out_bulk); | |
1779 | ||
1780 | hcd->uses_new_polling = 1; | |
ec95d35a | 1781 | hcd->has_tt = 1; |
550a7375 FB |
1782 | |
1783 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; | |
f7f9d63e | 1784 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
456bb169 | 1785 | dev_set_drvdata(dev, musb); |
550a7375 FB |
1786 | musb->mregs = mbase; |
1787 | musb->ctrl_base = mbase; | |
1788 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1789 | musb->config = config; |
02582b92 | 1790 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1791 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1792 | epnum < musb->config->num_eps; |
550a7375 | 1793 | epnum++, ep++) { |
550a7375 FB |
1794 | ep->musb = musb; |
1795 | ep->epnum = epnum; | |
1796 | } | |
1797 | ||
1798 | musb->controller = dev; | |
743411b3 | 1799 | |
550a7375 FB |
1800 | return musb; |
1801 | } | |
1802 | ||
1803 | static void musb_free(struct musb *musb) | |
1804 | { | |
1805 | /* this has multiple entry modes. it handles fault cleanup after | |
1806 | * probe(), where things may be partially set up, as well as rmmod | |
1807 | * cleanup after everything's been de-activated. | |
1808 | */ | |
1809 | ||
1810 | #ifdef CONFIG_SYSFS | |
94375751 | 1811 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1812 | #endif |
1813 | ||
97a39896 AKG |
1814 | if (musb->nIrq >= 0) { |
1815 | if (musb->irq_wake) | |
1816 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1817 | free_irq(musb->nIrq, musb); |
1818 | } | |
1819 | if (is_dma_capable() && musb->dma_controller) { | |
1820 | struct dma_controller *c = musb->dma_controller; | |
1821 | ||
1822 | (void) c->stop(c); | |
1823 | dma_controller_destroy(c); | |
1824 | } | |
1825 | ||
decadacb | 1826 | usb_put_hcd(musb_to_hcd(musb)); |
550a7375 FB |
1827 | } |
1828 | ||
1829 | /* | |
1830 | * Perform generic per-controller initialization. | |
1831 | * | |
28dd924a SS |
1832 | * @dev: the controller (already clocked, etc) |
1833 | * @nIrq: IRQ number | |
1834 | * @ctrl: virtual address of controller registers, | |
550a7375 FB |
1835 | * not yet corrected for platform-specific offsets |
1836 | */ | |
41ac7b3a | 1837 | static int |
550a7375 FB |
1838 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
1839 | { | |
1840 | int status; | |
1841 | struct musb *musb; | |
1842 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
032ec49f | 1843 | struct usb_hcd *hcd; |
550a7375 FB |
1844 | |
1845 | /* The driver might handle more features than the board; OK. | |
1846 | * Fail when the board needs a feature that's not enabled. | |
1847 | */ | |
1848 | if (!plat) { | |
1849 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1850 | status = -ENODEV; |
1851 | goto fail0; | |
550a7375 | 1852 | } |
34e2beb2 | 1853 | |
550a7375 | 1854 | /* allocate */ |
ca6d1b13 | 1855 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1856 | if (!musb) { |
1857 | status = -ENOMEM; | |
1858 | goto fail0; | |
1859 | } | |
550a7375 | 1860 | |
7acc6197 HH |
1861 | pm_runtime_use_autosuspend(musb->controller); |
1862 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
1863 | pm_runtime_enable(musb->controller); | |
1864 | ||
550a7375 | 1865 | spin_lock_init(&musb->lock); |
550a7375 | 1866 | musb->board_set_power = plat->set_power; |
550a7375 | 1867 | musb->min_power = plat->min_power; |
f7ec9437 | 1868 | musb->ops = plat->platform_ops; |
550a7375 | 1869 | |
84e250ff | 1870 | /* The musb_platform_init() call: |
baef653a PDS |
1871 | * - adjusts musb->mregs |
1872 | * - sets the musb->isr | |
84e250ff | 1873 | * - may initialize an integrated tranceiver |
721002ec | 1874 | * - initializes musb->xceiv, usually by otg_get_phy() |
84e250ff | 1875 | * - stops powering VBUS |
84e250ff | 1876 | * |
7c9d440e | 1877 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
1878 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
1879 | * external/discrete ones in various flavors (twl4030 family, | |
1880 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 | 1881 | */ |
ea65df57 | 1882 | status = musb_platform_init(musb); |
550a7375 | 1883 | if (status < 0) |
03491761 | 1884 | goto fail1; |
34e2beb2 | 1885 | |
550a7375 FB |
1886 | if (!musb->isr) { |
1887 | status = -ENODEV; | |
c04352a5 | 1888 | goto fail2; |
550a7375 FB |
1889 | } |
1890 | ||
ffb865b1 | 1891 | if (!musb->xceiv->io_ops) { |
bf070bc1 | 1892 | musb->xceiv->io_dev = musb->controller; |
ffb865b1 HK |
1893 | musb->xceiv->io_priv = musb->mregs; |
1894 | musb->xceiv->io_ops = &musb_ulpi_access; | |
1895 | } | |
1896 | ||
c04352a5 GI |
1897 | pm_runtime_get_sync(musb->controller); |
1898 | ||
550a7375 FB |
1899 | #ifndef CONFIG_MUSB_PIO_ONLY |
1900 | if (use_dma && dev->dma_mask) { | |
1901 | struct dma_controller *c; | |
1902 | ||
1903 | c = dma_controller_create(musb, musb->mregs); | |
1904 | musb->dma_controller = c; | |
1905 | if (c) | |
1906 | (void) c->start(c); | |
1907 | } | |
1908 | #endif | |
1909 | /* ideally this would be abstracted in platform setup */ | |
1910 | if (!is_dma_capable() || !musb->dma_controller) | |
1911 | dev->dma_mask = NULL; | |
1912 | ||
1913 | /* be sure interrupts are disabled before connecting ISR */ | |
1914 | musb_platform_disable(musb); | |
1915 | musb_generic_disable(musb); | |
1916 | ||
1917 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1918 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1919 | ? MUSB_CONTROLLER_MHDRC |
1920 | : MUSB_CONTROLLER_HDRC, musb); | |
1921 | if (status < 0) | |
34e2beb2 | 1922 | goto fail3; |
550a7375 | 1923 | |
f7f9d63e | 1924 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 1925 | |
550a7375 FB |
1926 | /* Init IRQ workqueue before request_irq */ |
1927 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1928 | ||
1929 | /* attach to the IRQ */ | |
427c4f33 | 1930 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1931 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1932 | status = -ENODEV; | |
34e2beb2 | 1933 | goto fail3; |
550a7375 FB |
1934 | } |
1935 | musb->nIrq = nIrq; | |
032ec49f | 1936 | /* FIXME this handles wakeup irqs wrong */ |
c48a5155 FB |
1937 | if (enable_irq_wake(nIrq) == 0) { |
1938 | musb->irq_wake = 1; | |
550a7375 | 1939 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1940 | } else { |
1941 | musb->irq_wake = 0; | |
1942 | } | |
550a7375 | 1943 | |
84e250ff | 1944 | /* host side needs more setup */ |
032ec49f FB |
1945 | hcd = musb_to_hcd(musb); |
1946 | otg_set_host(musb->xceiv->otg, &hcd->self); | |
1947 | hcd->self.otg_port = 1; | |
1948 | musb->xceiv->otg->host = &hcd->self; | |
1949 | hcd->power_budget = 2 * (plat->power ? : 250); | |
1950 | ||
1951 | /* program PHY to use external vBus if required */ | |
1952 | if (plat->extvbus) { | |
1953 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
1954 | busctl |= MUSB_ULPI_USE_EXTVBUS; | |
1955 | musb_write_ulpi_buscontrol(musb->mregs, busctl); | |
550a7375 | 1956 | } |
550a7375 | 1957 | |
032ec49f FB |
1958 | MUSB_DEV_MODE(musb); |
1959 | musb->xceiv->otg->default_a = 0; | |
1960 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
550a7375 | 1961 | |
032ec49f | 1962 | status = musb_gadget_setup(musb); |
550a7375 | 1963 | |
461972d8 | 1964 | if (status < 0) |
34e2beb2 | 1965 | goto fail3; |
550a7375 | 1966 | |
7f7f9e2a FB |
1967 | status = musb_init_debugfs(musb); |
1968 | if (status < 0) | |
b0f9da7e | 1969 | goto fail4; |
7f7f9e2a | 1970 | |
550a7375 | 1971 | #ifdef CONFIG_SYSFS |
94375751 | 1972 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 1973 | if (status) |
b0f9da7e | 1974 | goto fail5; |
461972d8 | 1975 | #endif |
550a7375 | 1976 | |
c04352a5 GI |
1977 | pm_runtime_put(musb->controller); |
1978 | ||
28c2c51c | 1979 | return 0; |
550a7375 | 1980 | |
b0f9da7e FB |
1981 | fail5: |
1982 | musb_exit_debugfs(musb); | |
1983 | ||
34e2beb2 | 1984 | fail4: |
032ec49f | 1985 | musb_gadget_cleanup(musb); |
34e2beb2 SS |
1986 | |
1987 | fail3: | |
c04352a5 GI |
1988 | pm_runtime_put_sync(musb->controller); |
1989 | ||
1990 | fail2: | |
34e2beb2 SS |
1991 | if (musb->irq_wake) |
1992 | device_init_wakeup(dev, 0); | |
550a7375 | 1993 | musb_platform_exit(musb); |
28c2c51c | 1994 | |
34e2beb2 SS |
1995 | fail1: |
1996 | dev_err(musb->controller, | |
1997 | "musb_init_controller failed with status %d\n", status); | |
1998 | ||
28c2c51c FB |
1999 | musb_free(musb); |
2000 | ||
34e2beb2 SS |
2001 | fail0: |
2002 | ||
28c2c51c FB |
2003 | return status; |
2004 | ||
550a7375 FB |
2005 | } |
2006 | ||
2007 | /*-------------------------------------------------------------------------*/ | |
2008 | ||
2009 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2010 | * bridge to a platform device; this driver then suffices. | |
2011 | */ | |
41ac7b3a | 2012 | static int musb_probe(struct platform_device *pdev) |
550a7375 FB |
2013 | { |
2014 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2015 | int irq = platform_get_irq_byname(pdev, "mc"); |
da5108e1 | 2016 | int status; |
550a7375 FB |
2017 | struct resource *iomem; |
2018 | void __iomem *base; | |
2019 | ||
2020 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
541079de | 2021 | if (!iomem || irq <= 0) |
550a7375 FB |
2022 | return -ENODEV; |
2023 | ||
195e9e46 | 2024 | base = ioremap(iomem->start, resource_size(iomem)); |
550a7375 FB |
2025 | if (!base) { |
2026 | dev_err(dev, "ioremap failed\n"); | |
2027 | return -ENOMEM; | |
2028 | } | |
2029 | ||
da5108e1 FB |
2030 | status = musb_init_controller(dev, irq, base); |
2031 | if (status < 0) | |
2032 | iounmap(base); | |
2033 | ||
2034 | return status; | |
550a7375 FB |
2035 | } |
2036 | ||
e9e8c85e | 2037 | static int __devexit musb_remove(struct platform_device *pdev) |
550a7375 | 2038 | { |
8d2421e6 AKG |
2039 | struct device *dev = &pdev->dev; |
2040 | struct musb *musb = dev_to_musb(dev); | |
550a7375 FB |
2041 | void __iomem *ctrl_base = musb->ctrl_base; |
2042 | ||
2043 | /* this gets called on rmmod. | |
2044 | * - Host mode: host may still be active | |
2045 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2046 | * - OTG mode: both roles are deactivated (or never-activated) | |
2047 | */ | |
7f7f9e2a | 2048 | musb_exit_debugfs(musb); |
550a7375 | 2049 | musb_shutdown(pdev); |
461972d8 | 2050 | |
550a7375 FB |
2051 | musb_free(musb); |
2052 | iounmap(ctrl_base); | |
8d2421e6 | 2053 | device_init_wakeup(dev, 0); |
550a7375 | 2054 | #ifndef CONFIG_MUSB_PIO_ONLY |
8d2421e6 | 2055 | dma_set_mask(dev, *dev->parent->dma_mask); |
550a7375 FB |
2056 | #endif |
2057 | return 0; | |
2058 | } | |
2059 | ||
2060 | #ifdef CONFIG_PM | |
2061 | ||
3c8a5fcc | 2062 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2063 | { |
2064 | int i; | |
2065 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2066 | void __iomem *epio; |
4f712e01 | 2067 | |
032ec49f FB |
2068 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2069 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2070 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
7421107b | 2071 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
7421107b FB |
2072 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); |
2073 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2074 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2075 | |
ae9b2ad2 | 2076 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2077 | struct musb_hw_ep *hw_ep; |
2078 | ||
2079 | hw_ep = &musb->endpoints[i]; | |
2080 | if (!hw_ep) | |
2081 | continue; | |
2082 | ||
2083 | epio = hw_ep->regs; | |
2084 | if (!epio) | |
2085 | continue; | |
2086 | ||
ea737554 | 2087 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2088 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2089 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2090 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2091 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2092 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2093 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2094 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2095 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2096 | |
2097 | if (musb->dyn_fifo) { | |
7421107b | 2098 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2099 | musb_read_txfifoadd(musb_base); |
7421107b | 2100 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2101 | musb_read_rxfifoadd(musb_base); |
7421107b | 2102 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2103 | musb_read_txfifosz(musb_base); |
7421107b | 2104 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2105 | musb_read_rxfifosz(musb_base); |
2106 | } | |
032ec49f FB |
2107 | |
2108 | musb->context.index_regs[i].txtype = | |
2109 | musb_readb(epio, MUSB_TXTYPE); | |
2110 | musb->context.index_regs[i].txinterval = | |
2111 | musb_readb(epio, MUSB_TXINTERVAL); | |
2112 | musb->context.index_regs[i].rxtype = | |
2113 | musb_readb(epio, MUSB_RXTYPE); | |
2114 | musb->context.index_regs[i].rxinterval = | |
2115 | musb_readb(epio, MUSB_RXINTERVAL); | |
2116 | ||
2117 | musb->context.index_regs[i].txfunaddr = | |
2118 | musb_read_txfunaddr(musb_base, i); | |
2119 | musb->context.index_regs[i].txhubaddr = | |
2120 | musb_read_txhubaddr(musb_base, i); | |
2121 | musb->context.index_regs[i].txhubport = | |
2122 | musb_read_txhubport(musb_base, i); | |
2123 | ||
2124 | musb->context.index_regs[i].rxfunaddr = | |
2125 | musb_read_rxfunaddr(musb_base, i); | |
2126 | musb->context.index_regs[i].rxhubaddr = | |
2127 | musb_read_rxhubaddr(musb_base, i); | |
2128 | musb->context.index_regs[i].rxhubport = | |
2129 | musb_read_rxhubport(musb_base, i); | |
4f712e01 | 2130 | } |
4f712e01 AKG |
2131 | } |
2132 | ||
3c8a5fcc | 2133 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2134 | { |
2135 | int i; | |
2136 | void __iomem *musb_base = musb->mregs; | |
2137 | void __iomem *ep_target_regs; | |
ae9b2ad2 | 2138 | void __iomem *epio; |
4f712e01 | 2139 | |
032ec49f FB |
2140 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2141 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2142 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
7421107b | 2143 | musb_writeb(musb_base, MUSB_POWER, musb->context.power); |
b18d26f6 | 2144 | musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); |
af5ec14d | 2145 | musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); |
7421107b FB |
2146 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); |
2147 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2148 | |
ae9b2ad2 | 2149 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2150 | struct musb_hw_ep *hw_ep; |
2151 | ||
2152 | hw_ep = &musb->endpoints[i]; | |
2153 | if (!hw_ep) | |
2154 | continue; | |
2155 | ||
2156 | epio = hw_ep->regs; | |
2157 | if (!epio) | |
2158 | continue; | |
2159 | ||
ea737554 | 2160 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2161 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2162 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2163 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2164 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2165 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2166 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2167 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2168 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2169 | |
2170 | if (musb->dyn_fifo) { | |
2171 | musb_write_txfifosz(musb_base, | |
7421107b | 2172 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2173 | musb_write_rxfifosz(musb_base, |
7421107b | 2174 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2175 | musb_write_txfifoadd(musb_base, |
7421107b | 2176 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2177 | musb_write_rxfifoadd(musb_base, |
7421107b | 2178 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2179 | } |
2180 | ||
032ec49f | 2181 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2182 | musb->context.index_regs[i].txtype); |
032ec49f | 2183 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2184 | musb->context.index_regs[i].txinterval); |
032ec49f | 2185 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2186 | musb->context.index_regs[i].rxtype); |
032ec49f | 2187 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2188 | |
032ec49f FB |
2189 | musb->context.index_regs[i].rxinterval); |
2190 | musb_write_txfunaddr(musb_base, i, | |
7421107b | 2191 | musb->context.index_regs[i].txfunaddr); |
032ec49f | 2192 | musb_write_txhubaddr(musb_base, i, |
7421107b | 2193 | musb->context.index_regs[i].txhubaddr); |
032ec49f | 2194 | musb_write_txhubport(musb_base, i, |
7421107b | 2195 | musb->context.index_regs[i].txhubport); |
4f712e01 | 2196 | |
032ec49f FB |
2197 | ep_target_regs = |
2198 | musb_read_target_reg_base(i, musb_base); | |
4f712e01 | 2199 | |
032ec49f | 2200 | musb_write_rxfunaddr(ep_target_regs, |
7421107b | 2201 | musb->context.index_regs[i].rxfunaddr); |
032ec49f | 2202 | musb_write_rxhubaddr(ep_target_regs, |
7421107b | 2203 | musb->context.index_regs[i].rxhubaddr); |
032ec49f | 2204 | musb_write_rxhubport(ep_target_regs, |
7421107b | 2205 | musb->context.index_regs[i].rxhubport); |
4f712e01 | 2206 | } |
3c5fec75 | 2207 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2208 | } |
2209 | ||
48fea965 | 2210 | static int musb_suspend(struct device *dev) |
550a7375 | 2211 | { |
8220796d | 2212 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2213 | unsigned long flags; |
550a7375 | 2214 | |
550a7375 FB |
2215 | spin_lock_irqsave(&musb->lock, flags); |
2216 | ||
2217 | if (is_peripheral_active(musb)) { | |
2218 | /* FIXME force disconnect unless we know USB will wake | |
2219 | * the system up quickly enough to respond ... | |
2220 | */ | |
2221 | } else if (is_host_active(musb)) { | |
2222 | /* we know all the children are suspended; sometimes | |
2223 | * they will even be wakeup-enabled. | |
2224 | */ | |
2225 | } | |
2226 | ||
550a7375 FB |
2227 | spin_unlock_irqrestore(&musb->lock, flags); |
2228 | return 0; | |
2229 | } | |
2230 | ||
48fea965 | 2231 | static int musb_resume_noirq(struct device *dev) |
550a7375 | 2232 | { |
550a7375 | 2233 | /* for static cmos like DaVinci, register values were preserved |
0ec8fd70 KK |
2234 | * unless for some reason the whole soc powered down or the USB |
2235 | * module got reset through the PSC (vs just being disabled). | |
550a7375 | 2236 | */ |
550a7375 FB |
2237 | return 0; |
2238 | } | |
2239 | ||
7acc6197 HH |
2240 | static int musb_runtime_suspend(struct device *dev) |
2241 | { | |
2242 | struct musb *musb = dev_to_musb(dev); | |
2243 | ||
2244 | musb_save_context(musb); | |
2245 | ||
2246 | return 0; | |
2247 | } | |
2248 | ||
2249 | static int musb_runtime_resume(struct device *dev) | |
2250 | { | |
2251 | struct musb *musb = dev_to_musb(dev); | |
2252 | static int first = 1; | |
2253 | ||
2254 | /* | |
2255 | * When pm_runtime_get_sync called for the first time in driver | |
2256 | * init, some of the structure is still not initialized which is | |
2257 | * used in restore function. But clock needs to be | |
2258 | * enabled before any register access, so | |
2259 | * pm_runtime_get_sync has to be called. | |
2260 | * Also context restore without save does not make | |
2261 | * any sense | |
2262 | */ | |
2263 | if (!first) | |
2264 | musb_restore_context(musb); | |
2265 | first = 0; | |
2266 | ||
2267 | return 0; | |
2268 | } | |
2269 | ||
47145210 | 2270 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 MD |
2271 | .suspend = musb_suspend, |
2272 | .resume_noirq = musb_resume_noirq, | |
7acc6197 HH |
2273 | .runtime_suspend = musb_runtime_suspend, |
2274 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2275 | }; |
2276 | ||
2277 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2278 | #else |
48fea965 | 2279 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2280 | #endif |
2281 | ||
2282 | static struct platform_driver musb_driver = { | |
2283 | .driver = { | |
2284 | .name = (char *)musb_driver_name, | |
2285 | .bus = &platform_bus_type, | |
2286 | .owner = THIS_MODULE, | |
48fea965 | 2287 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2288 | }, |
e9e8c85e | 2289 | .probe = musb_probe, |
7690417d | 2290 | .remove = musb_remove, |
550a7375 | 2291 | .shutdown = musb_shutdown, |
550a7375 FB |
2292 | }; |
2293 | ||
2294 | /*-------------------------------------------------------------------------*/ | |
2295 | ||
2296 | static int __init musb_init(void) | |
2297 | { | |
550a7375 FB |
2298 | if (usb_disabled()) |
2299 | return 0; | |
550a7375 FB |
2300 | |
2301 | pr_info("%s: version " MUSB_VERSION ", " | |
550a7375 | 2302 | "?dma?" |
550a7375 | 2303 | ", " |
62285963 | 2304 | "otg (peripheral+host)", |
5c8a86e1 | 2305 | musb_driver_name); |
e9e8c85e | 2306 | return platform_driver_register(&musb_driver); |
550a7375 | 2307 | } |
e9e8c85e | 2308 | module_init(musb_init); |
550a7375 FB |
2309 | |
2310 | static void __exit musb_cleanup(void) | |
2311 | { | |
2312 | platform_driver_unregister(&musb_driver); | |
2313 | } | |
2314 | module_exit(musb_cleanup); |