Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 FB |
85 | * - platform_device for addressing, irq, and platform_data |
86 | * - platform_data is mostly for board-specific informarion | |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
9303961f | 99 | #include <linux/prefetch.h> |
550a7375 FB |
100 | #include <linux/platform_device.h> |
101 | #include <linux/io.h> | |
102 | ||
550a7375 FB |
103 | #include "musb_core.h" |
104 | ||
f7f9d63e | 105 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
106 | |
107 | ||
550a7375 FB |
108 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
109 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
110 | ||
e8164f64 | 111 | #define MUSB_VERSION "6.0" |
550a7375 FB |
112 | |
113 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
114 | ||
05ac10dd | 115 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
116 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
117 | ||
118 | MODULE_DESCRIPTION(DRIVER_INFO); | |
119 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
120 | MODULE_LICENSE("GPL"); | |
121 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
122 | ||
123 | ||
124 | /*-------------------------------------------------------------------------*/ | |
125 | ||
126 | static inline struct musb *dev_to_musb(struct device *dev) | |
127 | { | |
550a7375 | 128 | return dev_get_drvdata(dev); |
550a7375 FB |
129 | } |
130 | ||
131 | /*-------------------------------------------------------------------------*/ | |
132 | ||
ffb865b1 | 133 | #ifndef CONFIG_BLACKFIN |
b96d3b08 | 134 | static int musb_ulpi_read(struct usb_phy *phy, u32 offset) |
ffb865b1 | 135 | { |
b96d3b08 | 136 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
137 | int i = 0; |
138 | u8 r; | |
139 | u8 power; | |
bf070bc1 GI |
140 | int ret; |
141 | ||
142 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
143 | |
144 | /* Make sure the transceiver is not in low power mode */ | |
145 | power = musb_readb(addr, MUSB_POWER); | |
146 | power &= ~MUSB_POWER_SUSPENDM; | |
147 | musb_writeb(addr, MUSB_POWER, power); | |
148 | ||
149 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
150 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
151 | */ | |
152 | ||
153 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
154 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
155 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
156 | ||
157 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
158 | & MUSB_ULPI_REG_CMPLT)) { | |
159 | i++; | |
bf070bc1 GI |
160 | if (i == 10000) { |
161 | ret = -ETIMEDOUT; | |
162 | goto out; | |
163 | } | |
ffb865b1 HK |
164 | |
165 | } | |
166 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
167 | r &= ~MUSB_ULPI_REG_CMPLT; | |
168 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
169 | ||
bf070bc1 GI |
170 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
171 | ||
172 | out: | |
173 | pm_runtime_put(phy->io_dev); | |
174 | ||
175 | return ret; | |
ffb865b1 HK |
176 | } |
177 | ||
b96d3b08 | 178 | static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) |
ffb865b1 | 179 | { |
b96d3b08 | 180 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
181 | int i = 0; |
182 | u8 r = 0; | |
183 | u8 power; | |
bf070bc1 GI |
184 | int ret = 0; |
185 | ||
186 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
187 | |
188 | /* Make sure the transceiver is not in low power mode */ | |
189 | power = musb_readb(addr, MUSB_POWER); | |
190 | power &= ~MUSB_POWER_SUSPENDM; | |
191 | musb_writeb(addr, MUSB_POWER, power); | |
192 | ||
193 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
194 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
195 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
196 | ||
197 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
198 | & MUSB_ULPI_REG_CMPLT)) { | |
199 | i++; | |
bf070bc1 GI |
200 | if (i == 10000) { |
201 | ret = -ETIMEDOUT; | |
202 | goto out; | |
203 | } | |
ffb865b1 HK |
204 | } |
205 | ||
206 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
207 | r &= ~MUSB_ULPI_REG_CMPLT; | |
208 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
209 | ||
bf070bc1 GI |
210 | out: |
211 | pm_runtime_put(phy->io_dev); | |
212 | ||
213 | return ret; | |
ffb865b1 HK |
214 | } |
215 | #else | |
f2263db7 MF |
216 | #define musb_ulpi_read NULL |
217 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
218 | #endif |
219 | ||
b96d3b08 | 220 | static struct usb_phy_io_ops musb_ulpi_access = { |
ffb865b1 HK |
221 | .read = musb_ulpi_read, |
222 | .write = musb_ulpi_write, | |
223 | }; | |
224 | ||
225 | /*-------------------------------------------------------------------------*/ | |
226 | ||
7c925546 | 227 | #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) |
c6cf8b00 | 228 | |
550a7375 FB |
229 | /* |
230 | * Load an endpoint's FIFO | |
231 | */ | |
232 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
233 | { | |
5c8a86e1 | 234 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
235 | void __iomem *fifo = hw_ep->fifo; |
236 | ||
603fe2b2 AKG |
237 | if (unlikely(len == 0)) |
238 | return; | |
239 | ||
550a7375 FB |
240 | prefetch((u8 *)src); |
241 | ||
5c8a86e1 | 242 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
243 | 'T', hw_ep->epnum, fifo, len, src); |
244 | ||
245 | /* we can't assume unaligned reads work */ | |
246 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
247 | u16 index = 0; | |
248 | ||
249 | /* best case is 32bit-aligned source address */ | |
250 | if ((0x02 & (unsigned long) src) == 0) { | |
251 | if (len >= 4) { | |
252 | writesl(fifo, src + index, len >> 2); | |
253 | index += len & ~0x03; | |
254 | } | |
255 | if (len & 0x02) { | |
256 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
257 | index += 2; | |
258 | } | |
259 | } else { | |
260 | if (len >= 2) { | |
261 | writesw(fifo, src + index, len >> 1); | |
262 | index += len & ~0x01; | |
263 | } | |
264 | } | |
265 | if (len & 0x01) | |
266 | musb_writeb(fifo, 0, src[index]); | |
267 | } else { | |
268 | /* byte aligned */ | |
269 | writesb(fifo, src, len); | |
270 | } | |
271 | } | |
272 | ||
843bb1d0 | 273 | #if !defined(CONFIG_USB_MUSB_AM35X) |
550a7375 FB |
274 | /* |
275 | * Unload an endpoint's FIFO | |
276 | */ | |
277 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
278 | { | |
5c8a86e1 | 279 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
280 | void __iomem *fifo = hw_ep->fifo; |
281 | ||
603fe2b2 AKG |
282 | if (unlikely(len == 0)) |
283 | return; | |
284 | ||
5c8a86e1 | 285 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
286 | 'R', hw_ep->epnum, fifo, len, dst); |
287 | ||
288 | /* we can't assume unaligned writes work */ | |
289 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
290 | u16 index = 0; | |
291 | ||
292 | /* best case is 32bit-aligned destination address */ | |
293 | if ((0x02 & (unsigned long) dst) == 0) { | |
294 | if (len >= 4) { | |
295 | readsl(fifo, dst, len >> 2); | |
296 | index = len & ~0x03; | |
297 | } | |
298 | if (len & 0x02) { | |
299 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
300 | index += 2; | |
301 | } | |
302 | } else { | |
303 | if (len >= 2) { | |
304 | readsw(fifo, dst, len >> 1); | |
305 | index = len & ~0x01; | |
306 | } | |
307 | } | |
308 | if (len & 0x01) | |
309 | dst[index] = musb_readb(fifo, 0); | |
310 | } else { | |
311 | /* byte aligned */ | |
312 | readsb(fifo, dst, len); | |
313 | } | |
314 | } | |
843bb1d0 | 315 | #endif |
550a7375 FB |
316 | |
317 | #endif /* normal PIO */ | |
318 | ||
319 | ||
320 | /*-------------------------------------------------------------------------*/ | |
321 | ||
322 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
323 | static const u8 musb_test_packet[53] = { | |
324 | /* implicit SYNC then DATA0 to start */ | |
325 | ||
326 | /* JKJKJKJK x9 */ | |
327 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
328 | /* JJKKJJKK x8 */ | |
329 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
330 | /* JJJJKKKK x8 */ | |
331 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
332 | /* JJJJJJJKKKKKKK x8 */ | |
333 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
334 | /* JJJJJJJK x8 */ | |
335 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
336 | /* JKKKKKKK x10, JK */ | |
337 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
338 | ||
339 | /* implicit CRC16 then EOP to end */ | |
340 | }; | |
341 | ||
342 | void musb_load_testpacket(struct musb *musb) | |
343 | { | |
344 | void __iomem *regs = musb->endpoints[0].regs; | |
345 | ||
346 | musb_ep_select(musb->mregs, 0); | |
347 | musb_write_fifo(musb->control_ep, | |
348 | sizeof(musb_test_packet), musb_test_packet); | |
349 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
350 | } | |
351 | ||
352 | /*-------------------------------------------------------------------------*/ | |
353 | ||
550a7375 FB |
354 | /* |
355 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
356 | */ | |
a156544b | 357 | static void musb_otg_timer_func(unsigned long data) |
550a7375 FB |
358 | { |
359 | struct musb *musb = (struct musb *)data; | |
360 | unsigned long flags; | |
361 | ||
362 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 363 | switch (musb->xceiv->state) { |
550a7375 | 364 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 365 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 366 | musb_g_disconnect(musb); |
84e250ff | 367 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
368 | musb->is_active = 0; |
369 | break; | |
ab983f2a | 370 | case OTG_STATE_A_SUSPEND: |
550a7375 | 371 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 372 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
3df00453 | 373 | otg_state_string(musb->xceiv->state)); |
743411b3 | 374 | musb_platform_set_vbus(musb, 0); |
ab983f2a | 375 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
376 | break; |
377 | default: | |
5c8a86e1 | 378 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
3df00453 | 379 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
380 | } |
381 | musb->ignore_disconnect = 0; | |
382 | spin_unlock_irqrestore(&musb->lock, flags); | |
383 | } | |
384 | ||
550a7375 | 385 | /* |
f7f9d63e | 386 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
387 | */ |
388 | void musb_hnp_stop(struct musb *musb) | |
389 | { | |
390 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
391 | void __iomem *mbase = musb->mregs; | |
392 | u8 reg; | |
393 | ||
5c8a86e1 | 394 | dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); |
ab983f2a | 395 | |
84e250ff | 396 | switch (musb->xceiv->state) { |
550a7375 | 397 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 398 | musb_g_disconnect(musb); |
5c8a86e1 | 399 | dev_dbg(musb->controller, "HNP: back to %s\n", |
3df00453 | 400 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
401 | break; |
402 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 403 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
550a7375 | 404 | hcd->self.is_b_host = 0; |
84e250ff | 405 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
406 | MUSB_DEV_MODE(musb); |
407 | reg = musb_readb(mbase, MUSB_POWER); | |
408 | reg |= MUSB_POWER_SUSPENDM; | |
409 | musb_writeb(mbase, MUSB_POWER, reg); | |
410 | /* REVISIT: Start SESSION_REQUEST here? */ | |
411 | break; | |
412 | default: | |
5c8a86e1 | 413 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
3df00453 | 414 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
415 | } |
416 | ||
417 | /* | |
418 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
419 | * which cause occasional OPT A "Did not receive reset after connect" | |
420 | * errors. | |
421 | */ | |
749da5f8 | 422 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
423 | } |
424 | ||
550a7375 FB |
425 | /* |
426 | * Interrupt Service Routine to record USB "global" interrupts. | |
427 | * Since these do not happen often and signify things of | |
428 | * paramount importance, it seems OK to check them individually; | |
429 | * the order of the tests is specified in the manual | |
430 | * | |
431 | * @param musb instance pointer | |
432 | * @param int_usb register contents | |
433 | * @param devctl | |
434 | * @param power | |
435 | */ | |
436 | ||
550a7375 FB |
437 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
438 | u8 devctl, u8 power) | |
439 | { | |
d445b6da | 440 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 441 | irqreturn_t handled = IRQ_NONE; |
550a7375 | 442 | |
5c8a86e1 | 443 | dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, |
550a7375 FB |
444 | int_usb); |
445 | ||
446 | /* in host mode, the peripheral may issue remote wakeup. | |
447 | * in peripheral mode, the host may resume the link. | |
448 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
449 | */ | |
450 | if (int_usb & MUSB_INTR_RESUME) { | |
451 | handled = IRQ_HANDLED; | |
5c8a86e1 | 452 | dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
453 | |
454 | if (devctl & MUSB_DEVCTL_HM) { | |
aa471456 FB |
455 | void __iomem *mbase = musb->mregs; |
456 | ||
84e250ff | 457 | switch (musb->xceiv->state) { |
550a7375 FB |
458 | case OTG_STATE_A_SUSPEND: |
459 | /* remote wakeup? later, GetPortStatus | |
460 | * will stop RESUME signaling | |
461 | */ | |
462 | ||
463 | if (power & MUSB_POWER_SUSPENDM) { | |
464 | /* spurious */ | |
465 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
5c8a86e1 | 466 | dev_dbg(musb->controller, "Spurious SUSPENDM\n"); |
550a7375 FB |
467 | break; |
468 | } | |
469 | ||
470 | power &= ~MUSB_POWER_SUSPENDM; | |
471 | musb_writeb(mbase, MUSB_POWER, | |
472 | power | MUSB_POWER_RESUME); | |
473 | ||
474 | musb->port1_status |= | |
475 | (USB_PORT_STAT_C_SUSPEND << 16) | |
476 | | MUSB_PORT_STAT_RESUME; | |
477 | musb->rh_timer = jiffies | |
478 | + msecs_to_jiffies(20); | |
479 | ||
84e250ff | 480 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
481 | musb->is_active = 1; |
482 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
483 | break; | |
484 | case OTG_STATE_B_WAIT_ACON: | |
84e250ff | 485 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
486 | musb->is_active = 1; |
487 | MUSB_DEV_MODE(musb); | |
488 | break; | |
489 | default: | |
490 | WARNING("bogus %s RESUME (%s)\n", | |
491 | "host", | |
3df00453 | 492 | otg_state_string(musb->xceiv->state)); |
550a7375 | 493 | } |
550a7375 | 494 | } else { |
84e250ff | 495 | switch (musb->xceiv->state) { |
550a7375 FB |
496 | case OTG_STATE_A_SUSPEND: |
497 | /* possibly DISCONNECT is upcoming */ | |
84e250ff | 498 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
499 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); |
500 | break; | |
550a7375 FB |
501 | case OTG_STATE_B_WAIT_ACON: |
502 | case OTG_STATE_B_PERIPHERAL: | |
503 | /* disconnect while suspended? we may | |
504 | * not get a disconnect irq... | |
505 | */ | |
506 | if ((devctl & MUSB_DEVCTL_VBUS) | |
507 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
508 | ) { | |
509 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
510 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
511 | break; | |
512 | } | |
513 | musb_g_resume(musb); | |
514 | break; | |
515 | case OTG_STATE_B_IDLE: | |
516 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
517 | break; | |
550a7375 FB |
518 | default: |
519 | WARNING("bogus %s RESUME (%s)\n", | |
520 | "peripheral", | |
3df00453 | 521 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
522 | } |
523 | } | |
524 | } | |
525 | ||
550a7375 FB |
526 | /* see manual for the order of the tests */ |
527 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
528 | void __iomem *mbase = musb->mregs; |
529 | ||
19aab56c HK |
530 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
531 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 532 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
533 | return IRQ_HANDLED; |
534 | } | |
535 | ||
5c8a86e1 | 536 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
3df00453 | 537 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
538 | |
539 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
540 | * is removed) SRP. responses are time critical: | |
541 | * - turn on VBUS (with silicon-specific mechanism) | |
542 | * - go through A_WAIT_VRISE | |
543 | * - ... to A_WAIT_BCON. | |
544 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
545 | */ | |
546 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
547 | musb->ep0_stage = MUSB_EP0_START; | |
84e250ff | 548 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 549 | MUSB_HST_MODE(musb); |
743411b3 | 550 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
551 | |
552 | handled = IRQ_HANDLED; | |
553 | } | |
554 | ||
555 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
556 | int ignore = 0; | |
557 | ||
558 | /* During connection as an A-Device, we may see a short | |
559 | * current spikes causing voltage drop, because of cable | |
560 | * and peripheral capacitance combined with vbus draw. | |
561 | * (So: less common with truly self-powered devices, where | |
562 | * vbus doesn't act like a power supply.) | |
563 | * | |
564 | * Such spikes are short; usually less than ~500 usec, max | |
565 | * of ~2 msec. That is, they're not sustained overcurrent | |
566 | * errors, though they're reported using VBUSERROR irqs. | |
567 | * | |
568 | * Workarounds: (a) hardware: use self powered devices. | |
569 | * (b) software: ignore non-repeated VBUS errors. | |
570 | * | |
571 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
572 | * make trouble here, keeping VBUS < 4.4V ? | |
573 | */ | |
84e250ff | 574 | switch (musb->xceiv->state) { |
550a7375 FB |
575 | case OTG_STATE_A_HOST: |
576 | /* recovery is dicey once we've gotten past the | |
577 | * initial stages of enumeration, but if VBUS | |
578 | * stayed ok at the other end of the link, and | |
579 | * another reset is due (at least for high speed, | |
580 | * to redo the chirp etc), it might work OK... | |
581 | */ | |
582 | case OTG_STATE_A_WAIT_BCON: | |
583 | case OTG_STATE_A_WAIT_VRISE: | |
584 | if (musb->vbuserr_retry) { | |
aa471456 FB |
585 | void __iomem *mbase = musb->mregs; |
586 | ||
550a7375 FB |
587 | musb->vbuserr_retry--; |
588 | ignore = 1; | |
589 | devctl |= MUSB_DEVCTL_SESSION; | |
590 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
591 | } else { | |
592 | musb->port1_status |= | |
749da5f8 AS |
593 | USB_PORT_STAT_OVERCURRENT |
594 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
595 | } |
596 | break; | |
597 | default: | |
598 | break; | |
599 | } | |
600 | ||
5c8a86e1 | 601 | dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", |
3df00453 | 602 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
603 | devctl, |
604 | ({ char *s; | |
605 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
606 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
607 | s = "<SessEnd"; break; | |
608 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
609 | s = "<AValid"; break; | |
610 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
611 | s = "<VBusValid"; break; | |
612 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
613 | default: | |
614 | s = "VALID"; break; | |
615 | }; s; }), | |
616 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
617 | musb->port1_status); | |
618 | ||
619 | /* go through A_WAIT_VFALL then start a new session */ | |
620 | if (!ignore) | |
743411b3 | 621 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
622 | handled = IRQ_HANDLED; |
623 | } | |
624 | ||
1c25fda4 | 625 | if (int_usb & MUSB_INTR_SUSPEND) { |
5c8a86e1 | 626 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", |
3df00453 | 627 | otg_state_string(musb->xceiv->state), devctl, power); |
1c25fda4 AM |
628 | handled = IRQ_HANDLED; |
629 | ||
630 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
631 | case OTG_STATE_A_PERIPHERAL: |
632 | /* We also come here if the cable is removed, since | |
633 | * this silicon doesn't report ID-no-longer-grounded. | |
634 | * | |
635 | * We depend on T(a_wait_bcon) to shut us down, and | |
636 | * hope users don't do anything dicey during this | |
637 | * undesired detour through A_WAIT_BCON. | |
638 | */ | |
639 | musb_hnp_stop(musb); | |
640 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
641 | musb_root_disconnect(musb); | |
642 | musb_platform_try_idle(musb, jiffies | |
643 | + msecs_to_jiffies(musb->a_wait_bcon | |
644 | ? : OTG_TIME_A_WAIT_BCON)); | |
645 | ||
646 | break; | |
1c25fda4 AM |
647 | case OTG_STATE_B_IDLE: |
648 | if (!musb->is_active) | |
649 | break; | |
650 | case OTG_STATE_B_PERIPHERAL: | |
651 | musb_g_suspend(musb); | |
652 | musb->is_active = is_otg_enabled(musb) | |
d445b6da | 653 | && otg->gadget->b_hnp_enable; |
1c25fda4 | 654 | if (musb->is_active) { |
1c25fda4 | 655 | musb->xceiv->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 656 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
657 | mod_timer(&musb->otg_timer, jiffies |
658 | + msecs_to_jiffies( | |
659 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
660 | } |
661 | break; | |
662 | case OTG_STATE_A_WAIT_BCON: | |
663 | if (musb->a_wait_bcon != 0) | |
664 | musb_platform_try_idle(musb, jiffies | |
665 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
666 | break; | |
667 | case OTG_STATE_A_HOST: | |
668 | musb->xceiv->state = OTG_STATE_A_SUSPEND; | |
669 | musb->is_active = is_otg_enabled(musb) | |
d445b6da | 670 | && otg->host->b_hnp_enable; |
1c25fda4 AM |
671 | break; |
672 | case OTG_STATE_B_HOST: | |
673 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 674 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
675 | break; |
676 | default: | |
677 | /* "should not happen" */ | |
678 | musb->is_active = 0; | |
679 | break; | |
680 | } | |
681 | } | |
682 | ||
550a7375 FB |
683 | if (int_usb & MUSB_INTR_CONNECT) { |
684 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
685 | ||
686 | handled = IRQ_HANDLED; | |
687 | musb->is_active = 1; | |
550a7375 FB |
688 | |
689 | musb->ep0_stage = MUSB_EP0_START; | |
690 | ||
550a7375 FB |
691 | /* flush endpoints when transitioning from Device Mode */ |
692 | if (is_peripheral_active(musb)) { | |
693 | /* REVISIT HNP; just force disconnect */ | |
694 | } | |
d709d22e AKG |
695 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); |
696 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
697 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); | |
550a7375 FB |
698 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
699 | |USB_PORT_STAT_HIGH_SPEED | |
700 | |USB_PORT_STAT_ENABLE | |
701 | ); | |
702 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
703 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
704 | ||
705 | /* high vs full speed is just a guess until after reset */ | |
706 | if (devctl & MUSB_DEVCTL_LSDEV) | |
707 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
708 | ||
550a7375 | 709 | /* indicate new connection to OTG machine */ |
84e250ff | 710 | switch (musb->xceiv->state) { |
550a7375 FB |
711 | case OTG_STATE_B_PERIPHERAL: |
712 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 713 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 714 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 715 | goto b_host; |
550a7375 | 716 | } else |
5c8a86e1 | 717 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
718 | break; |
719 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 720 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 721 | b_host: |
84e250ff | 722 | musb->xceiv->state = OTG_STATE_B_HOST; |
550a7375 | 723 | hcd->self.is_b_host = 1; |
1de00dae DB |
724 | musb->ignore_disconnect = 0; |
725 | del_timer(&musb->otg_timer); | |
550a7375 FB |
726 | break; |
727 | default: | |
728 | if ((devctl & MUSB_DEVCTL_VBUS) | |
729 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
84e250ff | 730 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
731 | hcd->self.is_b_host = 0; |
732 | } | |
733 | break; | |
734 | } | |
1de00dae DB |
735 | |
736 | /* poke the root hub */ | |
737 | MUSB_HST_MODE(musb); | |
738 | if (hcd->status_urb) | |
739 | usb_hcd_poll_rh_status(hcd); | |
740 | else | |
741 | usb_hcd_resume_root_hub(hcd); | |
742 | ||
5c8a86e1 | 743 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
3df00453 | 744 | otg_state_string(musb->xceiv->state), devctl); |
550a7375 | 745 | } |
550a7375 | 746 | |
1c25fda4 | 747 | if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { |
5c8a86e1 | 748 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
3df00453 | 749 | otg_state_string(musb->xceiv->state), |
1c25fda4 AM |
750 | MUSB_MODE(musb), devctl); |
751 | handled = IRQ_HANDLED; | |
752 | ||
753 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
754 | case OTG_STATE_A_HOST: |
755 | case OTG_STATE_A_SUSPEND: | |
756 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
757 | musb_root_disconnect(musb); | |
758 | if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) | |
759 | musb_platform_try_idle(musb, jiffies | |
760 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
761 | break; | |
1c25fda4 AM |
762 | case OTG_STATE_B_HOST: |
763 | /* REVISIT this behaves for "real disconnect" | |
764 | * cases; make sure the other transitions from | |
765 | * from B_HOST act right too. The B_HOST code | |
766 | * in hnp_stop() is currently not used... | |
767 | */ | |
768 | musb_root_disconnect(musb); | |
769 | musb_to_hcd(musb)->self.is_b_host = 0; | |
770 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; | |
771 | MUSB_DEV_MODE(musb); | |
772 | musb_g_disconnect(musb); | |
773 | break; | |
774 | case OTG_STATE_A_PERIPHERAL: | |
775 | musb_hnp_stop(musb); | |
776 | musb_root_disconnect(musb); | |
777 | /* FALLTHROUGH */ | |
778 | case OTG_STATE_B_WAIT_ACON: | |
779 | /* FALLTHROUGH */ | |
1c25fda4 AM |
780 | case OTG_STATE_B_PERIPHERAL: |
781 | case OTG_STATE_B_IDLE: | |
782 | musb_g_disconnect(musb); | |
783 | break; | |
1c25fda4 AM |
784 | default: |
785 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
3df00453 | 786 | otg_state_string(musb->xceiv->state)); |
1c25fda4 AM |
787 | break; |
788 | } | |
789 | } | |
790 | ||
550a7375 FB |
791 | /* mentor saves a bit: bus reset and babble share the same irq. |
792 | * only host sees babble; only peripheral sees bus reset. | |
793 | */ | |
794 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 795 | handled = IRQ_HANDLED; |
550a7375 FB |
796 | if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { |
797 | /* | |
798 | * Looks like non-HS BABBLE can be ignored, but | |
799 | * HS BABBLE is an error condition. For HS the solution | |
800 | * is to avoid babble in the first place and fix what | |
801 | * caused BABBLE. When HS BABBLE happens we can only | |
802 | * stop the session. | |
803 | */ | |
804 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
5c8a86e1 | 805 | dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); |
550a7375 FB |
806 | else { |
807 | ERR("Stopping host session -- babble\n"); | |
1c25fda4 | 808 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
550a7375 FB |
809 | } |
810 | } else if (is_peripheral_capable()) { | |
5c8a86e1 | 811 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
3df00453 | 812 | otg_state_string(musb->xceiv->state)); |
84e250ff | 813 | switch (musb->xceiv->state) { |
550a7375 FB |
814 | case OTG_STATE_A_SUSPEND: |
815 | /* We need to ignore disconnect on suspend | |
816 | * otherwise tusb 2.0 won't reconnect after a | |
817 | * power cycle, which breaks otg compliance. | |
818 | */ | |
819 | musb->ignore_disconnect = 1; | |
820 | musb_g_reset(musb); | |
821 | /* FALLTHROUGH */ | |
822 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 823 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 824 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
3df00453 AG |
825 | otg_state_string(musb->xceiv->state), |
826 | TA_WAIT_BCON(musb)); | |
f7f9d63e DB |
827 | mod_timer(&musb->otg_timer, jiffies |
828 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
829 | break; |
830 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
831 | musb->ignore_disconnect = 0; |
832 | del_timer(&musb->otg_timer); | |
833 | musb_g_reset(musb); | |
550a7375 FB |
834 | break; |
835 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 836 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
3df00453 | 837 | otg_state_string(musb->xceiv->state)); |
84e250ff | 838 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
839 | musb_g_reset(musb); |
840 | break; | |
550a7375 | 841 | case OTG_STATE_B_IDLE: |
84e250ff | 842 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
843 | /* FALLTHROUGH */ |
844 | case OTG_STATE_B_PERIPHERAL: | |
845 | musb_g_reset(musb); | |
846 | break; | |
847 | default: | |
5c8a86e1 | 848 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
3df00453 | 849 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
850 | } |
851 | } | |
550a7375 | 852 | } |
550a7375 FB |
853 | |
854 | #if 0 | |
855 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
856 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
857 | * limits of a given frame or microframe. | |
858 | * | |
859 | * It's not needed for peripheral side, which dedicates endpoints; | |
860 | * though it _might_ use SOF irqs for other purposes. | |
861 | * | |
862 | * And it's not currently needed for host side, which also dedicates | |
863 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
864 | * to support ISO transfers yet. | |
865 | */ | |
866 | if (int_usb & MUSB_INTR_SOF) { | |
867 | void __iomem *mbase = musb->mregs; | |
868 | struct musb_hw_ep *ep; | |
869 | u8 epnum; | |
870 | u16 frame; | |
871 | ||
5c8a86e1 | 872 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
873 | handled = IRQ_HANDLED; |
874 | ||
875 | /* start any periodic Tx transfers waiting for current frame */ | |
876 | frame = musb_readw(mbase, MUSB_FRAME); | |
877 | ep = musb->endpoints; | |
878 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
879 | && (musb->epmask >= (1 << epnum)); | |
880 | epnum++, ep++) { | |
881 | /* | |
882 | * FIXME handle framecounter wraps (12 bits) | |
883 | * eliminate duplicated StartUrb logic | |
884 | */ | |
885 | if (ep->dwWaitFrame >= frame) { | |
886 | ep->dwWaitFrame = 0; | |
887 | pr_debug("SOF --> periodic TX%s on %d\n", | |
888 | ep->tx_channel ? " DMA" : "", | |
889 | epnum); | |
890 | if (!ep->tx_channel) | |
891 | musb_h_tx_start(musb, epnum); | |
892 | else | |
893 | cppi_hostdma_start(musb, epnum); | |
894 | } | |
895 | } /* end of for loop */ | |
896 | } | |
897 | #endif | |
898 | ||
1c25fda4 | 899 | schedule_work(&musb->irq_work); |
550a7375 FB |
900 | |
901 | return handled; | |
902 | } | |
903 | ||
904 | /*-------------------------------------------------------------------------*/ | |
905 | ||
906 | /* | |
907 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
908 | */ | |
909 | void musb_start(struct musb *musb) | |
910 | { | |
911 | void __iomem *regs = musb->mregs; | |
912 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
913 | ||
5c8a86e1 | 914 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); |
550a7375 FB |
915 | |
916 | /* Set INT enable registers, enable interrupts */ | |
917 | musb_writew(regs, MUSB_INTRTXE, musb->epmask); | |
918 | musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
919 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
920 | ||
921 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
922 | ||
923 | /* put into basic highspeed mode and start session */ | |
924 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
550a7375 FB |
925 | | MUSB_POWER_HSENAB |
926 | /* ENSUSPEND wedges tusb */ | |
927 | /* | MUSB_POWER_ENSUSPEND */ | |
928 | ); | |
929 | ||
930 | musb->is_active = 0; | |
931 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
932 | devctl &= ~MUSB_DEVCTL_SESSION; | |
933 | ||
934 | if (is_otg_enabled(musb)) { | |
935 | /* session started after: | |
936 | * (a) ID-grounded irq, host mode; | |
937 | * (b) vbus present/connect IRQ, peripheral mode; | |
938 | * (c) peripheral initiates, using SRP | |
939 | */ | |
940 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
941 | musb->is_active = 1; | |
942 | else | |
943 | devctl |= MUSB_DEVCTL_SESSION; | |
944 | ||
945 | } else if (is_host_enabled(musb)) { | |
946 | /* assume ID pin is hard-wired to ground */ | |
947 | devctl |= MUSB_DEVCTL_SESSION; | |
948 | ||
949 | } else /* peripheral is enabled */ { | |
950 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
951 | musb->is_active = 1; | |
952 | } | |
953 | musb_platform_enable(musb); | |
954 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
955 | } | |
956 | ||
957 | ||
958 | static void musb_generic_disable(struct musb *musb) | |
959 | { | |
960 | void __iomem *mbase = musb->mregs; | |
961 | u16 temp; | |
962 | ||
963 | /* disable interrupts */ | |
964 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
965 | musb_writew(mbase, MUSB_INTRTXE, 0); | |
966 | musb_writew(mbase, MUSB_INTRRXE, 0); | |
967 | ||
968 | /* off */ | |
969 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
970 | ||
971 | /* flush pending interrupts */ | |
972 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
973 | temp = musb_readw(mbase, MUSB_INTRTX); | |
974 | temp = musb_readw(mbase, MUSB_INTRRX); | |
975 | ||
976 | } | |
977 | ||
978 | /* | |
979 | * Make the HDRC stop (disable interrupts, etc.); | |
980 | * reversible by musb_start | |
981 | * called on gadget driver unregister | |
982 | * with controller locked, irqs blocked | |
983 | * acts as a NOP unless some role activated the hardware | |
984 | */ | |
985 | void musb_stop(struct musb *musb) | |
986 | { | |
987 | /* stop IRQs, timers, ... */ | |
988 | musb_platform_disable(musb); | |
989 | musb_generic_disable(musb); | |
5c8a86e1 | 990 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
991 | |
992 | /* FIXME | |
993 | * - mark host and/or peripheral drivers unusable/inactive | |
994 | * - disable DMA (and enable it in HdrcStart) | |
995 | * - make sure we can musb_start() after musb_stop(); with | |
996 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
997 | * - ... | |
998 | */ | |
999 | musb_platform_try_idle(musb, 0); | |
1000 | } | |
1001 | ||
1002 | static void musb_shutdown(struct platform_device *pdev) | |
1003 | { | |
1004 | struct musb *musb = dev_to_musb(&pdev->dev); | |
1005 | unsigned long flags; | |
1006 | ||
4f9edd2d | 1007 | pm_runtime_get_sync(musb->controller); |
24307cae GI |
1008 | |
1009 | musb_gadget_cleanup(musb); | |
1010 | ||
550a7375 FB |
1011 | spin_lock_irqsave(&musb->lock, flags); |
1012 | musb_platform_disable(musb); | |
1013 | musb_generic_disable(musb); | |
550a7375 FB |
1014 | spin_unlock_irqrestore(&musb->lock, flags); |
1015 | ||
120d074c GI |
1016 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) |
1017 | usb_remove_hcd(musb_to_hcd(musb)); | |
1018 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
1019 | musb_platform_exit(musb); | |
120d074c | 1020 | |
4f9edd2d | 1021 | pm_runtime_put(musb->controller); |
550a7375 FB |
1022 | /* FIXME power down */ |
1023 | } | |
1024 | ||
1025 | ||
1026 | /*-------------------------------------------------------------------------*/ | |
1027 | ||
1028 | /* | |
1029 | * The silicon either has hard-wired endpoint configurations, or else | |
1030 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1031 | * writing only the dynamic sizing is very well tested. Since we switched |
1032 | * away from compile-time hardware parameters, we can no longer rely on | |
1033 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1034 | * |
1035 | * We don't currently use dynamic fifo setup capability to do anything | |
1036 | * more than selecting one of a bunch of predefined configurations. | |
1037 | */ | |
ee34e51a FB |
1038 | #if defined(CONFIG_USB_MUSB_TUSB6010) \ |
1039 | || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ | |
1040 | || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ | |
1041 | || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ | |
1042 | || defined(CONFIG_USB_MUSB_AM35X) \ | |
9ecb8875 AKG |
1043 | || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ |
1044 | || defined(CONFIG_USB_MUSB_DSPS) \ | |
1045 | || defined(CONFIG_USB_MUSB_DSPS_MODULE) | |
e9e8c85e | 1046 | static ushort __devinitdata fifo_mode = 4; |
ee34e51a FB |
1047 | #elif defined(CONFIG_USB_MUSB_UX500) \ |
1048 | || defined(CONFIG_USB_MUSB_UX500_MODULE) | |
e9e8c85e | 1049 | static ushort __devinitdata fifo_mode = 5; |
550a7375 | 1050 | #else |
e9e8c85e | 1051 | static ushort __devinitdata fifo_mode = 2; |
550a7375 FB |
1052 | #endif |
1053 | ||
1054 | /* "modprobe ... fifo_mode=1" etc */ | |
1055 | module_param(fifo_mode, ushort, 0); | |
1056 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1057 | ||
550a7375 FB |
1058 | /* |
1059 | * tables defining fifo_mode values. define more if you like. | |
1060 | * for host side, make sure both halves of ep1 are set up. | |
1061 | */ | |
1062 | ||
1063 | /* mode 0 - fits in 2KB */ | |
e9e8c85e | 1064 | static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { |
550a7375 FB |
1065 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1066 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1067 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1068 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1069 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1070 | }; | |
1071 | ||
1072 | /* mode 1 - fits in 4KB */ | |
e9e8c85e | 1073 | static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { |
550a7375 FB |
1074 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1075 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1076 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1077 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1078 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1079 | }; | |
1080 | ||
1081 | /* mode 2 - fits in 4KB */ | |
e9e8c85e | 1082 | static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { |
550a7375 FB |
1083 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1084 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1085 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1086 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1087 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1088 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1089 | }; | |
1090 | ||
1091 | /* mode 3 - fits in 4KB */ | |
e9e8c85e | 1092 | static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { |
550a7375 FB |
1093 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1094 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1095 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1096 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1097 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1098 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1099 | }; | |
1100 | ||
1101 | /* mode 4 - fits in 16KB */ | |
e9e8c85e | 1102 | static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { |
550a7375 FB |
1103 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1104 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1105 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1106 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1107 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1108 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1109 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1110 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1111 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1112 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1113 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1114 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1115 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1116 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1117 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1118 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1119 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1120 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1121 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1122 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1123 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1124 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1125 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1126 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1127 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1128 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1129 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1130 | }; | |
1131 | ||
3b151526 | 1132 | /* mode 5 - fits in 8KB */ |
e9e8c85e | 1133 | static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { |
3b151526 AKG |
1134 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1135 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1136 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1137 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1138 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1139 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1140 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1141 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1142 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1143 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1144 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1145 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1146 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1147 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1148 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1149 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1150 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1151 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1152 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1153 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1154 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1155 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1156 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1157 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1158 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1159 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1160 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1161 | }; | |
550a7375 FB |
1162 | |
1163 | /* | |
1164 | * configure a fifo; for non-shared endpoints, this may be called | |
1165 | * once for a tx fifo and once for an rx fifo. | |
1166 | * | |
1167 | * returns negative errno or offset for next fifo. | |
1168 | */ | |
e9e8c85e | 1169 | static int __devinit |
550a7375 | 1170 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
e6c213b2 | 1171 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1172 | { |
1173 | void __iomem *mbase = musb->mregs; | |
1174 | int size = 0; | |
1175 | u16 maxpacket = cfg->maxpacket; | |
1176 | u16 c_off = offset >> 3; | |
1177 | u8 c_size; | |
1178 | ||
1179 | /* expect hw_ep has already been zero-initialized */ | |
1180 | ||
1181 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1182 | maxpacket = 1 << size; | |
1183 | ||
1184 | c_size = size - 3; | |
1185 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1186 | if ((offset + (maxpacket << 1)) > |
1187 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1188 | return -EMSGSIZE; |
1189 | c_size |= MUSB_FIFOSZ_DPB; | |
1190 | } else { | |
ca6d1b13 | 1191 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1192 | return -EMSGSIZE; |
1193 | } | |
1194 | ||
1195 | /* configure the FIFO */ | |
1196 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1197 | ||
550a7375 FB |
1198 | /* EP0 reserved endpoint for control, bidirectional; |
1199 | * EP1 reserved for bulk, two unidirection halves. | |
1200 | */ | |
1201 | if (hw_ep->epnum == 1) | |
1202 | musb->bulk_ep = hw_ep; | |
1203 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1204 | switch (cfg->style) { |
1205 | case FIFO_TX: | |
c6cf8b00 BW |
1206 | musb_write_txfifosz(mbase, c_size); |
1207 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1208 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1209 | hw_ep->max_packet_sz_tx = maxpacket; | |
1210 | break; | |
1211 | case FIFO_RX: | |
c6cf8b00 BW |
1212 | musb_write_rxfifosz(mbase, c_size); |
1213 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1214 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1215 | hw_ep->max_packet_sz_rx = maxpacket; | |
1216 | break; | |
1217 | case FIFO_RXTX: | |
c6cf8b00 BW |
1218 | musb_write_txfifosz(mbase, c_size); |
1219 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1220 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1221 | hw_ep->max_packet_sz_rx = maxpacket; | |
1222 | ||
c6cf8b00 BW |
1223 | musb_write_rxfifosz(mbase, c_size); |
1224 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1225 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1226 | hw_ep->max_packet_sz_tx = maxpacket; | |
1227 | ||
1228 | hw_ep->is_shared_fifo = true; | |
1229 | break; | |
1230 | } | |
1231 | ||
1232 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1233 | * which happens to be ok | |
1234 | */ | |
1235 | musb->epmask |= (1 << hw_ep->epnum); | |
1236 | ||
1237 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1238 | } | |
1239 | ||
e9e8c85e | 1240 | static struct musb_fifo_cfg __devinitdata ep0_cfg = { |
550a7375 FB |
1241 | .style = FIFO_RXTX, .maxpacket = 64, |
1242 | }; | |
1243 | ||
e9e8c85e | 1244 | static int __devinit ep_config_from_table(struct musb *musb) |
550a7375 | 1245 | { |
e6c213b2 | 1246 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1247 | unsigned i, n; |
1248 | int offset; | |
1249 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1250 | ||
e6c213b2 FB |
1251 | if (musb->config->fifo_cfg) { |
1252 | cfg = musb->config->fifo_cfg; | |
1253 | n = musb->config->fifo_cfg_size; | |
1254 | goto done; | |
1255 | } | |
1256 | ||
550a7375 FB |
1257 | switch (fifo_mode) { |
1258 | default: | |
1259 | fifo_mode = 0; | |
1260 | /* FALLTHROUGH */ | |
1261 | case 0: | |
1262 | cfg = mode_0_cfg; | |
1263 | n = ARRAY_SIZE(mode_0_cfg); | |
1264 | break; | |
1265 | case 1: | |
1266 | cfg = mode_1_cfg; | |
1267 | n = ARRAY_SIZE(mode_1_cfg); | |
1268 | break; | |
1269 | case 2: | |
1270 | cfg = mode_2_cfg; | |
1271 | n = ARRAY_SIZE(mode_2_cfg); | |
1272 | break; | |
1273 | case 3: | |
1274 | cfg = mode_3_cfg; | |
1275 | n = ARRAY_SIZE(mode_3_cfg); | |
1276 | break; | |
1277 | case 4: | |
1278 | cfg = mode_4_cfg; | |
1279 | n = ARRAY_SIZE(mode_4_cfg); | |
1280 | break; | |
3b151526 AKG |
1281 | case 5: |
1282 | cfg = mode_5_cfg; | |
1283 | n = ARRAY_SIZE(mode_5_cfg); | |
1284 | break; | |
550a7375 FB |
1285 | } |
1286 | ||
1287 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1288 | musb_driver_name, fifo_mode); | |
1289 | ||
1290 | ||
e6c213b2 | 1291 | done: |
550a7375 FB |
1292 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1293 | /* assert(offset > 0) */ | |
1294 | ||
1295 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1296 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1297 | */ |
1298 | ||
1299 | for (i = 0; i < n; i++) { | |
1300 | u8 epn = cfg->hw_ep_num; | |
1301 | ||
ca6d1b13 | 1302 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1303 | pr_debug("%s: invalid ep %d\n", |
1304 | musb_driver_name, epn); | |
bb1c9ef1 | 1305 | return -EINVAL; |
550a7375 FB |
1306 | } |
1307 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1308 | if (offset < 0) { | |
1309 | pr_debug("%s: mem overrun, ep %d\n", | |
1310 | musb_driver_name, epn); | |
1311 | return -EINVAL; | |
1312 | } | |
1313 | epn++; | |
1314 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1315 | } | |
1316 | ||
1317 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1318 | musb_driver_name, | |
ca6d1b13 FB |
1319 | n + 1, musb->config->num_eps * 2 - 1, |
1320 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1321 | |
550a7375 FB |
1322 | if (!musb->bulk_ep) { |
1323 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1324 | return -EINVAL; | |
1325 | } | |
550a7375 FB |
1326 | |
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | ||
1331 | /* | |
1332 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1333 | * @param musb the controller | |
1334 | */ | |
e9e8c85e | 1335 | static int __devinit ep_config_from_hw(struct musb *musb) |
550a7375 | 1336 | { |
c6cf8b00 | 1337 | u8 epnum = 0; |
550a7375 | 1338 | struct musb_hw_ep *hw_ep; |
a156544b | 1339 | void __iomem *mbase = musb->mregs; |
c6cf8b00 | 1340 | int ret = 0; |
550a7375 | 1341 | |
5c8a86e1 | 1342 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1343 | |
1344 | /* FIXME pick up ep0 maxpacket size */ | |
1345 | ||
ca6d1b13 | 1346 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1347 | musb_ep_select(mbase, epnum); |
1348 | hw_ep = musb->endpoints + epnum; | |
1349 | ||
c6cf8b00 BW |
1350 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1351 | if (ret < 0) | |
550a7375 | 1352 | break; |
550a7375 FB |
1353 | |
1354 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1355 | ||
550a7375 FB |
1356 | /* pick an RX/TX endpoint for bulk */ |
1357 | if (hw_ep->max_packet_sz_tx < 512 | |
1358 | || hw_ep->max_packet_sz_rx < 512) | |
1359 | continue; | |
1360 | ||
1361 | /* REVISIT: this algorithm is lazy, we should at least | |
1362 | * try to pick a double buffered endpoint. | |
1363 | */ | |
1364 | if (musb->bulk_ep) | |
1365 | continue; | |
1366 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1367 | } |
1368 | ||
550a7375 FB |
1369 | if (!musb->bulk_ep) { |
1370 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1371 | return -EINVAL; | |
1372 | } | |
550a7375 FB |
1373 | |
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1378 | ||
1379 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1380 | * configure endpoints, or take their config from silicon | |
1381 | */ | |
e9e8c85e | 1382 | static int __devinit musb_core_init(u16 musb_type, struct musb *musb) |
550a7375 | 1383 | { |
550a7375 FB |
1384 | u8 reg; |
1385 | char *type; | |
0ea52ff4 | 1386 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1387 | void __iomem *mbase = musb->mregs; |
1388 | int status = 0; | |
1389 | int i; | |
1390 | ||
1391 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1392 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1393 | |
1394 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1395 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1396 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1397 | musb->dyn_fifo = true; |
1398 | } | |
550a7375 FB |
1399 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1400 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1401 | musb->bulk_combine = true; |
550a7375 FB |
1402 | } |
1403 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1404 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1405 | musb->bulk_split = true; |
550a7375 FB |
1406 | } |
1407 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1408 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1409 | musb->hb_iso_rx = true; |
550a7375 FB |
1410 | } |
1411 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1412 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1413 | musb->hb_iso_tx = true; |
550a7375 FB |
1414 | } |
1415 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1416 | strcat(aInfo, ", SoftConn"); | |
1417 | ||
1418 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1419 | musb_driver_name, reg, aInfo); | |
1420 | ||
550a7375 | 1421 | aDate[0] = 0; |
550a7375 FB |
1422 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1423 | musb->is_multipoint = 1; | |
1424 | type = "M"; | |
1425 | } else { | |
1426 | musb->is_multipoint = 0; | |
1427 | type = ""; | |
550a7375 FB |
1428 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1429 | printk(KERN_ERR | |
1430 | "%s: kernel must blacklist external hubs\n", | |
1431 | musb_driver_name); | |
550a7375 FB |
1432 | #endif |
1433 | } | |
1434 | ||
1435 | /* log release info */ | |
32c3b94e AG |
1436 | musb->hwvers = musb_read_hwvers(mbase); |
1437 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1438 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1439 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1440 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1441 | musb_driver_name, type, aRevision, aDate); | |
1442 | ||
1443 | /* configure ep0 */ | |
c6cf8b00 | 1444 | musb_configure_ep0(musb); |
550a7375 FB |
1445 | |
1446 | /* discover endpoint configuration */ | |
1447 | musb->nr_endpoints = 1; | |
1448 | musb->epmask = 1; | |
1449 | ||
ad517e9e FB |
1450 | if (musb->dyn_fifo) |
1451 | status = ep_config_from_table(musb); | |
1452 | else | |
1453 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1454 | |
1455 | if (status < 0) | |
1456 | return status; | |
1457 | ||
1458 | /* finish init, and print endpoint config */ | |
1459 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1460 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1461 | ||
1462 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
9a35f876 | 1463 | #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) |
550a7375 FB |
1464 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); |
1465 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1466 | hw_ep->fifo_sync_va = | |
1467 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1468 | ||
1469 | if (i == 0) | |
1470 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1471 | else | |
1472 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1473 | #endif | |
1474 | ||
1475 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
c6cf8b00 | 1476 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1477 | hw_ep->rx_reinit = 1; |
1478 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1479 | |
1480 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1481 | dev_dbg(musb->controller, |
550a7375 FB |
1482 | "%s: hw_ep %d%s, %smax %d\n", |
1483 | musb_driver_name, i, | |
1484 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1485 | hw_ep->tx_double_buffered | |
1486 | ? "doublebuffer, " : "", | |
1487 | hw_ep->max_packet_sz_tx); | |
1488 | } | |
1489 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1490 | dev_dbg(musb->controller, |
550a7375 FB |
1491 | "%s: hw_ep %d%s, %smax %d\n", |
1492 | musb_driver_name, i, | |
1493 | "rx", | |
1494 | hw_ep->rx_double_buffered | |
1495 | ? "doublebuffer, " : "", | |
1496 | hw_ep->max_packet_sz_rx); | |
1497 | } | |
1498 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1499 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1500 | } |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | /*-------------------------------------------------------------------------*/ | |
1506 | ||
59b479e0 | 1507 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ |
d0678594 | 1508 | defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) |
550a7375 FB |
1509 | |
1510 | static irqreturn_t generic_interrupt(int irq, void *__hci) | |
1511 | { | |
1512 | unsigned long flags; | |
1513 | irqreturn_t retval = IRQ_NONE; | |
1514 | struct musb *musb = __hci; | |
1515 | ||
1516 | spin_lock_irqsave(&musb->lock, flags); | |
1517 | ||
1518 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); | |
1519 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); | |
1520 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); | |
1521 | ||
1522 | if (musb->int_usb || musb->int_tx || musb->int_rx) | |
1523 | retval = musb_interrupt(musb); | |
1524 | ||
1525 | spin_unlock_irqrestore(&musb->lock, flags); | |
1526 | ||
a5073b52 | 1527 | return retval; |
550a7375 FB |
1528 | } |
1529 | ||
1530 | #else | |
1531 | #define generic_interrupt NULL | |
1532 | #endif | |
1533 | ||
1534 | /* | |
1535 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1536 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1537 | * will be assigned, and the irq will already have been acked. | |
1538 | * | |
1539 | * called in irq context with spinlock held, irqs blocked | |
1540 | */ | |
1541 | irqreturn_t musb_interrupt(struct musb *musb) | |
1542 | { | |
1543 | irqreturn_t retval = IRQ_NONE; | |
1544 | u8 devctl, power; | |
1545 | int ep_num; | |
1546 | u32 reg; | |
1547 | ||
1548 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1549 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1550 | ||
5c8a86e1 | 1551 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
550a7375 FB |
1552 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", |
1553 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1554 | ||
1555 | /* the core can interrupt us for multiple reasons; docs have | |
1556 | * a generic interrupt flowchart to follow | |
1557 | */ | |
7d9645fd | 1558 | if (musb->int_usb) |
550a7375 FB |
1559 | retval |= musb_stage0_irq(musb, musb->int_usb, |
1560 | devctl, power); | |
1561 | ||
1562 | /* "stage 1" is handling endpoint irqs */ | |
1563 | ||
1564 | /* handle endpoint 0 first */ | |
1565 | if (musb->int_tx & 1) { | |
1566 | if (devctl & MUSB_DEVCTL_HM) | |
1567 | retval |= musb_h_ep0_irq(musb); | |
1568 | else | |
1569 | retval |= musb_g_ep0_irq(musb); | |
1570 | } | |
1571 | ||
1572 | /* RX on endpoints 1-15 */ | |
1573 | reg = musb->int_rx >> 1; | |
1574 | ep_num = 1; | |
1575 | while (reg) { | |
1576 | if (reg & 1) { | |
1577 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1578 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1579 | retval = IRQ_HANDLED; | |
1580 | if (devctl & MUSB_DEVCTL_HM) { | |
1581 | if (is_host_capable()) | |
1582 | musb_host_rx(musb, ep_num); | |
1583 | } else { | |
1584 | if (is_peripheral_capable()) | |
1585 | musb_g_rx(musb, ep_num); | |
1586 | } | |
1587 | } | |
1588 | ||
1589 | reg >>= 1; | |
1590 | ep_num++; | |
1591 | } | |
1592 | ||
1593 | /* TX on endpoints 1-15 */ | |
1594 | reg = musb->int_tx >> 1; | |
1595 | ep_num = 1; | |
1596 | while (reg) { | |
1597 | if (reg & 1) { | |
1598 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1599 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1600 | retval = IRQ_HANDLED; | |
1601 | if (devctl & MUSB_DEVCTL_HM) { | |
1602 | if (is_host_capable()) | |
1603 | musb_host_tx(musb, ep_num); | |
1604 | } else { | |
1605 | if (is_peripheral_capable()) | |
1606 | musb_g_tx(musb, ep_num); | |
1607 | } | |
1608 | } | |
1609 | reg >>= 1; | |
1610 | ep_num++; | |
1611 | } | |
1612 | ||
550a7375 FB |
1613 | return retval; |
1614 | } | |
981430a1 | 1615 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1616 | |
1617 | #ifndef CONFIG_MUSB_PIO_ONLY | |
e9e8c85e | 1618 | static bool __devinitdata use_dma = 1; |
550a7375 FB |
1619 | |
1620 | /* "modprobe ... use_dma=0" etc */ | |
1621 | module_param(use_dma, bool, 0); | |
1622 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1623 | ||
1624 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1625 | { | |
1626 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1627 | ||
1628 | /* called with controller lock already held */ | |
1629 | ||
1630 | if (!epnum) { | |
1631 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1632 | if (!is_cppi_enabled()) { | |
1633 | /* endpoint 0 */ | |
1634 | if (devctl & MUSB_DEVCTL_HM) | |
1635 | musb_h_ep0_irq(musb); | |
1636 | else | |
1637 | musb_g_ep0_irq(musb); | |
1638 | } | |
1639 | #endif | |
1640 | } else { | |
1641 | /* endpoints 1..15 */ | |
1642 | if (transmit) { | |
1643 | if (devctl & MUSB_DEVCTL_HM) { | |
1644 | if (is_host_capable()) | |
1645 | musb_host_tx(musb, epnum); | |
1646 | } else { | |
1647 | if (is_peripheral_capable()) | |
1648 | musb_g_tx(musb, epnum); | |
1649 | } | |
1650 | } else { | |
1651 | /* receive */ | |
1652 | if (devctl & MUSB_DEVCTL_HM) { | |
1653 | if (is_host_capable()) | |
1654 | musb_host_rx(musb, epnum); | |
1655 | } else { | |
1656 | if (is_peripheral_capable()) | |
1657 | musb_g_rx(musb, epnum); | |
1658 | } | |
1659 | } | |
1660 | } | |
1661 | } | |
9a35f876 | 1662 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1663 | |
1664 | #else | |
1665 | #define use_dma 0 | |
1666 | #endif | |
1667 | ||
1668 | /*-------------------------------------------------------------------------*/ | |
1669 | ||
1670 | #ifdef CONFIG_SYSFS | |
1671 | ||
1672 | static ssize_t | |
1673 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1674 | { | |
1675 | struct musb *musb = dev_to_musb(dev); | |
1676 | unsigned long flags; | |
1677 | int ret = -EINVAL; | |
1678 | ||
1679 | spin_lock_irqsave(&musb->lock, flags); | |
3df00453 | 1680 | ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1681 | spin_unlock_irqrestore(&musb->lock, flags); |
1682 | ||
1683 | return ret; | |
1684 | } | |
1685 | ||
1686 | static ssize_t | |
1687 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1688 | const char *buf, size_t n) | |
1689 | { | |
1690 | struct musb *musb = dev_to_musb(dev); | |
1691 | unsigned long flags; | |
96a274d1 | 1692 | int status; |
550a7375 FB |
1693 | |
1694 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1695 | if (sysfs_streq(buf, "host")) |
1696 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1697 | else if (sysfs_streq(buf, "peripheral")) | |
1698 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1699 | else if (sysfs_streq(buf, "otg")) | |
1700 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1701 | else | |
1702 | status = -EINVAL; | |
550a7375 FB |
1703 | spin_unlock_irqrestore(&musb->lock, flags); |
1704 | ||
96a274d1 | 1705 | return (status == 0) ? n : status; |
550a7375 FB |
1706 | } |
1707 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1708 | ||
1709 | static ssize_t | |
1710 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1711 | const char *buf, size_t n) | |
1712 | { | |
1713 | struct musb *musb = dev_to_musb(dev); | |
1714 | unsigned long flags; | |
1715 | unsigned long val; | |
1716 | ||
1717 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1718 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1719 | return -EINVAL; |
1720 | } | |
1721 | ||
1722 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1723 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1724 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
84e250ff | 1725 | if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1726 | musb->is_active = 0; |
1727 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1728 | spin_unlock_irqrestore(&musb->lock, flags); | |
1729 | ||
1730 | return n; | |
1731 | } | |
1732 | ||
1733 | static ssize_t | |
1734 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1735 | { | |
1736 | struct musb *musb = dev_to_musb(dev); | |
1737 | unsigned long flags; | |
1738 | unsigned long val; | |
1739 | int vbus; | |
1740 | ||
1741 | spin_lock_irqsave(&musb->lock, flags); | |
1742 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1743 | /* FIXME get_vbus_status() is normally #defined as false... |
1744 | * and is effectively TUSB-specific. | |
1745 | */ | |
550a7375 FB |
1746 | vbus = musb_platform_get_vbus_status(musb); |
1747 | spin_unlock_irqrestore(&musb->lock, flags); | |
1748 | ||
f7f9d63e | 1749 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1750 | vbus ? "on" : "off", val); |
1751 | } | |
1752 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1753 | ||
550a7375 FB |
1754 | /* Gadget drivers can't know that a host is connected so they might want |
1755 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1756 | */ | |
1757 | static ssize_t | |
1758 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1759 | const char *buf, size_t n) | |
1760 | { | |
1761 | struct musb *musb = dev_to_musb(dev); | |
1762 | unsigned short srp; | |
1763 | ||
1764 | if (sscanf(buf, "%hu", &srp) != 1 | |
1765 | || (srp != 1)) { | |
b3b1cc3b | 1766 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1767 | return -EINVAL; |
1768 | } | |
1769 | ||
1770 | if (srp == 1) | |
1771 | musb_g_wakeup(musb); | |
1772 | ||
1773 | return n; | |
1774 | } | |
1775 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1776 | ||
94375751 FB |
1777 | static struct attribute *musb_attributes[] = { |
1778 | &dev_attr_mode.attr, | |
1779 | &dev_attr_vbus.attr, | |
94375751 | 1780 | &dev_attr_srp.attr, |
94375751 FB |
1781 | NULL |
1782 | }; | |
1783 | ||
1784 | static const struct attribute_group musb_attr_group = { | |
1785 | .attrs = musb_attributes, | |
1786 | }; | |
1787 | ||
550a7375 FB |
1788 | #endif /* sysfs */ |
1789 | ||
1790 | /* Only used to provide driver mode change events */ | |
1791 | static void musb_irq_work(struct work_struct *data) | |
1792 | { | |
1793 | struct musb *musb = container_of(data, struct musb, irq_work); | |
1794 | static int old_state; | |
1795 | ||
84e250ff DB |
1796 | if (musb->xceiv->state != old_state) { |
1797 | old_state = musb->xceiv->state; | |
550a7375 FB |
1798 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1799 | } | |
1800 | } | |
1801 | ||
1802 | /* -------------------------------------------------------------------------- | |
1803 | * Init support | |
1804 | */ | |
1805 | ||
e9e8c85e | 1806 | static struct musb *__devinit |
ca6d1b13 FB |
1807 | allocate_instance(struct device *dev, |
1808 | struct musb_hdrc_config *config, void __iomem *mbase) | |
550a7375 FB |
1809 | { |
1810 | struct musb *musb; | |
1811 | struct musb_hw_ep *ep; | |
1812 | int epnum; | |
550a7375 FB |
1813 | struct usb_hcd *hcd; |
1814 | ||
427c4f33 | 1815 | hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); |
550a7375 FB |
1816 | if (!hcd) |
1817 | return NULL; | |
1818 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
1819 | ||
1820 | musb = hcd_to_musb(hcd); | |
1821 | INIT_LIST_HEAD(&musb->control); | |
1822 | INIT_LIST_HEAD(&musb->in_bulk); | |
1823 | INIT_LIST_HEAD(&musb->out_bulk); | |
1824 | ||
1825 | hcd->uses_new_polling = 1; | |
ec95d35a | 1826 | hcd->has_tt = 1; |
550a7375 FB |
1827 | |
1828 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; | |
f7f9d63e | 1829 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
456bb169 | 1830 | dev_set_drvdata(dev, musb); |
550a7375 FB |
1831 | musb->mregs = mbase; |
1832 | musb->ctrl_base = mbase; | |
1833 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1834 | musb->config = config; |
02582b92 | 1835 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1836 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1837 | epnum < musb->config->num_eps; |
550a7375 | 1838 | epnum++, ep++) { |
550a7375 FB |
1839 | ep->musb = musb; |
1840 | ep->epnum = epnum; | |
1841 | } | |
1842 | ||
1843 | musb->controller = dev; | |
743411b3 | 1844 | |
550a7375 FB |
1845 | return musb; |
1846 | } | |
1847 | ||
1848 | static void musb_free(struct musb *musb) | |
1849 | { | |
1850 | /* this has multiple entry modes. it handles fault cleanup after | |
1851 | * probe(), where things may be partially set up, as well as rmmod | |
1852 | * cleanup after everything's been de-activated. | |
1853 | */ | |
1854 | ||
1855 | #ifdef CONFIG_SYSFS | |
94375751 | 1856 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1857 | #endif |
1858 | ||
97a39896 AKG |
1859 | if (musb->nIrq >= 0) { |
1860 | if (musb->irq_wake) | |
1861 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1862 | free_irq(musb->nIrq, musb); |
1863 | } | |
1864 | if (is_dma_capable() && musb->dma_controller) { | |
1865 | struct dma_controller *c = musb->dma_controller; | |
1866 | ||
1867 | (void) c->stop(c); | |
1868 | dma_controller_destroy(c); | |
1869 | } | |
1870 | ||
decadacb | 1871 | usb_put_hcd(musb_to_hcd(musb)); |
550a7375 FB |
1872 | } |
1873 | ||
1874 | /* | |
1875 | * Perform generic per-controller initialization. | |
1876 | * | |
1877 | * @pDevice: the controller (already clocked, etc) | |
1878 | * @nIrq: irq | |
1879 | * @mregs: virtual address of controller registers, | |
1880 | * not yet corrected for platform-specific offsets | |
1881 | */ | |
e9e8c85e | 1882 | static int __devinit |
550a7375 FB |
1883 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
1884 | { | |
1885 | int status; | |
1886 | struct musb *musb; | |
1887 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
1888 | ||
1889 | /* The driver might handle more features than the board; OK. | |
1890 | * Fail when the board needs a feature that's not enabled. | |
1891 | */ | |
1892 | if (!plat) { | |
1893 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1894 | status = -ENODEV; |
1895 | goto fail0; | |
550a7375 | 1896 | } |
34e2beb2 | 1897 | |
550a7375 | 1898 | /* allocate */ |
ca6d1b13 | 1899 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1900 | if (!musb) { |
1901 | status = -ENOMEM; | |
1902 | goto fail0; | |
1903 | } | |
550a7375 | 1904 | |
7acc6197 HH |
1905 | pm_runtime_use_autosuspend(musb->controller); |
1906 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
1907 | pm_runtime_enable(musb->controller); | |
1908 | ||
550a7375 FB |
1909 | spin_lock_init(&musb->lock); |
1910 | musb->board_mode = plat->mode; | |
1911 | musb->board_set_power = plat->set_power; | |
550a7375 | 1912 | musb->min_power = plat->min_power; |
f7ec9437 | 1913 | musb->ops = plat->platform_ops; |
550a7375 | 1914 | |
84e250ff DB |
1915 | /* The musb_platform_init() call: |
1916 | * - adjusts musb->mregs and musb->isr if needed, | |
1917 | * - may initialize an integrated tranceiver | |
721002ec | 1918 | * - initializes musb->xceiv, usually by otg_get_phy() |
84e250ff | 1919 | * - stops powering VBUS |
84e250ff | 1920 | * |
7c9d440e | 1921 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
1922 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
1923 | * external/discrete ones in various flavors (twl4030 family, | |
1924 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 FB |
1925 | */ |
1926 | musb->isr = generic_interrupt; | |
ea65df57 | 1927 | status = musb_platform_init(musb); |
550a7375 | 1928 | if (status < 0) |
03491761 | 1929 | goto fail1; |
34e2beb2 | 1930 | |
550a7375 FB |
1931 | if (!musb->isr) { |
1932 | status = -ENODEV; | |
c04352a5 | 1933 | goto fail2; |
550a7375 FB |
1934 | } |
1935 | ||
ffb865b1 | 1936 | if (!musb->xceiv->io_ops) { |
bf070bc1 | 1937 | musb->xceiv->io_dev = musb->controller; |
ffb865b1 HK |
1938 | musb->xceiv->io_priv = musb->mregs; |
1939 | musb->xceiv->io_ops = &musb_ulpi_access; | |
1940 | } | |
1941 | ||
c04352a5 GI |
1942 | pm_runtime_get_sync(musb->controller); |
1943 | ||
550a7375 FB |
1944 | #ifndef CONFIG_MUSB_PIO_ONLY |
1945 | if (use_dma && dev->dma_mask) { | |
1946 | struct dma_controller *c; | |
1947 | ||
1948 | c = dma_controller_create(musb, musb->mregs); | |
1949 | musb->dma_controller = c; | |
1950 | if (c) | |
1951 | (void) c->start(c); | |
1952 | } | |
1953 | #endif | |
1954 | /* ideally this would be abstracted in platform setup */ | |
1955 | if (!is_dma_capable() || !musb->dma_controller) | |
1956 | dev->dma_mask = NULL; | |
1957 | ||
1958 | /* be sure interrupts are disabled before connecting ISR */ | |
1959 | musb_platform_disable(musb); | |
1960 | musb_generic_disable(musb); | |
1961 | ||
1962 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1963 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1964 | ? MUSB_CONTROLLER_MHDRC |
1965 | : MUSB_CONTROLLER_HDRC, musb); | |
1966 | if (status < 0) | |
34e2beb2 | 1967 | goto fail3; |
550a7375 | 1968 | |
f7f9d63e | 1969 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 1970 | |
550a7375 FB |
1971 | /* Init IRQ workqueue before request_irq */ |
1972 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1973 | ||
1974 | /* attach to the IRQ */ | |
427c4f33 | 1975 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1976 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1977 | status = -ENODEV; | |
34e2beb2 | 1978 | goto fail3; |
550a7375 FB |
1979 | } |
1980 | musb->nIrq = nIrq; | |
1981 | /* FIXME this handles wakeup irqs wrong */ | |
c48a5155 FB |
1982 | if (enable_irq_wake(nIrq) == 0) { |
1983 | musb->irq_wake = 1; | |
550a7375 | 1984 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1985 | } else { |
1986 | musb->irq_wake = 0; | |
1987 | } | |
550a7375 | 1988 | |
84e250ff DB |
1989 | /* host side needs more setup */ |
1990 | if (is_host_enabled(musb)) { | |
550a7375 FB |
1991 | struct usb_hcd *hcd = musb_to_hcd(musb); |
1992 | ||
6e13c650 | 1993 | otg_set_host(musb->xceiv->otg, &hcd->self); |
84e250ff DB |
1994 | |
1995 | if (is_otg_enabled(musb)) | |
550a7375 | 1996 | hcd->self.otg_port = 1; |
d445b6da | 1997 | musb->xceiv->otg->host = &hcd->self; |
550a7375 | 1998 | hcd->power_budget = 2 * (plat->power ? : 250); |
5fc4e779 AKG |
1999 | |
2000 | /* program PHY to use external vBus if required */ | |
2001 | if (plat->extvbus) { | |
adb3ee42 | 2002 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); |
5fc4e779 | 2003 | busctl |= MUSB_ULPI_USE_EXTVBUS; |
adb3ee42 | 2004 | musb_write_ulpi_buscontrol(musb->mregs, busctl); |
5fc4e779 | 2005 | } |
550a7375 | 2006 | } |
550a7375 FB |
2007 | |
2008 | /* For the host-only role, we can activate right away. | |
2009 | * (We expect the ID pin to be forcibly grounded!!) | |
2010 | * Otherwise, wait till the gadget driver hooks up. | |
2011 | */ | |
2012 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) { | |
07a8cdd2 AG |
2013 | struct usb_hcd *hcd = musb_to_hcd(musb); |
2014 | ||
550a7375 | 2015 | MUSB_HST_MODE(musb); |
d445b6da | 2016 | musb->xceiv->otg->default_a = 1; |
84e250ff | 2017 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 2018 | |
cd70469d | 2019 | status = usb_add_hcd(musb_to_hcd(musb), 0, 0); |
550a7375 | 2020 | |
07a8cdd2 | 2021 | hcd->self.uses_pio_for_control = 1; |
5c8a86e1 | 2022 | dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", |
550a7375 FB |
2023 | "HOST", status, |
2024 | musb_readb(musb->mregs, MUSB_DEVCTL), | |
2025 | (musb_readb(musb->mregs, MUSB_DEVCTL) | |
2026 | & MUSB_DEVCTL_BDEVICE | |
2027 | ? 'B' : 'A')); | |
2028 | ||
2029 | } else /* peripheral is enabled */ { | |
2030 | MUSB_DEV_MODE(musb); | |
d445b6da | 2031 | musb->xceiv->otg->default_a = 0; |
84e250ff | 2032 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
2033 | |
2034 | status = musb_gadget_setup(musb); | |
2035 | ||
5c8a86e1 | 2036 | dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", |
550a7375 FB |
2037 | is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", |
2038 | status, | |
2039 | musb_readb(musb->mregs, MUSB_DEVCTL)); | |
2040 | ||
2041 | } | |
461972d8 | 2042 | if (status < 0) |
34e2beb2 | 2043 | goto fail3; |
550a7375 | 2044 | |
7f7f9e2a FB |
2045 | status = musb_init_debugfs(musb); |
2046 | if (status < 0) | |
b0f9da7e | 2047 | goto fail4; |
7f7f9e2a | 2048 | |
550a7375 | 2049 | #ifdef CONFIG_SYSFS |
94375751 | 2050 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 2051 | if (status) |
b0f9da7e | 2052 | goto fail5; |
461972d8 | 2053 | #endif |
550a7375 | 2054 | |
c04352a5 GI |
2055 | pm_runtime_put(musb->controller); |
2056 | ||
ab3bbfa1 FB |
2057 | dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", |
2058 | ({char *s; | |
2059 | switch (musb->board_mode) { | |
2060 | case MUSB_HOST: s = "Host"; break; | |
2061 | case MUSB_PERIPHERAL: s = "Peripheral"; break; | |
2062 | default: s = "OTG"; break; | |
2063 | }; s; }), | |
2064 | ctrl, | |
2065 | (is_dma_capable() && musb->dma_controller) | |
2066 | ? "DMA" : "PIO", | |
2067 | musb->nIrq); | |
2068 | ||
28c2c51c | 2069 | return 0; |
550a7375 | 2070 | |
b0f9da7e FB |
2071 | fail5: |
2072 | musb_exit_debugfs(musb); | |
2073 | ||
34e2beb2 SS |
2074 | fail4: |
2075 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) | |
2076 | usb_remove_hcd(musb_to_hcd(musb)); | |
2077 | else | |
2078 | musb_gadget_cleanup(musb); | |
2079 | ||
2080 | fail3: | |
c04352a5 GI |
2081 | pm_runtime_put_sync(musb->controller); |
2082 | ||
2083 | fail2: | |
34e2beb2 SS |
2084 | if (musb->irq_wake) |
2085 | device_init_wakeup(dev, 0); | |
550a7375 | 2086 | musb_platform_exit(musb); |
28c2c51c | 2087 | |
34e2beb2 SS |
2088 | fail1: |
2089 | dev_err(musb->controller, | |
2090 | "musb_init_controller failed with status %d\n", status); | |
2091 | ||
28c2c51c FB |
2092 | musb_free(musb); |
2093 | ||
34e2beb2 SS |
2094 | fail0: |
2095 | ||
28c2c51c FB |
2096 | return status; |
2097 | ||
550a7375 FB |
2098 | } |
2099 | ||
2100 | /*-------------------------------------------------------------------------*/ | |
2101 | ||
2102 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2103 | * bridge to a platform device; this driver then suffices. | |
2104 | */ | |
2105 | ||
2106 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2107 | static u64 *orig_dma_mask; | |
2108 | #endif | |
2109 | ||
e9e8c85e | 2110 | static int __devinit musb_probe(struct platform_device *pdev) |
550a7375 FB |
2111 | { |
2112 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2113 | int irq = platform_get_irq_byname(pdev, "mc"); |
da5108e1 | 2114 | int status; |
550a7375 FB |
2115 | struct resource *iomem; |
2116 | void __iomem *base; | |
2117 | ||
2118 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
541079de | 2119 | if (!iomem || irq <= 0) |
550a7375 FB |
2120 | return -ENODEV; |
2121 | ||
195e9e46 | 2122 | base = ioremap(iomem->start, resource_size(iomem)); |
550a7375 FB |
2123 | if (!base) { |
2124 | dev_err(dev, "ioremap failed\n"); | |
2125 | return -ENOMEM; | |
2126 | } | |
2127 | ||
2128 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2129 | /* clobbered by use_dma=n */ | |
2130 | orig_dma_mask = dev->dma_mask; | |
2131 | #endif | |
da5108e1 FB |
2132 | status = musb_init_controller(dev, irq, base); |
2133 | if (status < 0) | |
2134 | iounmap(base); | |
2135 | ||
2136 | return status; | |
550a7375 FB |
2137 | } |
2138 | ||
e9e8c85e | 2139 | static int __devexit musb_remove(struct platform_device *pdev) |
550a7375 FB |
2140 | { |
2141 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2142 | void __iomem *ctrl_base = musb->ctrl_base; | |
2143 | ||
2144 | /* this gets called on rmmod. | |
2145 | * - Host mode: host may still be active | |
2146 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2147 | * - OTG mode: both roles are deactivated (or never-activated) | |
2148 | */ | |
7f7f9e2a | 2149 | musb_exit_debugfs(musb); |
550a7375 | 2150 | musb_shutdown(pdev); |
461972d8 | 2151 | |
550a7375 FB |
2152 | musb_free(musb); |
2153 | iounmap(ctrl_base); | |
2154 | device_init_wakeup(&pdev->dev, 0); | |
2155 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2156 | pdev->dev.dma_mask = orig_dma_mask; | |
2157 | #endif | |
2158 | return 0; | |
2159 | } | |
2160 | ||
2161 | #ifdef CONFIG_PM | |
2162 | ||
3c8a5fcc | 2163 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2164 | { |
2165 | int i; | |
2166 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2167 | void __iomem *epio; |
4f712e01 AKG |
2168 | |
2169 | if (is_host_enabled(musb)) { | |
7421107b FB |
2170 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2171 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2172 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
4f712e01 | 2173 | } |
7421107b FB |
2174 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
2175 | musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); | |
2176 | musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); | |
2177 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); | |
2178 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2179 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2180 | |
ae9b2ad2 | 2181 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2182 | struct musb_hw_ep *hw_ep; |
2183 | ||
2184 | hw_ep = &musb->endpoints[i]; | |
2185 | if (!hw_ep) | |
2186 | continue; | |
2187 | ||
2188 | epio = hw_ep->regs; | |
2189 | if (!epio) | |
2190 | continue; | |
2191 | ||
ea737554 | 2192 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2193 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2194 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2195 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2196 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2197 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2198 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2199 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2200 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2201 | |
2202 | if (musb->dyn_fifo) { | |
7421107b | 2203 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2204 | musb_read_txfifoadd(musb_base); |
7421107b | 2205 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2206 | musb_read_rxfifoadd(musb_base); |
7421107b | 2207 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2208 | musb_read_txfifosz(musb_base); |
7421107b | 2209 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2210 | musb_read_rxfifosz(musb_base); |
2211 | } | |
2212 | if (is_host_enabled(musb)) { | |
7421107b | 2213 | musb->context.index_regs[i].txtype = |
ae9b2ad2 | 2214 | musb_readb(epio, MUSB_TXTYPE); |
7421107b | 2215 | musb->context.index_regs[i].txinterval = |
ae9b2ad2 | 2216 | musb_readb(epio, MUSB_TXINTERVAL); |
7421107b | 2217 | musb->context.index_regs[i].rxtype = |
ae9b2ad2 | 2218 | musb_readb(epio, MUSB_RXTYPE); |
7421107b | 2219 | musb->context.index_regs[i].rxinterval = |
ae9b2ad2 | 2220 | musb_readb(epio, MUSB_RXINTERVAL); |
4f712e01 | 2221 | |
7421107b | 2222 | musb->context.index_regs[i].txfunaddr = |
4f712e01 | 2223 | musb_read_txfunaddr(musb_base, i); |
7421107b | 2224 | musb->context.index_regs[i].txhubaddr = |
4f712e01 | 2225 | musb_read_txhubaddr(musb_base, i); |
7421107b | 2226 | musb->context.index_regs[i].txhubport = |
4f712e01 AKG |
2227 | musb_read_txhubport(musb_base, i); |
2228 | ||
7421107b | 2229 | musb->context.index_regs[i].rxfunaddr = |
4f712e01 | 2230 | musb_read_rxfunaddr(musb_base, i); |
7421107b | 2231 | musb->context.index_regs[i].rxhubaddr = |
4f712e01 | 2232 | musb_read_rxhubaddr(musb_base, i); |
7421107b | 2233 | musb->context.index_regs[i].rxhubport = |
4f712e01 AKG |
2234 | musb_read_rxhubport(musb_base, i); |
2235 | } | |
2236 | } | |
4f712e01 AKG |
2237 | } |
2238 | ||
3c8a5fcc | 2239 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2240 | { |
2241 | int i; | |
2242 | void __iomem *musb_base = musb->mregs; | |
2243 | void __iomem *ep_target_regs; | |
ae9b2ad2 | 2244 | void __iomem *epio; |
4f712e01 | 2245 | |
4f712e01 | 2246 | if (is_host_enabled(musb)) { |
7421107b FB |
2247 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2248 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2249 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
4f712e01 | 2250 | } |
7421107b FB |
2251 | musb_writeb(musb_base, MUSB_POWER, musb->context.power); |
2252 | musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); | |
2253 | musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); | |
2254 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); | |
2255 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2256 | |
ae9b2ad2 | 2257 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2258 | struct musb_hw_ep *hw_ep; |
2259 | ||
2260 | hw_ep = &musb->endpoints[i]; | |
2261 | if (!hw_ep) | |
2262 | continue; | |
2263 | ||
2264 | epio = hw_ep->regs; | |
2265 | if (!epio) | |
2266 | continue; | |
2267 | ||
ea737554 | 2268 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2269 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2270 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2271 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2272 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2273 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2274 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2275 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2276 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2277 | |
2278 | if (musb->dyn_fifo) { | |
2279 | musb_write_txfifosz(musb_base, | |
7421107b | 2280 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2281 | musb_write_rxfifosz(musb_base, |
7421107b | 2282 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2283 | musb_write_txfifoadd(musb_base, |
7421107b | 2284 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2285 | musb_write_rxfifoadd(musb_base, |
7421107b | 2286 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2287 | } |
2288 | ||
2289 | if (is_host_enabled(musb)) { | |
ae9b2ad2 | 2290 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2291 | musb->context.index_regs[i].txtype); |
ae9b2ad2 | 2292 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2293 | musb->context.index_regs[i].txinterval); |
ae9b2ad2 | 2294 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2295 | musb->context.index_regs[i].rxtype); |
ae9b2ad2 | 2296 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2297 | |
7421107b | 2298 | musb->context.index_regs[i].rxinterval); |
4f712e01 | 2299 | musb_write_txfunaddr(musb_base, i, |
7421107b | 2300 | musb->context.index_regs[i].txfunaddr); |
4f712e01 | 2301 | musb_write_txhubaddr(musb_base, i, |
7421107b | 2302 | musb->context.index_regs[i].txhubaddr); |
4f712e01 | 2303 | musb_write_txhubport(musb_base, i, |
7421107b | 2304 | musb->context.index_regs[i].txhubport); |
4f712e01 AKG |
2305 | |
2306 | ep_target_regs = | |
2307 | musb_read_target_reg_base(i, musb_base); | |
2308 | ||
2309 | musb_write_rxfunaddr(ep_target_regs, | |
7421107b | 2310 | musb->context.index_regs[i].rxfunaddr); |
4f712e01 | 2311 | musb_write_rxhubaddr(ep_target_regs, |
7421107b | 2312 | musb->context.index_regs[i].rxhubaddr); |
4f712e01 | 2313 | musb_write_rxhubport(ep_target_regs, |
7421107b | 2314 | musb->context.index_regs[i].rxhubport); |
4f712e01 AKG |
2315 | } |
2316 | } | |
3c5fec75 | 2317 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2318 | } |
2319 | ||
48fea965 | 2320 | static int musb_suspend(struct device *dev) |
550a7375 | 2321 | { |
8220796d | 2322 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2323 | unsigned long flags; |
550a7375 | 2324 | |
550a7375 FB |
2325 | spin_lock_irqsave(&musb->lock, flags); |
2326 | ||
2327 | if (is_peripheral_active(musb)) { | |
2328 | /* FIXME force disconnect unless we know USB will wake | |
2329 | * the system up quickly enough to respond ... | |
2330 | */ | |
2331 | } else if (is_host_active(musb)) { | |
2332 | /* we know all the children are suspended; sometimes | |
2333 | * they will even be wakeup-enabled. | |
2334 | */ | |
2335 | } | |
2336 | ||
550a7375 FB |
2337 | spin_unlock_irqrestore(&musb->lock, flags); |
2338 | return 0; | |
2339 | } | |
2340 | ||
48fea965 | 2341 | static int musb_resume_noirq(struct device *dev) |
550a7375 | 2342 | { |
550a7375 | 2343 | /* for static cmos like DaVinci, register values were preserved |
0ec8fd70 KK |
2344 | * unless for some reason the whole soc powered down or the USB |
2345 | * module got reset through the PSC (vs just being disabled). | |
550a7375 | 2346 | */ |
550a7375 FB |
2347 | return 0; |
2348 | } | |
2349 | ||
7acc6197 HH |
2350 | static int musb_runtime_suspend(struct device *dev) |
2351 | { | |
2352 | struct musb *musb = dev_to_musb(dev); | |
2353 | ||
2354 | musb_save_context(musb); | |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 | ||
2359 | static int musb_runtime_resume(struct device *dev) | |
2360 | { | |
2361 | struct musb *musb = dev_to_musb(dev); | |
2362 | static int first = 1; | |
2363 | ||
2364 | /* | |
2365 | * When pm_runtime_get_sync called for the first time in driver | |
2366 | * init, some of the structure is still not initialized which is | |
2367 | * used in restore function. But clock needs to be | |
2368 | * enabled before any register access, so | |
2369 | * pm_runtime_get_sync has to be called. | |
2370 | * Also context restore without save does not make | |
2371 | * any sense | |
2372 | */ | |
2373 | if (!first) | |
2374 | musb_restore_context(musb); | |
2375 | first = 0; | |
2376 | ||
2377 | return 0; | |
2378 | } | |
2379 | ||
47145210 | 2380 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 MD |
2381 | .suspend = musb_suspend, |
2382 | .resume_noirq = musb_resume_noirq, | |
7acc6197 HH |
2383 | .runtime_suspend = musb_runtime_suspend, |
2384 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2385 | }; |
2386 | ||
2387 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2388 | #else |
48fea965 | 2389 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2390 | #endif |
2391 | ||
2392 | static struct platform_driver musb_driver = { | |
2393 | .driver = { | |
2394 | .name = (char *)musb_driver_name, | |
2395 | .bus = &platform_bus_type, | |
2396 | .owner = THIS_MODULE, | |
48fea965 | 2397 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2398 | }, |
e9e8c85e FB |
2399 | .probe = musb_probe, |
2400 | .remove = __devexit_p(musb_remove), | |
550a7375 | 2401 | .shutdown = musb_shutdown, |
550a7375 FB |
2402 | }; |
2403 | ||
2404 | /*-------------------------------------------------------------------------*/ | |
2405 | ||
2406 | static int __init musb_init(void) | |
2407 | { | |
550a7375 FB |
2408 | if (usb_disabled()) |
2409 | return 0; | |
550a7375 FB |
2410 | |
2411 | pr_info("%s: version " MUSB_VERSION ", " | |
550a7375 | 2412 | "?dma?" |
550a7375 | 2413 | ", " |
62285963 | 2414 | "otg (peripheral+host)", |
5c8a86e1 | 2415 | musb_driver_name); |
e9e8c85e | 2416 | return platform_driver_register(&musb_driver); |
550a7375 | 2417 | } |
e9e8c85e | 2418 | module_init(musb_init); |
550a7375 FB |
2419 | |
2420 | static void __exit musb_cleanup(void) | |
2421 | { | |
2422 | platform_driver_unregister(&musb_driver); | |
2423 | } | |
2424 | module_exit(musb_cleanup); |