projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: musb: avoid FADDR read access
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375
FB		 85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
9303961f 99#include <linux/prefetch.h>
550a7375
FB		 100#include <linux/platform_device.h>
101#include <linux/io.h>
65b3d52d 102#include <linux/idr.h>
8d2421e6 103#include <linux/dma-mapping.h>
550a7375 104
550a7375
FB		 105#include "musb_core.h"
106
f7f9d63e 107#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 108
109
550a7375
FB		 110#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112
e8164f64 113#define MUSB_VERSION "6.0"
550a7375
FB		 114
115#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116
05ac10dd 117#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375 118const char musb_driver_name[] = MUSB_DRIVER_NAME;
65b3d52d 119static DEFINE_IDA(musb_ida);
550a7375
FB		 120
121MODULE_DESCRIPTION(DRIVER_INFO);
122MODULE_AUTHOR(DRIVER_AUTHOR);
123MODULE_LICENSE("GPL");
124MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125
126
127/*-------------------------------------------------------------------------*/
128
129static inline struct musb *dev_to_musb(struct device *dev)
130{
550a7375 131 return dev_get_drvdata(dev);
550a7375
FB		 132}
133
134/*-------------------------------------------------------------------------*/
135
65b3d52d
R		 136int musb_get_id(struct device *dev, gfp_t gfp_mask)
137{
138 int ret;
139 int id;
140
141 ret = ida_pre_get(&musb_ida, gfp_mask);
142 if (!ret) {
143 dev_err(dev, "failed to reserve resource for id\n");
144 return -ENOMEM;
145 }
146
147 ret = ida_get_new(&musb_ida, &id);
148 if (ret < 0) {
149 dev_err(dev, "failed to allocate a new id\n");
150 return ret;
151 }
152
153 return id;
154}
155EXPORT_SYMBOL_GPL(musb_get_id);
156
157void musb_put_id(struct device *dev, int id)
158{
159
160 dev_dbg(dev, "removing id %d\n", id);
161 ida_remove(&musb_ida, id);
162}
163EXPORT_SYMBOL_GPL(musb_put_id);
164
ffb865b1 165#ifndef CONFIG_BLACKFIN
b96d3b08 166static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
ffb865b1 167{
b96d3b08 168 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 169 int i = 0;
170 u8 r;
171 u8 power;
bf070bc1
GI		 172 int ret;
173
174 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 175
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
180
181 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
182 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
183 */
184
185 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
186 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
187 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
188
189 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
190 & MUSB_ULPI_REG_CMPLT)) {
191 i++;
bf070bc1
GI		 192 if (i == 10000) {
193 ret = -ETIMEDOUT;
194 goto out;
195 }
ffb865b1
HK		 196
197 }
198 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
199 r &= ~MUSB_ULPI_REG_CMPLT;
200 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
201
bf070bc1
GI		 202 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
203
204out:
205 pm_runtime_put(phy->io_dev);
206
207 return ret;
ffb865b1
HK		 208}
209
b96d3b08 210static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
ffb865b1 211{
b96d3b08 212 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 213 int i = 0;
214 u8 r = 0;
215 u8 power;
bf070bc1
GI		 216 int ret = 0;
217
218 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 219
220 /* Make sure the transceiver is not in low power mode */
221 power = musb_readb(addr, MUSB_POWER);
222 power &= ~MUSB_POWER_SUSPENDM;
223 musb_writeb(addr, MUSB_POWER, power);
224
225 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
226 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
227 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
228
229 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
230 & MUSB_ULPI_REG_CMPLT)) {
231 i++;
bf070bc1
GI		 232 if (i == 10000) {
233 ret = -ETIMEDOUT;
234 goto out;
235 }
ffb865b1
HK		 236 }
237
238 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
239 r &= ~MUSB_ULPI_REG_CMPLT;
240 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
241
bf070bc1
GI		 242out:
243 pm_runtime_put(phy->io_dev);
244
245 return ret;
ffb865b1
HK		 246}
247#else
f2263db7
MF		 248#define musb_ulpi_read NULL
249#define musb_ulpi_write NULL
ffb865b1
HK		 250#endif
251
b96d3b08 252static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 253 .read = musb_ulpi_read,
254 .write = musb_ulpi_write,
255};
256
257/*-------------------------------------------------------------------------*/
258
7c925546 259#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
c6cf8b00 260
550a7375
FB		 261/*
262 * Load an endpoint's FIFO
263 */
264void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
265{
5c8a86e1 266 struct musb *musb = hw_ep->musb;
550a7375
FB		 267 void __iomem *fifo = hw_ep->fifo;
268
603fe2b2
AKG		 269 if (unlikely(len == 0))
270 return;
271
550a7375
FB		 272 prefetch((u8 *)src);
273
5c8a86e1 274 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 275 'T', hw_ep->epnum, fifo, len, src);
276
277 /* we can't assume unaligned reads work */
278 if (likely((0x01 & (unsigned long) src) == 0)) {
279 u16 index = 0;
280
281 /* best case is 32bit-aligned source address */
282 if ((0x02 & (unsigned long) src) == 0) {
283 if (len >= 4) {
284 writesl(fifo, src + index, len >> 2);
285 index += len & ~0x03;
286 }
287 if (len & 0x02) {
288 musb_writew(fifo, 0, *(u16 *)&src[index]);
289 index += 2;
290 }
291 } else {
292 if (len >= 2) {
293 writesw(fifo, src + index, len >> 1);
294 index += len & ~0x01;
295 }
296 }
297 if (len & 0x01)
298 musb_writeb(fifo, 0, src[index]);
299 } else {
300 /* byte aligned */
301 writesb(fifo, src, len);
302 }
303}
304
843bb1d0 305#if !defined(CONFIG_USB_MUSB_AM35X)
550a7375
FB		 306/*
307 * Unload an endpoint's FIFO
308 */
309void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
310{
5c8a86e1 311 struct musb *musb = hw_ep->musb;
550a7375
FB		 312 void __iomem *fifo = hw_ep->fifo;
313
603fe2b2
AKG		 314 if (unlikely(len == 0))
315 return;
316
5c8a86e1 317 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 318 'R', hw_ep->epnum, fifo, len, dst);
319
320 /* we can't assume unaligned writes work */
321 if (likely((0x01 & (unsigned long) dst) == 0)) {
322 u16 index = 0;
323
324 /* best case is 32bit-aligned destination address */
325 if ((0x02 & (unsigned long) dst) == 0) {
326 if (len >= 4) {
327 readsl(fifo, dst, len >> 2);
328 index = len & ~0x03;
329 }
330 if (len & 0x02) {
331 *(u16 *)&dst[index] = musb_readw(fifo, 0);
332 index += 2;
333 }
334 } else {
335 if (len >= 2) {
336 readsw(fifo, dst, len >> 1);
337 index = len & ~0x01;
338 }
339 }
340 if (len & 0x01)
341 dst[index] = musb_readb(fifo, 0);
342 } else {
343 /* byte aligned */
344 readsb(fifo, dst, len);
345 }
346}
843bb1d0 347#endif
550a7375
FB		 348
349#endif /* normal PIO */
350
351
352/*-------------------------------------------------------------------------*/
353
354/* for high speed test mode; see USB 2.0 spec 7.1.20 */
355static const u8 musb_test_packet[53] = {
356 /* implicit SYNC then DATA0 to start */
357
358 /* JKJKJKJK x9 */
359 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
360 /* JJKKJJKK x8 */
361 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
362 /* JJJJKKKK x8 */
363 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
364 /* JJJJJJJKKKKKKK x8 */
365 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
366 /* JJJJJJJK x8 */
367 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
368 /* JKKKKKKK x10, JK */
369 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
370
371 /* implicit CRC16 then EOP to end */
372};
373
374void musb_load_testpacket(struct musb *musb)
375{
376 void __iomem *regs = musb->endpoints[0].regs;
377
378 musb_ep_select(musb->mregs, 0);
379 musb_write_fifo(musb->control_ep,
380 sizeof(musb_test_packet), musb_test_packet);
381 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
382}
383
384/*-------------------------------------------------------------------------*/
385
550a7375
FB		 386/*
387 * Handles OTG hnp timeouts, such as b_ase0_brst
388 */
a156544b 389static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 390{
391 struct musb *musb = (struct musb *)data;
392 unsigned long flags;
393
394 spin_lock_irqsave(&musb->lock, flags);
84e250ff 395 switch (musb->xceiv->state) {
550a7375 396 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 397 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 398 musb_g_disconnect(musb);
84e250ff 399 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 400 musb->is_active = 0;
401 break;
ab983f2a 402 case OTG_STATE_A_SUSPEND:
550a7375 403 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 404 dev_dbg(musb->controller, "HNP: %s timeout\n",
3df00453 405 otg_state_string(musb->xceiv->state));
743411b3 406 musb_platform_set_vbus(musb, 0);
ab983f2a 407 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 408 break;
409 default:
5c8a86e1 410 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
3df00453 411 otg_state_string(musb->xceiv->state));
550a7375
FB		 412 }
413 musb->ignore_disconnect = 0;
414 spin_unlock_irqrestore(&musb->lock, flags);
415}
416
550a7375 417/*
f7f9d63e 418 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 419 */
420void musb_hnp_stop(struct musb *musb)
421{
422 struct usb_hcd *hcd = musb_to_hcd(musb);
423 void __iomem *mbase = musb->mregs;
424 u8 reg;
425
5c8a86e1 426 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
ab983f2a 427
84e250ff 428 switch (musb->xceiv->state) {
550a7375 429 case OTG_STATE_A_PERIPHERAL:
550a7375 430 musb_g_disconnect(musb);
5c8a86e1 431 dev_dbg(musb->controller, "HNP: back to %s\n",
3df00453 432 otg_state_string(musb->xceiv->state));
550a7375
FB		 433 break;
434 case OTG_STATE_B_HOST:
5c8a86e1 435 dev_dbg(musb->controller, "HNP: Disabling HR\n");
550a7375 436 hcd->self.is_b_host = 0;
84e250ff 437 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 438 MUSB_DEV_MODE(musb);
439 reg = musb_readb(mbase, MUSB_POWER);
440 reg |= MUSB_POWER_SUSPENDM;
441 musb_writeb(mbase, MUSB_POWER, reg);
442 /* REVISIT: Start SESSION_REQUEST here? */
443 break;
444 default:
5c8a86e1 445 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
3df00453 446 otg_state_string(musb->xceiv->state));
550a7375
FB		 447 }
448
449 /*
450 * When returning to A state after HNP, avoid hub_port_rebounce(),
451 * which cause occasional OPT A "Did not receive reset after connect"
452 * errors.
453 */
749da5f8 454 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 455}
456
550a7375
FB		 457/*
458 * Interrupt Service Routine to record USB "global" interrupts.
459 * Since these do not happen often and signify things of
460 * paramount importance, it seems OK to check them individually;
461 * the order of the tests is specified in the manual
462 *
463 * @param musb instance pointer
464 * @param int_usb register contents
465 * @param devctl
466 * @param power
467 */
468
550a7375 469static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 470 u8 devctl)
550a7375 471{
d445b6da 472 struct usb_otg *otg = musb->xceiv->otg;
550a7375 473 irqreturn_t handled = IRQ_NONE;
550a7375 474
b11e94d0 475 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 476 int_usb);
477
478 /* in host mode, the peripheral may issue remote wakeup.
479 * in peripheral mode, the host may resume the link.
480 * spurious RESUME irqs happen too, paired with SUSPEND.
481 */
482 if (int_usb & MUSB_INTR_RESUME) {
483 handled = IRQ_HANDLED;
5c8a86e1 484 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
550a7375
FB		 485
486 if (devctl & MUSB_DEVCTL_HM) {
aa471456 487 void __iomem *mbase = musb->mregs;
b11e94d0 488 u8 power;
aa471456 489
84e250ff 490 switch (musb->xceiv->state) {
550a7375
FB		 491 case OTG_STATE_A_SUSPEND:
492 /* remote wakeup? later, GetPortStatus
493 * will stop RESUME signaling
494 */
495
b11e94d0 496 power = musb_readb(musb->mregs, MUSB_POWER);
550a7375
FB		 497 if (power & MUSB_POWER_SUSPENDM) {
498 /* spurious */
499 musb->int_usb &= ~MUSB_INTR_SUSPEND;
5c8a86e1 500 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
550a7375
FB		 501 break;
502 }
503
504 power &= ~MUSB_POWER_SUSPENDM;
505 musb_writeb(mbase, MUSB_POWER,
506 power | MUSB_POWER_RESUME);
507
508 musb->port1_status |=
509 (USB_PORT_STAT_C_SUSPEND << 16)
510 | MUSB_PORT_STAT_RESUME;
511 musb->rh_timer = jiffies
512 + msecs_to_jiffies(20);
513
84e250ff 514 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 515 musb->is_active = 1;
516 usb_hcd_resume_root_hub(musb_to_hcd(musb));
517 break;
518 case OTG_STATE_B_WAIT_ACON:
84e250ff 519 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 520 musb->is_active = 1;
521 MUSB_DEV_MODE(musb);
522 break;
523 default:
524 WARNING("bogus %s RESUME (%s)\n",
525 "host",
3df00453 526 otg_state_string(musb->xceiv->state));
550a7375 527 }
550a7375 528 } else {
84e250ff 529 switch (musb->xceiv->state) {
550a7375
FB		 530 case OTG_STATE_A_SUSPEND:
531 /* possibly DISCONNECT is upcoming */
84e250ff 532 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 533 usb_hcd_resume_root_hub(musb_to_hcd(musb));
534 break;
550a7375
FB		 535 case OTG_STATE_B_WAIT_ACON:
536 case OTG_STATE_B_PERIPHERAL:
537 /* disconnect while suspended? we may
538 * not get a disconnect irq...
539 */
540 if ((devctl & MUSB_DEVCTL_VBUS)
541 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
542 ) {
543 musb->int_usb |= MUSB_INTR_DISCONNECT;
544 musb->int_usb &= ~MUSB_INTR_SUSPEND;
545 break;
546 }
547 musb_g_resume(musb);
548 break;
549 case OTG_STATE_B_IDLE:
550 musb->int_usb &= ~MUSB_INTR_SUSPEND;
551 break;
550a7375
FB		 552 default:
553 WARNING("bogus %s RESUME (%s)\n",
554 "peripheral",
3df00453 555 otg_state_string(musb->xceiv->state));
550a7375
FB		 556 }
557 }
558 }
559
550a7375
FB		 560 /* see manual for the order of the tests */
561 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 562 void __iomem *mbase = musb->mregs;
563
19aab56c
HK		 564 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
565 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 566 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 567 return IRQ_HANDLED;
568 }
569
5c8a86e1 570 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
3df00453 571 otg_state_string(musb->xceiv->state));
550a7375
FB		 572
573 /* IRQ arrives from ID pin sense or (later, if VBUS power
574 * is removed) SRP. responses are time critical:
575 * - turn on VBUS (with silicon-specific mechanism)
576 * - go through A_WAIT_VRISE
577 * - ... to A_WAIT_BCON.
578 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
579 */
580 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
581 musb->ep0_stage = MUSB_EP0_START;
84e250ff 582 musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 583 MUSB_HST_MODE(musb);
743411b3 584 musb_platform_set_vbus(musb, 1);
550a7375
FB		 585
586 handled = IRQ_HANDLED;
587 }
588
589 if (int_usb & MUSB_INTR_VBUSERROR) {
590 int ignore = 0;
591
592 /* During connection as an A-Device, we may see a short
593 * current spikes causing voltage drop, because of cable
594 * and peripheral capacitance combined with vbus draw.
595 * (So: less common with truly self-powered devices, where
596 * vbus doesn't act like a power supply.)
597 *
598 * Such spikes are short; usually less than ~500 usec, max
599 * of ~2 msec. That is, they're not sustained overcurrent
600 * errors, though they're reported using VBUSERROR irqs.
601 *
602 * Workarounds: (a) hardware: use self powered devices.
603 * (b) software: ignore non-repeated VBUS errors.
604 *
605 * REVISIT: do delays from lots of DEBUG_KERNEL checks
606 * make trouble here, keeping VBUS < 4.4V ?
607 */
84e250ff 608 switch (musb->xceiv->state) {
550a7375
FB		 609 case OTG_STATE_A_HOST:
610 /* recovery is dicey once we've gotten past the
611 * initial stages of enumeration, but if VBUS
612 * stayed ok at the other end of the link, and
613 * another reset is due (at least for high speed,
614 * to redo the chirp etc), it might work OK...
615 */
616 case OTG_STATE_A_WAIT_BCON:
617 case OTG_STATE_A_WAIT_VRISE:
618 if (musb->vbuserr_retry) {
aa471456
FB		 619 void __iomem *mbase = musb->mregs;
620
550a7375
FB		 621 musb->vbuserr_retry--;
622 ignore = 1;
623 devctl |= MUSB_DEVCTL_SESSION;
624 musb_writeb(mbase, MUSB_DEVCTL, devctl);
625 } else {
626 musb->port1_status |=
749da5f8
AS		 627 USB_PORT_STAT_OVERCURRENT
628 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 629 }
630 break;
631 default:
632 break;
633 }
634
5c8a86e1 635 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
3df00453 636 otg_state_string(musb->xceiv->state),
550a7375
FB		 637 devctl,
638 ({ char *s;
639 switch (devctl & MUSB_DEVCTL_VBUS) {
640 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
641 s = "<SessEnd"; break;
642 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
643 s = "<AValid"; break;
644 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
645 s = "<VBusValid"; break;
646 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
647 default:
648 s = "VALID"; break;
649 }; s; }),
650 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
651 musb->port1_status);
652
653 /* go through A_WAIT_VFALL then start a new session */
654 if (!ignore)
743411b3 655 musb_platform_set_vbus(musb, 0);
550a7375
FB		 656 handled = IRQ_HANDLED;
657 }
658
1c25fda4 659 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0
SAS		 660 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
661 otg_state_string(musb->xceiv->state), devctl);
1c25fda4
AM		 662 handled = IRQ_HANDLED;
663
664 switch (musb->xceiv->state) {
1c25fda4
AM		 665 case OTG_STATE_A_PERIPHERAL:
666 /* We also come here if the cable is removed, since
667 * this silicon doesn't report ID-no-longer-grounded.
668 *
669 * We depend on T(a_wait_bcon) to shut us down, and
670 * hope users don't do anything dicey during this
671 * undesired detour through A_WAIT_BCON.
672 */
673 musb_hnp_stop(musb);
674 usb_hcd_resume_root_hub(musb_to_hcd(musb));
675 musb_root_disconnect(musb);
676 musb_platform_try_idle(musb, jiffies
677 + msecs_to_jiffies(musb->a_wait_bcon
678 ? : OTG_TIME_A_WAIT_BCON));
679
680 break;
1c25fda4
AM		 681 case OTG_STATE_B_IDLE:
682 if (!musb->is_active)
683 break;
684 case OTG_STATE_B_PERIPHERAL:
685 musb_g_suspend(musb);
032ec49f 686 musb->is_active = otg->gadget->b_hnp_enable;
1c25fda4 687 if (musb->is_active) {
1c25fda4 688 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 689 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 690 mod_timer(&musb->otg_timer, jiffies
691 + msecs_to_jiffies(
692 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 693 }
694 break;
695 case OTG_STATE_A_WAIT_BCON:
696 if (musb->a_wait_bcon != 0)
697 musb_platform_try_idle(musb, jiffies
698 + msecs_to_jiffies(musb->a_wait_bcon));
699 break;
700 case OTG_STATE_A_HOST:
701 musb->xceiv->state = OTG_STATE_A_SUSPEND;
032ec49f 702 musb->is_active = otg->host->b_hnp_enable;
1c25fda4
AM		 703 break;
704 case OTG_STATE_B_HOST:
705 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 706 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 707 break;
708 default:
709 /* "should not happen" */
710 musb->is_active = 0;
711 break;
712 }
713 }
714
550a7375
FB		 715 if (int_usb & MUSB_INTR_CONNECT) {
716 struct usb_hcd *hcd = musb_to_hcd(musb);
717
718 handled = IRQ_HANDLED;
719 musb->is_active = 1;
550a7375
FB		 720
721 musb->ep0_stage = MUSB_EP0_START;
722
550a7375
FB		 723 /* flush endpoints when transitioning from Device Mode */
724 if (is_peripheral_active(musb)) {
725 /* REVISIT HNP; just force disconnect */
726 }
d709d22e
AKG		 727 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
728 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
729 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 730 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
731 |USB_PORT_STAT_HIGH_SPEED
732 |USB_PORT_STAT_ENABLE
733 );
734 musb->port1_status |= USB_PORT_STAT_CONNECTION
735 |(USB_PORT_STAT_C_CONNECTION << 16);
736
737 /* high vs full speed is just a guess until after reset */
738 if (devctl & MUSB_DEVCTL_LSDEV)
739 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
740
550a7375 741 /* indicate new connection to OTG machine */
84e250ff 742 switch (musb->xceiv->state) {
550a7375
FB		 743 case OTG_STATE_B_PERIPHERAL:
744 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 745 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 746 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 747 goto b_host;
550a7375 748 } else
5c8a86e1 749 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 750 break;
751 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 752 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 753b_host:
84e250ff 754 musb->xceiv->state = OTG_STATE_B_HOST;
550a7375 755 hcd->self.is_b_host = 1;
1de00dae
DB		 756 musb->ignore_disconnect = 0;
757 del_timer(&musb->otg_timer);
550a7375
FB		 758 break;
759 default:
760 if ((devctl & MUSB_DEVCTL_VBUS)
761 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
84e250ff 762 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 763 hcd->self.is_b_host = 0;
764 }
765 break;
766 }
1de00dae
DB		 767
768 /* poke the root hub */
769 MUSB_HST_MODE(musb);
770 if (hcd->status_urb)
771 usb_hcd_poll_rh_status(hcd);
772 else
773 usb_hcd_resume_root_hub(hcd);
774
5c8a86e1 775 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
3df00453 776 otg_state_string(musb->xceiv->state), devctl);
550a7375 777 }
550a7375 778
1c25fda4 779 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
5c8a86e1 780 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
3df00453 781 otg_state_string(musb->xceiv->state),
1c25fda4
AM		 782 MUSB_MODE(musb), devctl);
783 handled = IRQ_HANDLED;
784
785 switch (musb->xceiv->state) {
1c25fda4
AM		 786 case OTG_STATE_A_HOST:
787 case OTG_STATE_A_SUSPEND:
788 usb_hcd_resume_root_hub(musb_to_hcd(musb));
789 musb_root_disconnect(musb);
032ec49f 790 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 791 musb_platform_try_idle(musb, jiffies
792 + msecs_to_jiffies(musb->a_wait_bcon));
793 break;
1c25fda4
AM		 794 case OTG_STATE_B_HOST:
795 /* REVISIT this behaves for "real disconnect"
796 * cases; make sure the other transitions from
797 * from B_HOST act right too. The B_HOST code
798 * in hnp_stop() is currently not used...
799 */
800 musb_root_disconnect(musb);
801 musb_to_hcd(musb)->self.is_b_host = 0;
802 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
803 MUSB_DEV_MODE(musb);
804 musb_g_disconnect(musb);
805 break;
806 case OTG_STATE_A_PERIPHERAL:
807 musb_hnp_stop(musb);
808 musb_root_disconnect(musb);
809 /* FALLTHROUGH */
810 case OTG_STATE_B_WAIT_ACON:
811 /* FALLTHROUGH */
1c25fda4
AM		 812 case OTG_STATE_B_PERIPHERAL:
813 case OTG_STATE_B_IDLE:
814 musb_g_disconnect(musb);
815 break;
1c25fda4
AM		 816 default:
817 WARNING("unhandled DISCONNECT transition (%s)\n",
3df00453 818 otg_state_string(musb->xceiv->state));
1c25fda4
AM		 819 break;
820 }
821 }
822
550a7375
FB		 823 /* mentor saves a bit: bus reset and babble share the same irq.
824 * only host sees babble; only peripheral sees bus reset.
825 */
826 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 827 handled = IRQ_HANDLED;
a04d46d0 828 if ((devctl & MUSB_DEVCTL_HM) != 0) {
550a7375
FB		 829 /*
830 * Looks like non-HS BABBLE can be ignored, but
831 * HS BABBLE is an error condition. For HS the solution
832 * is to avoid babble in the first place and fix what
833 * caused BABBLE. When HS BABBLE happens we can only
834 * stop the session.
835 */
836 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
5c8a86e1 837 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
550a7375
FB		 838 else {
839 ERR("Stopping host session -- babble\n");
1c25fda4 840 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 841 }
a04d46d0 842 } else {
5c8a86e1 843 dev_dbg(musb->controller, "BUS RESET as %s\n",
3df00453 844 otg_state_string(musb->xceiv->state));
84e250ff 845 switch (musb->xceiv->state) {
550a7375
FB		 846 case OTG_STATE_A_SUSPEND:
847 /* We need to ignore disconnect on suspend
848 * otherwise tusb 2.0 won't reconnect after a
849 * power cycle, which breaks otg compliance.
850 */
851 musb->ignore_disconnect = 1;
852 musb_g_reset(musb);
853 /* FALLTHROUGH */
854 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 855 /* never use invalid T(a_wait_bcon) */
5c8a86e1 856 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
3df00453
AG		 857 otg_state_string(musb->xceiv->state),
858 TA_WAIT_BCON(musb));
f7f9d63e
DB		 859 mod_timer(&musb->otg_timer, jiffies
860 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 861 break;
862 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 863 musb->ignore_disconnect = 0;
864 del_timer(&musb->otg_timer);
865 musb_g_reset(musb);
550a7375
FB		 866 break;
867 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 868 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
3df00453 869 otg_state_string(musb->xceiv->state));
84e250ff 870 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 871 musb_g_reset(musb);
872 break;
550a7375 873 case OTG_STATE_B_IDLE:
84e250ff 874 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 875 /* FALLTHROUGH */
876 case OTG_STATE_B_PERIPHERAL:
877 musb_g_reset(musb);
878 break;
879 default:
5c8a86e1 880 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
3df00453 881 otg_state_string(musb->xceiv->state));
550a7375
FB		 882 }
883 }
550a7375 884 }
550a7375
FB		 885
886#if 0
887/* REVISIT ... this would be for multiplexing periodic endpoints, or
888 * supporting transfer phasing to prevent exceeding ISO bandwidth
889 * limits of a given frame or microframe.
890 *
891 * It's not needed for peripheral side, which dedicates endpoints;
892 * though it _might_ use SOF irqs for other purposes.
893 *
894 * And it's not currently needed for host side, which also dedicates
895 * endpoints, relies on TX/RX interval registers, and isn't claimed
896 * to support ISO transfers yet.
897 */
898 if (int_usb & MUSB_INTR_SOF) {
899 void __iomem *mbase = musb->mregs;
900 struct musb_hw_ep *ep;
901 u8 epnum;
902 u16 frame;
903
5c8a86e1 904 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 905 handled = IRQ_HANDLED;
906
907 /* start any periodic Tx transfers waiting for current frame */
908 frame = musb_readw(mbase, MUSB_FRAME);
909 ep = musb->endpoints;
910 for (epnum = 1; (epnum < musb->nr_endpoints)
911 && (musb->epmask >= (1 << epnum));
912 epnum++, ep++) {
913 /*
914 * FIXME handle framecounter wraps (12 bits)
915 * eliminate duplicated StartUrb logic
916 */
917 if (ep->dwWaitFrame >= frame) {
918 ep->dwWaitFrame = 0;
919 pr_debug("SOF --> periodic TX%s on %d\n",
920 ep->tx_channel ? " DMA" : "",
921 epnum);
922 if (!ep->tx_channel)
923 musb_h_tx_start(musb, epnum);
924 else
925 cppi_hostdma_start(musb, epnum);
926 }
927 } /* end of for loop */
928 }
929#endif
930
1c25fda4 931 schedule_work(&musb->irq_work);
550a7375
FB		 932
933 return handled;
934}
935
936/*-------------------------------------------------------------------------*/
937
938/*
939* Program the HDRC to start (enable interrupts, dma, etc.).
940*/
941void musb_start(struct musb *musb)
942{
943 void __iomem *regs = musb->mregs;
944 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
945
5c8a86e1 946 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
550a7375
FB		 947
948 /* Set INT enable registers, enable interrupts */
949 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
950 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
951 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
952
953 musb_writeb(regs, MUSB_TESTMODE, 0);
954
955 /* put into basic highspeed mode and start session */
956 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
550a7375
FB		 957 | MUSB_POWER_HSENAB
958 /* ENSUSPEND wedges tusb */
959 /* | MUSB_POWER_ENSUSPEND */
960 );
961
962 musb->is_active = 0;
963 devctl = musb_readb(regs, MUSB_DEVCTL);
964 devctl &= ~MUSB_DEVCTL_SESSION;
965
032ec49f
FB		 966 /* session started after:
967 * (a) ID-grounded irq, host mode;
968 * (b) vbus present/connect IRQ, peripheral mode;
969 * (c) peripheral initiates, using SRP
970 */
971 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
972 musb->is_active = 1;
973 else
550a7375
FB		 974 devctl |= MUSB_DEVCTL_SESSION;
975
550a7375
FB		 976 musb_platform_enable(musb);
977 musb_writeb(regs, MUSB_DEVCTL, devctl);
978}
979
980
981static void musb_generic_disable(struct musb *musb)
982{
983 void __iomem *mbase = musb->mregs;
984 u16 temp;
985
986 /* disable interrupts */
987 musb_writeb(mbase, MUSB_INTRUSBE, 0);
988 musb_writew(mbase, MUSB_INTRTXE, 0);
989 musb_writew(mbase, MUSB_INTRRXE, 0);
990
991 /* off */
992 musb_writeb(mbase, MUSB_DEVCTL, 0);
993
994 /* flush pending interrupts */
995 temp = musb_readb(mbase, MUSB_INTRUSB);
996 temp = musb_readw(mbase, MUSB_INTRTX);
997 temp = musb_readw(mbase, MUSB_INTRRX);
998
999}
1000
1001/*
1002 * Make the HDRC stop (disable interrupts, etc.);
1003 * reversible by musb_start
1004 * called on gadget driver unregister
1005 * with controller locked, irqs blocked
1006 * acts as a NOP unless some role activated the hardware
1007 */
1008void musb_stop(struct musb *musb)
1009{
1010 /* stop IRQs, timers, ... */
1011 musb_platform_disable(musb);
1012 musb_generic_disable(musb);
5c8a86e1 1013 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 1014
1015 /* FIXME
1016 * - mark host and/or peripheral drivers unusable/inactive
1017 * - disable DMA (and enable it in HdrcStart)
1018 * - make sure we can musb_start() after musb_stop(); with
1019 * OTG mode, gadget driver module rmmod/modprobe cycles that
1020 * - ...
1021 */
1022 musb_platform_try_idle(musb, 0);
1023}
1024
1025static void musb_shutdown(struct platform_device *pdev)
1026{
1027 struct musb *musb = dev_to_musb(&pdev->dev);
1028 unsigned long flags;
1029
4f9edd2d 1030 pm_runtime_get_sync(musb->controller);
24307cae
GI		 1031
1032 musb_gadget_cleanup(musb);
1033
550a7375
FB		 1034 spin_lock_irqsave(&musb->lock, flags);
1035 musb_platform_disable(musb);
1036 musb_generic_disable(musb);
550a7375
FB		 1037 spin_unlock_irqrestore(&musb->lock, flags);
1038
120d074c
GI		 1039 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1040 musb_platform_exit(musb);
120d074c 1041
4f9edd2d 1042 pm_runtime_put(musb->controller);
550a7375
FB		 1043 /* FIXME power down */
1044}
1045
1046
1047/*-------------------------------------------------------------------------*/
1048
1049/*
1050 * The silicon either has hard-wired endpoint configurations, or else
1051 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1052 * writing only the dynamic sizing is very well tested. Since we switched
1053 * away from compile-time hardware parameters, we can no longer rely on
1054 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1055 *
1056 * We don't currently use dynamic fifo setup capability to do anything
1057 * more than selecting one of a bunch of predefined configurations.
1058 */
ee34e51a
FB		 1059#if defined(CONFIG_USB_MUSB_TUSB6010) \
1060 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1061 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1062 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1063 || defined(CONFIG_USB_MUSB_AM35X) \
9ecb8875
AKG		 1064 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1065 || defined(CONFIG_USB_MUSB_DSPS) \
1066 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
e9e8c85e 1067static ushort __devinitdata fifo_mode = 4;
ee34e51a
FB		 1068#elif defined(CONFIG_USB_MUSB_UX500) \
1069 || defined(CONFIG_USB_MUSB_UX500_MODULE)
e9e8c85e 1070static ushort __devinitdata fifo_mode = 5;
550a7375 1071#else
e9e8c85e 1072static ushort __devinitdata fifo_mode = 2;
550a7375
FB		 1073#endif
1074
1075/* "modprobe ... fifo_mode=1" etc */
1076module_param(fifo_mode, ushort, 0);
1077MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1078
550a7375
FB		 1079/*
1080 * tables defining fifo_mode values. define more if you like.
1081 * for host side, make sure both halves of ep1 are set up.
1082 */
1083
1084/* mode 0 - fits in 2KB */
e9e8c85e 1085static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
550a7375
FB		 1086{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1087{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1088{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1089{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1090{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1091};
1092
1093/* mode 1 - fits in 4KB */
e9e8c85e 1094static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
550a7375
FB		 1095{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1096{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1097{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1098{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1099{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1100};
1101
1102/* mode 2 - fits in 4KB */
e9e8c85e 1103static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
550a7375
FB		 1104{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1105{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1106{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1107{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1108{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1109{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1110};
1111
1112/* mode 3 - fits in 4KB */
e9e8c85e 1113static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
550a7375
FB		 1114{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1115{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1116{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1117{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1118{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1119{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1120};
1121
1122/* mode 4 - fits in 16KB */
e9e8c85e 1123static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
550a7375
FB		 1124{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1125{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1126{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1127{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1128{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1129{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1130{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1131{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1132{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1133{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1134{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1135{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1136{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1137{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1138{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1139{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1140{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1141{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1142{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1143{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1144{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1145{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1146{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1147{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1148{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1149{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1150{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1151};
1152
3b151526 1153/* mode 5 - fits in 8KB */
e9e8c85e 1154static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
3b151526
AKG		 1155{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1156{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1157{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1158{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1159{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1160{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1161{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1164{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1165{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1166{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1167{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1168{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1169{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1170{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1171{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1172{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1173{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1174{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1175{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1176{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1177{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1178{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1179{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1180{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1181{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1182};
550a7375
FB		 1183
1184/*
1185 * configure a fifo; for non-shared endpoints, this may be called
1186 * once for a tx fifo and once for an rx fifo.
1187 *
1188 * returns negative errno or offset for next fifo.
1189 */
e9e8c85e 1190static int __devinit
550a7375 1191fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1192 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1193{
1194 void __iomem *mbase = musb->mregs;
1195 int size = 0;
1196 u16 maxpacket = cfg->maxpacket;
1197 u16 c_off = offset >> 3;
1198 u8 c_size;
1199
1200 /* expect hw_ep has already been zero-initialized */
1201
1202 size = ffs(max(maxpacket, (u16) 8)) - 1;
1203 maxpacket = 1 << size;
1204
1205 c_size = size - 3;
1206 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1207 if ((offset + (maxpacket << 1)) >
1208 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1209 return -EMSGSIZE;
1210 c_size |= MUSB_FIFOSZ_DPB;
1211 } else {
ca6d1b13 1212 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1213 return -EMSGSIZE;
1214 }
1215
1216 /* configure the FIFO */
1217 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1218
550a7375
FB		 1219 /* EP0 reserved endpoint for control, bidirectional;
1220 * EP1 reserved for bulk, two unidirection halves.
1221 */
1222 if (hw_ep->epnum == 1)
1223 musb->bulk_ep = hw_ep;
1224 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1225 switch (cfg->style) {
1226 case FIFO_TX:
c6cf8b00
BW		 1227 musb_write_txfifosz(mbase, c_size);
1228 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1229 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1230 hw_ep->max_packet_sz_tx = maxpacket;
1231 break;
1232 case FIFO_RX:
c6cf8b00
BW		 1233 musb_write_rxfifosz(mbase, c_size);
1234 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1235 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1236 hw_ep->max_packet_sz_rx = maxpacket;
1237 break;
1238 case FIFO_RXTX:
c6cf8b00
BW		 1239 musb_write_txfifosz(mbase, c_size);
1240 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1241 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1242 hw_ep->max_packet_sz_rx = maxpacket;
1243
c6cf8b00
BW		 1244 musb_write_rxfifosz(mbase, c_size);
1245 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1246 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1247 hw_ep->max_packet_sz_tx = maxpacket;
1248
1249 hw_ep->is_shared_fifo = true;
1250 break;
1251 }
1252
1253 /* NOTE rx and tx endpoint irqs aren't managed separately,
1254 * which happens to be ok
1255 */
1256 musb->epmask |= (1 << hw_ep->epnum);
1257
1258 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1259}
1260
e9e8c85e 1261static struct musb_fifo_cfg __devinitdata ep0_cfg = {
550a7375
FB		 1262 .style = FIFO_RXTX, .maxpacket = 64,
1263};
1264
e9e8c85e 1265static int __devinit ep_config_from_table(struct musb *musb)
550a7375 1266{
e6c213b2 1267 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1268 unsigned i, n;
1269 int offset;
1270 struct musb_hw_ep *hw_ep = musb->endpoints;
1271
e6c213b2
FB		 1272 if (musb->config->fifo_cfg) {
1273 cfg = musb->config->fifo_cfg;
1274 n = musb->config->fifo_cfg_size;
1275 goto done;
1276 }
1277
550a7375
FB		 1278 switch (fifo_mode) {
1279 default:
1280 fifo_mode = 0;
1281 /* FALLTHROUGH */
1282 case 0:
1283 cfg = mode_0_cfg;
1284 n = ARRAY_SIZE(mode_0_cfg);
1285 break;
1286 case 1:
1287 cfg = mode_1_cfg;
1288 n = ARRAY_SIZE(mode_1_cfg);
1289 break;
1290 case 2:
1291 cfg = mode_2_cfg;
1292 n = ARRAY_SIZE(mode_2_cfg);
1293 break;
1294 case 3:
1295 cfg = mode_3_cfg;
1296 n = ARRAY_SIZE(mode_3_cfg);
1297 break;
1298 case 4:
1299 cfg = mode_4_cfg;
1300 n = ARRAY_SIZE(mode_4_cfg);
1301 break;
3b151526
AKG		 1302 case 5:
1303 cfg = mode_5_cfg;
1304 n = ARRAY_SIZE(mode_5_cfg);
1305 break;
550a7375
FB		 1306 }
1307
1308 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1309 musb_driver_name, fifo_mode);
1310
1311
e6c213b2 1312done:
550a7375
FB		 1313 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1314 /* assert(offset > 0) */
1315
1316 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1317 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1318 */
1319
1320 for (i = 0; i < n; i++) {
1321 u8 epn = cfg->hw_ep_num;
1322
ca6d1b13 1323 if (epn >= musb->config->num_eps) {
550a7375
FB		 1324 pr_debug("%s: invalid ep %d\n",
1325 musb_driver_name, epn);
bb1c9ef1 1326 return -EINVAL;
550a7375
FB		 1327 }
1328 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1329 if (offset < 0) {
1330 pr_debug("%s: mem overrun, ep %d\n",
1331 musb_driver_name, epn);
f69dfa1f 1332 return offset;
550a7375
FB		 1333 }
1334 epn++;
1335 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1336 }
1337
1338 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1339 musb_driver_name,
ca6d1b13
FB		 1340 n + 1, musb->config->num_eps * 2 - 1,
1341 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1342
550a7375
FB		 1343 if (!musb->bulk_ep) {
1344 pr_debug("%s: missing bulk\n", musb_driver_name);
1345 return -EINVAL;
1346 }
550a7375
FB		 1347
1348 return 0;
1349}
1350
1351
1352/*
1353 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1354 * @param musb the controller
1355 */
e9e8c85e 1356static int __devinit ep_config_from_hw(struct musb *musb)
550a7375 1357{
c6cf8b00 1358 u8 epnum = 0;
550a7375 1359 struct musb_hw_ep *hw_ep;
a156544b 1360 void __iomem *mbase = musb->mregs;
c6cf8b00 1361 int ret = 0;
550a7375 1362
5c8a86e1 1363 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1364
1365 /* FIXME pick up ep0 maxpacket size */
1366
ca6d1b13 1367 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1368 musb_ep_select(mbase, epnum);
1369 hw_ep = musb->endpoints + epnum;
1370
c6cf8b00
BW		 1371 ret = musb_read_fifosize(musb, hw_ep, epnum);
1372 if (ret < 0)
550a7375 1373 break;
550a7375
FB		 1374
1375 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1376
550a7375
FB		 1377 /* pick an RX/TX endpoint for bulk */
1378 if (hw_ep->max_packet_sz_tx < 512
1379 || hw_ep->max_packet_sz_rx < 512)
1380 continue;
1381
1382 /* REVISIT: this algorithm is lazy, we should at least
1383 * try to pick a double buffered endpoint.
1384 */
1385 if (musb->bulk_ep)
1386 continue;
1387 musb->bulk_ep = hw_ep;
550a7375
FB		 1388 }
1389
550a7375
FB		 1390 if (!musb->bulk_ep) {
1391 pr_debug("%s: missing bulk\n", musb_driver_name);
1392 return -EINVAL;
1393 }
550a7375
FB		 1394
1395 return 0;
1396}
1397
1398enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1399
1400/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1401 * configure endpoints, or take their config from silicon
1402 */
e9e8c85e 1403static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1404{
550a7375
FB		 1405 u8 reg;
1406 char *type;
0ea52ff4 1407 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1408 void __iomem *mbase = musb->mregs;
1409 int status = 0;
1410 int i;
1411
1412 /* log core options (read using indexed model) */
c6cf8b00 1413 reg = musb_read_configdata(mbase);
550a7375
FB		 1414
1415 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1416 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1417 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1418 musb->dyn_fifo = true;
1419 }
550a7375
FB		 1420 if (reg & MUSB_CONFIGDATA_MPRXE) {
1421 strcat(aInfo, ", bulk combine");
550a7375 1422 musb->bulk_combine = true;
550a7375
FB		 1423 }
1424 if (reg & MUSB_CONFIGDATA_MPTXE) {
1425 strcat(aInfo, ", bulk split");
550a7375 1426 musb->bulk_split = true;
550a7375
FB		 1427 }
1428 if (reg & MUSB_CONFIGDATA_HBRXE) {
1429 strcat(aInfo, ", HB-ISO Rx");
a483d706 1430 musb->hb_iso_rx = true;
550a7375
FB		 1431 }
1432 if (reg & MUSB_CONFIGDATA_HBTXE) {
1433 strcat(aInfo, ", HB-ISO Tx");
a483d706 1434 musb->hb_iso_tx = true;
550a7375
FB		 1435 }
1436 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1437 strcat(aInfo, ", SoftConn");
1438
1439 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1440 musb_driver_name, reg, aInfo);
1441
550a7375 1442 aDate[0] = 0;
550a7375
FB		 1443 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1444 musb->is_multipoint = 1;
1445 type = "M";
1446 } else {
1447 musb->is_multipoint = 0;
1448 type = "";
550a7375
FB		 1449#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1450 printk(KERN_ERR
1451 "%s: kernel must blacklist external hubs\n",
1452 musb_driver_name);
550a7375
FB		 1453#endif
1454 }
1455
1456 /* log release info */
32c3b94e
AG		 1457 musb->hwvers = musb_read_hwvers(mbase);
1458 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1459 MUSB_HWVERS_MINOR(musb->hwvers),
1460 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1461 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1462 musb_driver_name, type, aRevision, aDate);
1463
1464 /* configure ep0 */
c6cf8b00 1465 musb_configure_ep0(musb);
550a7375
FB		 1466
1467 /* discover endpoint configuration */
1468 musb->nr_endpoints = 1;
1469 musb->epmask = 1;
1470
ad517e9e
FB		 1471 if (musb->dyn_fifo)
1472 status = ep_config_from_table(musb);
1473 else
1474 status = ep_config_from_hw(musb);
550a7375
FB		 1475
1476 if (status < 0)
1477 return status;
1478
1479 /* finish init, and print endpoint config */
1480 for (i = 0; i < musb->nr_endpoints; i++) {
1481 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1482
1483 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
9a35f876 1484#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
550a7375
FB		 1485 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1486 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1487 hw_ep->fifo_sync_va =
1488 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1489
1490 if (i == 0)
1491 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1492 else
1493 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1494#endif
1495
1496 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
c6cf8b00 1497 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1498 hw_ep->rx_reinit = 1;
1499 hw_ep->tx_reinit = 1;
550a7375
FB		 1500
1501 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1502 dev_dbg(musb->controller,
550a7375
FB		 1503 "%s: hw_ep %d%s, %smax %d\n",
1504 musb_driver_name, i,
1505 hw_ep->is_shared_fifo ? "shared" : "tx",
1506 hw_ep->tx_double_buffered
1507 ? "doublebuffer, " : "",
1508 hw_ep->max_packet_sz_tx);
1509 }
1510 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1511 dev_dbg(musb->controller,
550a7375
FB		 1512 "%s: hw_ep %d%s, %smax %d\n",
1513 musb_driver_name, i,
1514 "rx",
1515 hw_ep->rx_double_buffered
1516 ? "doublebuffer, " : "",
1517 hw_ep->max_packet_sz_rx);
1518 }
1519 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1520 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1521 }
1522
1523 return 0;
1524}
1525
1526/*-------------------------------------------------------------------------*/
1527
59b479e0 1528#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
d0678594 1529 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
550a7375
FB		 1530
1531static irqreturn_t generic_interrupt(int irq, void *__hci)
1532{
1533 unsigned long flags;
1534 irqreturn_t retval = IRQ_NONE;
1535 struct musb *musb = __hci;
1536
1537 spin_lock_irqsave(&musb->lock, flags);
1538
1539 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1540 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1541 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1542
1543 if (musb->int_usb || musb->int_tx || musb->int_rx)
1544 retval = musb_interrupt(musb);
1545
1546 spin_unlock_irqrestore(&musb->lock, flags);
1547
a5073b52 1548 return retval;
550a7375
FB		 1549}
1550
1551#else
1552#define generic_interrupt NULL
1553#endif
1554
1555/*
1556 * handle all the irqs defined by the HDRC core. for now we expect: other
1557 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1558 * will be assigned, and the irq will already have been acked.
1559 *
1560 * called in irq context with spinlock held, irqs blocked
1561 */
1562irqreturn_t musb_interrupt(struct musb *musb)
1563{
1564 irqreturn_t retval = IRQ_NONE;
b11e94d0 1565 u8 devctl;
550a7375
FB		 1566 int ep_num;
1567 u32 reg;
1568
1569 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1570
5c8a86e1 1571 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
550a7375
FB		 1572 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1573 musb->int_usb, musb->int_tx, musb->int_rx);
1574
1575 /* the core can interrupt us for multiple reasons; docs have
1576 * a generic interrupt flowchart to follow
1577 */
7d9645fd 1578 if (musb->int_usb)
550a7375 1579 retval |= musb_stage0_irq(musb, musb->int_usb,
b11e94d0 1580 devctl);
550a7375
FB		 1581
1582 /* "stage 1" is handling endpoint irqs */
1583
1584 /* handle endpoint 0 first */
1585 if (musb->int_tx & 1) {
1586 if (devctl & MUSB_DEVCTL_HM)
1587 retval |= musb_h_ep0_irq(musb);
1588 else
1589 retval |= musb_g_ep0_irq(musb);
1590 }
1591
1592 /* RX on endpoints 1-15 */
1593 reg = musb->int_rx >> 1;
1594 ep_num = 1;
1595 while (reg) {
1596 if (reg & 1) {
1597 /* musb_ep_select(musb->mregs, ep_num); */
1598 /* REVISIT just retval = ep->rx_irq(...) */
1599 retval = IRQ_HANDLED;
a04d46d0
FB		 1600 if (devctl & MUSB_DEVCTL_HM)
1601 musb_host_rx(musb, ep_num);
1602 else
1603 musb_g_rx(musb, ep_num);
550a7375
FB		 1604 }
1605
1606 reg >>= 1;
1607 ep_num++;
1608 }
1609
1610 /* TX on endpoints 1-15 */
1611 reg = musb->int_tx >> 1;
1612 ep_num = 1;
1613 while (reg) {
1614 if (reg & 1) {
1615 /* musb_ep_select(musb->mregs, ep_num); */
1616 /* REVISIT just retval |= ep->tx_irq(...) */
1617 retval = IRQ_HANDLED;
a04d46d0
FB		 1618 if (devctl & MUSB_DEVCTL_HM)
1619 musb_host_tx(musb, ep_num);
1620 else
1621 musb_g_tx(musb, ep_num);
550a7375
FB		 1622 }
1623 reg >>= 1;
1624 ep_num++;
1625 }
1626
550a7375
FB		 1627 return retval;
1628}
981430a1 1629EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1630
1631#ifndef CONFIG_MUSB_PIO_ONLY
e9e8c85e 1632static bool __devinitdata use_dma = 1;
550a7375
FB		 1633
1634/* "modprobe ... use_dma=0" etc */
1635module_param(use_dma, bool, 0);
1636MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1637
1638void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1639{
1640 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1641
1642 /* called with controller lock already held */
1643
1644 if (!epnum) {
1645#ifndef CONFIG_USB_TUSB_OMAP_DMA
1646 if (!is_cppi_enabled()) {
1647 /* endpoint 0 */
1648 if (devctl & MUSB_DEVCTL_HM)
1649 musb_h_ep0_irq(musb);
1650 else
1651 musb_g_ep0_irq(musb);
1652 }
1653#endif
1654 } else {
1655 /* endpoints 1..15 */
1656 if (transmit) {
a04d46d0
FB		 1657 if (devctl & MUSB_DEVCTL_HM)
1658 musb_host_tx(musb, epnum);
1659 else
1660 musb_g_tx(musb, epnum);
550a7375
FB		 1661 } else {
1662 /* receive */
a04d46d0
FB		 1663 if (devctl & MUSB_DEVCTL_HM)
1664 musb_host_rx(musb, epnum);
1665 else
1666 musb_g_rx(musb, epnum);
550a7375
FB		 1667 }
1668 }
1669}
9a35f876 1670EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1671
1672#else
1673#define use_dma 0
1674#endif
1675
1676/*-------------------------------------------------------------------------*/
1677
1678#ifdef CONFIG_SYSFS
1679
1680static ssize_t
1681musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1682{
1683 struct musb *musb = dev_to_musb(dev);
1684 unsigned long flags;
1685 int ret = -EINVAL;
1686
1687 spin_lock_irqsave(&musb->lock, flags);
3df00453 1688 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
550a7375
FB		 1689 spin_unlock_irqrestore(&musb->lock, flags);
1690
1691 return ret;
1692}
1693
1694static ssize_t
1695musb_mode_store(struct device *dev, struct device_attribute *attr,
1696 const char *buf, size_t n)
1697{
1698 struct musb *musb = dev_to_musb(dev);
1699 unsigned long flags;
96a274d1 1700 int status;
550a7375
FB		 1701
1702 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1703 if (sysfs_streq(buf, "host"))
1704 status = musb_platform_set_mode(musb, MUSB_HOST);
1705 else if (sysfs_streq(buf, "peripheral"))
1706 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1707 else if (sysfs_streq(buf, "otg"))
1708 status = musb_platform_set_mode(musb, MUSB_OTG);
1709 else
1710 status = -EINVAL;
550a7375
FB		 1711 spin_unlock_irqrestore(&musb->lock, flags);
1712
96a274d1 1713 return (status == 0) ? n : status;
550a7375
FB		 1714}
1715static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1716
1717static ssize_t
1718musb_vbus_store(struct device *dev, struct device_attribute *attr,
1719 const char *buf, size_t n)
1720{
1721 struct musb *musb = dev_to_musb(dev);
1722 unsigned long flags;
1723 unsigned long val;
1724
1725 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1726 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1727 return -EINVAL;
1728 }
1729
1730 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1731 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1732 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
84e250ff 1733 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1734 musb->is_active = 0;
1735 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1736 spin_unlock_irqrestore(&musb->lock, flags);
1737
1738 return n;
1739}
1740
1741static ssize_t
1742musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1743{
1744 struct musb *musb = dev_to_musb(dev);
1745 unsigned long flags;
1746 unsigned long val;
1747 int vbus;
1748
1749 spin_lock_irqsave(&musb->lock, flags);
1750 val = musb->a_wait_bcon;
f7f9d63e
DB		 1751 /* FIXME get_vbus_status() is normally #defined as false...
1752 * and is effectively TUSB-specific.
1753 */
550a7375
FB		 1754 vbus = musb_platform_get_vbus_status(musb);
1755 spin_unlock_irqrestore(&musb->lock, flags);
1756
f7f9d63e 1757 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1758 vbus ? "on" : "off", val);
1759}
1760static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1761
550a7375
FB		 1762/* Gadget drivers can't know that a host is connected so they might want
1763 * to start SRP, but users can. This allows userspace to trigger SRP.
1764 */
1765static ssize_t
1766musb_srp_store(struct device *dev, struct device_attribute *attr,
1767 const char *buf, size_t n)
1768{
1769 struct musb *musb = dev_to_musb(dev);
1770 unsigned short srp;
1771
1772 if (sscanf(buf, "%hu", &srp) != 1
1773 || (srp != 1)) {
b3b1cc3b 1774 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1775 return -EINVAL;
1776 }
1777
1778 if (srp == 1)
1779 musb_g_wakeup(musb);
1780
1781 return n;
1782}
1783static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1784
94375751
FB		 1785static struct attribute *musb_attributes[] = {
1786 &dev_attr_mode.attr,
1787 &dev_attr_vbus.attr,
94375751 1788 &dev_attr_srp.attr,
94375751
FB		 1789 NULL
1790};
1791
1792static const struct attribute_group musb_attr_group = {
1793 .attrs = musb_attributes,
1794};
1795
550a7375
FB		 1796#endif /* sysfs */
1797
1798/* Only used to provide driver mode change events */
1799static void musb_irq_work(struct work_struct *data)
1800{
1801 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1802
8d2421e6
AKG		 1803 if (musb->xceiv->state != musb->xceiv_old_state) {
1804 musb->xceiv_old_state = musb->xceiv->state;
550a7375
FB		 1805 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1806 }
1807}
1808
1809/* --------------------------------------------------------------------------
1810 * Init support
1811 */
1812
e9e8c85e 1813static struct musb *__devinit
ca6d1b13
FB		 1814allocate_instance(struct device *dev,
1815 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1816{
1817 struct musb *musb;
1818 struct musb_hw_ep *ep;
1819 int epnum;
550a7375
FB		 1820 struct usb_hcd *hcd;
1821
427c4f33 1822 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
550a7375
FB		 1823 if (!hcd)
1824 return NULL;
1825 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1826
1827 musb = hcd_to_musb(hcd);
1828 INIT_LIST_HEAD(&musb->control);
1829 INIT_LIST_HEAD(&musb->in_bulk);
1830 INIT_LIST_HEAD(&musb->out_bulk);
1831
1832 hcd->uses_new_polling = 1;
ec95d35a 1833 hcd->has_tt = 1;
550a7375
FB		 1834
1835 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1836 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
456bb169 1837 dev_set_drvdata(dev, musb);
550a7375
FB		 1838 musb->mregs = mbase;
1839 musb->ctrl_base = mbase;
1840 musb->nIrq = -ENODEV;
ca6d1b13 1841 musb->config = config;
02582b92 1842 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1843 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1844 epnum < musb->config->num_eps;
550a7375 1845 epnum++, ep++) {
550a7375
FB		 1846 ep->musb = musb;
1847 ep->epnum = epnum;
1848 }
1849
1850 musb->controller = dev;
743411b3 1851
550a7375
FB		 1852 return musb;
1853}
1854
1855static void musb_free(struct musb *musb)
1856{
1857 /* this has multiple entry modes. it handles fault cleanup after
1858 * probe(), where things may be partially set up, as well as rmmod
1859 * cleanup after everything's been de-activated.
1860 */
1861
1862#ifdef CONFIG_SYSFS
94375751 1863 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1864#endif
1865
97a39896
AKG		 1866 if (musb->nIrq >= 0) {
1867 if (musb->irq_wake)
1868 disable_irq_wake(musb->nIrq);
550a7375
FB		 1869 free_irq(musb->nIrq, musb);
1870 }
1871 if (is_dma_capable() && musb->dma_controller) {
1872 struct dma_controller *c = musb->dma_controller;
1873
1874 (void) c->stop(c);
1875 dma_controller_destroy(c);
1876 }
1877
decadacb 1878 usb_put_hcd(musb_to_hcd(musb));
550a7375
FB		 1879}
1880
1881/*
1882 * Perform generic per-controller initialization.
1883 *
28dd924a
SS		 1884 * @dev: the controller (already clocked, etc)
1885 * @nIrq: IRQ number
1886 * @ctrl: virtual address of controller registers,
550a7375
FB		 1887 * not yet corrected for platform-specific offsets
1888 */
e9e8c85e 1889static int __devinit
550a7375
FB		 1890musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1891{
1892 int status;
1893 struct musb *musb;
1894 struct musb_hdrc_platform_data *plat = dev->platform_data;
032ec49f 1895 struct usb_hcd *hcd;
550a7375
FB		 1896
1897 /* The driver might handle more features than the board; OK.
1898 * Fail when the board needs a feature that's not enabled.
1899 */
1900 if (!plat) {
1901 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 1902 status = -ENODEV;
1903 goto fail0;
550a7375 1904 }
34e2beb2 1905
550a7375 1906 /* allocate */
ca6d1b13 1907 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 1908 if (!musb) {
1909 status = -ENOMEM;
1910 goto fail0;
1911 }
550a7375 1912
7acc6197
HH		 1913 pm_runtime_use_autosuspend(musb->controller);
1914 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1915 pm_runtime_enable(musb->controller);
1916
550a7375 1917 spin_lock_init(&musb->lock);
550a7375 1918 musb->board_set_power = plat->set_power;
550a7375 1919 musb->min_power = plat->min_power;
f7ec9437 1920 musb->ops = plat->platform_ops;
550a7375 1921
84e250ff
DB		 1922 /* The musb_platform_init() call:
1923 * - adjusts musb->mregs and musb->isr if needed,
1924 * - may initialize an integrated tranceiver
721002ec 1925 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 1926 * - stops powering VBUS
84e250ff 1927 *
7c9d440e 1928 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 1929 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1930 * external/discrete ones in various flavors (twl4030 family,
1931 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375
FB		 1932 */
1933 musb->isr = generic_interrupt;
ea65df57 1934 status = musb_platform_init(musb);
550a7375 1935 if (status < 0)
03491761 1936 goto fail1;
34e2beb2 1937
550a7375
FB		 1938 if (!musb->isr) {
1939 status = -ENODEV;
c04352a5 1940 goto fail2;
550a7375
FB		 1941 }
1942
ffb865b1 1943 if (!musb->xceiv->io_ops) {
bf070bc1 1944 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 1945 musb->xceiv->io_priv = musb->mregs;
1946 musb->xceiv->io_ops = &musb_ulpi_access;
1947 }
1948
c04352a5
GI		 1949 pm_runtime_get_sync(musb->controller);
1950
550a7375
FB		 1951#ifndef CONFIG_MUSB_PIO_ONLY
1952 if (use_dma && dev->dma_mask) {
1953 struct dma_controller *c;
1954
1955 c = dma_controller_create(musb, musb->mregs);
1956 musb->dma_controller = c;
1957 if (c)
1958 (void) c->start(c);
1959 }
1960#endif
1961 /* ideally this would be abstracted in platform setup */
1962 if (!is_dma_capable() || !musb->dma_controller)
1963 dev->dma_mask = NULL;
1964
1965 /* be sure interrupts are disabled before connecting ISR */
1966 musb_platform_disable(musb);
1967 musb_generic_disable(musb);
1968
1969 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 1970 status = musb_core_init(plat->config->multipoint
550a7375
FB		 1971 ? MUSB_CONTROLLER_MHDRC
1972 : MUSB_CONTROLLER_HDRC, musb);
1973 if (status < 0)
34e2beb2 1974 goto fail3;
550a7375 1975
f7f9d63e 1976 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 1977
550a7375
FB		 1978 /* Init IRQ workqueue before request_irq */
1979 INIT_WORK(&musb->irq_work, musb_irq_work);
1980
1981 /* attach to the IRQ */
427c4f33 1982 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 1983 dev_err(dev, "request_irq %d failed!\n", nIrq);
1984 status = -ENODEV;
34e2beb2 1985 goto fail3;
550a7375
FB		 1986 }
1987 musb->nIrq = nIrq;
032ec49f 1988 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 1989 if (enable_irq_wake(nIrq) == 0) {
1990 musb->irq_wake = 1;
550a7375 1991 device_init_wakeup(dev, 1);
c48a5155
FB		 1992 } else {
1993 musb->irq_wake = 0;
1994 }
550a7375 1995
84e250ff 1996 /* host side needs more setup */
032ec49f
FB		 1997 hcd = musb_to_hcd(musb);
1998 otg_set_host(musb->xceiv->otg, &hcd->self);
1999 hcd->self.otg_port = 1;
2000 musb->xceiv->otg->host = &hcd->self;
2001 hcd->power_budget = 2 * (plat->power ? : 250);
2002
2003 /* program PHY to use external vBus if required */
2004 if (plat->extvbus) {
2005 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2006 busctl |= MUSB_ULPI_USE_EXTVBUS;
2007 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2008 }
550a7375 2009
032ec49f
FB		 2010 MUSB_DEV_MODE(musb);
2011 musb->xceiv->otg->default_a = 0;
2012 musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 2013
032ec49f 2014 status = musb_gadget_setup(musb);
550a7375 2015
461972d8 2016 if (status < 0)
34e2beb2 2017 goto fail3;
550a7375 2018
7f7f9e2a
FB		 2019 status = musb_init_debugfs(musb);
2020 if (status < 0)
b0f9da7e 2021 goto fail4;
7f7f9e2a 2022
550a7375 2023#ifdef CONFIG_SYSFS
94375751 2024 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2025 if (status)
b0f9da7e 2026 goto fail5;
461972d8 2027#endif
550a7375 2028
c04352a5
GI		 2029 pm_runtime_put(musb->controller);
2030
28c2c51c 2031 return 0;
550a7375 2032
b0f9da7e
FB		 2033fail5:
2034 musb_exit_debugfs(musb);
2035
34e2beb2 2036fail4:
032ec49f 2037 musb_gadget_cleanup(musb);
34e2beb2
SS		 2038
2039fail3:
c04352a5
GI		 2040 pm_runtime_put_sync(musb->controller);
2041
2042fail2:
34e2beb2
SS		 2043 if (musb->irq_wake)
2044 device_init_wakeup(dev, 0);
550a7375 2045 musb_platform_exit(musb);
28c2c51c 2046
34e2beb2
SS		 2047fail1:
2048 dev_err(musb->controller,
2049 "musb_init_controller failed with status %d\n", status);
2050
28c2c51c
FB		 2051 musb_free(musb);
2052
34e2beb2
SS		 2053fail0:
2054
28c2c51c
FB		 2055 return status;
2056
550a7375
FB		 2057}
2058
2059/*-------------------------------------------------------------------------*/
2060
2061/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2062 * bridge to a platform device; this driver then suffices.
2063 */
e9e8c85e 2064static int __devinit musb_probe(struct platform_device *pdev)
550a7375
FB		 2065{
2066 struct device *dev = &pdev->dev;
fcf173e4 2067 int irq = platform_get_irq_byname(pdev, "mc");
da5108e1 2068 int status;
550a7375
FB		 2069 struct resource *iomem;
2070 void __iomem *base;
2071
2072 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
541079de 2073 if (!iomem || irq <= 0)
550a7375
FB		 2074 return -ENODEV;
2075
195e9e46 2076 base = ioremap(iomem->start, resource_size(iomem));
550a7375
FB		 2077 if (!base) {
2078 dev_err(dev, "ioremap failed\n");
2079 return -ENOMEM;
2080 }
2081
da5108e1
FB		 2082 status = musb_init_controller(dev, irq, base);
2083 if (status < 0)
2084 iounmap(base);
2085
2086 return status;
550a7375
FB		 2087}
2088
e9e8c85e 2089static int __devexit musb_remove(struct platform_device *pdev)
550a7375 2090{
8d2421e6
AKG		 2091 struct device *dev = &pdev->dev;
2092 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2093 void __iomem *ctrl_base = musb->ctrl_base;
2094
2095 /* this gets called on rmmod.
2096 * - Host mode: host may still be active
2097 * - Peripheral mode: peripheral is deactivated (or never-activated)
2098 * - OTG mode: both roles are deactivated (or never-activated)
2099 */
7f7f9e2a 2100 musb_exit_debugfs(musb);
550a7375 2101 musb_shutdown(pdev);
461972d8 2102
550a7375
FB		 2103 musb_free(musb);
2104 iounmap(ctrl_base);
8d2421e6 2105 device_init_wakeup(dev, 0);
550a7375 2106#ifndef CONFIG_MUSB_PIO_ONLY
8d2421e6 2107 dma_set_mask(dev, *dev->parent->dma_mask);
550a7375
FB		 2108#endif
2109 return 0;
2110}
2111
2112#ifdef CONFIG_PM
2113
3c8a5fcc 2114static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2115{
2116 int i;
2117 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2118 void __iomem *epio;
4f712e01 2119
032ec49f
FB		 2120 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2121 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2122 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b
FB		 2123 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2124 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2125 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2126 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2127 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2128 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2129
ae9b2ad2 2130 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2131 struct musb_hw_ep *hw_ep;
2132
2133 hw_ep = &musb->endpoints[i];
2134 if (!hw_ep)
2135 continue;
2136
2137 epio = hw_ep->regs;
2138 if (!epio)
2139 continue;
2140
ea737554 2141 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2142 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2143 musb_readw(epio, MUSB_TXMAXP);
7421107b 2144 musb->context.index_regs[i].txcsr =
ae9b2ad2 2145 musb_readw(epio, MUSB_TXCSR);
7421107b 2146 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2147 musb_readw(epio, MUSB_RXMAXP);
7421107b 2148 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2149 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2150
2151 if (musb->dyn_fifo) {
7421107b 2152 musb->context.index_regs[i].txfifoadd =
4f712e01 2153 musb_read_txfifoadd(musb_base);
7421107b 2154 musb->context.index_regs[i].rxfifoadd =
4f712e01 2155 musb_read_rxfifoadd(musb_base);
7421107b 2156 musb->context.index_regs[i].txfifosz =
4f712e01 2157 musb_read_txfifosz(musb_base);
7421107b 2158 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2159 musb_read_rxfifosz(musb_base);
2160 }
032ec49f
FB		 2161
2162 musb->context.index_regs[i].txtype =
2163 musb_readb(epio, MUSB_TXTYPE);
2164 musb->context.index_regs[i].txinterval =
2165 musb_readb(epio, MUSB_TXINTERVAL);
2166 musb->context.index_regs[i].rxtype =
2167 musb_readb(epio, MUSB_RXTYPE);
2168 musb->context.index_regs[i].rxinterval =
2169 musb_readb(epio, MUSB_RXINTERVAL);
2170
2171 musb->context.index_regs[i].txfunaddr =
2172 musb_read_txfunaddr(musb_base, i);
2173 musb->context.index_regs[i].txhubaddr =
2174 musb_read_txhubaddr(musb_base, i);
2175 musb->context.index_regs[i].txhubport =
2176 musb_read_txhubport(musb_base, i);
2177
2178 musb->context.index_regs[i].rxfunaddr =
2179 musb_read_rxfunaddr(musb_base, i);
2180 musb->context.index_regs[i].rxhubaddr =
2181 musb_read_rxhubaddr(musb_base, i);
2182 musb->context.index_regs[i].rxhubport =
2183 musb_read_rxhubport(musb_base, i);
4f712e01 2184 }
4f712e01
AKG		 2185}
2186
3c8a5fcc 2187static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2188{
2189 int i;
2190 void __iomem *musb_base = musb->mregs;
2191 void __iomem *ep_target_regs;
ae9b2ad2 2192 void __iomem *epio;
4f712e01 2193
032ec49f
FB		 2194 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2195 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2196 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
7421107b
FB		 2197 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2198 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2199 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2200 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2201 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2202
ae9b2ad2 2203 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2204 struct musb_hw_ep *hw_ep;
2205
2206 hw_ep = &musb->endpoints[i];
2207 if (!hw_ep)
2208 continue;
2209
2210 epio = hw_ep->regs;
2211 if (!epio)
2212 continue;
2213
ea737554 2214 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2215 musb_writew(epio, MUSB_TXMAXP,
7421107b 2216 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2217 musb_writew(epio, MUSB_TXCSR,
7421107b 2218 musb->context.index_regs[i].txcsr);
ae9b2ad2 2219 musb_writew(epio, MUSB_RXMAXP,
7421107b 2220 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2221 musb_writew(epio, MUSB_RXCSR,
7421107b 2222 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2223
2224 if (musb->dyn_fifo) {
2225 musb_write_txfifosz(musb_base,
7421107b 2226 musb->context.index_regs[i].txfifosz);
4f712e01 2227 musb_write_rxfifosz(musb_base,
7421107b 2228 musb->context.index_regs[i].rxfifosz);
4f712e01 2229 musb_write_txfifoadd(musb_base,
7421107b 2230 musb->context.index_regs[i].txfifoadd);
4f712e01 2231 musb_write_rxfifoadd(musb_base,
7421107b 2232 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2233 }
2234
032ec49f 2235 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2236 musb->context.index_regs[i].txtype);
032ec49f 2237 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2238 musb->context.index_regs[i].txinterval);
032ec49f 2239 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2240 musb->context.index_regs[i].rxtype);
032ec49f 2241 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2242
032ec49f
FB		 2243 musb->context.index_regs[i].rxinterval);
2244 musb_write_txfunaddr(musb_base, i,
7421107b 2245 musb->context.index_regs[i].txfunaddr);
032ec49f 2246 musb_write_txhubaddr(musb_base, i,
7421107b 2247 musb->context.index_regs[i].txhubaddr);
032ec49f 2248 musb_write_txhubport(musb_base, i,
7421107b 2249 musb->context.index_regs[i].txhubport);
4f712e01 2250
032ec49f
FB		 2251 ep_target_regs =
2252 musb_read_target_reg_base(i, musb_base);
4f712e01 2253
032ec49f 2254 musb_write_rxfunaddr(ep_target_regs,
7421107b 2255 musb->context.index_regs[i].rxfunaddr);
032ec49f 2256 musb_write_rxhubaddr(ep_target_regs,
7421107b 2257 musb->context.index_regs[i].rxhubaddr);
032ec49f 2258 musb_write_rxhubport(ep_target_regs,
7421107b 2259 musb->context.index_regs[i].rxhubport);
4f712e01 2260 }
3c5fec75 2261 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2262}
2263
48fea965 2264static int musb_suspend(struct device *dev)
550a7375 2265{
8220796d 2266 struct musb *musb = dev_to_musb(dev);
550a7375 2267 unsigned long flags;
550a7375 2268
550a7375
FB		 2269 spin_lock_irqsave(&musb->lock, flags);
2270
2271 if (is_peripheral_active(musb)) {
2272 /* FIXME force disconnect unless we know USB will wake
2273 * the system up quickly enough to respond ...
2274 */
2275 } else if (is_host_active(musb)) {
2276 /* we know all the children are suspended; sometimes
2277 * they will even be wakeup-enabled.
2278 */
2279 }
2280
550a7375
FB		 2281 spin_unlock_irqrestore(&musb->lock, flags);
2282 return 0;
2283}
2284
48fea965 2285static int musb_resume_noirq(struct device *dev)
550a7375 2286{
550a7375 2287 /* for static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2288 * unless for some reason the whole soc powered down or the USB
2289 * module got reset through the PSC (vs just being disabled).
550a7375 2290 */
550a7375
FB		 2291 return 0;
2292}
2293
7acc6197
HH		 2294static int musb_runtime_suspend(struct device *dev)
2295{
2296 struct musb *musb = dev_to_musb(dev);
2297
2298 musb_save_context(musb);
2299
2300 return 0;
2301}
2302
2303static int musb_runtime_resume(struct device *dev)
2304{
2305 struct musb *musb = dev_to_musb(dev);
2306 static int first = 1;
2307
2308 /*
2309 * When pm_runtime_get_sync called for the first time in driver
2310 * init, some of the structure is still not initialized which is
2311 * used in restore function. But clock needs to be
2312 * enabled before any register access, so
2313 * pm_runtime_get_sync has to be called.
2314 * Also context restore without save does not make
2315 * any sense
2316 */
2317 if (!first)
2318 musb_restore_context(musb);
2319 first = 0;
2320
2321 return 0;
2322}
2323
47145210 2324static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965
MD		 2325 .suspend = musb_suspend,
2326 .resume_noirq = musb_resume_noirq,
7acc6197
HH		 2327 .runtime_suspend = musb_runtime_suspend,
2328 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2329};
2330
2331#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2332#else
48fea965 2333#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2334#endif
2335
2336static struct platform_driver musb_driver = {
2337 .driver = {
2338 .name = (char *)musb_driver_name,
2339 .bus = &platform_bus_type,
2340 .owner = THIS_MODULE,
48fea965 2341 .pm = MUSB_DEV_PM_OPS,
550a7375 2342 },
e9e8c85e
FB		 2343 .probe = musb_probe,
2344 .remove = __devexit_p(musb_remove),
550a7375 2345 .shutdown = musb_shutdown,
550a7375
FB		 2346};
2347
2348/*-------------------------------------------------------------------------*/
2349
2350static int __init musb_init(void)
2351{
550a7375
FB		 2352 if (usb_disabled())
2353 return 0;
550a7375
FB		 2354
2355 pr_info("%s: version " MUSB_VERSION ", "
550a7375 2356 "?dma?"
550a7375 2357 ", "
62285963 2358 "otg (peripheral+host)",
5c8a86e1 2359 musb_driver_name);
e9e8c85e 2360 return platform_driver_register(&musb_driver);
550a7375 2361}
e9e8c85e 2362module_init(musb_init);
550a7375
FB		 2363
2364static void __exit musb_cleanup(void)
2365{
2366 platform_driver_unregister(&musb_driver);
2367}
2368module_exit(musb_cleanup);
Linux kernel - Deliverables
This page took 0.634244 seconds and 5 git commands to generate.