Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 FB |
85 | * - platform_device for addressing, irq, and platform_data |
86 | * - platform_data is mostly for board-specific informarion | |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
9303961f | 99 | #include <linux/prefetch.h> |
550a7375 FB |
100 | #include <linux/platform_device.h> |
101 | #include <linux/io.h> | |
102 | ||
550a7375 FB |
103 | #include "musb_core.h" |
104 | ||
f7f9d63e | 105 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
106 | |
107 | ||
550a7375 FB |
108 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
109 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
110 | ||
e8164f64 | 111 | #define MUSB_VERSION "6.0" |
550a7375 FB |
112 | |
113 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
114 | ||
05ac10dd | 115 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
116 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
117 | ||
118 | MODULE_DESCRIPTION(DRIVER_INFO); | |
119 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
120 | MODULE_LICENSE("GPL"); | |
121 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
122 | ||
123 | ||
124 | /*-------------------------------------------------------------------------*/ | |
125 | ||
126 | static inline struct musb *dev_to_musb(struct device *dev) | |
127 | { | |
550a7375 | 128 | return dev_get_drvdata(dev); |
550a7375 FB |
129 | } |
130 | ||
131 | /*-------------------------------------------------------------------------*/ | |
132 | ||
ffb865b1 | 133 | #ifndef CONFIG_BLACKFIN |
b96d3b08 | 134 | static int musb_ulpi_read(struct usb_phy *phy, u32 offset) |
ffb865b1 | 135 | { |
b96d3b08 | 136 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
137 | int i = 0; |
138 | u8 r; | |
139 | u8 power; | |
bf070bc1 GI |
140 | int ret; |
141 | ||
142 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
143 | |
144 | /* Make sure the transceiver is not in low power mode */ | |
145 | power = musb_readb(addr, MUSB_POWER); | |
146 | power &= ~MUSB_POWER_SUSPENDM; | |
147 | musb_writeb(addr, MUSB_POWER, power); | |
148 | ||
149 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
150 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
151 | */ | |
152 | ||
153 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
154 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
155 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
156 | ||
157 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
158 | & MUSB_ULPI_REG_CMPLT)) { | |
159 | i++; | |
bf070bc1 GI |
160 | if (i == 10000) { |
161 | ret = -ETIMEDOUT; | |
162 | goto out; | |
163 | } | |
ffb865b1 HK |
164 | |
165 | } | |
166 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
167 | r &= ~MUSB_ULPI_REG_CMPLT; | |
168 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
169 | ||
bf070bc1 GI |
170 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
171 | ||
172 | out: | |
173 | pm_runtime_put(phy->io_dev); | |
174 | ||
175 | return ret; | |
ffb865b1 HK |
176 | } |
177 | ||
b96d3b08 | 178 | static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) |
ffb865b1 | 179 | { |
b96d3b08 | 180 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
181 | int i = 0; |
182 | u8 r = 0; | |
183 | u8 power; | |
bf070bc1 GI |
184 | int ret = 0; |
185 | ||
186 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
187 | |
188 | /* Make sure the transceiver is not in low power mode */ | |
189 | power = musb_readb(addr, MUSB_POWER); | |
190 | power &= ~MUSB_POWER_SUSPENDM; | |
191 | musb_writeb(addr, MUSB_POWER, power); | |
192 | ||
193 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
194 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
195 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
196 | ||
197 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
198 | & MUSB_ULPI_REG_CMPLT)) { | |
199 | i++; | |
bf070bc1 GI |
200 | if (i == 10000) { |
201 | ret = -ETIMEDOUT; | |
202 | goto out; | |
203 | } | |
ffb865b1 HK |
204 | } |
205 | ||
206 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
207 | r &= ~MUSB_ULPI_REG_CMPLT; | |
208 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
209 | ||
bf070bc1 GI |
210 | out: |
211 | pm_runtime_put(phy->io_dev); | |
212 | ||
213 | return ret; | |
ffb865b1 HK |
214 | } |
215 | #else | |
f2263db7 MF |
216 | #define musb_ulpi_read NULL |
217 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
218 | #endif |
219 | ||
b96d3b08 | 220 | static struct usb_phy_io_ops musb_ulpi_access = { |
ffb865b1 HK |
221 | .read = musb_ulpi_read, |
222 | .write = musb_ulpi_write, | |
223 | }; | |
224 | ||
225 | /*-------------------------------------------------------------------------*/ | |
226 | ||
7c925546 | 227 | #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) |
c6cf8b00 | 228 | |
550a7375 FB |
229 | /* |
230 | * Load an endpoint's FIFO | |
231 | */ | |
232 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
233 | { | |
5c8a86e1 | 234 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
235 | void __iomem *fifo = hw_ep->fifo; |
236 | ||
603fe2b2 AKG |
237 | if (unlikely(len == 0)) |
238 | return; | |
239 | ||
550a7375 FB |
240 | prefetch((u8 *)src); |
241 | ||
5c8a86e1 | 242 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
243 | 'T', hw_ep->epnum, fifo, len, src); |
244 | ||
245 | /* we can't assume unaligned reads work */ | |
246 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
247 | u16 index = 0; | |
248 | ||
249 | /* best case is 32bit-aligned source address */ | |
250 | if ((0x02 & (unsigned long) src) == 0) { | |
251 | if (len >= 4) { | |
252 | writesl(fifo, src + index, len >> 2); | |
253 | index += len & ~0x03; | |
254 | } | |
255 | if (len & 0x02) { | |
256 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
257 | index += 2; | |
258 | } | |
259 | } else { | |
260 | if (len >= 2) { | |
261 | writesw(fifo, src + index, len >> 1); | |
262 | index += len & ~0x01; | |
263 | } | |
264 | } | |
265 | if (len & 0x01) | |
266 | musb_writeb(fifo, 0, src[index]); | |
267 | } else { | |
268 | /* byte aligned */ | |
269 | writesb(fifo, src, len); | |
270 | } | |
271 | } | |
272 | ||
843bb1d0 | 273 | #if !defined(CONFIG_USB_MUSB_AM35X) |
550a7375 FB |
274 | /* |
275 | * Unload an endpoint's FIFO | |
276 | */ | |
277 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
278 | { | |
5c8a86e1 | 279 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
280 | void __iomem *fifo = hw_ep->fifo; |
281 | ||
603fe2b2 AKG |
282 | if (unlikely(len == 0)) |
283 | return; | |
284 | ||
5c8a86e1 | 285 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
286 | 'R', hw_ep->epnum, fifo, len, dst); |
287 | ||
288 | /* we can't assume unaligned writes work */ | |
289 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
290 | u16 index = 0; | |
291 | ||
292 | /* best case is 32bit-aligned destination address */ | |
293 | if ((0x02 & (unsigned long) dst) == 0) { | |
294 | if (len >= 4) { | |
295 | readsl(fifo, dst, len >> 2); | |
296 | index = len & ~0x03; | |
297 | } | |
298 | if (len & 0x02) { | |
299 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
300 | index += 2; | |
301 | } | |
302 | } else { | |
303 | if (len >= 2) { | |
304 | readsw(fifo, dst, len >> 1); | |
305 | index = len & ~0x01; | |
306 | } | |
307 | } | |
308 | if (len & 0x01) | |
309 | dst[index] = musb_readb(fifo, 0); | |
310 | } else { | |
311 | /* byte aligned */ | |
312 | readsb(fifo, dst, len); | |
313 | } | |
314 | } | |
843bb1d0 | 315 | #endif |
550a7375 FB |
316 | |
317 | #endif /* normal PIO */ | |
318 | ||
319 | ||
320 | /*-------------------------------------------------------------------------*/ | |
321 | ||
322 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
323 | static const u8 musb_test_packet[53] = { | |
324 | /* implicit SYNC then DATA0 to start */ | |
325 | ||
326 | /* JKJKJKJK x9 */ | |
327 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
328 | /* JJKKJJKK x8 */ | |
329 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
330 | /* JJJJKKKK x8 */ | |
331 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
332 | /* JJJJJJJKKKKKKK x8 */ | |
333 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
334 | /* JJJJJJJK x8 */ | |
335 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
336 | /* JKKKKKKK x10, JK */ | |
337 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
338 | ||
339 | /* implicit CRC16 then EOP to end */ | |
340 | }; | |
341 | ||
342 | void musb_load_testpacket(struct musb *musb) | |
343 | { | |
344 | void __iomem *regs = musb->endpoints[0].regs; | |
345 | ||
346 | musb_ep_select(musb->mregs, 0); | |
347 | musb_write_fifo(musb->control_ep, | |
348 | sizeof(musb_test_packet), musb_test_packet); | |
349 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
350 | } | |
351 | ||
352 | /*-------------------------------------------------------------------------*/ | |
353 | ||
550a7375 FB |
354 | /* |
355 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
356 | */ | |
a156544b | 357 | static void musb_otg_timer_func(unsigned long data) |
550a7375 FB |
358 | { |
359 | struct musb *musb = (struct musb *)data; | |
360 | unsigned long flags; | |
361 | ||
362 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 363 | switch (musb->xceiv->state) { |
550a7375 | 364 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 365 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 366 | musb_g_disconnect(musb); |
84e250ff | 367 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
368 | musb->is_active = 0; |
369 | break; | |
ab983f2a | 370 | case OTG_STATE_A_SUSPEND: |
550a7375 | 371 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 372 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
3df00453 | 373 | otg_state_string(musb->xceiv->state)); |
743411b3 | 374 | musb_platform_set_vbus(musb, 0); |
ab983f2a | 375 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
376 | break; |
377 | default: | |
5c8a86e1 | 378 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
3df00453 | 379 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
380 | } |
381 | musb->ignore_disconnect = 0; | |
382 | spin_unlock_irqrestore(&musb->lock, flags); | |
383 | } | |
384 | ||
550a7375 | 385 | /* |
f7f9d63e | 386 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
387 | */ |
388 | void musb_hnp_stop(struct musb *musb) | |
389 | { | |
390 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
391 | void __iomem *mbase = musb->mregs; | |
392 | u8 reg; | |
393 | ||
5c8a86e1 | 394 | dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); |
ab983f2a | 395 | |
84e250ff | 396 | switch (musb->xceiv->state) { |
550a7375 | 397 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 398 | musb_g_disconnect(musb); |
5c8a86e1 | 399 | dev_dbg(musb->controller, "HNP: back to %s\n", |
3df00453 | 400 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
401 | break; |
402 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 403 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
550a7375 | 404 | hcd->self.is_b_host = 0; |
84e250ff | 405 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
406 | MUSB_DEV_MODE(musb); |
407 | reg = musb_readb(mbase, MUSB_POWER); | |
408 | reg |= MUSB_POWER_SUSPENDM; | |
409 | musb_writeb(mbase, MUSB_POWER, reg); | |
410 | /* REVISIT: Start SESSION_REQUEST here? */ | |
411 | break; | |
412 | default: | |
5c8a86e1 | 413 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
3df00453 | 414 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
415 | } |
416 | ||
417 | /* | |
418 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
419 | * which cause occasional OPT A "Did not receive reset after connect" | |
420 | * errors. | |
421 | */ | |
749da5f8 | 422 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
423 | } |
424 | ||
550a7375 FB |
425 | /* |
426 | * Interrupt Service Routine to record USB "global" interrupts. | |
427 | * Since these do not happen often and signify things of | |
428 | * paramount importance, it seems OK to check them individually; | |
429 | * the order of the tests is specified in the manual | |
430 | * | |
431 | * @param musb instance pointer | |
432 | * @param int_usb register contents | |
433 | * @param devctl | |
434 | * @param power | |
435 | */ | |
436 | ||
550a7375 FB |
437 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
438 | u8 devctl, u8 power) | |
439 | { | |
d445b6da | 440 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 441 | irqreturn_t handled = IRQ_NONE; |
550a7375 | 442 | |
5c8a86e1 | 443 | dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, |
550a7375 FB |
444 | int_usb); |
445 | ||
446 | /* in host mode, the peripheral may issue remote wakeup. | |
447 | * in peripheral mode, the host may resume the link. | |
448 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
449 | */ | |
450 | if (int_usb & MUSB_INTR_RESUME) { | |
451 | handled = IRQ_HANDLED; | |
5c8a86e1 | 452 | dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
453 | |
454 | if (devctl & MUSB_DEVCTL_HM) { | |
aa471456 FB |
455 | void __iomem *mbase = musb->mregs; |
456 | ||
84e250ff | 457 | switch (musb->xceiv->state) { |
550a7375 FB |
458 | case OTG_STATE_A_SUSPEND: |
459 | /* remote wakeup? later, GetPortStatus | |
460 | * will stop RESUME signaling | |
461 | */ | |
462 | ||
463 | if (power & MUSB_POWER_SUSPENDM) { | |
464 | /* spurious */ | |
465 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
5c8a86e1 | 466 | dev_dbg(musb->controller, "Spurious SUSPENDM\n"); |
550a7375 FB |
467 | break; |
468 | } | |
469 | ||
470 | power &= ~MUSB_POWER_SUSPENDM; | |
471 | musb_writeb(mbase, MUSB_POWER, | |
472 | power | MUSB_POWER_RESUME); | |
473 | ||
474 | musb->port1_status |= | |
475 | (USB_PORT_STAT_C_SUSPEND << 16) | |
476 | | MUSB_PORT_STAT_RESUME; | |
477 | musb->rh_timer = jiffies | |
478 | + msecs_to_jiffies(20); | |
479 | ||
84e250ff | 480 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
481 | musb->is_active = 1; |
482 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
483 | break; | |
484 | case OTG_STATE_B_WAIT_ACON: | |
84e250ff | 485 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
486 | musb->is_active = 1; |
487 | MUSB_DEV_MODE(musb); | |
488 | break; | |
489 | default: | |
490 | WARNING("bogus %s RESUME (%s)\n", | |
491 | "host", | |
3df00453 | 492 | otg_state_string(musb->xceiv->state)); |
550a7375 | 493 | } |
550a7375 | 494 | } else { |
84e250ff | 495 | switch (musb->xceiv->state) { |
550a7375 FB |
496 | case OTG_STATE_A_SUSPEND: |
497 | /* possibly DISCONNECT is upcoming */ | |
84e250ff | 498 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
499 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); |
500 | break; | |
550a7375 FB |
501 | case OTG_STATE_B_WAIT_ACON: |
502 | case OTG_STATE_B_PERIPHERAL: | |
503 | /* disconnect while suspended? we may | |
504 | * not get a disconnect irq... | |
505 | */ | |
506 | if ((devctl & MUSB_DEVCTL_VBUS) | |
507 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
508 | ) { | |
509 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
510 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
511 | break; | |
512 | } | |
513 | musb_g_resume(musb); | |
514 | break; | |
515 | case OTG_STATE_B_IDLE: | |
516 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
517 | break; | |
550a7375 FB |
518 | default: |
519 | WARNING("bogus %s RESUME (%s)\n", | |
520 | "peripheral", | |
3df00453 | 521 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
522 | } |
523 | } | |
524 | } | |
525 | ||
550a7375 FB |
526 | /* see manual for the order of the tests */ |
527 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
528 | void __iomem *mbase = musb->mregs; |
529 | ||
19aab56c HK |
530 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
531 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 532 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
533 | return IRQ_HANDLED; |
534 | } | |
535 | ||
5c8a86e1 | 536 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
3df00453 | 537 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
538 | |
539 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
540 | * is removed) SRP. responses are time critical: | |
541 | * - turn on VBUS (with silicon-specific mechanism) | |
542 | * - go through A_WAIT_VRISE | |
543 | * - ... to A_WAIT_BCON. | |
544 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
545 | */ | |
546 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
547 | musb->ep0_stage = MUSB_EP0_START; | |
84e250ff | 548 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 549 | MUSB_HST_MODE(musb); |
743411b3 | 550 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
551 | |
552 | handled = IRQ_HANDLED; | |
553 | } | |
554 | ||
555 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
556 | int ignore = 0; | |
557 | ||
558 | /* During connection as an A-Device, we may see a short | |
559 | * current spikes causing voltage drop, because of cable | |
560 | * and peripheral capacitance combined with vbus draw. | |
561 | * (So: less common with truly self-powered devices, where | |
562 | * vbus doesn't act like a power supply.) | |
563 | * | |
564 | * Such spikes are short; usually less than ~500 usec, max | |
565 | * of ~2 msec. That is, they're not sustained overcurrent | |
566 | * errors, though they're reported using VBUSERROR irqs. | |
567 | * | |
568 | * Workarounds: (a) hardware: use self powered devices. | |
569 | * (b) software: ignore non-repeated VBUS errors. | |
570 | * | |
571 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
572 | * make trouble here, keeping VBUS < 4.4V ? | |
573 | */ | |
84e250ff | 574 | switch (musb->xceiv->state) { |
550a7375 FB |
575 | case OTG_STATE_A_HOST: |
576 | /* recovery is dicey once we've gotten past the | |
577 | * initial stages of enumeration, but if VBUS | |
578 | * stayed ok at the other end of the link, and | |
579 | * another reset is due (at least for high speed, | |
580 | * to redo the chirp etc), it might work OK... | |
581 | */ | |
582 | case OTG_STATE_A_WAIT_BCON: | |
583 | case OTG_STATE_A_WAIT_VRISE: | |
584 | if (musb->vbuserr_retry) { | |
aa471456 FB |
585 | void __iomem *mbase = musb->mregs; |
586 | ||
550a7375 FB |
587 | musb->vbuserr_retry--; |
588 | ignore = 1; | |
589 | devctl |= MUSB_DEVCTL_SESSION; | |
590 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
591 | } else { | |
592 | musb->port1_status |= | |
749da5f8 AS |
593 | USB_PORT_STAT_OVERCURRENT |
594 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
595 | } |
596 | break; | |
597 | default: | |
598 | break; | |
599 | } | |
600 | ||
5c8a86e1 | 601 | dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", |
3df00453 | 602 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
603 | devctl, |
604 | ({ char *s; | |
605 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
606 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
607 | s = "<SessEnd"; break; | |
608 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
609 | s = "<AValid"; break; | |
610 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
611 | s = "<VBusValid"; break; | |
612 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
613 | default: | |
614 | s = "VALID"; break; | |
615 | }; s; }), | |
616 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
617 | musb->port1_status); | |
618 | ||
619 | /* go through A_WAIT_VFALL then start a new session */ | |
620 | if (!ignore) | |
743411b3 | 621 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
622 | handled = IRQ_HANDLED; |
623 | } | |
624 | ||
1c25fda4 | 625 | if (int_usb & MUSB_INTR_SUSPEND) { |
5c8a86e1 | 626 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", |
3df00453 | 627 | otg_state_string(musb->xceiv->state), devctl, power); |
1c25fda4 AM |
628 | handled = IRQ_HANDLED; |
629 | ||
630 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
631 | case OTG_STATE_A_PERIPHERAL: |
632 | /* We also come here if the cable is removed, since | |
633 | * this silicon doesn't report ID-no-longer-grounded. | |
634 | * | |
635 | * We depend on T(a_wait_bcon) to shut us down, and | |
636 | * hope users don't do anything dicey during this | |
637 | * undesired detour through A_WAIT_BCON. | |
638 | */ | |
639 | musb_hnp_stop(musb); | |
640 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
641 | musb_root_disconnect(musb); | |
642 | musb_platform_try_idle(musb, jiffies | |
643 | + msecs_to_jiffies(musb->a_wait_bcon | |
644 | ? : OTG_TIME_A_WAIT_BCON)); | |
645 | ||
646 | break; | |
1c25fda4 AM |
647 | case OTG_STATE_B_IDLE: |
648 | if (!musb->is_active) | |
649 | break; | |
650 | case OTG_STATE_B_PERIPHERAL: | |
651 | musb_g_suspend(musb); | |
032ec49f | 652 | musb->is_active = otg->gadget->b_hnp_enable; |
1c25fda4 | 653 | if (musb->is_active) { |
1c25fda4 | 654 | musb->xceiv->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 655 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
656 | mod_timer(&musb->otg_timer, jiffies |
657 | + msecs_to_jiffies( | |
658 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
659 | } |
660 | break; | |
661 | case OTG_STATE_A_WAIT_BCON: | |
662 | if (musb->a_wait_bcon != 0) | |
663 | musb_platform_try_idle(musb, jiffies | |
664 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
665 | break; | |
666 | case OTG_STATE_A_HOST: | |
667 | musb->xceiv->state = OTG_STATE_A_SUSPEND; | |
032ec49f | 668 | musb->is_active = otg->host->b_hnp_enable; |
1c25fda4 AM |
669 | break; |
670 | case OTG_STATE_B_HOST: | |
671 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 672 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
673 | break; |
674 | default: | |
675 | /* "should not happen" */ | |
676 | musb->is_active = 0; | |
677 | break; | |
678 | } | |
679 | } | |
680 | ||
550a7375 FB |
681 | if (int_usb & MUSB_INTR_CONNECT) { |
682 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
683 | ||
684 | handled = IRQ_HANDLED; | |
685 | musb->is_active = 1; | |
550a7375 FB |
686 | |
687 | musb->ep0_stage = MUSB_EP0_START; | |
688 | ||
550a7375 FB |
689 | /* flush endpoints when transitioning from Device Mode */ |
690 | if (is_peripheral_active(musb)) { | |
691 | /* REVISIT HNP; just force disconnect */ | |
692 | } | |
d709d22e AKG |
693 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); |
694 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
695 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); | |
550a7375 FB |
696 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
697 | |USB_PORT_STAT_HIGH_SPEED | |
698 | |USB_PORT_STAT_ENABLE | |
699 | ); | |
700 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
701 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
702 | ||
703 | /* high vs full speed is just a guess until after reset */ | |
704 | if (devctl & MUSB_DEVCTL_LSDEV) | |
705 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
706 | ||
550a7375 | 707 | /* indicate new connection to OTG machine */ |
84e250ff | 708 | switch (musb->xceiv->state) { |
550a7375 FB |
709 | case OTG_STATE_B_PERIPHERAL: |
710 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 711 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 712 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 713 | goto b_host; |
550a7375 | 714 | } else |
5c8a86e1 | 715 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
716 | break; |
717 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 718 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 719 | b_host: |
84e250ff | 720 | musb->xceiv->state = OTG_STATE_B_HOST; |
550a7375 | 721 | hcd->self.is_b_host = 1; |
1de00dae DB |
722 | musb->ignore_disconnect = 0; |
723 | del_timer(&musb->otg_timer); | |
550a7375 FB |
724 | break; |
725 | default: | |
726 | if ((devctl & MUSB_DEVCTL_VBUS) | |
727 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
84e250ff | 728 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
729 | hcd->self.is_b_host = 0; |
730 | } | |
731 | break; | |
732 | } | |
1de00dae DB |
733 | |
734 | /* poke the root hub */ | |
735 | MUSB_HST_MODE(musb); | |
736 | if (hcd->status_urb) | |
737 | usb_hcd_poll_rh_status(hcd); | |
738 | else | |
739 | usb_hcd_resume_root_hub(hcd); | |
740 | ||
5c8a86e1 | 741 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
3df00453 | 742 | otg_state_string(musb->xceiv->state), devctl); |
550a7375 | 743 | } |
550a7375 | 744 | |
1c25fda4 | 745 | if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { |
5c8a86e1 | 746 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
3df00453 | 747 | otg_state_string(musb->xceiv->state), |
1c25fda4 AM |
748 | MUSB_MODE(musb), devctl); |
749 | handled = IRQ_HANDLED; | |
750 | ||
751 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
752 | case OTG_STATE_A_HOST: |
753 | case OTG_STATE_A_SUSPEND: | |
754 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
755 | musb_root_disconnect(musb); | |
032ec49f | 756 | if (musb->a_wait_bcon != 0) |
1c25fda4 AM |
757 | musb_platform_try_idle(musb, jiffies |
758 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
759 | break; | |
1c25fda4 AM |
760 | case OTG_STATE_B_HOST: |
761 | /* REVISIT this behaves for "real disconnect" | |
762 | * cases; make sure the other transitions from | |
763 | * from B_HOST act right too. The B_HOST code | |
764 | * in hnp_stop() is currently not used... | |
765 | */ | |
766 | musb_root_disconnect(musb); | |
767 | musb_to_hcd(musb)->self.is_b_host = 0; | |
768 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; | |
769 | MUSB_DEV_MODE(musb); | |
770 | musb_g_disconnect(musb); | |
771 | break; | |
772 | case OTG_STATE_A_PERIPHERAL: | |
773 | musb_hnp_stop(musb); | |
774 | musb_root_disconnect(musb); | |
775 | /* FALLTHROUGH */ | |
776 | case OTG_STATE_B_WAIT_ACON: | |
777 | /* FALLTHROUGH */ | |
1c25fda4 AM |
778 | case OTG_STATE_B_PERIPHERAL: |
779 | case OTG_STATE_B_IDLE: | |
780 | musb_g_disconnect(musb); | |
781 | break; | |
1c25fda4 AM |
782 | default: |
783 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
3df00453 | 784 | otg_state_string(musb->xceiv->state)); |
1c25fda4 AM |
785 | break; |
786 | } | |
787 | } | |
788 | ||
550a7375 FB |
789 | /* mentor saves a bit: bus reset and babble share the same irq. |
790 | * only host sees babble; only peripheral sees bus reset. | |
791 | */ | |
792 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 793 | handled = IRQ_HANDLED; |
a04d46d0 | 794 | if ((devctl & MUSB_DEVCTL_HM) != 0) { |
550a7375 FB |
795 | /* |
796 | * Looks like non-HS BABBLE can be ignored, but | |
797 | * HS BABBLE is an error condition. For HS the solution | |
798 | * is to avoid babble in the first place and fix what | |
799 | * caused BABBLE. When HS BABBLE happens we can only | |
800 | * stop the session. | |
801 | */ | |
802 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
5c8a86e1 | 803 | dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); |
550a7375 FB |
804 | else { |
805 | ERR("Stopping host session -- babble\n"); | |
1c25fda4 | 806 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
550a7375 | 807 | } |
a04d46d0 | 808 | } else { |
5c8a86e1 | 809 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
3df00453 | 810 | otg_state_string(musb->xceiv->state)); |
84e250ff | 811 | switch (musb->xceiv->state) { |
550a7375 FB |
812 | case OTG_STATE_A_SUSPEND: |
813 | /* We need to ignore disconnect on suspend | |
814 | * otherwise tusb 2.0 won't reconnect after a | |
815 | * power cycle, which breaks otg compliance. | |
816 | */ | |
817 | musb->ignore_disconnect = 1; | |
818 | musb_g_reset(musb); | |
819 | /* FALLTHROUGH */ | |
820 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 821 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 822 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
3df00453 AG |
823 | otg_state_string(musb->xceiv->state), |
824 | TA_WAIT_BCON(musb)); | |
f7f9d63e DB |
825 | mod_timer(&musb->otg_timer, jiffies |
826 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
827 | break; |
828 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
829 | musb->ignore_disconnect = 0; |
830 | del_timer(&musb->otg_timer); | |
831 | musb_g_reset(musb); | |
550a7375 FB |
832 | break; |
833 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 834 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
3df00453 | 835 | otg_state_string(musb->xceiv->state)); |
84e250ff | 836 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
837 | musb_g_reset(musb); |
838 | break; | |
550a7375 | 839 | case OTG_STATE_B_IDLE: |
84e250ff | 840 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
841 | /* FALLTHROUGH */ |
842 | case OTG_STATE_B_PERIPHERAL: | |
843 | musb_g_reset(musb); | |
844 | break; | |
845 | default: | |
5c8a86e1 | 846 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
3df00453 | 847 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
848 | } |
849 | } | |
550a7375 | 850 | } |
550a7375 FB |
851 | |
852 | #if 0 | |
853 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
854 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
855 | * limits of a given frame or microframe. | |
856 | * | |
857 | * It's not needed for peripheral side, which dedicates endpoints; | |
858 | * though it _might_ use SOF irqs for other purposes. | |
859 | * | |
860 | * And it's not currently needed for host side, which also dedicates | |
861 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
862 | * to support ISO transfers yet. | |
863 | */ | |
864 | if (int_usb & MUSB_INTR_SOF) { | |
865 | void __iomem *mbase = musb->mregs; | |
866 | struct musb_hw_ep *ep; | |
867 | u8 epnum; | |
868 | u16 frame; | |
869 | ||
5c8a86e1 | 870 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
871 | handled = IRQ_HANDLED; |
872 | ||
873 | /* start any periodic Tx transfers waiting for current frame */ | |
874 | frame = musb_readw(mbase, MUSB_FRAME); | |
875 | ep = musb->endpoints; | |
876 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
877 | && (musb->epmask >= (1 << epnum)); | |
878 | epnum++, ep++) { | |
879 | /* | |
880 | * FIXME handle framecounter wraps (12 bits) | |
881 | * eliminate duplicated StartUrb logic | |
882 | */ | |
883 | if (ep->dwWaitFrame >= frame) { | |
884 | ep->dwWaitFrame = 0; | |
885 | pr_debug("SOF --> periodic TX%s on %d\n", | |
886 | ep->tx_channel ? " DMA" : "", | |
887 | epnum); | |
888 | if (!ep->tx_channel) | |
889 | musb_h_tx_start(musb, epnum); | |
890 | else | |
891 | cppi_hostdma_start(musb, epnum); | |
892 | } | |
893 | } /* end of for loop */ | |
894 | } | |
895 | #endif | |
896 | ||
1c25fda4 | 897 | schedule_work(&musb->irq_work); |
550a7375 FB |
898 | |
899 | return handled; | |
900 | } | |
901 | ||
902 | /*-------------------------------------------------------------------------*/ | |
903 | ||
904 | /* | |
905 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
906 | */ | |
907 | void musb_start(struct musb *musb) | |
908 | { | |
909 | void __iomem *regs = musb->mregs; | |
910 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
911 | ||
5c8a86e1 | 912 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); |
550a7375 FB |
913 | |
914 | /* Set INT enable registers, enable interrupts */ | |
915 | musb_writew(regs, MUSB_INTRTXE, musb->epmask); | |
916 | musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
917 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
918 | ||
919 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
920 | ||
921 | /* put into basic highspeed mode and start session */ | |
922 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
550a7375 FB |
923 | | MUSB_POWER_HSENAB |
924 | /* ENSUSPEND wedges tusb */ | |
925 | /* | MUSB_POWER_ENSUSPEND */ | |
926 | ); | |
927 | ||
928 | musb->is_active = 0; | |
929 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
930 | devctl &= ~MUSB_DEVCTL_SESSION; | |
931 | ||
032ec49f FB |
932 | /* session started after: |
933 | * (a) ID-grounded irq, host mode; | |
934 | * (b) vbus present/connect IRQ, peripheral mode; | |
935 | * (c) peripheral initiates, using SRP | |
936 | */ | |
937 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
938 | musb->is_active = 1; | |
939 | else | |
550a7375 FB |
940 | devctl |= MUSB_DEVCTL_SESSION; |
941 | ||
550a7375 FB |
942 | musb_platform_enable(musb); |
943 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
944 | } | |
945 | ||
946 | ||
947 | static void musb_generic_disable(struct musb *musb) | |
948 | { | |
949 | void __iomem *mbase = musb->mregs; | |
950 | u16 temp; | |
951 | ||
952 | /* disable interrupts */ | |
953 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
954 | musb_writew(mbase, MUSB_INTRTXE, 0); | |
955 | musb_writew(mbase, MUSB_INTRRXE, 0); | |
956 | ||
957 | /* off */ | |
958 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
959 | ||
960 | /* flush pending interrupts */ | |
961 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
962 | temp = musb_readw(mbase, MUSB_INTRTX); | |
963 | temp = musb_readw(mbase, MUSB_INTRRX); | |
964 | ||
965 | } | |
966 | ||
967 | /* | |
968 | * Make the HDRC stop (disable interrupts, etc.); | |
969 | * reversible by musb_start | |
970 | * called on gadget driver unregister | |
971 | * with controller locked, irqs blocked | |
972 | * acts as a NOP unless some role activated the hardware | |
973 | */ | |
974 | void musb_stop(struct musb *musb) | |
975 | { | |
976 | /* stop IRQs, timers, ... */ | |
977 | musb_platform_disable(musb); | |
978 | musb_generic_disable(musb); | |
5c8a86e1 | 979 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
980 | |
981 | /* FIXME | |
982 | * - mark host and/or peripheral drivers unusable/inactive | |
983 | * - disable DMA (and enable it in HdrcStart) | |
984 | * - make sure we can musb_start() after musb_stop(); with | |
985 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
986 | * - ... | |
987 | */ | |
988 | musb_platform_try_idle(musb, 0); | |
989 | } | |
990 | ||
991 | static void musb_shutdown(struct platform_device *pdev) | |
992 | { | |
993 | struct musb *musb = dev_to_musb(&pdev->dev); | |
994 | unsigned long flags; | |
995 | ||
4f9edd2d | 996 | pm_runtime_get_sync(musb->controller); |
24307cae GI |
997 | |
998 | musb_gadget_cleanup(musb); | |
999 | ||
550a7375 FB |
1000 | spin_lock_irqsave(&musb->lock, flags); |
1001 | musb_platform_disable(musb); | |
1002 | musb_generic_disable(musb); | |
550a7375 FB |
1003 | spin_unlock_irqrestore(&musb->lock, flags); |
1004 | ||
120d074c GI |
1005 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
1006 | musb_platform_exit(musb); | |
120d074c | 1007 | |
4f9edd2d | 1008 | pm_runtime_put(musb->controller); |
550a7375 FB |
1009 | /* FIXME power down */ |
1010 | } | |
1011 | ||
1012 | ||
1013 | /*-------------------------------------------------------------------------*/ | |
1014 | ||
1015 | /* | |
1016 | * The silicon either has hard-wired endpoint configurations, or else | |
1017 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1018 | * writing only the dynamic sizing is very well tested. Since we switched |
1019 | * away from compile-time hardware parameters, we can no longer rely on | |
1020 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1021 | * |
1022 | * We don't currently use dynamic fifo setup capability to do anything | |
1023 | * more than selecting one of a bunch of predefined configurations. | |
1024 | */ | |
ee34e51a FB |
1025 | #if defined(CONFIG_USB_MUSB_TUSB6010) \ |
1026 | || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ | |
1027 | || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ | |
1028 | || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ | |
1029 | || defined(CONFIG_USB_MUSB_AM35X) \ | |
9ecb8875 AKG |
1030 | || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ |
1031 | || defined(CONFIG_USB_MUSB_DSPS) \ | |
1032 | || defined(CONFIG_USB_MUSB_DSPS_MODULE) | |
e9e8c85e | 1033 | static ushort __devinitdata fifo_mode = 4; |
ee34e51a FB |
1034 | #elif defined(CONFIG_USB_MUSB_UX500) \ |
1035 | || defined(CONFIG_USB_MUSB_UX500_MODULE) | |
e9e8c85e | 1036 | static ushort __devinitdata fifo_mode = 5; |
550a7375 | 1037 | #else |
e9e8c85e | 1038 | static ushort __devinitdata fifo_mode = 2; |
550a7375 FB |
1039 | #endif |
1040 | ||
1041 | /* "modprobe ... fifo_mode=1" etc */ | |
1042 | module_param(fifo_mode, ushort, 0); | |
1043 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1044 | ||
550a7375 FB |
1045 | /* |
1046 | * tables defining fifo_mode values. define more if you like. | |
1047 | * for host side, make sure both halves of ep1 are set up. | |
1048 | */ | |
1049 | ||
1050 | /* mode 0 - fits in 2KB */ | |
e9e8c85e | 1051 | static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { |
550a7375 FB |
1052 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1053 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1054 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1055 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1056 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1057 | }; | |
1058 | ||
1059 | /* mode 1 - fits in 4KB */ | |
e9e8c85e | 1060 | static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { |
550a7375 FB |
1061 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1062 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1063 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1064 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1065 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1066 | }; | |
1067 | ||
1068 | /* mode 2 - fits in 4KB */ | |
e9e8c85e | 1069 | static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { |
550a7375 FB |
1070 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1071 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1072 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1073 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1074 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1075 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1076 | }; | |
1077 | ||
1078 | /* mode 3 - fits in 4KB */ | |
e9e8c85e | 1079 | static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { |
550a7375 FB |
1080 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1081 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1082 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1083 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1084 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1085 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1086 | }; | |
1087 | ||
1088 | /* mode 4 - fits in 16KB */ | |
e9e8c85e | 1089 | static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { |
550a7375 FB |
1090 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1091 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1092 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1093 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1094 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1095 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1096 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1097 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1098 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1099 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1100 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1101 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1102 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1103 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1104 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1105 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1106 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1107 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1108 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1109 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1110 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1111 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1112 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1113 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1114 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1115 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1116 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1117 | }; | |
1118 | ||
3b151526 | 1119 | /* mode 5 - fits in 8KB */ |
e9e8c85e | 1120 | static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { |
3b151526 AKG |
1121 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1122 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1123 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1124 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1125 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1126 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1127 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1128 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1129 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1130 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1131 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1132 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1133 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1134 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1135 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1136 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1137 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1138 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1139 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1140 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1141 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1142 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1143 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1144 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1145 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1146 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1147 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1148 | }; | |
550a7375 FB |
1149 | |
1150 | /* | |
1151 | * configure a fifo; for non-shared endpoints, this may be called | |
1152 | * once for a tx fifo and once for an rx fifo. | |
1153 | * | |
1154 | * returns negative errno or offset for next fifo. | |
1155 | */ | |
e9e8c85e | 1156 | static int __devinit |
550a7375 | 1157 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
e6c213b2 | 1158 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1159 | { |
1160 | void __iomem *mbase = musb->mregs; | |
1161 | int size = 0; | |
1162 | u16 maxpacket = cfg->maxpacket; | |
1163 | u16 c_off = offset >> 3; | |
1164 | u8 c_size; | |
1165 | ||
1166 | /* expect hw_ep has already been zero-initialized */ | |
1167 | ||
1168 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1169 | maxpacket = 1 << size; | |
1170 | ||
1171 | c_size = size - 3; | |
1172 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1173 | if ((offset + (maxpacket << 1)) > |
1174 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1175 | return -EMSGSIZE; |
1176 | c_size |= MUSB_FIFOSZ_DPB; | |
1177 | } else { | |
ca6d1b13 | 1178 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1179 | return -EMSGSIZE; |
1180 | } | |
1181 | ||
1182 | /* configure the FIFO */ | |
1183 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1184 | ||
550a7375 FB |
1185 | /* EP0 reserved endpoint for control, bidirectional; |
1186 | * EP1 reserved for bulk, two unidirection halves. | |
1187 | */ | |
1188 | if (hw_ep->epnum == 1) | |
1189 | musb->bulk_ep = hw_ep; | |
1190 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1191 | switch (cfg->style) { |
1192 | case FIFO_TX: | |
c6cf8b00 BW |
1193 | musb_write_txfifosz(mbase, c_size); |
1194 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1195 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1196 | hw_ep->max_packet_sz_tx = maxpacket; | |
1197 | break; | |
1198 | case FIFO_RX: | |
c6cf8b00 BW |
1199 | musb_write_rxfifosz(mbase, c_size); |
1200 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1201 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1202 | hw_ep->max_packet_sz_rx = maxpacket; | |
1203 | break; | |
1204 | case FIFO_RXTX: | |
c6cf8b00 BW |
1205 | musb_write_txfifosz(mbase, c_size); |
1206 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1207 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1208 | hw_ep->max_packet_sz_rx = maxpacket; | |
1209 | ||
c6cf8b00 BW |
1210 | musb_write_rxfifosz(mbase, c_size); |
1211 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1212 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1213 | hw_ep->max_packet_sz_tx = maxpacket; | |
1214 | ||
1215 | hw_ep->is_shared_fifo = true; | |
1216 | break; | |
1217 | } | |
1218 | ||
1219 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1220 | * which happens to be ok | |
1221 | */ | |
1222 | musb->epmask |= (1 << hw_ep->epnum); | |
1223 | ||
1224 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1225 | } | |
1226 | ||
e9e8c85e | 1227 | static struct musb_fifo_cfg __devinitdata ep0_cfg = { |
550a7375 FB |
1228 | .style = FIFO_RXTX, .maxpacket = 64, |
1229 | }; | |
1230 | ||
e9e8c85e | 1231 | static int __devinit ep_config_from_table(struct musb *musb) |
550a7375 | 1232 | { |
e6c213b2 | 1233 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1234 | unsigned i, n; |
1235 | int offset; | |
1236 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1237 | ||
e6c213b2 FB |
1238 | if (musb->config->fifo_cfg) { |
1239 | cfg = musb->config->fifo_cfg; | |
1240 | n = musb->config->fifo_cfg_size; | |
1241 | goto done; | |
1242 | } | |
1243 | ||
550a7375 FB |
1244 | switch (fifo_mode) { |
1245 | default: | |
1246 | fifo_mode = 0; | |
1247 | /* FALLTHROUGH */ | |
1248 | case 0: | |
1249 | cfg = mode_0_cfg; | |
1250 | n = ARRAY_SIZE(mode_0_cfg); | |
1251 | break; | |
1252 | case 1: | |
1253 | cfg = mode_1_cfg; | |
1254 | n = ARRAY_SIZE(mode_1_cfg); | |
1255 | break; | |
1256 | case 2: | |
1257 | cfg = mode_2_cfg; | |
1258 | n = ARRAY_SIZE(mode_2_cfg); | |
1259 | break; | |
1260 | case 3: | |
1261 | cfg = mode_3_cfg; | |
1262 | n = ARRAY_SIZE(mode_3_cfg); | |
1263 | break; | |
1264 | case 4: | |
1265 | cfg = mode_4_cfg; | |
1266 | n = ARRAY_SIZE(mode_4_cfg); | |
1267 | break; | |
3b151526 AKG |
1268 | case 5: |
1269 | cfg = mode_5_cfg; | |
1270 | n = ARRAY_SIZE(mode_5_cfg); | |
1271 | break; | |
550a7375 FB |
1272 | } |
1273 | ||
1274 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1275 | musb_driver_name, fifo_mode); | |
1276 | ||
1277 | ||
e6c213b2 | 1278 | done: |
550a7375 FB |
1279 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1280 | /* assert(offset > 0) */ | |
1281 | ||
1282 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1283 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1284 | */ |
1285 | ||
1286 | for (i = 0; i < n; i++) { | |
1287 | u8 epn = cfg->hw_ep_num; | |
1288 | ||
ca6d1b13 | 1289 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1290 | pr_debug("%s: invalid ep %d\n", |
1291 | musb_driver_name, epn); | |
bb1c9ef1 | 1292 | return -EINVAL; |
550a7375 FB |
1293 | } |
1294 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1295 | if (offset < 0) { | |
1296 | pr_debug("%s: mem overrun, ep %d\n", | |
1297 | musb_driver_name, epn); | |
f69dfa1f | 1298 | return offset; |
550a7375 FB |
1299 | } |
1300 | epn++; | |
1301 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1302 | } | |
1303 | ||
1304 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1305 | musb_driver_name, | |
ca6d1b13 FB |
1306 | n + 1, musb->config->num_eps * 2 - 1, |
1307 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1308 | |
550a7375 FB |
1309 | if (!musb->bulk_ep) { |
1310 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1311 | return -EINVAL; | |
1312 | } | |
550a7375 FB |
1313 | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | ||
1318 | /* | |
1319 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1320 | * @param musb the controller | |
1321 | */ | |
e9e8c85e | 1322 | static int __devinit ep_config_from_hw(struct musb *musb) |
550a7375 | 1323 | { |
c6cf8b00 | 1324 | u8 epnum = 0; |
550a7375 | 1325 | struct musb_hw_ep *hw_ep; |
a156544b | 1326 | void __iomem *mbase = musb->mregs; |
c6cf8b00 | 1327 | int ret = 0; |
550a7375 | 1328 | |
5c8a86e1 | 1329 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1330 | |
1331 | /* FIXME pick up ep0 maxpacket size */ | |
1332 | ||
ca6d1b13 | 1333 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1334 | musb_ep_select(mbase, epnum); |
1335 | hw_ep = musb->endpoints + epnum; | |
1336 | ||
c6cf8b00 BW |
1337 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1338 | if (ret < 0) | |
550a7375 | 1339 | break; |
550a7375 FB |
1340 | |
1341 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1342 | ||
550a7375 FB |
1343 | /* pick an RX/TX endpoint for bulk */ |
1344 | if (hw_ep->max_packet_sz_tx < 512 | |
1345 | || hw_ep->max_packet_sz_rx < 512) | |
1346 | continue; | |
1347 | ||
1348 | /* REVISIT: this algorithm is lazy, we should at least | |
1349 | * try to pick a double buffered endpoint. | |
1350 | */ | |
1351 | if (musb->bulk_ep) | |
1352 | continue; | |
1353 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1354 | } |
1355 | ||
550a7375 FB |
1356 | if (!musb->bulk_ep) { |
1357 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1358 | return -EINVAL; | |
1359 | } | |
550a7375 FB |
1360 | |
1361 | return 0; | |
1362 | } | |
1363 | ||
1364 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1365 | ||
1366 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1367 | * configure endpoints, or take their config from silicon | |
1368 | */ | |
e9e8c85e | 1369 | static int __devinit musb_core_init(u16 musb_type, struct musb *musb) |
550a7375 | 1370 | { |
550a7375 FB |
1371 | u8 reg; |
1372 | char *type; | |
0ea52ff4 | 1373 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1374 | void __iomem *mbase = musb->mregs; |
1375 | int status = 0; | |
1376 | int i; | |
1377 | ||
1378 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1379 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1380 | |
1381 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1382 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1383 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1384 | musb->dyn_fifo = true; |
1385 | } | |
550a7375 FB |
1386 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1387 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1388 | musb->bulk_combine = true; |
550a7375 FB |
1389 | } |
1390 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1391 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1392 | musb->bulk_split = true; |
550a7375 FB |
1393 | } |
1394 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1395 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1396 | musb->hb_iso_rx = true; |
550a7375 FB |
1397 | } |
1398 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1399 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1400 | musb->hb_iso_tx = true; |
550a7375 FB |
1401 | } |
1402 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1403 | strcat(aInfo, ", SoftConn"); | |
1404 | ||
1405 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1406 | musb_driver_name, reg, aInfo); | |
1407 | ||
550a7375 | 1408 | aDate[0] = 0; |
550a7375 FB |
1409 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1410 | musb->is_multipoint = 1; | |
1411 | type = "M"; | |
1412 | } else { | |
1413 | musb->is_multipoint = 0; | |
1414 | type = ""; | |
550a7375 FB |
1415 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1416 | printk(KERN_ERR | |
1417 | "%s: kernel must blacklist external hubs\n", | |
1418 | musb_driver_name); | |
550a7375 FB |
1419 | #endif |
1420 | } | |
1421 | ||
1422 | /* log release info */ | |
32c3b94e AG |
1423 | musb->hwvers = musb_read_hwvers(mbase); |
1424 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1425 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1426 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1427 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1428 | musb_driver_name, type, aRevision, aDate); | |
1429 | ||
1430 | /* configure ep0 */ | |
c6cf8b00 | 1431 | musb_configure_ep0(musb); |
550a7375 FB |
1432 | |
1433 | /* discover endpoint configuration */ | |
1434 | musb->nr_endpoints = 1; | |
1435 | musb->epmask = 1; | |
1436 | ||
ad517e9e FB |
1437 | if (musb->dyn_fifo) |
1438 | status = ep_config_from_table(musb); | |
1439 | else | |
1440 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1441 | |
1442 | if (status < 0) | |
1443 | return status; | |
1444 | ||
1445 | /* finish init, and print endpoint config */ | |
1446 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1447 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1448 | ||
1449 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
9a35f876 | 1450 | #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) |
550a7375 FB |
1451 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); |
1452 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1453 | hw_ep->fifo_sync_va = | |
1454 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1455 | ||
1456 | if (i == 0) | |
1457 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1458 | else | |
1459 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1460 | #endif | |
1461 | ||
1462 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
c6cf8b00 | 1463 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1464 | hw_ep->rx_reinit = 1; |
1465 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1466 | |
1467 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1468 | dev_dbg(musb->controller, |
550a7375 FB |
1469 | "%s: hw_ep %d%s, %smax %d\n", |
1470 | musb_driver_name, i, | |
1471 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1472 | hw_ep->tx_double_buffered | |
1473 | ? "doublebuffer, " : "", | |
1474 | hw_ep->max_packet_sz_tx); | |
1475 | } | |
1476 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1477 | dev_dbg(musb->controller, |
550a7375 FB |
1478 | "%s: hw_ep %d%s, %smax %d\n", |
1479 | musb_driver_name, i, | |
1480 | "rx", | |
1481 | hw_ep->rx_double_buffered | |
1482 | ? "doublebuffer, " : "", | |
1483 | hw_ep->max_packet_sz_rx); | |
1484 | } | |
1485 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1486 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1487 | } |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | /*-------------------------------------------------------------------------*/ | |
1493 | ||
59b479e0 | 1494 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ |
d0678594 | 1495 | defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) |
550a7375 FB |
1496 | |
1497 | static irqreturn_t generic_interrupt(int irq, void *__hci) | |
1498 | { | |
1499 | unsigned long flags; | |
1500 | irqreturn_t retval = IRQ_NONE; | |
1501 | struct musb *musb = __hci; | |
1502 | ||
1503 | spin_lock_irqsave(&musb->lock, flags); | |
1504 | ||
1505 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); | |
1506 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); | |
1507 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); | |
1508 | ||
1509 | if (musb->int_usb || musb->int_tx || musb->int_rx) | |
1510 | retval = musb_interrupt(musb); | |
1511 | ||
1512 | spin_unlock_irqrestore(&musb->lock, flags); | |
1513 | ||
a5073b52 | 1514 | return retval; |
550a7375 FB |
1515 | } |
1516 | ||
1517 | #else | |
1518 | #define generic_interrupt NULL | |
1519 | #endif | |
1520 | ||
1521 | /* | |
1522 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1523 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1524 | * will be assigned, and the irq will already have been acked. | |
1525 | * | |
1526 | * called in irq context with spinlock held, irqs blocked | |
1527 | */ | |
1528 | irqreturn_t musb_interrupt(struct musb *musb) | |
1529 | { | |
1530 | irqreturn_t retval = IRQ_NONE; | |
1531 | u8 devctl, power; | |
1532 | int ep_num; | |
1533 | u32 reg; | |
1534 | ||
1535 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1536 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1537 | ||
5c8a86e1 | 1538 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
550a7375 FB |
1539 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", |
1540 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1541 | ||
1542 | /* the core can interrupt us for multiple reasons; docs have | |
1543 | * a generic interrupt flowchart to follow | |
1544 | */ | |
7d9645fd | 1545 | if (musb->int_usb) |
550a7375 FB |
1546 | retval |= musb_stage0_irq(musb, musb->int_usb, |
1547 | devctl, power); | |
1548 | ||
1549 | /* "stage 1" is handling endpoint irqs */ | |
1550 | ||
1551 | /* handle endpoint 0 first */ | |
1552 | if (musb->int_tx & 1) { | |
1553 | if (devctl & MUSB_DEVCTL_HM) | |
1554 | retval |= musb_h_ep0_irq(musb); | |
1555 | else | |
1556 | retval |= musb_g_ep0_irq(musb); | |
1557 | } | |
1558 | ||
1559 | /* RX on endpoints 1-15 */ | |
1560 | reg = musb->int_rx >> 1; | |
1561 | ep_num = 1; | |
1562 | while (reg) { | |
1563 | if (reg & 1) { | |
1564 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1565 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1566 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1567 | if (devctl & MUSB_DEVCTL_HM) |
1568 | musb_host_rx(musb, ep_num); | |
1569 | else | |
1570 | musb_g_rx(musb, ep_num); | |
550a7375 FB |
1571 | } |
1572 | ||
1573 | reg >>= 1; | |
1574 | ep_num++; | |
1575 | } | |
1576 | ||
1577 | /* TX on endpoints 1-15 */ | |
1578 | reg = musb->int_tx >> 1; | |
1579 | ep_num = 1; | |
1580 | while (reg) { | |
1581 | if (reg & 1) { | |
1582 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1583 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1584 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1585 | if (devctl & MUSB_DEVCTL_HM) |
1586 | musb_host_tx(musb, ep_num); | |
1587 | else | |
1588 | musb_g_tx(musb, ep_num); | |
550a7375 FB |
1589 | } |
1590 | reg >>= 1; | |
1591 | ep_num++; | |
1592 | } | |
1593 | ||
550a7375 FB |
1594 | return retval; |
1595 | } | |
981430a1 | 1596 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1597 | |
1598 | #ifndef CONFIG_MUSB_PIO_ONLY | |
e9e8c85e | 1599 | static bool __devinitdata use_dma = 1; |
550a7375 FB |
1600 | |
1601 | /* "modprobe ... use_dma=0" etc */ | |
1602 | module_param(use_dma, bool, 0); | |
1603 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1604 | ||
1605 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1606 | { | |
1607 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1608 | ||
1609 | /* called with controller lock already held */ | |
1610 | ||
1611 | if (!epnum) { | |
1612 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1613 | if (!is_cppi_enabled()) { | |
1614 | /* endpoint 0 */ | |
1615 | if (devctl & MUSB_DEVCTL_HM) | |
1616 | musb_h_ep0_irq(musb); | |
1617 | else | |
1618 | musb_g_ep0_irq(musb); | |
1619 | } | |
1620 | #endif | |
1621 | } else { | |
1622 | /* endpoints 1..15 */ | |
1623 | if (transmit) { | |
a04d46d0 FB |
1624 | if (devctl & MUSB_DEVCTL_HM) |
1625 | musb_host_tx(musb, epnum); | |
1626 | else | |
1627 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1628 | } else { |
1629 | /* receive */ | |
a04d46d0 FB |
1630 | if (devctl & MUSB_DEVCTL_HM) |
1631 | musb_host_rx(musb, epnum); | |
1632 | else | |
1633 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1634 | } |
1635 | } | |
1636 | } | |
9a35f876 | 1637 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1638 | |
1639 | #else | |
1640 | #define use_dma 0 | |
1641 | #endif | |
1642 | ||
1643 | /*-------------------------------------------------------------------------*/ | |
1644 | ||
1645 | #ifdef CONFIG_SYSFS | |
1646 | ||
1647 | static ssize_t | |
1648 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1649 | { | |
1650 | struct musb *musb = dev_to_musb(dev); | |
1651 | unsigned long flags; | |
1652 | int ret = -EINVAL; | |
1653 | ||
1654 | spin_lock_irqsave(&musb->lock, flags); | |
3df00453 | 1655 | ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1656 | spin_unlock_irqrestore(&musb->lock, flags); |
1657 | ||
1658 | return ret; | |
1659 | } | |
1660 | ||
1661 | static ssize_t | |
1662 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1663 | const char *buf, size_t n) | |
1664 | { | |
1665 | struct musb *musb = dev_to_musb(dev); | |
1666 | unsigned long flags; | |
96a274d1 | 1667 | int status; |
550a7375 FB |
1668 | |
1669 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1670 | if (sysfs_streq(buf, "host")) |
1671 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1672 | else if (sysfs_streq(buf, "peripheral")) | |
1673 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1674 | else if (sysfs_streq(buf, "otg")) | |
1675 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1676 | else | |
1677 | status = -EINVAL; | |
550a7375 FB |
1678 | spin_unlock_irqrestore(&musb->lock, flags); |
1679 | ||
96a274d1 | 1680 | return (status == 0) ? n : status; |
550a7375 FB |
1681 | } |
1682 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1683 | ||
1684 | static ssize_t | |
1685 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1686 | const char *buf, size_t n) | |
1687 | { | |
1688 | struct musb *musb = dev_to_musb(dev); | |
1689 | unsigned long flags; | |
1690 | unsigned long val; | |
1691 | ||
1692 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1693 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1694 | return -EINVAL; |
1695 | } | |
1696 | ||
1697 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1698 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1699 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
84e250ff | 1700 | if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1701 | musb->is_active = 0; |
1702 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1703 | spin_unlock_irqrestore(&musb->lock, flags); | |
1704 | ||
1705 | return n; | |
1706 | } | |
1707 | ||
1708 | static ssize_t | |
1709 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1710 | { | |
1711 | struct musb *musb = dev_to_musb(dev); | |
1712 | unsigned long flags; | |
1713 | unsigned long val; | |
1714 | int vbus; | |
1715 | ||
1716 | spin_lock_irqsave(&musb->lock, flags); | |
1717 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1718 | /* FIXME get_vbus_status() is normally #defined as false... |
1719 | * and is effectively TUSB-specific. | |
1720 | */ | |
550a7375 FB |
1721 | vbus = musb_platform_get_vbus_status(musb); |
1722 | spin_unlock_irqrestore(&musb->lock, flags); | |
1723 | ||
f7f9d63e | 1724 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1725 | vbus ? "on" : "off", val); |
1726 | } | |
1727 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1728 | ||
550a7375 FB |
1729 | /* Gadget drivers can't know that a host is connected so they might want |
1730 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1731 | */ | |
1732 | static ssize_t | |
1733 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1734 | const char *buf, size_t n) | |
1735 | { | |
1736 | struct musb *musb = dev_to_musb(dev); | |
1737 | unsigned short srp; | |
1738 | ||
1739 | if (sscanf(buf, "%hu", &srp) != 1 | |
1740 | || (srp != 1)) { | |
b3b1cc3b | 1741 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1742 | return -EINVAL; |
1743 | } | |
1744 | ||
1745 | if (srp == 1) | |
1746 | musb_g_wakeup(musb); | |
1747 | ||
1748 | return n; | |
1749 | } | |
1750 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1751 | ||
94375751 FB |
1752 | static struct attribute *musb_attributes[] = { |
1753 | &dev_attr_mode.attr, | |
1754 | &dev_attr_vbus.attr, | |
94375751 | 1755 | &dev_attr_srp.attr, |
94375751 FB |
1756 | NULL |
1757 | }; | |
1758 | ||
1759 | static const struct attribute_group musb_attr_group = { | |
1760 | .attrs = musb_attributes, | |
1761 | }; | |
1762 | ||
550a7375 FB |
1763 | #endif /* sysfs */ |
1764 | ||
1765 | /* Only used to provide driver mode change events */ | |
1766 | static void musb_irq_work(struct work_struct *data) | |
1767 | { | |
1768 | struct musb *musb = container_of(data, struct musb, irq_work); | |
1769 | static int old_state; | |
1770 | ||
84e250ff DB |
1771 | if (musb->xceiv->state != old_state) { |
1772 | old_state = musb->xceiv->state; | |
550a7375 FB |
1773 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1774 | } | |
1775 | } | |
1776 | ||
1777 | /* -------------------------------------------------------------------------- | |
1778 | * Init support | |
1779 | */ | |
1780 | ||
e9e8c85e | 1781 | static struct musb *__devinit |
ca6d1b13 FB |
1782 | allocate_instance(struct device *dev, |
1783 | struct musb_hdrc_config *config, void __iomem *mbase) | |
550a7375 FB |
1784 | { |
1785 | struct musb *musb; | |
1786 | struct musb_hw_ep *ep; | |
1787 | int epnum; | |
550a7375 FB |
1788 | struct usb_hcd *hcd; |
1789 | ||
427c4f33 | 1790 | hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); |
550a7375 FB |
1791 | if (!hcd) |
1792 | return NULL; | |
1793 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
1794 | ||
1795 | musb = hcd_to_musb(hcd); | |
1796 | INIT_LIST_HEAD(&musb->control); | |
1797 | INIT_LIST_HEAD(&musb->in_bulk); | |
1798 | INIT_LIST_HEAD(&musb->out_bulk); | |
1799 | ||
1800 | hcd->uses_new_polling = 1; | |
ec95d35a | 1801 | hcd->has_tt = 1; |
550a7375 FB |
1802 | |
1803 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; | |
f7f9d63e | 1804 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
456bb169 | 1805 | dev_set_drvdata(dev, musb); |
550a7375 FB |
1806 | musb->mregs = mbase; |
1807 | musb->ctrl_base = mbase; | |
1808 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1809 | musb->config = config; |
02582b92 | 1810 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1811 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1812 | epnum < musb->config->num_eps; |
550a7375 | 1813 | epnum++, ep++) { |
550a7375 FB |
1814 | ep->musb = musb; |
1815 | ep->epnum = epnum; | |
1816 | } | |
1817 | ||
1818 | musb->controller = dev; | |
743411b3 | 1819 | |
550a7375 FB |
1820 | return musb; |
1821 | } | |
1822 | ||
1823 | static void musb_free(struct musb *musb) | |
1824 | { | |
1825 | /* this has multiple entry modes. it handles fault cleanup after | |
1826 | * probe(), where things may be partially set up, as well as rmmod | |
1827 | * cleanup after everything's been de-activated. | |
1828 | */ | |
1829 | ||
1830 | #ifdef CONFIG_SYSFS | |
94375751 | 1831 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1832 | #endif |
1833 | ||
97a39896 AKG |
1834 | if (musb->nIrq >= 0) { |
1835 | if (musb->irq_wake) | |
1836 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1837 | free_irq(musb->nIrq, musb); |
1838 | } | |
1839 | if (is_dma_capable() && musb->dma_controller) { | |
1840 | struct dma_controller *c = musb->dma_controller; | |
1841 | ||
1842 | (void) c->stop(c); | |
1843 | dma_controller_destroy(c); | |
1844 | } | |
1845 | ||
decadacb | 1846 | usb_put_hcd(musb_to_hcd(musb)); |
550a7375 FB |
1847 | } |
1848 | ||
1849 | /* | |
1850 | * Perform generic per-controller initialization. | |
1851 | * | |
1852 | * @pDevice: the controller (already clocked, etc) | |
1853 | * @nIrq: irq | |
1854 | * @mregs: virtual address of controller registers, | |
1855 | * not yet corrected for platform-specific offsets | |
1856 | */ | |
e9e8c85e | 1857 | static int __devinit |
550a7375 FB |
1858 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
1859 | { | |
1860 | int status; | |
1861 | struct musb *musb; | |
1862 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
032ec49f | 1863 | struct usb_hcd *hcd; |
550a7375 FB |
1864 | |
1865 | /* The driver might handle more features than the board; OK. | |
1866 | * Fail when the board needs a feature that's not enabled. | |
1867 | */ | |
1868 | if (!plat) { | |
1869 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1870 | status = -ENODEV; |
1871 | goto fail0; | |
550a7375 | 1872 | } |
34e2beb2 | 1873 | |
550a7375 | 1874 | /* allocate */ |
ca6d1b13 | 1875 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1876 | if (!musb) { |
1877 | status = -ENOMEM; | |
1878 | goto fail0; | |
1879 | } | |
550a7375 | 1880 | |
7acc6197 HH |
1881 | pm_runtime_use_autosuspend(musb->controller); |
1882 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
1883 | pm_runtime_enable(musb->controller); | |
1884 | ||
550a7375 | 1885 | spin_lock_init(&musb->lock); |
550a7375 | 1886 | musb->board_set_power = plat->set_power; |
550a7375 | 1887 | musb->min_power = plat->min_power; |
f7ec9437 | 1888 | musb->ops = plat->platform_ops; |
550a7375 | 1889 | |
84e250ff DB |
1890 | /* The musb_platform_init() call: |
1891 | * - adjusts musb->mregs and musb->isr if needed, | |
1892 | * - may initialize an integrated tranceiver | |
721002ec | 1893 | * - initializes musb->xceiv, usually by otg_get_phy() |
84e250ff | 1894 | * - stops powering VBUS |
84e250ff | 1895 | * |
7c9d440e | 1896 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
1897 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
1898 | * external/discrete ones in various flavors (twl4030 family, | |
1899 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 FB |
1900 | */ |
1901 | musb->isr = generic_interrupt; | |
ea65df57 | 1902 | status = musb_platform_init(musb); |
550a7375 | 1903 | if (status < 0) |
03491761 | 1904 | goto fail1; |
34e2beb2 | 1905 | |
550a7375 FB |
1906 | if (!musb->isr) { |
1907 | status = -ENODEV; | |
c04352a5 | 1908 | goto fail2; |
550a7375 FB |
1909 | } |
1910 | ||
ffb865b1 | 1911 | if (!musb->xceiv->io_ops) { |
bf070bc1 | 1912 | musb->xceiv->io_dev = musb->controller; |
ffb865b1 HK |
1913 | musb->xceiv->io_priv = musb->mregs; |
1914 | musb->xceiv->io_ops = &musb_ulpi_access; | |
1915 | } | |
1916 | ||
c04352a5 GI |
1917 | pm_runtime_get_sync(musb->controller); |
1918 | ||
550a7375 FB |
1919 | #ifndef CONFIG_MUSB_PIO_ONLY |
1920 | if (use_dma && dev->dma_mask) { | |
1921 | struct dma_controller *c; | |
1922 | ||
1923 | c = dma_controller_create(musb, musb->mregs); | |
1924 | musb->dma_controller = c; | |
1925 | if (c) | |
1926 | (void) c->start(c); | |
1927 | } | |
1928 | #endif | |
1929 | /* ideally this would be abstracted in platform setup */ | |
1930 | if (!is_dma_capable() || !musb->dma_controller) | |
1931 | dev->dma_mask = NULL; | |
1932 | ||
1933 | /* be sure interrupts are disabled before connecting ISR */ | |
1934 | musb_platform_disable(musb); | |
1935 | musb_generic_disable(musb); | |
1936 | ||
1937 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1938 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1939 | ? MUSB_CONTROLLER_MHDRC |
1940 | : MUSB_CONTROLLER_HDRC, musb); | |
1941 | if (status < 0) | |
34e2beb2 | 1942 | goto fail3; |
550a7375 | 1943 | |
f7f9d63e | 1944 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 1945 | |
550a7375 FB |
1946 | /* Init IRQ workqueue before request_irq */ |
1947 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1948 | ||
1949 | /* attach to the IRQ */ | |
427c4f33 | 1950 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1951 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1952 | status = -ENODEV; | |
34e2beb2 | 1953 | goto fail3; |
550a7375 FB |
1954 | } |
1955 | musb->nIrq = nIrq; | |
032ec49f | 1956 | /* FIXME this handles wakeup irqs wrong */ |
c48a5155 FB |
1957 | if (enable_irq_wake(nIrq) == 0) { |
1958 | musb->irq_wake = 1; | |
550a7375 | 1959 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1960 | } else { |
1961 | musb->irq_wake = 0; | |
1962 | } | |
550a7375 | 1963 | |
84e250ff | 1964 | /* host side needs more setup */ |
032ec49f FB |
1965 | hcd = musb_to_hcd(musb); |
1966 | otg_set_host(musb->xceiv->otg, &hcd->self); | |
1967 | hcd->self.otg_port = 1; | |
1968 | musb->xceiv->otg->host = &hcd->self; | |
1969 | hcd->power_budget = 2 * (plat->power ? : 250); | |
1970 | ||
1971 | /* program PHY to use external vBus if required */ | |
1972 | if (plat->extvbus) { | |
1973 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
1974 | busctl |= MUSB_ULPI_USE_EXTVBUS; | |
1975 | musb_write_ulpi_buscontrol(musb->mregs, busctl); | |
550a7375 | 1976 | } |
550a7375 | 1977 | |
032ec49f FB |
1978 | MUSB_DEV_MODE(musb); |
1979 | musb->xceiv->otg->default_a = 0; | |
1980 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
550a7375 | 1981 | |
032ec49f | 1982 | status = musb_gadget_setup(musb); |
550a7375 | 1983 | |
461972d8 | 1984 | if (status < 0) |
34e2beb2 | 1985 | goto fail3; |
550a7375 | 1986 | |
7f7f9e2a FB |
1987 | status = musb_init_debugfs(musb); |
1988 | if (status < 0) | |
b0f9da7e | 1989 | goto fail4; |
7f7f9e2a | 1990 | |
550a7375 | 1991 | #ifdef CONFIG_SYSFS |
94375751 | 1992 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 1993 | if (status) |
b0f9da7e | 1994 | goto fail5; |
461972d8 | 1995 | #endif |
550a7375 | 1996 | |
c04352a5 GI |
1997 | pm_runtime_put(musb->controller); |
1998 | ||
28c2c51c | 1999 | return 0; |
550a7375 | 2000 | |
b0f9da7e FB |
2001 | fail5: |
2002 | musb_exit_debugfs(musb); | |
2003 | ||
34e2beb2 | 2004 | fail4: |
032ec49f | 2005 | musb_gadget_cleanup(musb); |
34e2beb2 SS |
2006 | |
2007 | fail3: | |
c04352a5 GI |
2008 | pm_runtime_put_sync(musb->controller); |
2009 | ||
2010 | fail2: | |
34e2beb2 SS |
2011 | if (musb->irq_wake) |
2012 | device_init_wakeup(dev, 0); | |
550a7375 | 2013 | musb_platform_exit(musb); |
28c2c51c | 2014 | |
34e2beb2 SS |
2015 | fail1: |
2016 | dev_err(musb->controller, | |
2017 | "musb_init_controller failed with status %d\n", status); | |
2018 | ||
28c2c51c FB |
2019 | musb_free(musb); |
2020 | ||
34e2beb2 SS |
2021 | fail0: |
2022 | ||
28c2c51c FB |
2023 | return status; |
2024 | ||
550a7375 FB |
2025 | } |
2026 | ||
2027 | /*-------------------------------------------------------------------------*/ | |
2028 | ||
2029 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2030 | * bridge to a platform device; this driver then suffices. | |
2031 | */ | |
2032 | ||
2033 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2034 | static u64 *orig_dma_mask; | |
2035 | #endif | |
2036 | ||
e9e8c85e | 2037 | static int __devinit musb_probe(struct platform_device *pdev) |
550a7375 FB |
2038 | { |
2039 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2040 | int irq = platform_get_irq_byname(pdev, "mc"); |
da5108e1 | 2041 | int status; |
550a7375 FB |
2042 | struct resource *iomem; |
2043 | void __iomem *base; | |
2044 | ||
2045 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
541079de | 2046 | if (!iomem || irq <= 0) |
550a7375 FB |
2047 | return -ENODEV; |
2048 | ||
195e9e46 | 2049 | base = ioremap(iomem->start, resource_size(iomem)); |
550a7375 FB |
2050 | if (!base) { |
2051 | dev_err(dev, "ioremap failed\n"); | |
2052 | return -ENOMEM; | |
2053 | } | |
2054 | ||
2055 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2056 | /* clobbered by use_dma=n */ | |
2057 | orig_dma_mask = dev->dma_mask; | |
2058 | #endif | |
da5108e1 FB |
2059 | status = musb_init_controller(dev, irq, base); |
2060 | if (status < 0) | |
2061 | iounmap(base); | |
2062 | ||
2063 | return status; | |
550a7375 FB |
2064 | } |
2065 | ||
e9e8c85e | 2066 | static int __devexit musb_remove(struct platform_device *pdev) |
550a7375 FB |
2067 | { |
2068 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2069 | void __iomem *ctrl_base = musb->ctrl_base; | |
2070 | ||
2071 | /* this gets called on rmmod. | |
2072 | * - Host mode: host may still be active | |
2073 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2074 | * - OTG mode: both roles are deactivated (or never-activated) | |
2075 | */ | |
7f7f9e2a | 2076 | musb_exit_debugfs(musb); |
550a7375 | 2077 | musb_shutdown(pdev); |
461972d8 | 2078 | |
550a7375 FB |
2079 | musb_free(musb); |
2080 | iounmap(ctrl_base); | |
2081 | device_init_wakeup(&pdev->dev, 0); | |
2082 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2083 | pdev->dev.dma_mask = orig_dma_mask; | |
2084 | #endif | |
2085 | return 0; | |
2086 | } | |
2087 | ||
2088 | #ifdef CONFIG_PM | |
2089 | ||
3c8a5fcc | 2090 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2091 | { |
2092 | int i; | |
2093 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2094 | void __iomem *epio; |
4f712e01 | 2095 | |
032ec49f FB |
2096 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2097 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2098 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
7421107b FB |
2099 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
2100 | musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); | |
2101 | musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); | |
2102 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); | |
2103 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2104 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2105 | |
ae9b2ad2 | 2106 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2107 | struct musb_hw_ep *hw_ep; |
2108 | ||
2109 | hw_ep = &musb->endpoints[i]; | |
2110 | if (!hw_ep) | |
2111 | continue; | |
2112 | ||
2113 | epio = hw_ep->regs; | |
2114 | if (!epio) | |
2115 | continue; | |
2116 | ||
ea737554 | 2117 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2118 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2119 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2120 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2121 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2122 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2123 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2124 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2125 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2126 | |
2127 | if (musb->dyn_fifo) { | |
7421107b | 2128 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2129 | musb_read_txfifoadd(musb_base); |
7421107b | 2130 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2131 | musb_read_rxfifoadd(musb_base); |
7421107b | 2132 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2133 | musb_read_txfifosz(musb_base); |
7421107b | 2134 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2135 | musb_read_rxfifosz(musb_base); |
2136 | } | |
032ec49f FB |
2137 | |
2138 | musb->context.index_regs[i].txtype = | |
2139 | musb_readb(epio, MUSB_TXTYPE); | |
2140 | musb->context.index_regs[i].txinterval = | |
2141 | musb_readb(epio, MUSB_TXINTERVAL); | |
2142 | musb->context.index_regs[i].rxtype = | |
2143 | musb_readb(epio, MUSB_RXTYPE); | |
2144 | musb->context.index_regs[i].rxinterval = | |
2145 | musb_readb(epio, MUSB_RXINTERVAL); | |
2146 | ||
2147 | musb->context.index_regs[i].txfunaddr = | |
2148 | musb_read_txfunaddr(musb_base, i); | |
2149 | musb->context.index_regs[i].txhubaddr = | |
2150 | musb_read_txhubaddr(musb_base, i); | |
2151 | musb->context.index_regs[i].txhubport = | |
2152 | musb_read_txhubport(musb_base, i); | |
2153 | ||
2154 | musb->context.index_regs[i].rxfunaddr = | |
2155 | musb_read_rxfunaddr(musb_base, i); | |
2156 | musb->context.index_regs[i].rxhubaddr = | |
2157 | musb_read_rxhubaddr(musb_base, i); | |
2158 | musb->context.index_regs[i].rxhubport = | |
2159 | musb_read_rxhubport(musb_base, i); | |
4f712e01 | 2160 | } |
4f712e01 AKG |
2161 | } |
2162 | ||
3c8a5fcc | 2163 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2164 | { |
2165 | int i; | |
2166 | void __iomem *musb_base = musb->mregs; | |
2167 | void __iomem *ep_target_regs; | |
ae9b2ad2 | 2168 | void __iomem *epio; |
4f712e01 | 2169 | |
032ec49f FB |
2170 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2171 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2172 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
7421107b FB |
2173 | musb_writeb(musb_base, MUSB_POWER, musb->context.power); |
2174 | musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); | |
2175 | musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); | |
2176 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); | |
2177 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2178 | |
ae9b2ad2 | 2179 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2180 | struct musb_hw_ep *hw_ep; |
2181 | ||
2182 | hw_ep = &musb->endpoints[i]; | |
2183 | if (!hw_ep) | |
2184 | continue; | |
2185 | ||
2186 | epio = hw_ep->regs; | |
2187 | if (!epio) | |
2188 | continue; | |
2189 | ||
ea737554 | 2190 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2191 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2192 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2193 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2194 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2195 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2196 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2197 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2198 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2199 | |
2200 | if (musb->dyn_fifo) { | |
2201 | musb_write_txfifosz(musb_base, | |
7421107b | 2202 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2203 | musb_write_rxfifosz(musb_base, |
7421107b | 2204 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2205 | musb_write_txfifoadd(musb_base, |
7421107b | 2206 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2207 | musb_write_rxfifoadd(musb_base, |
7421107b | 2208 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2209 | } |
2210 | ||
032ec49f | 2211 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2212 | musb->context.index_regs[i].txtype); |
032ec49f | 2213 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2214 | musb->context.index_regs[i].txinterval); |
032ec49f | 2215 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2216 | musb->context.index_regs[i].rxtype); |
032ec49f | 2217 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2218 | |
032ec49f FB |
2219 | musb->context.index_regs[i].rxinterval); |
2220 | musb_write_txfunaddr(musb_base, i, | |
7421107b | 2221 | musb->context.index_regs[i].txfunaddr); |
032ec49f | 2222 | musb_write_txhubaddr(musb_base, i, |
7421107b | 2223 | musb->context.index_regs[i].txhubaddr); |
032ec49f | 2224 | musb_write_txhubport(musb_base, i, |
7421107b | 2225 | musb->context.index_regs[i].txhubport); |
4f712e01 | 2226 | |
032ec49f FB |
2227 | ep_target_regs = |
2228 | musb_read_target_reg_base(i, musb_base); | |
4f712e01 | 2229 | |
032ec49f | 2230 | musb_write_rxfunaddr(ep_target_regs, |
7421107b | 2231 | musb->context.index_regs[i].rxfunaddr); |
032ec49f | 2232 | musb_write_rxhubaddr(ep_target_regs, |
7421107b | 2233 | musb->context.index_regs[i].rxhubaddr); |
032ec49f | 2234 | musb_write_rxhubport(ep_target_regs, |
7421107b | 2235 | musb->context.index_regs[i].rxhubport); |
4f712e01 | 2236 | } |
3c5fec75 | 2237 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2238 | } |
2239 | ||
48fea965 | 2240 | static int musb_suspend(struct device *dev) |
550a7375 | 2241 | { |
8220796d | 2242 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2243 | unsigned long flags; |
550a7375 | 2244 | |
550a7375 FB |
2245 | spin_lock_irqsave(&musb->lock, flags); |
2246 | ||
2247 | if (is_peripheral_active(musb)) { | |
2248 | /* FIXME force disconnect unless we know USB will wake | |
2249 | * the system up quickly enough to respond ... | |
2250 | */ | |
2251 | } else if (is_host_active(musb)) { | |
2252 | /* we know all the children are suspended; sometimes | |
2253 | * they will even be wakeup-enabled. | |
2254 | */ | |
2255 | } | |
2256 | ||
550a7375 FB |
2257 | spin_unlock_irqrestore(&musb->lock, flags); |
2258 | return 0; | |
2259 | } | |
2260 | ||
48fea965 | 2261 | static int musb_resume_noirq(struct device *dev) |
550a7375 | 2262 | { |
550a7375 | 2263 | /* for static cmos like DaVinci, register values were preserved |
0ec8fd70 KK |
2264 | * unless for some reason the whole soc powered down or the USB |
2265 | * module got reset through the PSC (vs just being disabled). | |
550a7375 | 2266 | */ |
550a7375 FB |
2267 | return 0; |
2268 | } | |
2269 | ||
7acc6197 HH |
2270 | static int musb_runtime_suspend(struct device *dev) |
2271 | { | |
2272 | struct musb *musb = dev_to_musb(dev); | |
2273 | ||
2274 | musb_save_context(musb); | |
2275 | ||
2276 | return 0; | |
2277 | } | |
2278 | ||
2279 | static int musb_runtime_resume(struct device *dev) | |
2280 | { | |
2281 | struct musb *musb = dev_to_musb(dev); | |
2282 | static int first = 1; | |
2283 | ||
2284 | /* | |
2285 | * When pm_runtime_get_sync called for the first time in driver | |
2286 | * init, some of the structure is still not initialized which is | |
2287 | * used in restore function. But clock needs to be | |
2288 | * enabled before any register access, so | |
2289 | * pm_runtime_get_sync has to be called. | |
2290 | * Also context restore without save does not make | |
2291 | * any sense | |
2292 | */ | |
2293 | if (!first) | |
2294 | musb_restore_context(musb); | |
2295 | first = 0; | |
2296 | ||
2297 | return 0; | |
2298 | } | |
2299 | ||
47145210 | 2300 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 MD |
2301 | .suspend = musb_suspend, |
2302 | .resume_noirq = musb_resume_noirq, | |
7acc6197 HH |
2303 | .runtime_suspend = musb_runtime_suspend, |
2304 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2305 | }; |
2306 | ||
2307 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2308 | #else |
48fea965 | 2309 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2310 | #endif |
2311 | ||
2312 | static struct platform_driver musb_driver = { | |
2313 | .driver = { | |
2314 | .name = (char *)musb_driver_name, | |
2315 | .bus = &platform_bus_type, | |
2316 | .owner = THIS_MODULE, | |
48fea965 | 2317 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2318 | }, |
e9e8c85e FB |
2319 | .probe = musb_probe, |
2320 | .remove = __devexit_p(musb_remove), | |
550a7375 | 2321 | .shutdown = musb_shutdown, |
550a7375 FB |
2322 | }; |
2323 | ||
2324 | /*-------------------------------------------------------------------------*/ | |
2325 | ||
2326 | static int __init musb_init(void) | |
2327 | { | |
550a7375 FB |
2328 | if (usb_disabled()) |
2329 | return 0; | |
550a7375 FB |
2330 | |
2331 | pr_info("%s: version " MUSB_VERSION ", " | |
550a7375 | 2332 | "?dma?" |
550a7375 | 2333 | ", " |
62285963 | 2334 | "otg (peripheral+host)", |
5c8a86e1 | 2335 | musb_driver_name); |
e9e8c85e | 2336 | return platform_driver_register(&musb_driver); |
550a7375 | 2337 | } |
e9e8c85e | 2338 | module_init(musb_init); |
550a7375 FB |
2339 | |
2340 | static void __exit musb_cleanup(void) | |
2341 | { | |
2342 | platform_driver_unregister(&musb_driver); | |
2343 | } | |
2344 | module_exit(musb_cleanup); |