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USB: remove obsolete config in kernel source (USB_HCD_DMA)
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375
FB		 85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101
102#ifdef CONFIG_ARM
0590d587
FB		 103#include <mach/hardware.h>
104#include <mach/memory.h>
550a7375
FB		 105#include <asm/mach-types.h>
106#endif
107
108#include "musb_core.h"
109
110
111#ifdef CONFIG_ARCH_DAVINCI
112#include "davinci.h"
113#endif
114
f7f9d63e 115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 116
117
b60c72ab 118unsigned musb_debug;
34f32c97 119module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
e8164f64 120MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
550a7375
FB		 121
122#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
123#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124
e8164f64 125#define MUSB_VERSION "6.0"
550a7375
FB		 126
127#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128
129#define MUSB_DRIVER_NAME "musb_hdrc"
130const char musb_driver_name[] = MUSB_DRIVER_NAME;
131
132MODULE_DESCRIPTION(DRIVER_INFO);
133MODULE_AUTHOR(DRIVER_AUTHOR);
134MODULE_LICENSE("GPL");
135MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
136
137
138/*-------------------------------------------------------------------------*/
139
140static inline struct musb *dev_to_musb(struct device *dev)
141{
142#ifdef CONFIG_USB_MUSB_HDRC_HCD
143 /* usbcore insists dev->driver_data is a "struct hcd *" */
144 return hcd_to_musb(dev_get_drvdata(dev));
145#else
146 return dev_get_drvdata(dev);
147#endif
148}
149
150/*-------------------------------------------------------------------------*/
151
c6cf8b00
BW		 152#if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
153
550a7375
FB		 154/*
155 * Load an endpoint's FIFO
156 */
157void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
158{
159 void __iomem *fifo = hw_ep->fifo;
160
161 prefetch((u8 *)src);
162
163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
164 'T', hw_ep->epnum, fifo, len, src);
165
166 /* we can't assume unaligned reads work */
167 if (likely((0x01 & (unsigned long) src) == 0)) {
168 u16 index = 0;
169
170 /* best case is 32bit-aligned source address */
171 if ((0x02 & (unsigned long) src) == 0) {
172 if (len >= 4) {
173 writesl(fifo, src + index, len >> 2);
174 index += len & ~0x03;
175 }
176 if (len & 0x02) {
177 musb_writew(fifo, 0, *(u16 *)&src[index]);
178 index += 2;
179 }
180 } else {
181 if (len >= 2) {
182 writesw(fifo, src + index, len >> 1);
183 index += len & ~0x01;
184 }
185 }
186 if (len & 0x01)
187 musb_writeb(fifo, 0, src[index]);
188 } else {
189 /* byte aligned */
190 writesb(fifo, src, len);
191 }
192}
193
194/*
195 * Unload an endpoint's FIFO
196 */
197void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
198{
199 void __iomem *fifo = hw_ep->fifo;
200
201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
202 'R', hw_ep->epnum, fifo, len, dst);
203
204 /* we can't assume unaligned writes work */
205 if (likely((0x01 & (unsigned long) dst) == 0)) {
206 u16 index = 0;
207
208 /* best case is 32bit-aligned destination address */
209 if ((0x02 & (unsigned long) dst) == 0) {
210 if (len >= 4) {
211 readsl(fifo, dst, len >> 2);
212 index = len & ~0x03;
213 }
214 if (len & 0x02) {
215 *(u16 *)&dst[index] = musb_readw(fifo, 0);
216 index += 2;
217 }
218 } else {
219 if (len >= 2) {
220 readsw(fifo, dst, len >> 1);
221 index = len & ~0x01;
222 }
223 }
224 if (len & 0x01)
225 dst[index] = musb_readb(fifo, 0);
226 } else {
227 /* byte aligned */
228 readsb(fifo, dst, len);
229 }
230}
231
232#endif /* normal PIO */
233
234
235/*-------------------------------------------------------------------------*/
236
237/* for high speed test mode; see USB 2.0 spec 7.1.20 */
238static const u8 musb_test_packet[53] = {
239 /* implicit SYNC then DATA0 to start */
240
241 /* JKJKJKJK x9 */
242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 /* JJKKJJKK x8 */
244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
245 /* JJJJKKKK x8 */
246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
247 /* JJJJJJJKKKKKKK x8 */
248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
249 /* JJJJJJJK x8 */
250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
251 /* JKKKKKKK x10, JK */
252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
253
254 /* implicit CRC16 then EOP to end */
255};
256
257void musb_load_testpacket(struct musb *musb)
258{
259 void __iomem *regs = musb->endpoints[0].regs;
260
261 musb_ep_select(musb->mregs, 0);
262 musb_write_fifo(musb->control_ep,
263 sizeof(musb_test_packet), musb_test_packet);
264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
265}
266
267/*-------------------------------------------------------------------------*/
268
269const char *otg_state_string(struct musb *musb)
270{
84e250ff 271 switch (musb->xceiv->state) {
550a7375
FB		 272 case OTG_STATE_A_IDLE: return "a_idle";
273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
275 case OTG_STATE_A_HOST: return "a_host";
276 case OTG_STATE_A_SUSPEND: return "a_suspend";
277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
280 case OTG_STATE_B_IDLE: return "b_idle";
281 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
284 case OTG_STATE_B_HOST: return "b_host";
285 default: return "UNDEFINED";
286 }
287}
288
289#ifdef CONFIG_USB_MUSB_OTG
290
550a7375
FB		 291/*
292 * Handles OTG hnp timeouts, such as b_ase0_brst
293 */
294void musb_otg_timer_func(unsigned long data)
295{
296 struct musb *musb = (struct musb *)data;
297 unsigned long flags;
298
299 spin_lock_irqsave(&musb->lock, flags);
84e250ff 300 switch (musb->xceiv->state) {
550a7375
FB		 301 case OTG_STATE_B_WAIT_ACON:
302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
303 musb_g_disconnect(musb);
84e250ff 304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 305 musb->is_active = 0;
306 break;
ab983f2a 307 case OTG_STATE_A_SUSPEND:
550a7375 308 case OTG_STATE_A_WAIT_BCON:
ab983f2a
DB		 309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
310 musb_set_vbus(musb, 0);
311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 312 break;
313 default:
314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
315 }
316 musb->ignore_disconnect = 0;
317 spin_unlock_irqrestore(&musb->lock, flags);
318}
319
550a7375 320/*
f7f9d63e 321 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 322 */
323void musb_hnp_stop(struct musb *musb)
324{
325 struct usb_hcd *hcd = musb_to_hcd(musb);
326 void __iomem *mbase = musb->mregs;
327 u8 reg;
328
ab983f2a
DB		 329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
330
84e250ff 331 switch (musb->xceiv->state) {
550a7375 332 case OTG_STATE_A_PERIPHERAL:
550a7375 333 musb_g_disconnect(musb);
ab983f2a 334 DBG(1, "HNP: back to %s\n", otg_state_string(musb));
550a7375
FB		 335 break;
336 case OTG_STATE_B_HOST:
337 DBG(1, "HNP: Disabling HR\n");
338 hcd->self.is_b_host = 0;
84e250ff 339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 340 MUSB_DEV_MODE(musb);
341 reg = musb_readb(mbase, MUSB_POWER);
342 reg |= MUSB_POWER_SUSPENDM;
343 musb_writeb(mbase, MUSB_POWER, reg);
344 /* REVISIT: Start SESSION_REQUEST here? */
345 break;
346 default:
347 DBG(1, "HNP: Stopping in unknown state %s\n",
348 otg_state_string(musb));
349 }
350
351 /*
352 * When returning to A state after HNP, avoid hub_port_rebounce(),
353 * which cause occasional OPT A "Did not receive reset after connect"
354 * errors.
355 */
356 musb->port1_status &=
357 ~(1 << USB_PORT_FEAT_C_CONNECTION);
358}
359
360#endif
361
362/*
363 * Interrupt Service Routine to record USB "global" interrupts.
364 * Since these do not happen often and signify things of
365 * paramount importance, it seems OK to check them individually;
366 * the order of the tests is specified in the manual
367 *
368 * @param musb instance pointer
369 * @param int_usb register contents
370 * @param devctl
371 * @param power
372 */
373
374#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
376 | MUSB_INTR_RESET)
377
378static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
379 u8 devctl, u8 power)
380{
381 irqreturn_t handled = IRQ_NONE;
382 void __iomem *mbase = musb->mregs;
383
384 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
385 int_usb);
386
387 /* in host mode, the peripheral may issue remote wakeup.
388 * in peripheral mode, the host may resume the link.
389 * spurious RESUME irqs happen too, paired with SUSPEND.
390 */
391 if (int_usb & MUSB_INTR_RESUME) {
392 handled = IRQ_HANDLED;
393 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
394
395 if (devctl & MUSB_DEVCTL_HM) {
396#ifdef CONFIG_USB_MUSB_HDRC_HCD
84e250ff 397 switch (musb->xceiv->state) {
550a7375
FB		 398 case OTG_STATE_A_SUSPEND:
399 /* remote wakeup? later, GetPortStatus
400 * will stop RESUME signaling
401 */
402
403 if (power & MUSB_POWER_SUSPENDM) {
404 /* spurious */
405 musb->int_usb &= ~MUSB_INTR_SUSPEND;
406 DBG(2, "Spurious SUSPENDM\n");
407 break;
408 }
409
410 power &= ~MUSB_POWER_SUSPENDM;
411 musb_writeb(mbase, MUSB_POWER,
412 power | MUSB_POWER_RESUME);
413
414 musb->port1_status |=
415 (USB_PORT_STAT_C_SUSPEND << 16)
416 | MUSB_PORT_STAT_RESUME;
417 musb->rh_timer = jiffies
418 + msecs_to_jiffies(20);
419
84e250ff 420 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 421 musb->is_active = 1;
422 usb_hcd_resume_root_hub(musb_to_hcd(musb));
423 break;
424 case OTG_STATE_B_WAIT_ACON:
84e250ff 425 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 426 musb->is_active = 1;
427 MUSB_DEV_MODE(musb);
428 break;
429 default:
430 WARNING("bogus %s RESUME (%s)\n",
431 "host",
432 otg_state_string(musb));
433 }
434#endif
435 } else {
84e250ff 436 switch (musb->xceiv->state) {
550a7375
FB		 437#ifdef CONFIG_USB_MUSB_HDRC_HCD
438 case OTG_STATE_A_SUSPEND:
439 /* possibly DISCONNECT is upcoming */
84e250ff 440 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 441 usb_hcd_resume_root_hub(musb_to_hcd(musb));
442 break;
443#endif
444#ifdef CONFIG_USB_GADGET_MUSB_HDRC
445 case OTG_STATE_B_WAIT_ACON:
446 case OTG_STATE_B_PERIPHERAL:
447 /* disconnect while suspended? we may
448 * not get a disconnect irq...
449 */
450 if ((devctl & MUSB_DEVCTL_VBUS)
451 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
452 ) {
453 musb->int_usb |= MUSB_INTR_DISCONNECT;
454 musb->int_usb &= ~MUSB_INTR_SUSPEND;
455 break;
456 }
457 musb_g_resume(musb);
458 break;
459 case OTG_STATE_B_IDLE:
460 musb->int_usb &= ~MUSB_INTR_SUSPEND;
461 break;
462#endif
463 default:
464 WARNING("bogus %s RESUME (%s)\n",
465 "peripheral",
466 otg_state_string(musb));
467 }
468 }
469 }
470
471#ifdef CONFIG_USB_MUSB_HDRC_HCD
472 /* see manual for the order of the tests */
473 if (int_usb & MUSB_INTR_SESSREQ) {
474 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
475
476 /* IRQ arrives from ID pin sense or (later, if VBUS power
477 * is removed) SRP. responses are time critical:
478 * - turn on VBUS (with silicon-specific mechanism)
479 * - go through A_WAIT_VRISE
480 * - ... to A_WAIT_BCON.
481 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
482 */
483 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
484 musb->ep0_stage = MUSB_EP0_START;
84e250ff 485 musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375
FB		 486 MUSB_HST_MODE(musb);
487 musb_set_vbus(musb, 1);
488
489 handled = IRQ_HANDLED;
490 }
491
492 if (int_usb & MUSB_INTR_VBUSERROR) {
493 int ignore = 0;
494
495 /* During connection as an A-Device, we may see a short
496 * current spikes causing voltage drop, because of cable
497 * and peripheral capacitance combined with vbus draw.
498 * (So: less common with truly self-powered devices, where
499 * vbus doesn't act like a power supply.)
500 *
501 * Such spikes are short; usually less than ~500 usec, max
502 * of ~2 msec. That is, they're not sustained overcurrent
503 * errors, though they're reported using VBUSERROR irqs.
504 *
505 * Workarounds: (a) hardware: use self powered devices.
506 * (b) software: ignore non-repeated VBUS errors.
507 *
508 * REVISIT: do delays from lots of DEBUG_KERNEL checks
509 * make trouble here, keeping VBUS < 4.4V ?
510 */
84e250ff 511 switch (musb->xceiv->state) {
550a7375
FB		 512 case OTG_STATE_A_HOST:
513 /* recovery is dicey once we've gotten past the
514 * initial stages of enumeration, but if VBUS
515 * stayed ok at the other end of the link, and
516 * another reset is due (at least for high speed,
517 * to redo the chirp etc), it might work OK...
518 */
519 case OTG_STATE_A_WAIT_BCON:
520 case OTG_STATE_A_WAIT_VRISE:
521 if (musb->vbuserr_retry) {
522 musb->vbuserr_retry--;
523 ignore = 1;
524 devctl |= MUSB_DEVCTL_SESSION;
525 musb_writeb(mbase, MUSB_DEVCTL, devctl);
526 } else {
527 musb->port1_status |=
528 (1 << USB_PORT_FEAT_OVER_CURRENT)
529 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
530 }
531 break;
532 default:
533 break;
534 }
535
536 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
537 otg_state_string(musb),
538 devctl,
539 ({ char *s;
540 switch (devctl & MUSB_DEVCTL_VBUS) {
541 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
542 s = "<SessEnd"; break;
543 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
544 s = "<AValid"; break;
545 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
546 s = "<VBusValid"; break;
547 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
548 default:
549 s = "VALID"; break;
550 }; s; }),
551 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
552 musb->port1_status);
553
554 /* go through A_WAIT_VFALL then start a new session */
555 if (!ignore)
556 musb_set_vbus(musb, 0);
557 handled = IRQ_HANDLED;
558 }
559
1c25fda4
AM		 560
561 if (int_usb & MUSB_INTR_SUSPEND) {
562 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
563 otg_state_string(musb), devctl, power);
564 handled = IRQ_HANDLED;
565
566 switch (musb->xceiv->state) {
567#ifdef CONFIG_USB_MUSB_OTG
568 case OTG_STATE_A_PERIPHERAL:
569 /* We also come here if the cable is removed, since
570 * this silicon doesn't report ID-no-longer-grounded.
571 *
572 * We depend on T(a_wait_bcon) to shut us down, and
573 * hope users don't do anything dicey during this
574 * undesired detour through A_WAIT_BCON.
575 */
576 musb_hnp_stop(musb);
577 usb_hcd_resume_root_hub(musb_to_hcd(musb));
578 musb_root_disconnect(musb);
579 musb_platform_try_idle(musb, jiffies
580 + msecs_to_jiffies(musb->a_wait_bcon
581 ? : OTG_TIME_A_WAIT_BCON));
582
583 break;
584#endif
585 case OTG_STATE_B_IDLE:
586 if (!musb->is_active)
587 break;
588 case OTG_STATE_B_PERIPHERAL:
589 musb_g_suspend(musb);
590 musb->is_active = is_otg_enabled(musb)
591 && musb->xceiv->gadget->b_hnp_enable;
592 if (musb->is_active) {
593#ifdef CONFIG_USB_MUSB_OTG
594 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
595 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
596 mod_timer(&musb->otg_timer, jiffies
597 + msecs_to_jiffies(
598 OTG_TIME_B_ASE0_BRST));
599#endif
600 }
601 break;
602 case OTG_STATE_A_WAIT_BCON:
603 if (musb->a_wait_bcon != 0)
604 musb_platform_try_idle(musb, jiffies
605 + msecs_to_jiffies(musb->a_wait_bcon));
606 break;
607 case OTG_STATE_A_HOST:
608 musb->xceiv->state = OTG_STATE_A_SUSPEND;
609 musb->is_active = is_otg_enabled(musb)
610 && musb->xceiv->host->b_hnp_enable;
611 break;
612 case OTG_STATE_B_HOST:
613 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
614 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
615 break;
616 default:
617 /* "should not happen" */
618 musb->is_active = 0;
619 break;
620 }
621 }
622
550a7375
FB		 623 if (int_usb & MUSB_INTR_CONNECT) {
624 struct usb_hcd *hcd = musb_to_hcd(musb);
625
626 handled = IRQ_HANDLED;
627 musb->is_active = 1;
628 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
629
630 musb->ep0_stage = MUSB_EP0_START;
631
632#ifdef CONFIG_USB_MUSB_OTG
633 /* flush endpoints when transitioning from Device Mode */
634 if (is_peripheral_active(musb)) {
635 /* REVISIT HNP; just force disconnect */
636 }
637 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
638 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
639 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
640#endif
641 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
642 |USB_PORT_STAT_HIGH_SPEED
643 |USB_PORT_STAT_ENABLE
644 );
645 musb->port1_status |= USB_PORT_STAT_CONNECTION
646 |(USB_PORT_STAT_C_CONNECTION << 16);
647
648 /* high vs full speed is just a guess until after reset */
649 if (devctl & MUSB_DEVCTL_LSDEV)
650 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
651
550a7375 652 /* indicate new connection to OTG machine */
84e250ff 653 switch (musb->xceiv->state) {
550a7375
FB		 654 case OTG_STATE_B_PERIPHERAL:
655 if (int_usb & MUSB_INTR_SUSPEND) {
656 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 657 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 658 goto b_host;
550a7375
FB		 659 } else
660 DBG(1, "CONNECT as b_peripheral???\n");
661 break;
662 case OTG_STATE_B_WAIT_ACON:
1de00dae
DB		 663 DBG(1, "HNP: CONNECT, now b_host\n");
664b_host:
84e250ff 665 musb->xceiv->state = OTG_STATE_B_HOST;
550a7375 666 hcd->self.is_b_host = 1;
1de00dae
DB		 667 musb->ignore_disconnect = 0;
668 del_timer(&musb->otg_timer);
550a7375
FB		 669 break;
670 default:
671 if ((devctl & MUSB_DEVCTL_VBUS)
672 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
84e250ff 673 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375
FB		 674 hcd->self.is_b_host = 0;
675 }
676 break;
677 }
1de00dae
DB		 678
679 /* poke the root hub */
680 MUSB_HST_MODE(musb);
681 if (hcd->status_urb)
682 usb_hcd_poll_rh_status(hcd);
683 else
684 usb_hcd_resume_root_hub(hcd);
685
550a7375
FB		 686 DBG(1, "CONNECT (%s) devctl %02x\n",
687 otg_state_string(musb), devctl);
688 }
689#endif /* CONFIG_USB_MUSB_HDRC_HCD */
690
1c25fda4
AM		 691 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
692 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
693 otg_state_string(musb),
694 MUSB_MODE(musb), devctl);
695 handled = IRQ_HANDLED;
696
697 switch (musb->xceiv->state) {
698#ifdef CONFIG_USB_MUSB_HDRC_HCD
699 case OTG_STATE_A_HOST:
700 case OTG_STATE_A_SUSPEND:
701 usb_hcd_resume_root_hub(musb_to_hcd(musb));
702 musb_root_disconnect(musb);
703 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
704 musb_platform_try_idle(musb, jiffies
705 + msecs_to_jiffies(musb->a_wait_bcon));
706 break;
707#endif /* HOST */
708#ifdef CONFIG_USB_MUSB_OTG
709 case OTG_STATE_B_HOST:
710 /* REVISIT this behaves for "real disconnect"
711 * cases; make sure the other transitions from
712 * from B_HOST act right too. The B_HOST code
713 * in hnp_stop() is currently not used...
714 */
715 musb_root_disconnect(musb);
716 musb_to_hcd(musb)->self.is_b_host = 0;
717 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
718 MUSB_DEV_MODE(musb);
719 musb_g_disconnect(musb);
720 break;
721 case OTG_STATE_A_PERIPHERAL:
722 musb_hnp_stop(musb);
723 musb_root_disconnect(musb);
724 /* FALLTHROUGH */
725 case OTG_STATE_B_WAIT_ACON:
726 /* FALLTHROUGH */
727#endif /* OTG */
728#ifdef CONFIG_USB_GADGET_MUSB_HDRC
729 case OTG_STATE_B_PERIPHERAL:
730 case OTG_STATE_B_IDLE:
731 musb_g_disconnect(musb);
732 break;
733#endif /* GADGET */
734 default:
735 WARNING("unhandled DISCONNECT transition (%s)\n",
736 otg_state_string(musb));
737 break;
738 }
739 }
740
550a7375
FB		 741 /* mentor saves a bit: bus reset and babble share the same irq.
742 * only host sees babble; only peripheral sees bus reset.
743 */
744 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 745 handled = IRQ_HANDLED;
550a7375
FB		 746 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
747 /*
748 * Looks like non-HS BABBLE can be ignored, but
749 * HS BABBLE is an error condition. For HS the solution
750 * is to avoid babble in the first place and fix what
751 * caused BABBLE. When HS BABBLE happens we can only
752 * stop the session.
753 */
754 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
755 DBG(1, "BABBLE devctl: %02x\n", devctl);
756 else {
757 ERR("Stopping host session -- babble\n");
1c25fda4 758 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375
FB		 759 }
760 } else if (is_peripheral_capable()) {
761 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
84e250ff 762 switch (musb->xceiv->state) {
550a7375
FB		 763#ifdef CONFIG_USB_OTG
764 case OTG_STATE_A_SUSPEND:
765 /* We need to ignore disconnect on suspend
766 * otherwise tusb 2.0 won't reconnect after a
767 * power cycle, which breaks otg compliance.
768 */
769 musb->ignore_disconnect = 1;
770 musb_g_reset(musb);
771 /* FALLTHROUGH */
772 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e
DB		 773 /* never use invalid T(a_wait_bcon) */
774 DBG(1, "HNP: in %s, %d msec timeout\n",
775 otg_state_string(musb),
776 TA_WAIT_BCON(musb));
777 mod_timer(&musb->otg_timer, jiffies
778 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 779 break;
780 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 781 musb->ignore_disconnect = 0;
782 del_timer(&musb->otg_timer);
783 musb_g_reset(musb);
550a7375
FB		 784 break;
785 case OTG_STATE_B_WAIT_ACON:
786 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
787 otg_state_string(musb));
84e250ff 788 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 789 musb_g_reset(musb);
790 break;
791#endif
792 case OTG_STATE_B_IDLE:
84e250ff 793 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 794 /* FALLTHROUGH */
795 case OTG_STATE_B_PERIPHERAL:
796 musb_g_reset(musb);
797 break;
798 default:
799 DBG(1, "Unhandled BUS RESET as %s\n",
800 otg_state_string(musb));
801 }
802 }
550a7375 803 }
550a7375
FB		 804
805#if 0
806/* REVISIT ... this would be for multiplexing periodic endpoints, or
807 * supporting transfer phasing to prevent exceeding ISO bandwidth
808 * limits of a given frame or microframe.
809 *
810 * It's not needed for peripheral side, which dedicates endpoints;
811 * though it _might_ use SOF irqs for other purposes.
812 *
813 * And it's not currently needed for host side, which also dedicates
814 * endpoints, relies on TX/RX interval registers, and isn't claimed
815 * to support ISO transfers yet.
816 */
817 if (int_usb & MUSB_INTR_SOF) {
818 void __iomem *mbase = musb->mregs;
819 struct musb_hw_ep *ep;
820 u8 epnum;
821 u16 frame;
822
823 DBG(6, "START_OF_FRAME\n");
824 handled = IRQ_HANDLED;
825
826 /* start any periodic Tx transfers waiting for current frame */
827 frame = musb_readw(mbase, MUSB_FRAME);
828 ep = musb->endpoints;
829 for (epnum = 1; (epnum < musb->nr_endpoints)
830 && (musb->epmask >= (1 << epnum));
831 epnum++, ep++) {
832 /*
833 * FIXME handle framecounter wraps (12 bits)
834 * eliminate duplicated StartUrb logic
835 */
836 if (ep->dwWaitFrame >= frame) {
837 ep->dwWaitFrame = 0;
838 pr_debug("SOF --> periodic TX%s on %d\n",
839 ep->tx_channel ? " DMA" : "",
840 epnum);
841 if (!ep->tx_channel)
842 musb_h_tx_start(musb, epnum);
843 else
844 cppi_hostdma_start(musb, epnum);
845 }
846 } /* end of for loop */
847 }
848#endif
849
1c25fda4 850 schedule_work(&musb->irq_work);
550a7375
FB		 851
852 return handled;
853}
854
855/*-------------------------------------------------------------------------*/
856
857/*
858* Program the HDRC to start (enable interrupts, dma, etc.).
859*/
860void musb_start(struct musb *musb)
861{
862 void __iomem *regs = musb->mregs;
863 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
864
865 DBG(2, "<== devctl %02x\n", devctl);
866
867 /* Set INT enable registers, enable interrupts */
868 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
869 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
870 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
871
872 musb_writeb(regs, MUSB_TESTMODE, 0);
873
874 /* put into basic highspeed mode and start session */
875 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
876 | MUSB_POWER_SOFTCONN
877 | MUSB_POWER_HSENAB
878 /* ENSUSPEND wedges tusb */
879 /* | MUSB_POWER_ENSUSPEND */
880 );
881
882 musb->is_active = 0;
883 devctl = musb_readb(regs, MUSB_DEVCTL);
884 devctl &= ~MUSB_DEVCTL_SESSION;
885
886 if (is_otg_enabled(musb)) {
887 /* session started after:
888 * (a) ID-grounded irq, host mode;
889 * (b) vbus present/connect IRQ, peripheral mode;
890 * (c) peripheral initiates, using SRP
891 */
892 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
893 musb->is_active = 1;
894 else
895 devctl |= MUSB_DEVCTL_SESSION;
896
897 } else if (is_host_enabled(musb)) {
898 /* assume ID pin is hard-wired to ground */
899 devctl |= MUSB_DEVCTL_SESSION;
900
901 } else /* peripheral is enabled */ {
902 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
903 musb->is_active = 1;
904 }
905 musb_platform_enable(musb);
906 musb_writeb(regs, MUSB_DEVCTL, devctl);
907}
908
909
910static void musb_generic_disable(struct musb *musb)
911{
912 void __iomem *mbase = musb->mregs;
913 u16 temp;
914
915 /* disable interrupts */
916 musb_writeb(mbase, MUSB_INTRUSBE, 0);
917 musb_writew(mbase, MUSB_INTRTXE, 0);
918 musb_writew(mbase, MUSB_INTRRXE, 0);
919
920 /* off */
921 musb_writeb(mbase, MUSB_DEVCTL, 0);
922
923 /* flush pending interrupts */
924 temp = musb_readb(mbase, MUSB_INTRUSB);
925 temp = musb_readw(mbase, MUSB_INTRTX);
926 temp = musb_readw(mbase, MUSB_INTRRX);
927
928}
929
930/*
931 * Make the HDRC stop (disable interrupts, etc.);
932 * reversible by musb_start
933 * called on gadget driver unregister
934 * with controller locked, irqs blocked
935 * acts as a NOP unless some role activated the hardware
936 */
937void musb_stop(struct musb *musb)
938{
939 /* stop IRQs, timers, ... */
940 musb_platform_disable(musb);
941 musb_generic_disable(musb);
942 DBG(3, "HDRC disabled\n");
943
944 /* FIXME
945 * - mark host and/or peripheral drivers unusable/inactive
946 * - disable DMA (and enable it in HdrcStart)
947 * - make sure we can musb_start() after musb_stop(); with
948 * OTG mode, gadget driver module rmmod/modprobe cycles that
949 * - ...
950 */
951 musb_platform_try_idle(musb, 0);
952}
953
954static void musb_shutdown(struct platform_device *pdev)
955{
956 struct musb *musb = dev_to_musb(&pdev->dev);
957 unsigned long flags;
958
959 spin_lock_irqsave(&musb->lock, flags);
960 musb_platform_disable(musb);
961 musb_generic_disable(musb);
962 if (musb->clock) {
963 clk_put(musb->clock);
964 musb->clock = NULL;
965 }
966 spin_unlock_irqrestore(&musb->lock, flags);
967
968 /* FIXME power down */
969}
970
971
972/*-------------------------------------------------------------------------*/
973
974/*
975 * The silicon either has hard-wired endpoint configurations, or else
976 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 977 * writing only the dynamic sizing is very well tested. Since we switched
978 * away from compile-time hardware parameters, we can no longer rely on
979 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 980 *
981 * We don't currently use dynamic fifo setup capability to do anything
982 * more than selecting one of a bunch of predefined configurations.
983 */
550a7375
FB		 984#if defined(CONFIG_USB_TUSB6010) || \
985 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
986static ushort __initdata fifo_mode = 4;
987#else
988static ushort __initdata fifo_mode = 2;
989#endif
990
991/* "modprobe ... fifo_mode=1" etc */
992module_param(fifo_mode, ushort, 0);
993MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
994
995
550a7375
FB		 996enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
997enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
998
999struct fifo_cfg {
1000 u8 hw_ep_num;
1001 enum fifo_style style;
1002 enum buf_mode mode;
1003 u16 maxpacket;
1004};
1005
1006/*
1007 * tables defining fifo_mode values. define more if you like.
1008 * for host side, make sure both halves of ep1 are set up.
1009 */
1010
1011/* mode 0 - fits in 2KB */
1012static struct fifo_cfg __initdata mode_0_cfg[] = {
1013{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1014{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1015{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1016{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1017{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1018};
1019
1020/* mode 1 - fits in 4KB */
1021static struct fifo_cfg __initdata mode_1_cfg[] = {
1022{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1023{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1024{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1025{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1026{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1027};
1028
1029/* mode 2 - fits in 4KB */
1030static struct fifo_cfg __initdata mode_2_cfg[] = {
1031{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1032{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1033{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1034{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1035{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1036{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1037};
1038
1039/* mode 3 - fits in 4KB */
1040static struct fifo_cfg __initdata mode_3_cfg[] = {
1041{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1042{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1043{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1044{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1045{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1046{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1047};
1048
1049/* mode 4 - fits in 16KB */
1050static struct fifo_cfg __initdata mode_4_cfg[] = {
1051{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1052{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1053{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1054{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1055{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1056{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1057{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1058{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1059{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1060{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1061{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1062{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1063{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1064{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1065{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1066{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1067{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1068{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1069{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1070{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1071{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1072{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1073{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1074{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1075{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1076{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1077{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1078};
1079
3b151526
AKG		 1080/* mode 5 - fits in 8KB */
1081static struct fifo_cfg __initdata mode_5_cfg[] = {
1082{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1083{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1084{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1085{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1086{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1087{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1088{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1089{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1090{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1091{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1092{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1093{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1094{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1095{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1096{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1097{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1098{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1099{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1100{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1101{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1102{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1103{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1104{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1105{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1106{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1107{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1108{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1109};
550a7375
FB		 1110
1111/*
1112 * configure a fifo; for non-shared endpoints, this may be called
1113 * once for a tx fifo and once for an rx fifo.
1114 *
1115 * returns negative errno or offset for next fifo.
1116 */
1117static int __init
1118fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1119 const struct fifo_cfg *cfg, u16 offset)
1120{
1121 void __iomem *mbase = musb->mregs;
1122 int size = 0;
1123 u16 maxpacket = cfg->maxpacket;
1124 u16 c_off = offset >> 3;
1125 u8 c_size;
1126
1127 /* expect hw_ep has already been zero-initialized */
1128
1129 size = ffs(max(maxpacket, (u16) 8)) - 1;
1130 maxpacket = 1 << size;
1131
1132 c_size = size - 3;
1133 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1134 if ((offset + (maxpacket << 1)) >
1135 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1136 return -EMSGSIZE;
1137 c_size |= MUSB_FIFOSZ_DPB;
1138 } else {
ca6d1b13 1139 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1140 return -EMSGSIZE;
1141 }
1142
1143 /* configure the FIFO */
1144 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1145
1146#ifdef CONFIG_USB_MUSB_HDRC_HCD
1147 /* EP0 reserved endpoint for control, bidirectional;
1148 * EP1 reserved for bulk, two unidirection halves.
1149 */
1150 if (hw_ep->epnum == 1)
1151 musb->bulk_ep = hw_ep;
1152 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1153#endif
1154 switch (cfg->style) {
1155 case FIFO_TX:
c6cf8b00
BW		 1156 musb_write_txfifosz(mbase, c_size);
1157 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1158 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1159 hw_ep->max_packet_sz_tx = maxpacket;
1160 break;
1161 case FIFO_RX:
c6cf8b00
BW		 1162 musb_write_rxfifosz(mbase, c_size);
1163 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1164 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1165 hw_ep->max_packet_sz_rx = maxpacket;
1166 break;
1167 case FIFO_RXTX:
c6cf8b00
BW		 1168 musb_write_txfifosz(mbase, c_size);
1169 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1170 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1171 hw_ep->max_packet_sz_rx = maxpacket;
1172
c6cf8b00
BW		 1173 musb_write_rxfifosz(mbase, c_size);
1174 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1175 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1176 hw_ep->max_packet_sz_tx = maxpacket;
1177
1178 hw_ep->is_shared_fifo = true;
1179 break;
1180 }
1181
1182 /* NOTE rx and tx endpoint irqs aren't managed separately,
1183 * which happens to be ok
1184 */
1185 musb->epmask |= (1 << hw_ep->epnum);
1186
1187 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1188}
1189
1190static struct fifo_cfg __initdata ep0_cfg = {
1191 .style = FIFO_RXTX, .maxpacket = 64,
1192};
1193
1194static int __init ep_config_from_table(struct musb *musb)
1195{
1196 const struct fifo_cfg *cfg;
1197 unsigned i, n;
1198 int offset;
1199 struct musb_hw_ep *hw_ep = musb->endpoints;
1200
1201 switch (fifo_mode) {
1202 default:
1203 fifo_mode = 0;
1204 /* FALLTHROUGH */
1205 case 0:
1206 cfg = mode_0_cfg;
1207 n = ARRAY_SIZE(mode_0_cfg);
1208 break;
1209 case 1:
1210 cfg = mode_1_cfg;
1211 n = ARRAY_SIZE(mode_1_cfg);
1212 break;
1213 case 2:
1214 cfg = mode_2_cfg;
1215 n = ARRAY_SIZE(mode_2_cfg);
1216 break;
1217 case 3:
1218 cfg = mode_3_cfg;
1219 n = ARRAY_SIZE(mode_3_cfg);
1220 break;
1221 case 4:
1222 cfg = mode_4_cfg;
1223 n = ARRAY_SIZE(mode_4_cfg);
1224 break;
3b151526
AKG		 1225 case 5:
1226 cfg = mode_5_cfg;
1227 n = ARRAY_SIZE(mode_5_cfg);
1228 break;
550a7375
FB		 1229 }
1230
1231 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1232 musb_driver_name, fifo_mode);
1233
1234
1235 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1236 /* assert(offset > 0) */
1237
1238 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1239 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1240 */
1241
1242 for (i = 0; i < n; i++) {
1243 u8 epn = cfg->hw_ep_num;
1244
ca6d1b13 1245 if (epn >= musb->config->num_eps) {
550a7375
FB		 1246 pr_debug("%s: invalid ep %d\n",
1247 musb_driver_name, epn);
bb1c9ef1 1248 return -EINVAL;
550a7375
FB		 1249 }
1250 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1251 if (offset < 0) {
1252 pr_debug("%s: mem overrun, ep %d\n",
1253 musb_driver_name, epn);
1254 return -EINVAL;
1255 }
1256 epn++;
1257 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1258 }
1259
1260 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1261 musb_driver_name,
ca6d1b13
FB		 1262 n + 1, musb->config->num_eps * 2 - 1,
1263 offset, (1 << (musb->config->ram_bits + 2)));
550a7375
FB		 1264
1265#ifdef CONFIG_USB_MUSB_HDRC_HCD
1266 if (!musb->bulk_ep) {
1267 pr_debug("%s: missing bulk\n", musb_driver_name);
1268 return -EINVAL;
1269 }
1270#endif
1271
1272 return 0;
1273}
1274
1275
1276/*
1277 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1278 * @param musb the controller
1279 */
1280static int __init ep_config_from_hw(struct musb *musb)
1281{
c6cf8b00 1282 u8 epnum = 0;
550a7375
FB		 1283 struct musb_hw_ep *hw_ep;
1284 void *mbase = musb->mregs;
c6cf8b00 1285 int ret = 0;
550a7375
FB		 1286
1287 DBG(2, "<== static silicon ep config\n");
1288
1289 /* FIXME pick up ep0 maxpacket size */
1290
ca6d1b13 1291 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1292 musb_ep_select(mbase, epnum);
1293 hw_ep = musb->endpoints + epnum;
1294
c6cf8b00
BW		 1295 ret = musb_read_fifosize(musb, hw_ep, epnum);
1296 if (ret < 0)
550a7375 1297 break;
550a7375
FB		 1298
1299 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1300
1301#ifdef CONFIG_USB_MUSB_HDRC_HCD
1302 /* pick an RX/TX endpoint for bulk */
1303 if (hw_ep->max_packet_sz_tx < 512
1304 || hw_ep->max_packet_sz_rx < 512)
1305 continue;
1306
1307 /* REVISIT: this algorithm is lazy, we should at least
1308 * try to pick a double buffered endpoint.
1309 */
1310 if (musb->bulk_ep)
1311 continue;
1312 musb->bulk_ep = hw_ep;
1313#endif
1314 }
1315
1316#ifdef CONFIG_USB_MUSB_HDRC_HCD
1317 if (!musb->bulk_ep) {
1318 pr_debug("%s: missing bulk\n", musb_driver_name);
1319 return -EINVAL;
1320 }
1321#endif
1322
1323 return 0;
1324}
1325
1326enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1327
1328/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1329 * configure endpoints, or take their config from silicon
1330 */
1331static int __init musb_core_init(u16 musb_type, struct musb *musb)
1332{
550a7375
FB		 1333 u8 reg;
1334 char *type;
0ea52ff4 1335 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1336 void __iomem *mbase = musb->mregs;
1337 int status = 0;
1338 int i;
1339
1340 /* log core options (read using indexed model) */
c6cf8b00 1341 reg = musb_read_configdata(mbase);
550a7375
FB		 1342
1343 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1344 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1345 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1346 musb->dyn_fifo = true;
1347 }
550a7375
FB		 1348 if (reg & MUSB_CONFIGDATA_MPRXE) {
1349 strcat(aInfo, ", bulk combine");
550a7375 1350 musb->bulk_combine = true;
550a7375
FB		 1351 }
1352 if (reg & MUSB_CONFIGDATA_MPTXE) {
1353 strcat(aInfo, ", bulk split");
550a7375 1354 musb->bulk_split = true;
550a7375
FB		 1355 }
1356 if (reg & MUSB_CONFIGDATA_HBRXE) {
1357 strcat(aInfo, ", HB-ISO Rx");
a483d706 1358 musb->hb_iso_rx = true;
550a7375
FB		 1359 }
1360 if (reg & MUSB_CONFIGDATA_HBTXE) {
1361 strcat(aInfo, ", HB-ISO Tx");
a483d706 1362 musb->hb_iso_tx = true;
550a7375
FB		 1363 }
1364 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1365 strcat(aInfo, ", SoftConn");
1366
1367 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1368 musb_driver_name, reg, aInfo);
1369
550a7375 1370 aDate[0] = 0;
550a7375
FB		 1371 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1372 musb->is_multipoint = 1;
1373 type = "M";
1374 } else {
1375 musb->is_multipoint = 0;
1376 type = "";
1377#ifdef CONFIG_USB_MUSB_HDRC_HCD
1378#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1379 printk(KERN_ERR
1380 "%s: kernel must blacklist external hubs\n",
1381 musb_driver_name);
1382#endif
1383#endif
1384 }
1385
1386 /* log release info */
32c3b94e
AG		 1387 musb->hwvers = musb_read_hwvers(mbase);
1388 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1389 MUSB_HWVERS_MINOR(musb->hwvers),
1390 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1391 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1392 musb_driver_name, type, aRevision, aDate);
1393
1394 /* configure ep0 */
c6cf8b00 1395 musb_configure_ep0(musb);
550a7375
FB		 1396
1397 /* discover endpoint configuration */
1398 musb->nr_endpoints = 1;
1399 musb->epmask = 1;
1400
1401 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
ca6d1b13 1402 if (musb->config->dyn_fifo)
550a7375
FB		 1403 status = ep_config_from_table(musb);
1404 else {
1405 ERR("reconfigure software for Dynamic FIFOs\n");
1406 status = -ENODEV;
1407 }
1408 } else {
ca6d1b13 1409 if (!musb->config->dyn_fifo)
550a7375
FB		 1410 status = ep_config_from_hw(musb);
1411 else {
1412 ERR("reconfigure software for static FIFOs\n");
1413 return -ENODEV;
1414 }
1415 }
1416
1417 if (status < 0)
1418 return status;
1419
1420 /* finish init, and print endpoint config */
1421 for (i = 0; i < musb->nr_endpoints; i++) {
1422 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1423
1424 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1425#ifdef CONFIG_USB_TUSB6010
1426 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1427 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1428 hw_ep->fifo_sync_va =
1429 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1430
1431 if (i == 0)
1432 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1433 else
1434 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1435#endif
1436
1437 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1438#ifdef CONFIG_USB_MUSB_HDRC_HCD
c6cf8b00 1439 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1440 hw_ep->rx_reinit = 1;
1441 hw_ep->tx_reinit = 1;
1442#endif
1443
1444 if (hw_ep->max_packet_sz_tx) {
1230435c 1445 DBG(1,
550a7375
FB		 1446 "%s: hw_ep %d%s, %smax %d\n",
1447 musb_driver_name, i,
1448 hw_ep->is_shared_fifo ? "shared" : "tx",
1449 hw_ep->tx_double_buffered
1450 ? "doublebuffer, " : "",
1451 hw_ep->max_packet_sz_tx);
1452 }
1453 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1230435c 1454 DBG(1,
550a7375
FB		 1455 "%s: hw_ep %d%s, %smax %d\n",
1456 musb_driver_name, i,
1457 "rx",
1458 hw_ep->rx_double_buffered
1459 ? "doublebuffer, " : "",
1460 hw_ep->max_packet_sz_rx);
1461 }
1462 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1463 DBG(1, "hw_ep %d not configured\n", i);
1464 }
1465
1466 return 0;
1467}
1468
1469/*-------------------------------------------------------------------------*/
1470
1471#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1472
1473static irqreturn_t generic_interrupt(int irq, void *__hci)
1474{
1475 unsigned long flags;
1476 irqreturn_t retval = IRQ_NONE;
1477 struct musb *musb = __hci;
1478
1479 spin_lock_irqsave(&musb->lock, flags);
1480
1481 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1482 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1483 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1484
1485 if (musb->int_usb || musb->int_tx || musb->int_rx)
1486 retval = musb_interrupt(musb);
1487
1488 spin_unlock_irqrestore(&musb->lock, flags);
1489
a5073b52 1490 return retval;
550a7375
FB		 1491}
1492
1493#else
1494#define generic_interrupt NULL
1495#endif
1496
1497/*
1498 * handle all the irqs defined by the HDRC core. for now we expect: other
1499 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1500 * will be assigned, and the irq will already have been acked.
1501 *
1502 * called in irq context with spinlock held, irqs blocked
1503 */
1504irqreturn_t musb_interrupt(struct musb *musb)
1505{
1506 irqreturn_t retval = IRQ_NONE;
1507 u8 devctl, power;
1508 int ep_num;
1509 u32 reg;
1510
1511 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1512 power = musb_readb(musb->mregs, MUSB_POWER);
1513
1514 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1515 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1516 musb->int_usb, musb->int_tx, musb->int_rx);
1517
cd42fef0
FB		 1518#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1519 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1520 if (!musb->gadget_driver) {
1521 DBG(5, "No gadget driver loaded\n");
1522 return IRQ_HANDLED;
1523 }
1524#endif
1525
550a7375
FB		 1526 /* the core can interrupt us for multiple reasons; docs have
1527 * a generic interrupt flowchart to follow
1528 */
1529 if (musb->int_usb & STAGE0_MASK)
1530 retval |= musb_stage0_irq(musb, musb->int_usb,
1531 devctl, power);
1532
1533 /* "stage 1" is handling endpoint irqs */
1534
1535 /* handle endpoint 0 first */
1536 if (musb->int_tx & 1) {
1537 if (devctl & MUSB_DEVCTL_HM)
1538 retval |= musb_h_ep0_irq(musb);
1539 else
1540 retval |= musb_g_ep0_irq(musb);
1541 }
1542
1543 /* RX on endpoints 1-15 */
1544 reg = musb->int_rx >> 1;
1545 ep_num = 1;
1546 while (reg) {
1547 if (reg & 1) {
1548 /* musb_ep_select(musb->mregs, ep_num); */
1549 /* REVISIT just retval = ep->rx_irq(...) */
1550 retval = IRQ_HANDLED;
1551 if (devctl & MUSB_DEVCTL_HM) {
1552 if (is_host_capable())
1553 musb_host_rx(musb, ep_num);
1554 } else {
1555 if (is_peripheral_capable())
1556 musb_g_rx(musb, ep_num);
1557 }
1558 }
1559
1560 reg >>= 1;
1561 ep_num++;
1562 }
1563
1564 /* TX on endpoints 1-15 */
1565 reg = musb->int_tx >> 1;
1566 ep_num = 1;
1567 while (reg) {
1568 if (reg & 1) {
1569 /* musb_ep_select(musb->mregs, ep_num); */
1570 /* REVISIT just retval |= ep->tx_irq(...) */
1571 retval = IRQ_HANDLED;
1572 if (devctl & MUSB_DEVCTL_HM) {
1573 if (is_host_capable())
1574 musb_host_tx(musb, ep_num);
1575 } else {
1576 if (is_peripheral_capable())
1577 musb_g_tx(musb, ep_num);
1578 }
1579 }
1580 reg >>= 1;
1581 ep_num++;
1582 }
1583
550a7375
FB		 1584 return retval;
1585}
1586
1587
1588#ifndef CONFIG_MUSB_PIO_ONLY
1589static int __initdata use_dma = 1;
1590
1591/* "modprobe ... use_dma=0" etc */
1592module_param(use_dma, bool, 0);
1593MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1594
1595void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1596{
1597 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1598
1599 /* called with controller lock already held */
1600
1601 if (!epnum) {
1602#ifndef CONFIG_USB_TUSB_OMAP_DMA
1603 if (!is_cppi_enabled()) {
1604 /* endpoint 0 */
1605 if (devctl & MUSB_DEVCTL_HM)
1606 musb_h_ep0_irq(musb);
1607 else
1608 musb_g_ep0_irq(musb);
1609 }
1610#endif
1611 } else {
1612 /* endpoints 1..15 */
1613 if (transmit) {
1614 if (devctl & MUSB_DEVCTL_HM) {
1615 if (is_host_capable())
1616 musb_host_tx(musb, epnum);
1617 } else {
1618 if (is_peripheral_capable())
1619 musb_g_tx(musb, epnum);
1620 }
1621 } else {
1622 /* receive */
1623 if (devctl & MUSB_DEVCTL_HM) {
1624 if (is_host_capable())
1625 musb_host_rx(musb, epnum);
1626 } else {
1627 if (is_peripheral_capable())
1628 musb_g_rx(musb, epnum);
1629 }
1630 }
1631 }
1632}
1633
1634#else
1635#define use_dma 0
1636#endif
1637
1638/*-------------------------------------------------------------------------*/
1639
1640#ifdef CONFIG_SYSFS
1641
1642static ssize_t
1643musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1644{
1645 struct musb *musb = dev_to_musb(dev);
1646 unsigned long flags;
1647 int ret = -EINVAL;
1648
1649 spin_lock_irqsave(&musb->lock, flags);
1650 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1651 spin_unlock_irqrestore(&musb->lock, flags);
1652
1653 return ret;
1654}
1655
1656static ssize_t
1657musb_mode_store(struct device *dev, struct device_attribute *attr,
1658 const char *buf, size_t n)
1659{
1660 struct musb *musb = dev_to_musb(dev);
1661 unsigned long flags;
96a274d1 1662 int status;
550a7375
FB		 1663
1664 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1665 if (sysfs_streq(buf, "host"))
1666 status = musb_platform_set_mode(musb, MUSB_HOST);
1667 else if (sysfs_streq(buf, "peripheral"))
1668 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1669 else if (sysfs_streq(buf, "otg"))
1670 status = musb_platform_set_mode(musb, MUSB_OTG);
1671 else
1672 status = -EINVAL;
550a7375
FB		 1673 spin_unlock_irqrestore(&musb->lock, flags);
1674
96a274d1 1675 return (status == 0) ? n : status;
550a7375
FB		 1676}
1677static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1678
1679static ssize_t
1680musb_vbus_store(struct device *dev, struct device_attribute *attr,
1681 const char *buf, size_t n)
1682{
1683 struct musb *musb = dev_to_musb(dev);
1684 unsigned long flags;
1685 unsigned long val;
1686
1687 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1688 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1689 return -EINVAL;
1690 }
1691
1692 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1693 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1694 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
84e250ff 1695 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1696 musb->is_active = 0;
1697 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1698 spin_unlock_irqrestore(&musb->lock, flags);
1699
1700 return n;
1701}
1702
1703static ssize_t
1704musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1705{
1706 struct musb *musb = dev_to_musb(dev);
1707 unsigned long flags;
1708 unsigned long val;
1709 int vbus;
1710
1711 spin_lock_irqsave(&musb->lock, flags);
1712 val = musb->a_wait_bcon;
f7f9d63e
DB		 1713 /* FIXME get_vbus_status() is normally #defined as false...
1714 * and is effectively TUSB-specific.
1715 */
550a7375
FB		 1716 vbus = musb_platform_get_vbus_status(musb);
1717 spin_unlock_irqrestore(&musb->lock, flags);
1718
f7f9d63e 1719 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1720 vbus ? "on" : "off", val);
1721}
1722static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1723
1724#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1725
1726/* Gadget drivers can't know that a host is connected so they might want
1727 * to start SRP, but users can. This allows userspace to trigger SRP.
1728 */
1729static ssize_t
1730musb_srp_store(struct device *dev, struct device_attribute *attr,
1731 const char *buf, size_t n)
1732{
1733 struct musb *musb = dev_to_musb(dev);
1734 unsigned short srp;
1735
1736 if (sscanf(buf, "%hu", &srp) != 1
1737 || (srp != 1)) {
b3b1cc3b 1738 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1739 return -EINVAL;
1740 }
1741
1742 if (srp == 1)
1743 musb_g_wakeup(musb);
1744
1745 return n;
1746}
1747static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1748
1749#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1750
94375751
FB		 1751static struct attribute *musb_attributes[] = {
1752 &dev_attr_mode.attr,
1753 &dev_attr_vbus.attr,
1754#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1755 &dev_attr_srp.attr,
1756#endif
1757 NULL
1758};
1759
1760static const struct attribute_group musb_attr_group = {
1761 .attrs = musb_attributes,
1762};
1763
550a7375
FB		 1764#endif /* sysfs */
1765
1766/* Only used to provide driver mode change events */
1767static void musb_irq_work(struct work_struct *data)
1768{
1769 struct musb *musb = container_of(data, struct musb, irq_work);
1770 static int old_state;
1771
84e250ff
DB		 1772 if (musb->xceiv->state != old_state) {
1773 old_state = musb->xceiv->state;
550a7375
FB		 1774 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1775 }
1776}
1777
1778/* --------------------------------------------------------------------------
1779 * Init support
1780 */
1781
1782static struct musb *__init
ca6d1b13
FB		 1783allocate_instance(struct device *dev,
1784 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1785{
1786 struct musb *musb;
1787 struct musb_hw_ep *ep;
1788 int epnum;
1789#ifdef CONFIG_USB_MUSB_HDRC_HCD
1790 struct usb_hcd *hcd;
1791
427c4f33 1792 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
550a7375
FB		 1793 if (!hcd)
1794 return NULL;
1795 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1796
1797 musb = hcd_to_musb(hcd);
1798 INIT_LIST_HEAD(&musb->control);
1799 INIT_LIST_HEAD(&musb->in_bulk);
1800 INIT_LIST_HEAD(&musb->out_bulk);
1801
1802 hcd->uses_new_polling = 1;
1803
1804 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1805 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1806#else
1807 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1808 if (!musb)
1809 return NULL;
1810 dev_set_drvdata(dev, musb);
1811
1812#endif
1813
1814 musb->mregs = mbase;
1815 musb->ctrl_base = mbase;
1816 musb->nIrq = -ENODEV;
ca6d1b13 1817 musb->config = config;
02582b92 1818 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1819 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1820 epnum < musb->config->num_eps;
550a7375 1821 epnum++, ep++) {
550a7375
FB		 1822 ep->musb = musb;
1823 ep->epnum = epnum;
1824 }
1825
1826 musb->controller = dev;
1827 return musb;
1828}
1829
1830static void musb_free(struct musb *musb)
1831{
1832 /* this has multiple entry modes. it handles fault cleanup after
1833 * probe(), where things may be partially set up, as well as rmmod
1834 * cleanup after everything's been de-activated.
1835 */
1836
1837#ifdef CONFIG_SYSFS
94375751 1838 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1839#endif
1840
1841#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1842 musb_gadget_cleanup(musb);
1843#endif
1844
97a39896
AKG		 1845 if (musb->nIrq >= 0) {
1846 if (musb->irq_wake)
1847 disable_irq_wake(musb->nIrq);
550a7375
FB		 1848 free_irq(musb->nIrq, musb);
1849 }
1850 if (is_dma_capable() && musb->dma_controller) {
1851 struct dma_controller *c = musb->dma_controller;
1852
1853 (void) c->stop(c);
1854 dma_controller_destroy(c);
1855 }
1856
c740d0d8
AKG		 1857#ifdef CONFIG_USB_MUSB_OTG
1858 put_device(musb->xceiv->dev);
1859#endif
1860
550a7375
FB		 1861 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1862 musb_platform_exit(musb);
1863 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1864
1865 if (musb->clock) {
1866 clk_disable(musb->clock);
1867 clk_put(musb->clock);
1868 }
1869
550a7375
FB		 1870#ifdef CONFIG_USB_MUSB_HDRC_HCD
1871 usb_put_hcd(musb_to_hcd(musb));
1872#else
1873 kfree(musb);
1874#endif
1875}
1876
1877/*
1878 * Perform generic per-controller initialization.
1879 *
1880 * @pDevice: the controller (already clocked, etc)
1881 * @nIrq: irq
1882 * @mregs: virtual address of controller registers,
1883 * not yet corrected for platform-specific offsets
1884 */
1885static int __init
1886musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1887{
1888 int status;
1889 struct musb *musb;
1890 struct musb_hdrc_platform_data *plat = dev->platform_data;
1891
1892 /* The driver might handle more features than the board; OK.
1893 * Fail when the board needs a feature that's not enabled.
1894 */
1895 if (!plat) {
1896 dev_dbg(dev, "no platform_data?\n");
1897 return -ENODEV;
1898 }
1899 switch (plat->mode) {
1900 case MUSB_HOST:
1901#ifdef CONFIG_USB_MUSB_HDRC_HCD
1902 break;
1903#else
1904 goto bad_config;
1905#endif
1906 case MUSB_PERIPHERAL:
1907#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1908 break;
1909#else
1910 goto bad_config;
1911#endif
1912 case MUSB_OTG:
1913#ifdef CONFIG_USB_MUSB_OTG
1914 break;
1915#else
1916bad_config:
1917#endif
1918 default:
1919 dev_err(dev, "incompatible Kconfig role setting\n");
1920 return -EINVAL;
1921 }
1922
1923 /* allocate */
ca6d1b13 1924 musb = allocate_instance(dev, plat->config, ctrl);
550a7375
FB		 1925 if (!musb)
1926 return -ENOMEM;
1927
1928 spin_lock_init(&musb->lock);
1929 musb->board_mode = plat->mode;
1930 musb->board_set_power = plat->set_power;
1931 musb->set_clock = plat->set_clock;
1932 musb->min_power = plat->min_power;
1933
1934 /* Clock usage is chip-specific ... functional clock (DaVinci,
1935 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1936 * code does is make sure a clock handle is available; platform
1937 * code manages it during start/stop and suspend/resume.
1938 */
1939 if (plat->clock) {
1940 musb->clock = clk_get(dev, plat->clock);
1941 if (IS_ERR(musb->clock)) {
1942 status = PTR_ERR(musb->clock);
1943 musb->clock = NULL;
1944 goto fail;
1945 }
1946 }
1947
84e250ff
DB		 1948 /* The musb_platform_init() call:
1949 * - adjusts musb->mregs and musb->isr if needed,
1950 * - may initialize an integrated tranceiver
1951 * - initializes musb->xceiv, usually by otg_get_transceiver()
1952 * - activates clocks.
1953 * - stops powering VBUS
1954 * - assigns musb->board_set_vbus if host mode is enabled
1955 *
1956 * There are various transciever configurations. Blackfin,
1957 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1958 * external/discrete ones in various flavors (twl4030 family,
1959 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375
FB		 1960 */
1961 musb->isr = generic_interrupt;
1962 status = musb_platform_init(musb);
1963
1964 if (status < 0)
1965 goto fail;
1966 if (!musb->isr) {
1967 status = -ENODEV;
1968 goto fail2;
1969 }
1970
1971#ifndef CONFIG_MUSB_PIO_ONLY
1972 if (use_dma && dev->dma_mask) {
1973 struct dma_controller *c;
1974
1975 c = dma_controller_create(musb, musb->mregs);
1976 musb->dma_controller = c;
1977 if (c)
1978 (void) c->start(c);
1979 }
1980#endif
1981 /* ideally this would be abstracted in platform setup */
1982 if (!is_dma_capable() || !musb->dma_controller)
1983 dev->dma_mask = NULL;
1984
1985 /* be sure interrupts are disabled before connecting ISR */
1986 musb_platform_disable(musb);
1987 musb_generic_disable(musb);
1988
1989 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 1990 status = musb_core_init(plat->config->multipoint
550a7375
FB		 1991 ? MUSB_CONTROLLER_MHDRC
1992 : MUSB_CONTROLLER_HDRC, musb);
1993 if (status < 0)
1994 goto fail2;
1995
3a9f5bd8 1996#ifdef CONFIG_USB_MUSB_OTG
f7f9d63e
DB		 1997 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1998#endif
1999
550a7375
FB		 2000 /* Init IRQ workqueue before request_irq */
2001 INIT_WORK(&musb->irq_work, musb_irq_work);
2002
2003 /* attach to the IRQ */
427c4f33 2004 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2005 dev_err(dev, "request_irq %d failed!\n", nIrq);
2006 status = -ENODEV;
2007 goto fail2;
2008 }
2009 musb->nIrq = nIrq;
2010/* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2011 if (enable_irq_wake(nIrq) == 0) {
2012 musb->irq_wake = 1;
550a7375 2013 device_init_wakeup(dev, 1);
c48a5155
FB		 2014 } else {
2015 musb->irq_wake = 0;
2016 }
550a7375
FB		 2017
2018 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2019 musb_driver_name,
2020 ({char *s;
2021 switch (musb->board_mode) {
2022 case MUSB_HOST: s = "Host"; break;
2023 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2024 default: s = "OTG"; break;
2025 }; s; }),
2026 ctrl,
2027 (is_dma_capable() && musb->dma_controller)
2028 ? "DMA" : "PIO",
2029 musb->nIrq);
2030
84e250ff
DB		 2031 /* host side needs more setup */
2032 if (is_host_enabled(musb)) {
550a7375 2033 struct usb_hcd *hcd = musb_to_hcd(musb);
5fc4e779 2034 u8 busctl;
550a7375 2035
84e250ff
DB		 2036 otg_set_host(musb->xceiv, &hcd->self);
2037
2038 if (is_otg_enabled(musb))
550a7375 2039 hcd->self.otg_port = 1;
84e250ff 2040 musb->xceiv->host = &hcd->self;
550a7375 2041 hcd->power_budget = 2 * (plat->power ? : 250);
5fc4e779
AKG		 2042
2043 /* program PHY to use external vBus if required */
2044 if (plat->extvbus) {
2045 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
2046 busctl |= MUSB_ULPI_USE_EXTVBUS;
2047 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
2048 }
550a7375 2049 }
550a7375
FB		 2050
2051 /* For the host-only role, we can activate right away.
2052 * (We expect the ID pin to be forcibly grounded!!)
2053 * Otherwise, wait till the gadget driver hooks up.
2054 */
2055 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2056 MUSB_HST_MODE(musb);
84e250ff
DB		 2057 musb->xceiv->default_a = 1;
2058 musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375
FB		 2059
2060 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
746cdd0b
FB		 2061 if (status)
2062 goto fail;
550a7375
FB		 2063
2064 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2065 "HOST", status,
2066 musb_readb(musb->mregs, MUSB_DEVCTL),
2067 (musb_readb(musb->mregs, MUSB_DEVCTL)
2068 & MUSB_DEVCTL_BDEVICE
2069 ? 'B' : 'A'));
2070
2071 } else /* peripheral is enabled */ {
2072 MUSB_DEV_MODE(musb);
84e250ff
DB		 2073 musb->xceiv->default_a = 0;
2074 musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375
FB		 2075
2076 status = musb_gadget_setup(musb);
746cdd0b
FB		 2077 if (status)
2078 goto fail;
550a7375
FB		 2079
2080 DBG(1, "%s mode, status %d, dev%02x\n",
2081 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2082 status,
2083 musb_readb(musb->mregs, MUSB_DEVCTL));
2084
2085 }
2086
550a7375 2087#ifdef CONFIG_SYSFS
94375751 2088 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
550a7375 2089#endif
28c2c51c
FB		 2090 if (status)
2091 goto fail2;
550a7375 2092
28c2c51c 2093 return 0;
550a7375
FB		 2094
2095fail2:
2096 musb_platform_exit(musb);
28c2c51c
FB		 2097fail:
2098 dev_err(musb->controller,
2099 "musb_init_controller failed with status %d\n", status);
2100
2101 if (musb->clock)
2102 clk_put(musb->clock);
2103 device_init_wakeup(dev, 0);
2104 musb_free(musb);
2105
2106 return status;
2107
550a7375
FB		 2108}
2109
2110/*-------------------------------------------------------------------------*/
2111
2112/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2113 * bridge to a platform device; this driver then suffices.
2114 */
2115
2116#ifndef CONFIG_MUSB_PIO_ONLY
2117static u64 *orig_dma_mask;
2118#endif
2119
2120static int __init musb_probe(struct platform_device *pdev)
2121{
2122 struct device *dev = &pdev->dev;
2123 int irq = platform_get_irq(pdev, 0);
2124 struct resource *iomem;
2125 void __iomem *base;
2126
2127 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2128 if (!iomem || irq == 0)
2129 return -ENODEV;
2130
195e9e46 2131 base = ioremap(iomem->start, resource_size(iomem));
550a7375
FB		 2132 if (!base) {
2133 dev_err(dev, "ioremap failed\n");
2134 return -ENOMEM;
2135 }
2136
2137#ifndef CONFIG_MUSB_PIO_ONLY
2138 /* clobbered by use_dma=n */
2139 orig_dma_mask = dev->dma_mask;
2140#endif
2141 return musb_init_controller(dev, irq, base);
2142}
2143
e3060b17 2144static int __exit musb_remove(struct platform_device *pdev)
550a7375
FB		 2145{
2146 struct musb *musb = dev_to_musb(&pdev->dev);
2147 void __iomem *ctrl_base = musb->ctrl_base;
2148
2149 /* this gets called on rmmod.
2150 * - Host mode: host may still be active
2151 * - Peripheral mode: peripheral is deactivated (or never-activated)
2152 * - OTG mode: both roles are deactivated (or never-activated)
2153 */
2154 musb_shutdown(pdev);
550a7375
FB		 2155#ifdef CONFIG_USB_MUSB_HDRC_HCD
2156 if (musb->board_mode == MUSB_HOST)
2157 usb_remove_hcd(musb_to_hcd(musb));
2158#endif
2159 musb_free(musb);
2160 iounmap(ctrl_base);
2161 device_init_wakeup(&pdev->dev, 0);
2162#ifndef CONFIG_MUSB_PIO_ONLY
2163 pdev->dev.dma_mask = orig_dma_mask;
2164#endif
2165 return 0;
2166}
2167
2168#ifdef CONFIG_PM
2169
48fea965 2170static int musb_suspend(struct device *dev)
550a7375 2171{
48fea965 2172 struct platform_device *pdev = to_platform_device(dev);
550a7375
FB		 2173 unsigned long flags;
2174 struct musb *musb = dev_to_musb(&pdev->dev);
2175
2176 if (!musb->clock)
2177 return 0;
2178
2179 spin_lock_irqsave(&musb->lock, flags);
2180
2181 if (is_peripheral_active(musb)) {
2182 /* FIXME force disconnect unless we know USB will wake
2183 * the system up quickly enough to respond ...
2184 */
2185 } else if (is_host_active(musb)) {
2186 /* we know all the children are suspended; sometimes
2187 * they will even be wakeup-enabled.
2188 */
2189 }
2190
2191 if (musb->set_clock)
2192 musb->set_clock(musb->clock, 0);
2193 else
2194 clk_disable(musb->clock);
2195 spin_unlock_irqrestore(&musb->lock, flags);
2196 return 0;
2197}
2198
48fea965 2199static int musb_resume_noirq(struct device *dev)
550a7375 2200{
48fea965 2201 struct platform_device *pdev = to_platform_device(dev);
550a7375
FB		 2202 struct musb *musb = dev_to_musb(&pdev->dev);
2203
2204 if (!musb->clock)
2205 return 0;
2206
550a7375
FB		 2207 if (musb->set_clock)
2208 musb->set_clock(musb->clock, 1);
2209 else
2210 clk_enable(musb->clock);
2211
2212 /* for static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2213 * unless for some reason the whole soc powered down or the USB
2214 * module got reset through the PSC (vs just being disabled).
550a7375 2215 */
550a7375
FB		 2216 return 0;
2217}
2218
47145210 2219static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965
MD		 2220 .suspend = musb_suspend,
2221 .resume_noirq = musb_resume_noirq,
2222};
2223
2224#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2225#else
48fea965 2226#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2227#endif
2228
2229static struct platform_driver musb_driver = {
2230 .driver = {
2231 .name = (char *)musb_driver_name,
2232 .bus = &platform_bus_type,
2233 .owner = THIS_MODULE,
48fea965 2234 .pm = MUSB_DEV_PM_OPS,
550a7375 2235 },
e3060b17 2236 .remove = __exit_p(musb_remove),
550a7375 2237 .shutdown = musb_shutdown,
550a7375
FB		 2238};
2239
2240/*-------------------------------------------------------------------------*/
2241
2242static int __init musb_init(void)
2243{
2244#ifdef CONFIG_USB_MUSB_HDRC_HCD
2245 if (usb_disabled())
2246 return 0;
2247#endif
2248
2249 pr_info("%s: version " MUSB_VERSION ", "
2250#ifdef CONFIG_MUSB_PIO_ONLY
2251 "pio"
2252#elif defined(CONFIG_USB_TI_CPPI_DMA)
2253 "cppi-dma"
2254#elif defined(CONFIG_USB_INVENTRA_DMA)
2255 "musb-dma"
2256#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2257 "tusb-omap-dma"
2258#else
2259 "?dma?"
2260#endif
2261 ", "
2262#ifdef CONFIG_USB_MUSB_OTG
2263 "otg (peripheral+host)"
2264#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2265 "peripheral"
2266#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2267 "host"
2268#endif
2269 ", debug=%d\n",
b60c72ab 2270 musb_driver_name, musb_debug);
550a7375
FB		 2271 return platform_driver_probe(&musb_driver, musb_probe);
2272}
2273
34f32c97
DB		 2274/* make us init after usbcore and i2c (transceivers, regulators, etc)
2275 * and before usb gadget and host-side drivers start to register
550a7375 2276 */
34f32c97 2277fs_initcall(musb_init);
550a7375
FB		 2278
2279static void __exit musb_cleanup(void)
2280{
2281 platform_driver_unregister(&musb_driver);
2282}
2283module_exit(musb_cleanup);
Linux kernel - Deliverables
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