[deliverable/linux.git] / drivers / usb / musb / musb_dma.h

/*
 * MUSB OTG driver DMA controller abstraction
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2006 by Texas Instruments
 * Copyright (C) 2006-2007 Nokia Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef __MUSB_DMA_H__
#define __MUSB_DMA_H__

struct musb_hw_ep;

/*
 * DMA Controller Abstraction
 *
 * DMA Controllers are abstracted to allow use of a variety of different
 * implementations of DMA, as allowed by the Inventra USB cores.  On the
 * host side, usbcore sets up the DMA mappings and flushes caches; on the
 * peripheral side, the gadget controller driver does.  Responsibilities
 * of a DMA controller driver include:
 *
 *  - Handling the details of moving multiple USB packets
 *    in cooperation with the Inventra USB core, including especially
 *    the correct RX side treatment of short packets and buffer-full
 *    states (both of which terminate transfers).
 *
 *  - Knowing the correlation between dma channels and the
 *    Inventra core's local endpoint resources and data direction.
 *
 *  - Maintaining a list of allocated/available channels.
 *
 *  - Updating channel status on interrupts,
 *    whether shared with the Inventra core or separate.
 */

#define	DMA_ADDR_INVALID	(~(dma_addr_t)0)

#ifdef CONFIG_MUSB_PIO_ONLY
#define	is_dma_capable()	(0)
#else
#define	is_dma_capable()	(1)
#endif

#ifdef CONFIG_USB_UX500_DMA
#define musb_dma_ux500(musb)		(musb->io.quirks & MUSB_DMA_UX500)
#else
#define musb_dma_ux500(musb)		0
#endif

#ifdef CONFIG_USB_TI_CPPI41_DMA
#define musb_dma_cppi41(musb)		(musb->io.quirks & MUSB_DMA_CPPI41)
#else
#define musb_dma_cppi41(musb)		0
#endif

#ifdef CONFIG_USB_TI_CPPI_DMA
#define musb_dma_cppi(musb)		(musb->io.quirks & MUSB_DMA_CPPI)
#else
#define musb_dma_cppi(musb)		0
#endif

#ifdef CONFIG_USB_TUSB_OMAP_DMA
#define tusb_dma_omap(musb)		(musb->io.quirks & MUSB_DMA_TUSB_OMAP)
#else
#define tusb_dma_omap(musb)		0
#endif

#ifdef CONFIG_USB_INVENTRA_DMA
#define musb_dma_inventra(musb)		(musb->io.quirks & MUSB_DMA_INVENTRA)
#else
#define musb_dma_inventra(musb)		0
#endif

#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
#define	is_cppi_enabled(musb)		\
	(musb_dma_cppi(musb) || musb_dma_cppi41(musb))
#else
#define	is_cppi_enabled(musb)	0
#endif

/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
 *	Only allow DMA mode 1 to be used when the USB will actually generate the
 *	interrupts we expect.
 */
#ifdef CONFIG_BLACKFIN
# undef USE_MODE1
# if !ANOMALY_05000456
#  define USE_MODE1
# endif
#endif

/*
 * DMA channel status ... updated by the dma controller driver whenever that
 * status changes, and protected by the overall controller spinlock.
 */
enum dma_channel_status {
	/* unallocated */
	MUSB_DMA_STATUS_UNKNOWN,
	/* allocated ... but not busy, no errors */
	MUSB_DMA_STATUS_FREE,
	/* busy ... transactions are active */
	MUSB_DMA_STATUS_BUSY,
	/* transaction(s) aborted due to ... dma or memory bus error */
	MUSB_DMA_STATUS_BUS_ABORT,
	/* transaction(s) aborted due to ... core error or USB fault */
	MUSB_DMA_STATUS_CORE_ABORT
};

struct dma_controller;

/**
 * struct dma_channel - A DMA channel.
 * @private_data: channel-private data
 * @max_len: the maximum number of bytes the channel can move in one
 *	transaction (typically representing many USB maximum-sized packets)
 * @actual_len: how many bytes have been transferred
 * @status: current channel status (updated e.g. on interrupt)
 * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
 *
 * channels are associated with an endpoint for the duration of at least
 * one usb transfer.
 */
struct dma_channel {
	void			*private_data;
	/* FIXME not void* private_data, but a dma_controller * */
	size_t			max_len;
	size_t			actual_len;
	enum dma_channel_status	status;
	bool			desired_mode;
	bool			rx_packet_done;
};

/*
 * dma_channel_status - return status of dma channel
 * @c: the channel
 *
 * Returns the software's view of the channel status.  If that status is BUSY
 * then it's possible that the hardware has completed (or aborted) a transfer,
 * so the driver needs to update that status.
 */
static inline enum dma_channel_status
dma_channel_status(struct dma_channel *c)
{
	return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
}

/**
 * struct dma_controller - A DMA Controller.
 * @start: call this to start a DMA controller;
 *	return 0 on success, else negative errno
 * @stop: call this to stop a DMA controller
 *	return 0 on success, else negative errno
 * @channel_alloc: call this to allocate a DMA channel
 * @channel_release: call this to release a DMA channel
 * @channel_abort: call this to abort a pending DMA transaction,
 *	returning it to FREE (but allocated) state
 *
 * Controllers manage dma channels.
 */
struct dma_controller {
	struct dma_channel	*(*channel_alloc)(struct dma_controller *,
					struct musb_hw_ep *, u8 is_tx);
	void			(*channel_release)(struct dma_channel *);
	int			(*channel_program)(struct dma_channel *channel,
							u16 maxpacket, u8 mode,
							dma_addr_t dma_addr,
							u32 length);
	int			(*channel_abort)(struct dma_channel *);
	int			(*is_compatible)(struct dma_channel *channel,
							u16 maxpacket,
							void *buf, u32 length);
};

/* called after channel_program(), may indicate a fault */
extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);

#ifdef CONFIG_MUSB_PIO_ONLY
static inline struct dma_controller *
musb_dma_controller_create(struct musb *m, void __iomem *io)
{
	return NULL;
}

static inline void musb_dma_controller_destroy(struct dma_controller *d) { }

#else

extern struct dma_controller *
(*musb_dma_controller_create)(struct musb *, void __iomem *);

extern void (*musb_dma_controller_destroy)(struct dma_controller *);
#endif

/* Platform specific DMA functions */
extern struct dma_controller *
musbhs_dma_controller_create(struct musb *musb, void __iomem *base);
extern void musbhs_dma_controller_destroy(struct dma_controller *c);

extern struct dma_controller *
tusb_dma_controller_create(struct musb *musb, void __iomem *base);
extern void tusb_dma_controller_destroy(struct dma_controller *c);

extern struct dma_controller *
cppi_dma_controller_create(struct musb *musb, void __iomem *base);
extern void cppi_dma_controller_destroy(struct dma_controller *c);

extern struct dma_controller *
cppi41_dma_controller_create(struct musb *musb, void __iomem *base);
extern void cppi41_dma_controller_destroy(struct dma_controller *c);

extern struct dma_controller *
ux500_dma_controller_create(struct musb *musb, void __iomem *base);
extern void ux500_dma_controller_destroy(struct dma_controller *c);

#endif	/* __MUSB_DMA_H__ */
Commit	Line	Data
550a7375 FB	1	/*
	2	* MUSB OTG driver DMA controller abstraction
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2006 by Texas Instruments
	6	* Copyright (C) 2006-2007 Nokia Corporation
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	23	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	24	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	25	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	26	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	27	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	28	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	29	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	31	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	*/
	34
	35	#ifndef __MUSB_DMA_H__
	36	#define __MUSB_DMA_H__
	37
	38	struct musb_hw_ep;
	39
	40	/*
	41	* DMA Controller Abstraction
	42	*
	43	* DMA Controllers are abstracted to allow use of a variety of different
	44	* implementations of DMA, as allowed by the Inventra USB cores. On the
	45	* host side, usbcore sets up the DMA mappings and flushes caches; on the
	46	* peripheral side, the gadget controller driver does. Responsibilities
	47	* of a DMA controller driver include:
	48	*
	49	* - Handling the details of moving multiple USB packets
	50	* in cooperation with the Inventra USB core, including especially
	51	* the correct RX side treatment of short packets and buffer-full
	52	* states (both of which terminate transfers).
	53	*
	54	* - Knowing the correlation between dma channels and the
	55	* Inventra core's local endpoint resources and data direction.
	56	*
	57	* - Maintaining a list of allocated/available channels.
	58	*
	59	* - Updating channel status on interrupts,
	60	* whether shared with the Inventra core or separate.
	61	*/
	62
	63	#define DMA_ADDR_INVALID (~(dma_addr_t)0)
	64
260eba39	65	#ifdef CONFIG_MUSB_PIO_ONLY
550a7375	66	#define is_dma_capable() (0)
260eba39 SAS	67	#else
260eba39 SAS	68	#define is_dma_capable() (1)
550a7375 FB	69	#endif
550a7375 FB	70
f8e9f34f TL	71	#ifdef CONFIG_USB_UX500_DMA
	72	#define musb_dma_ux500(musb) (musb->io.quirks & MUSB_DMA_UX500)
	73	#else
	74	#define musb_dma_ux500(musb) 0
	75	#endif
	76
	77	#ifdef CONFIG_USB_TI_CPPI41_DMA
	78	#define musb_dma_cppi41(musb) (musb->io.quirks & MUSB_DMA_CPPI41)
	79	#else
	80	#define musb_dma_cppi41(musb) 0
	81	#endif
	82
	83	#ifdef CONFIG_USB_TI_CPPI_DMA
	84	#define musb_dma_cppi(musb) (musb->io.quirks & MUSB_DMA_CPPI)
550a7375	85	#else
f8e9f34f	86	#define musb_dma_cppi(musb) 0
550a7375 FB	87	#endif
	88
	89	#ifdef CONFIG_USB_TUSB_OMAP_DMA
f8e9f34f TL	90	#define tusb_dma_omap(musb) (musb->io.quirks & MUSB_DMA_TUSB_OMAP)
	91	#else
	92	#define tusb_dma_omap(musb) 0
	93	#endif
	94
	95	#ifdef CONFIG_USB_INVENTRA_DMA
	96	#define musb_dma_inventra(musb) (musb->io.quirks & MUSB_DMA_INVENTRA)
	97	#else
	98	#define musb_dma_inventra(musb) 0
	99	#endif
	100
	101	#if defined(CONFIG_USB_TI_CPPI_DMA) \|\| defined(CONFIG_USB_TI_CPPI41_DMA)
	102	#define is_cppi_enabled(musb) \
	103	(musb_dma_cppi(musb) \|\| musb_dma_cppi41(musb))
550a7375	104	#else
f8e9f34f	105	#define is_cppi_enabled(musb) 0
550a7375 FB	106	#endif
550a7375 FB	107
9720faec SZ	108	/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
	109	* Only allow DMA mode 1 to be used when the USB will actually generate the
	110	* interrupts we expect.
	111	*/
	112	#ifdef CONFIG_BLACKFIN
	113	# undef USE_MODE1
	114	# if !ANOMALY_05000456
	115	# define USE_MODE1
	116	# endif
	117	#endif
	118
550a7375 FB	119	/*
	120	* DMA channel status ... updated by the dma controller driver whenever that
	121	* status changes, and protected by the overall controller spinlock.
	122	*/
	123	enum dma_channel_status {
	124	/* unallocated */
	125	MUSB_DMA_STATUS_UNKNOWN,
	126	/* allocated ... but not busy, no errors */
	127	MUSB_DMA_STATUS_FREE,
	128	/* busy ... transactions are active */
	129	MUSB_DMA_STATUS_BUSY,
	130	/* transaction(s) aborted due to ... dma or memory bus error */
	131	MUSB_DMA_STATUS_BUS_ABORT,
	132	/* transaction(s) aborted due to ... core error or USB fault */
	133	MUSB_DMA_STATUS_CORE_ABORT
	134	};
	135
	136	struct dma_controller;
	137
	138	/**
	139	* struct dma_channel - A DMA channel.
	140	* @private_data: channel-private data
	141	* @max_len: the maximum number of bytes the channel can move in one
	142	* transaction (typically representing many USB maximum-sized packets)
	143	* @actual_len: how many bytes have been transferred
	144	* @status: current channel status (updated e.g. on interrupt)
	145	* @desired_mode: true if mode 1 is desired; false if mode 0 is desired
	146	*
	147	* channels are associated with an endpoint for the duration of at least
	148	* one usb transfer.
	149	*/
	150	struct dma_channel {
	151	void *private_data;
	152	/* FIXME not void* private_data, but a dma_controller * */
	153	size_t max_len;
	154	size_t actual_len;
	155	enum dma_channel_status status;
	156	bool desired_mode;
ff3fcac9	157	bool rx_packet_done;
550a7375 FB	158	};
	159
	160	/*
	161	* dma_channel_status - return status of dma channel
	162	* @c: the channel
	163	*
	164	* Returns the software's view of the channel status. If that status is BUSY
	165	* then it's possible that the hardware has completed (or aborted) a transfer,
	166	* so the driver needs to update that status.
	167	*/
	168	static inline enum dma_channel_status
	169	dma_channel_status(struct dma_channel *c)
	170	{
	171	return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
	172	}
	173
	174	/**
	175	* struct dma_controller - A DMA Controller.
	176	* @start: call this to start a DMA controller;
	177	* return 0 on success, else negative errno
	178	* @stop: call this to stop a DMA controller
	179	* return 0 on success, else negative errno
	180	* @channel_alloc: call this to allocate a DMA channel
	181	* @channel_release: call this to release a DMA channel
	182	* @channel_abort: call this to abort a pending DMA transaction,
	183	* returning it to FREE (but allocated) state
	184	*
	185	* Controllers manage dma channels.
	186	*/
	187	struct dma_controller {
550a7375 FB	188	struct dma_channel (channel_alloc)(struct dma_controller *,
	189	struct musb_hw_ep *, u8 is_tx);
	190	void (channel_release)(struct dma_channel );
	191	int (channel_program)(struct dma_channel channel,
	192	u16 maxpacket, u8 mode,
	193	dma_addr_t dma_addr,
	194	u32 length);
	195	int (channel_abort)(struct dma_channel );
5f5761cb MYK	196	int (is_compatible)(struct dma_channel channel,
	197	u16 maxpacket,
	198	void *buf, u32 length);
550a7375 FB	199	};
	200
	201	/* called after channel_program(), may indicate a fault */
	202	extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
	203
a6a20885	204	#ifdef CONFIG_MUSB_PIO_ONLY
7f6283ed TL	205	static inline struct dma_controller *
7f6283ed TL	206	musb_dma_controller_create(struct musb m, void __iomem io)
a6a20885 SAS	207	{
	208	return NULL;
	209	}
	210
7f6283ed	211	static inline void musb_dma_controller_destroy(struct dma_controller *d) { }
a6a20885 SAS	212
a6a20885 SAS	213	#else
550a7375	214
7f6283ed TL	215	extern struct dma_controller *
7f6283ed TL	216	(musb_dma_controller_create)(struct musb , void __iomem *);
550a7375	217
7f6283ed	218	extern void (musb_dma_controller_destroy)(struct dma_controller );
a6a20885	219	#endif
550a7375	220
7f6283ed TL	221	/* Platform specific DMA functions */
	222	extern struct dma_controller *
	223	musbhs_dma_controller_create(struct musb musb, void __iomem base);
	224	extern void musbhs_dma_controller_destroy(struct dma_controller *c);
	225
	226	extern struct dma_controller *
	227	tusb_dma_controller_create(struct musb musb, void __iomem base);
	228	extern void tusb_dma_controller_destroy(struct dma_controller *c);
	229
	230	extern struct dma_controller *
	231	cppi_dma_controller_create(struct musb musb, void __iomem base);
	232	extern void cppi_dma_controller_destroy(struct dma_controller *c);
	233
	234	extern struct dma_controller *
	235	cppi41_dma_controller_create(struct musb musb, void __iomem base);
	236	extern void cppi41_dma_controller_destroy(struct dma_controller *c);
	237
	238	extern struct dma_controller *
	239	ux500_dma_controller_create(struct musb musb, void __iomem base);
	240	extern void ux500_dma_controller_destroy(struct dma_controller *c);
	241
550a7375	242	#endif /* __MUSB_DMA_H__ */