Commit | Line | Data |
---|---|---|
f0ae849d HW |
1 | /* |
2 | * Intel Langwell USB OTG transceiver driver | |
56e9406c | 3 | * Copyright (C) 2008 - 2010, Intel Corporation. |
f0ae849d HW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
19 | /* This driver helps to switch Langwell OTG controller function between host | |
20 | * and peripheral. It works with EHCI driver and Langwell client controller | |
21 | * driver together. | |
22 | */ | |
23 | #include <linux/module.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/device.h> | |
30 | #include <linux/moduleparam.h> | |
31 | #include <linux/usb/ch9.h> | |
32 | #include <linux/usb/gadget.h> | |
33 | #include <linux/usb.h> | |
34 | #include <linux/usb/otg.h> | |
35 | #include <linux/usb/hcd.h> | |
36 | #include <linux/notifier.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/intel_scu_ipc.h> | |
39 | ||
40 | #include <linux/usb/langwell_otg.h> | |
41 | ||
42 | #define DRIVER_DESC "Intel Langwell USB OTG transceiver driver" | |
56e9406c | 43 | #define DRIVER_VERSION "July 10, 2010" |
f0ae849d HW |
44 | |
45 | MODULE_DESCRIPTION(DRIVER_DESC); | |
46 | MODULE_AUTHOR("Henry Yuan <hang.yuan@intel.com>, Hao Wu <hao.wu@intel.com>"); | |
47 | MODULE_VERSION(DRIVER_VERSION); | |
48 | MODULE_LICENSE("GPL"); | |
49 | ||
50 | static const char driver_name[] = "langwell_otg"; | |
51 | ||
52 | static int langwell_otg_probe(struct pci_dev *pdev, | |
53 | const struct pci_device_id *id); | |
54 | static void langwell_otg_remove(struct pci_dev *pdev); | |
55 | static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message); | |
56 | static int langwell_otg_resume(struct pci_dev *pdev); | |
57 | ||
58 | static int langwell_otg_set_host(struct otg_transceiver *otg, | |
59 | struct usb_bus *host); | |
60 | static int langwell_otg_set_peripheral(struct otg_transceiver *otg, | |
61 | struct usb_gadget *gadget); | |
62 | static int langwell_otg_start_srp(struct otg_transceiver *otg); | |
63 | ||
64 | static const struct pci_device_id pci_ids[] = {{ | |
65 | .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe), | |
66 | .class_mask = ~0, | |
67 | .vendor = 0x8086, | |
68 | .device = 0x0811, | |
69 | .subvendor = PCI_ANY_ID, | |
70 | .subdevice = PCI_ANY_ID, | |
71 | }, { /* end: all zeroes */ } | |
72 | }; | |
73 | ||
74 | static struct pci_driver otg_pci_driver = { | |
75 | .name = (char *) driver_name, | |
76 | .id_table = pci_ids, | |
77 | ||
78 | .probe = langwell_otg_probe, | |
79 | .remove = langwell_otg_remove, | |
80 | ||
81 | .suspend = langwell_otg_suspend, | |
82 | .resume = langwell_otg_resume, | |
83 | }; | |
84 | ||
85 | static const char *state_string(enum usb_otg_state state) | |
86 | { | |
87 | switch (state) { | |
88 | case OTG_STATE_A_IDLE: | |
89 | return "a_idle"; | |
90 | case OTG_STATE_A_WAIT_VRISE: | |
91 | return "a_wait_vrise"; | |
92 | case OTG_STATE_A_WAIT_BCON: | |
93 | return "a_wait_bcon"; | |
94 | case OTG_STATE_A_HOST: | |
95 | return "a_host"; | |
96 | case OTG_STATE_A_SUSPEND: | |
97 | return "a_suspend"; | |
98 | case OTG_STATE_A_PERIPHERAL: | |
99 | return "a_peripheral"; | |
100 | case OTG_STATE_A_WAIT_VFALL: | |
101 | return "a_wait_vfall"; | |
102 | case OTG_STATE_A_VBUS_ERR: | |
103 | return "a_vbus_err"; | |
104 | case OTG_STATE_B_IDLE: | |
105 | return "b_idle"; | |
106 | case OTG_STATE_B_SRP_INIT: | |
107 | return "b_srp_init"; | |
108 | case OTG_STATE_B_PERIPHERAL: | |
109 | return "b_peripheral"; | |
110 | case OTG_STATE_B_WAIT_ACON: | |
111 | return "b_wait_acon"; | |
112 | case OTG_STATE_B_HOST: | |
113 | return "b_host"; | |
114 | default: | |
115 | return "UNDEFINED"; | |
116 | } | |
117 | } | |
118 | ||
119 | /* HSM timers */ | |
120 | static inline struct langwell_otg_timer *otg_timer_initializer | |
121 | (void (*function)(unsigned long), unsigned long expires, unsigned long data) | |
122 | { | |
123 | struct langwell_otg_timer *timer; | |
124 | timer = kmalloc(sizeof(struct langwell_otg_timer), GFP_KERNEL); | |
125 | if (timer == NULL) | |
126 | return timer; | |
127 | ||
128 | timer->function = function; | |
129 | timer->expires = expires; | |
130 | timer->data = data; | |
131 | return timer; | |
132 | } | |
133 | ||
134 | static struct langwell_otg_timer *a_wait_vrise_tmr, *a_aidl_bdis_tmr, | |
135 | *b_se0_srp_tmr, *b_srp_init_tmr; | |
136 | ||
137 | static struct list_head active_timers; | |
138 | ||
139 | static struct langwell_otg *the_transceiver; | |
140 | ||
141 | /* host/client notify transceiver when event affects HNP state */ | |
142 | void langwell_update_transceiver(void) | |
143 | { | |
144 | struct langwell_otg *lnw = the_transceiver; | |
145 | ||
146 | dev_dbg(lnw->dev, "transceiver is updated\n"); | |
147 | ||
148 | if (!lnw->qwork) | |
149 | return ; | |
150 | ||
151 | queue_work(lnw->qwork, &lnw->work); | |
152 | } | |
153 | EXPORT_SYMBOL(langwell_update_transceiver); | |
154 | ||
155 | static int langwell_otg_set_host(struct otg_transceiver *otg, | |
156 | struct usb_bus *host) | |
157 | { | |
158 | otg->host = host; | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static int langwell_otg_set_peripheral(struct otg_transceiver *otg, | |
164 | struct usb_gadget *gadget) | |
165 | { | |
166 | otg->gadget = gadget; | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | static int langwell_otg_set_power(struct otg_transceiver *otg, | |
172 | unsigned mA) | |
173 | { | |
174 | return 0; | |
175 | } | |
176 | ||
1f15318c | 177 | /* A-device drives vbus, controlled through IPC commands */ |
f0ae849d HW |
178 | static int langwell_otg_set_vbus(struct otg_transceiver *otg, bool enabled) |
179 | { | |
180 | struct langwell_otg *lnw = the_transceiver; | |
1f15318c | 181 | u8 sub_id; |
f0ae849d HW |
182 | |
183 | dev_dbg(lnw->dev, "%s <--- %s\n", __func__, enabled ? "on" : "off"); | |
184 | ||
1f15318c HW |
185 | if (enabled) |
186 | sub_id = 0x8; /* Turn on the VBus */ | |
187 | else | |
188 | sub_id = 0x9; /* Turn off the VBus */ | |
f0ae849d | 189 | |
1f15318c HW |
190 | if (intel_scu_ipc_simple_command(0xef, sub_id)) { |
191 | dev_dbg(lnw->dev, "Failed to set Vbus via IPC commands\n"); | |
f0ae849d HW |
192 | return -EBUSY; |
193 | } | |
194 | ||
f0ae849d HW |
195 | dev_dbg(lnw->dev, "%s --->\n", __func__); |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | /* charge vbus or discharge vbus through a resistor to ground */ | |
201 | static void langwell_otg_chrg_vbus(int on) | |
202 | { | |
203 | struct langwell_otg *lnw = the_transceiver; | |
204 | u32 val; | |
205 | ||
206 | val = readl(lnw->iotg.base + CI_OTGSC); | |
207 | ||
208 | if (on) | |
209 | writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VC, | |
210 | lnw->iotg.base + CI_OTGSC); | |
211 | else | |
212 | writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VD, | |
213 | lnw->iotg.base + CI_OTGSC); | |
214 | } | |
215 | ||
216 | /* Start SRP */ | |
217 | static int langwell_otg_start_srp(struct otg_transceiver *otg) | |
218 | { | |
219 | struct langwell_otg *lnw = the_transceiver; | |
220 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
221 | u32 val; | |
222 | ||
223 | dev_dbg(lnw->dev, "%s --->\n", __func__); | |
224 | ||
225 | val = readl(iotg->base + CI_OTGSC); | |
226 | ||
227 | writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HADP, | |
228 | iotg->base + CI_OTGSC); | |
229 | ||
230 | /* Check if the data plus is finished or not */ | |
231 | msleep(8); | |
232 | val = readl(iotg->base + CI_OTGSC); | |
233 | if (val & (OTGSC_HADP | OTGSC_DP)) | |
234 | dev_dbg(lnw->dev, "DataLine SRP Error\n"); | |
235 | ||
236 | /* Disable interrupt - b_sess_vld */ | |
237 | val = readl(iotg->base + CI_OTGSC); | |
238 | val &= (~(OTGSC_BSVIE | OTGSC_BSEIE)); | |
239 | writel(val, iotg->base + CI_OTGSC); | |
240 | ||
241 | /* Start VBus SRP, drive vbus to generate VBus pulse */ | |
242 | iotg->otg.set_vbus(&iotg->otg, true); | |
243 | msleep(15); | |
244 | iotg->otg.set_vbus(&iotg->otg, false); | |
245 | ||
246 | /* Enable interrupt - b_sess_vld*/ | |
247 | val = readl(iotg->base + CI_OTGSC); | |
248 | dev_dbg(lnw->dev, "after VBUS pulse otgsc = %x\n", val); | |
249 | ||
250 | val |= (OTGSC_BSVIE | OTGSC_BSEIE); | |
251 | writel(val, iotg->base + CI_OTGSC); | |
252 | ||
253 | /* If Vbus is valid, then update the hsm */ | |
254 | if (val & OTGSC_BSV) { | |
255 | dev_dbg(lnw->dev, "no b_sess_vld interrupt\n"); | |
256 | ||
257 | lnw->iotg.hsm.b_sess_vld = 1; | |
258 | langwell_update_transceiver(); | |
259 | } | |
260 | ||
261 | dev_dbg(lnw->dev, "%s <---\n", __func__); | |
262 | return 0; | |
263 | } | |
264 | ||
265 | /* stop SOF via bus_suspend */ | |
266 | static void langwell_otg_loc_sof(int on) | |
267 | { | |
268 | struct langwell_otg *lnw = the_transceiver; | |
269 | struct usb_hcd *hcd; | |
270 | int err; | |
271 | ||
272 | dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "suspend" : "resume"); | |
273 | ||
274 | hcd = bus_to_hcd(lnw->iotg.otg.host); | |
275 | if (on) | |
276 | err = hcd->driver->bus_resume(hcd); | |
277 | else | |
278 | err = hcd->driver->bus_suspend(hcd); | |
279 | ||
280 | if (err) | |
281 | dev_dbg(lnw->dev, "Fail to resume/suspend USB bus - %d\n", err); | |
282 | ||
283 | dev_dbg(lnw->dev, "%s <---\n", __func__); | |
284 | } | |
285 | ||
286 | static int langwell_otg_check_otgsc(void) | |
287 | { | |
288 | struct langwell_otg *lnw = the_transceiver; | |
289 | u32 otgsc, usbcfg; | |
290 | ||
291 | dev_dbg(lnw->dev, "check sync OTGSC and USBCFG registers\n"); | |
292 | ||
293 | otgsc = readl(lnw->iotg.base + CI_OTGSC); | |
294 | usbcfg = readl(lnw->usbcfg); | |
295 | ||
296 | dev_dbg(lnw->dev, "OTGSC = %08x, USBCFG = %08x\n", | |
297 | otgsc, usbcfg); | |
298 | dev_dbg(lnw->dev, "OTGSC_AVV = %d\n", !!(otgsc & OTGSC_AVV)); | |
299 | dev_dbg(lnw->dev, "USBCFG.VBUSVAL = %d\n", | |
300 | !!(usbcfg & USBCFG_VBUSVAL)); | |
301 | dev_dbg(lnw->dev, "OTGSC_ASV = %d\n", !!(otgsc & OTGSC_ASV)); | |
302 | dev_dbg(lnw->dev, "USBCFG.AVALID = %d\n", | |
303 | !!(usbcfg & USBCFG_AVALID)); | |
304 | dev_dbg(lnw->dev, "OTGSC_BSV = %d\n", !!(otgsc & OTGSC_BSV)); | |
305 | dev_dbg(lnw->dev, "USBCFG.BVALID = %d\n", | |
306 | !!(usbcfg & USBCFG_BVALID)); | |
307 | dev_dbg(lnw->dev, "OTGSC_BSE = %d\n", !!(otgsc & OTGSC_BSE)); | |
308 | dev_dbg(lnw->dev, "USBCFG.SESEND = %d\n", | |
309 | !!(usbcfg & USBCFG_SESEND)); | |
310 | ||
311 | /* Check USBCFG VBusValid/AValid/BValid/SessEnd */ | |
312 | if (!!(otgsc & OTGSC_AVV) ^ !!(usbcfg & USBCFG_VBUSVAL)) { | |
313 | dev_dbg(lnw->dev, "OTGSC.AVV != USBCFG.VBUSVAL\n"); | |
314 | goto err; | |
315 | } | |
316 | if (!!(otgsc & OTGSC_ASV) ^ !!(usbcfg & USBCFG_AVALID)) { | |
317 | dev_dbg(lnw->dev, "OTGSC.ASV != USBCFG.AVALID\n"); | |
318 | goto err; | |
319 | } | |
320 | if (!!(otgsc & OTGSC_BSV) ^ !!(usbcfg & USBCFG_BVALID)) { | |
321 | dev_dbg(lnw->dev, "OTGSC.BSV != USBCFG.BVALID\n"); | |
322 | goto err; | |
323 | } | |
324 | if (!!(otgsc & OTGSC_BSE) ^ !!(usbcfg & USBCFG_SESEND)) { | |
325 | dev_dbg(lnw->dev, "OTGSC.BSE != USBCFG.SESSEN\n"); | |
326 | goto err; | |
327 | } | |
328 | ||
329 | dev_dbg(lnw->dev, "OTGSC and USBCFG are synced\n"); | |
330 | ||
331 | return 0; | |
332 | ||
333 | err: | |
334 | dev_warn(lnw->dev, "OTGSC isn't equal to USBCFG\n"); | |
335 | return -EPIPE; | |
336 | } | |
337 | ||
338 | ||
339 | static void langwell_otg_phy_low_power(int on) | |
340 | { | |
341 | struct langwell_otg *lnw = the_transceiver; | |
342 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
343 | u8 val, phcd; | |
344 | int retval; | |
345 | ||
346 | dev_dbg(lnw->dev, "%s ---> %s mode\n", | |
347 | __func__, on ? "Low power" : "Normal"); | |
348 | ||
349 | phcd = 0x40; | |
350 | ||
351 | val = readb(iotg->base + CI_HOSTPC1 + 2); | |
352 | ||
353 | if (on) { | |
354 | /* Due to hardware issue, after set PHCD, sync will failed | |
355 | * between USBCFG and OTGSC, so before set PHCD, check if | |
356 | * sync is in process now. If the answer is "yes", then do | |
357 | * not touch PHCD bit */ | |
358 | retval = langwell_otg_check_otgsc(); | |
359 | if (retval) { | |
360 | dev_dbg(lnw->dev, "Skip PHCD programming..\n"); | |
361 | return ; | |
362 | } | |
363 | ||
364 | writeb(val | phcd, iotg->base + CI_HOSTPC1 + 2); | |
365 | } else | |
366 | writeb(val & ~phcd, iotg->base + CI_HOSTPC1 + 2); | |
367 | ||
368 | dev_dbg(lnw->dev, "%s <--- done\n", __func__); | |
369 | } | |
370 | ||
1f15318c | 371 | /* After drv vbus, add 5 ms delay to set PHCD */ |
f0ae849d HW |
372 | static void langwell_otg_phy_low_power_wait(int on) |
373 | { | |
374 | struct langwell_otg *lnw = the_transceiver; | |
375 | ||
1f15318c | 376 | dev_dbg(lnw->dev, "add 5ms delay before programing PHCD\n"); |
f0ae849d | 377 | |
1f15318c | 378 | mdelay(5); |
f0ae849d HW |
379 | langwell_otg_phy_low_power(on); |
380 | } | |
381 | ||
382 | /* Enable/Disable OTG interrupt */ | |
383 | static void langwell_otg_intr(int on) | |
384 | { | |
385 | struct langwell_otg *lnw = the_transceiver; | |
386 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
387 | u32 val; | |
388 | ||
389 | dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off"); | |
390 | ||
391 | val = readl(iotg->base + CI_OTGSC); | |
392 | ||
393 | /* OTGSC_INT_MASK doesn't contains 1msInt */ | |
394 | if (on) { | |
395 | val = val | (OTGSC_INT_MASK); | |
396 | writel(val, iotg->base + CI_OTGSC); | |
397 | } else { | |
398 | val = val & ~(OTGSC_INT_MASK); | |
399 | writel(val, iotg->base + CI_OTGSC); | |
400 | } | |
401 | ||
402 | dev_dbg(lnw->dev, "%s <---\n", __func__); | |
403 | } | |
404 | ||
405 | /* set HAAR: Hardware Assist Auto-Reset */ | |
406 | static void langwell_otg_HAAR(int on) | |
407 | { | |
408 | struct langwell_otg *lnw = the_transceiver; | |
409 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
410 | u32 val; | |
411 | ||
412 | dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off"); | |
413 | ||
414 | val = readl(iotg->base + CI_OTGSC); | |
415 | if (on) | |
416 | writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HAAR, | |
417 | iotg->base + CI_OTGSC); | |
418 | else | |
419 | writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HAAR, | |
420 | iotg->base + CI_OTGSC); | |
421 | ||
422 | dev_dbg(lnw->dev, "%s <---\n", __func__); | |
423 | } | |
424 | ||
425 | /* set HABA: Hardware Assist B-Disconnect to A-Connect */ | |
426 | static void langwell_otg_HABA(int on) | |
427 | { | |
428 | struct langwell_otg *lnw = the_transceiver; | |
429 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
430 | u32 val; | |
431 | ||
432 | dev_dbg(lnw->dev, "%s ---> %s\n", __func__, on ? "on" : "off"); | |
433 | ||
434 | val = readl(iotg->base + CI_OTGSC); | |
435 | if (on) | |
436 | writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HABA, | |
437 | iotg->base + CI_OTGSC); | |
438 | else | |
439 | writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HABA, | |
440 | iotg->base + CI_OTGSC); | |
441 | ||
442 | dev_dbg(lnw->dev, "%s <---\n", __func__); | |
443 | } | |
444 | ||
445 | static int langwell_otg_check_se0_srp(int on) | |
446 | { | |
447 | struct langwell_otg *lnw = the_transceiver; | |
448 | int delay_time = TB_SE0_SRP * 10; | |
449 | u32 val; | |
450 | ||
451 | dev_dbg(lnw->dev, "%s --->\n", __func__); | |
452 | ||
453 | do { | |
454 | udelay(100); | |
455 | if (!delay_time--) | |
456 | break; | |
457 | val = readl(lnw->iotg.base + CI_PORTSC1); | |
458 | val &= PORTSC_LS; | |
459 | } while (!val); | |
460 | ||
461 | dev_dbg(lnw->dev, "%s <---\n", __func__); | |
462 | return val; | |
463 | } | |
464 | ||
465 | /* The timeout callback function to set time out bit */ | |
466 | static void set_tmout(unsigned long indicator) | |
467 | { | |
468 | *(int *)indicator = 1; | |
469 | } | |
470 | ||
471 | void langwell_otg_nsf_msg(unsigned long indicator) | |
472 | { | |
473 | struct langwell_otg *lnw = the_transceiver; | |
474 | ||
475 | switch (indicator) { | |
476 | case 2: | |
477 | case 4: | |
478 | case 6: | |
479 | case 7: | |
480 | dev_warn(lnw->dev, | |
481 | "OTG:NSF-%lu - deivce not responding\n", indicator); | |
482 | break; | |
483 | case 3: | |
484 | dev_warn(lnw->dev, | |
485 | "OTG:NSF-%lu - deivce not supported\n", indicator); | |
486 | break; | |
487 | default: | |
488 | dev_warn(lnw->dev, "Do not have this kind of NSF\n"); | |
489 | break; | |
490 | } | |
491 | } | |
492 | ||
493 | /* Initialize timers */ | |
494 | static int langwell_otg_init_timers(struct otg_hsm *hsm) | |
495 | { | |
496 | /* HSM used timers */ | |
497 | a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE, | |
498 | (unsigned long)&hsm->a_wait_vrise_tmout); | |
499 | if (a_wait_vrise_tmr == NULL) | |
500 | return -ENOMEM; | |
501 | a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS, | |
502 | (unsigned long)&hsm->a_aidl_bdis_tmout); | |
503 | if (a_aidl_bdis_tmr == NULL) | |
504 | return -ENOMEM; | |
505 | b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP, | |
506 | (unsigned long)&hsm->b_se0_srp); | |
507 | if (b_se0_srp_tmr == NULL) | |
508 | return -ENOMEM; | |
509 | b_srp_init_tmr = otg_timer_initializer(&set_tmout, TB_SRP_INIT, | |
510 | (unsigned long)&hsm->b_srp_init_tmout); | |
511 | if (b_srp_init_tmr == NULL) | |
512 | return -ENOMEM; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | /* Free timers */ | |
518 | static void langwell_otg_free_timers(void) | |
519 | { | |
520 | kfree(a_wait_vrise_tmr); | |
521 | kfree(a_aidl_bdis_tmr); | |
522 | kfree(b_se0_srp_tmr); | |
523 | kfree(b_srp_init_tmr); | |
524 | } | |
525 | ||
526 | /* The timeout callback function to set time out bit */ | |
527 | static void langwell_otg_timer_fn(unsigned long indicator) | |
528 | { | |
529 | struct langwell_otg *lnw = the_transceiver; | |
530 | ||
531 | *(int *)indicator = 1; | |
532 | ||
533 | dev_dbg(lnw->dev, "kernel timer - timeout\n"); | |
534 | ||
535 | langwell_update_transceiver(); | |
536 | } | |
537 | ||
538 | /* kernel timer used instead of HW based interrupt */ | |
539 | static void langwell_otg_add_ktimer(enum langwell_otg_timer_type timers) | |
540 | { | |
541 | struct langwell_otg *lnw = the_transceiver; | |
542 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
543 | unsigned long j = jiffies; | |
544 | unsigned long data, time; | |
545 | ||
546 | switch (timers) { | |
547 | case TA_WAIT_VRISE_TMR: | |
548 | iotg->hsm.a_wait_vrise_tmout = 0; | |
549 | data = (unsigned long)&iotg->hsm.a_wait_vrise_tmout; | |
550 | time = TA_WAIT_VRISE; | |
551 | break; | |
552 | case TA_WAIT_BCON_TMR: | |
553 | iotg->hsm.a_wait_bcon_tmout = 0; | |
554 | data = (unsigned long)&iotg->hsm.a_wait_bcon_tmout; | |
555 | time = TA_WAIT_BCON; | |
556 | break; | |
557 | case TA_AIDL_BDIS_TMR: | |
558 | iotg->hsm.a_aidl_bdis_tmout = 0; | |
559 | data = (unsigned long)&iotg->hsm.a_aidl_bdis_tmout; | |
560 | time = TA_AIDL_BDIS; | |
561 | break; | |
562 | case TB_ASE0_BRST_TMR: | |
563 | iotg->hsm.b_ase0_brst_tmout = 0; | |
564 | data = (unsigned long)&iotg->hsm.b_ase0_brst_tmout; | |
565 | time = TB_ASE0_BRST; | |
566 | break; | |
567 | case TB_SRP_INIT_TMR: | |
568 | iotg->hsm.b_srp_init_tmout = 0; | |
569 | data = (unsigned long)&iotg->hsm.b_srp_init_tmout; | |
570 | time = TB_SRP_INIT; | |
571 | break; | |
572 | case TB_SRP_FAIL_TMR: | |
573 | iotg->hsm.b_srp_fail_tmout = 0; | |
574 | data = (unsigned long)&iotg->hsm.b_srp_fail_tmout; | |
575 | time = TB_SRP_FAIL; | |
576 | break; | |
577 | case TB_BUS_SUSPEND_TMR: | |
578 | iotg->hsm.b_bus_suspend_tmout = 0; | |
579 | data = (unsigned long)&iotg->hsm.b_bus_suspend_tmout; | |
580 | time = TB_BUS_SUSPEND; | |
581 | break; | |
582 | default: | |
583 | dev_dbg(lnw->dev, "unkown timer, cannot enable it\n"); | |
584 | return; | |
585 | } | |
586 | ||
587 | lnw->hsm_timer.data = data; | |
588 | lnw->hsm_timer.function = langwell_otg_timer_fn; | |
589 | lnw->hsm_timer.expires = j + time * HZ / 1000; /* milliseconds */ | |
590 | ||
591 | add_timer(&lnw->hsm_timer); | |
592 | ||
593 | dev_dbg(lnw->dev, "add timer successfully\n"); | |
594 | } | |
595 | ||
596 | /* Add timer to timer list */ | |
597 | static void langwell_otg_add_timer(void *gtimer) | |
598 | { | |
599 | struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer; | |
600 | struct langwell_otg_timer *tmp_timer; | |
601 | struct intel_mid_otg_xceiv *iotg = &the_transceiver->iotg; | |
602 | u32 val32; | |
603 | ||
604 | /* Check if the timer is already in the active list, | |
605 | * if so update timer count | |
606 | */ | |
607 | list_for_each_entry(tmp_timer, &active_timers, list) | |
608 | if (tmp_timer == timer) { | |
609 | timer->count = timer->expires; | |
610 | return; | |
611 | } | |
612 | timer->count = timer->expires; | |
613 | ||
614 | if (list_empty(&active_timers)) { | |
615 | val32 = readl(iotg->base + CI_OTGSC); | |
616 | writel(val32 | OTGSC_1MSE, iotg->base + CI_OTGSC); | |
617 | } | |
618 | ||
619 | list_add_tail(&timer->list, &active_timers); | |
620 | } | |
621 | ||
622 | /* Remove timer from the timer list; clear timeout status */ | |
623 | static void langwell_otg_del_timer(void *gtimer) | |
624 | { | |
625 | struct langwell_otg *lnw = the_transceiver; | |
626 | struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer; | |
627 | struct langwell_otg_timer *tmp_timer, *del_tmp; | |
628 | u32 val32; | |
629 | ||
630 | list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) | |
631 | if (tmp_timer == timer) | |
632 | list_del(&timer->list); | |
633 | ||
634 | if (list_empty(&active_timers)) { | |
635 | val32 = readl(lnw->iotg.base + CI_OTGSC); | |
636 | writel(val32 & ~OTGSC_1MSE, lnw->iotg.base + CI_OTGSC); | |
637 | } | |
638 | } | |
639 | ||
640 | /* Reduce timer count by 1, and find timeout conditions.*/ | |
641 | static int langwell_otg_tick_timer(u32 *int_sts) | |
642 | { | |
643 | struct langwell_otg *lnw = the_transceiver; | |
644 | struct langwell_otg_timer *tmp_timer, *del_tmp; | |
645 | int expired = 0; | |
646 | ||
647 | list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) { | |
648 | tmp_timer->count--; | |
649 | /* check if timer expires */ | |
650 | if (!tmp_timer->count) { | |
651 | list_del(&tmp_timer->list); | |
652 | tmp_timer->function(tmp_timer->data); | |
653 | expired = 1; | |
654 | } | |
655 | } | |
656 | ||
657 | if (list_empty(&active_timers)) { | |
658 | dev_dbg(lnw->dev, "tick timer: disable 1ms int\n"); | |
659 | *int_sts = *int_sts & ~OTGSC_1MSE; | |
660 | } | |
661 | return expired; | |
662 | } | |
663 | ||
664 | static void reset_otg(void) | |
665 | { | |
666 | struct langwell_otg *lnw = the_transceiver; | |
667 | int delay_time = 1000; | |
668 | u32 val; | |
669 | ||
670 | dev_dbg(lnw->dev, "reseting OTG controller ...\n"); | |
671 | val = readl(lnw->iotg.base + CI_USBCMD); | |
672 | writel(val | USBCMD_RST, lnw->iotg.base + CI_USBCMD); | |
673 | do { | |
674 | udelay(100); | |
675 | if (!delay_time--) | |
676 | dev_dbg(lnw->dev, "reset timeout\n"); | |
677 | val = readl(lnw->iotg.base + CI_USBCMD); | |
678 | val &= USBCMD_RST; | |
679 | } while (val != 0); | |
680 | dev_dbg(lnw->dev, "reset done.\n"); | |
681 | } | |
682 | ||
683 | static void set_host_mode(void) | |
684 | { | |
685 | struct langwell_otg *lnw = the_transceiver; | |
686 | u32 val; | |
687 | ||
688 | reset_otg(); | |
689 | val = readl(lnw->iotg.base + CI_USBMODE); | |
690 | val = (val & (~USBMODE_CM)) | USBMODE_HOST; | |
691 | writel(val, lnw->iotg.base + CI_USBMODE); | |
692 | } | |
693 | ||
694 | static void set_client_mode(void) | |
695 | { | |
696 | struct langwell_otg *lnw = the_transceiver; | |
697 | u32 val; | |
698 | ||
699 | reset_otg(); | |
700 | val = readl(lnw->iotg.base + CI_USBMODE); | |
701 | val = (val & (~USBMODE_CM)) | USBMODE_DEVICE; | |
702 | writel(val, lnw->iotg.base + CI_USBMODE); | |
703 | } | |
704 | ||
705 | static void init_hsm(void) | |
706 | { | |
707 | struct langwell_otg *lnw = the_transceiver; | |
708 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
709 | u32 val32; | |
710 | ||
711 | /* read OTGSC after reset */ | |
712 | val32 = readl(lnw->iotg.base + CI_OTGSC); | |
713 | dev_dbg(lnw->dev, "%s: OTGSC init value = 0x%x\n", __func__, val32); | |
714 | ||
715 | /* set init state */ | |
716 | if (val32 & OTGSC_ID) { | |
717 | iotg->hsm.id = 1; | |
718 | iotg->otg.default_a = 0; | |
719 | set_client_mode(); | |
720 | iotg->otg.state = OTG_STATE_B_IDLE; | |
721 | } else { | |
722 | iotg->hsm.id = 0; | |
723 | iotg->otg.default_a = 1; | |
724 | set_host_mode(); | |
725 | iotg->otg.state = OTG_STATE_A_IDLE; | |
726 | } | |
727 | ||
728 | /* set session indicator */ | |
729 | if (val32 & OTGSC_BSE) | |
730 | iotg->hsm.b_sess_end = 1; | |
731 | if (val32 & OTGSC_BSV) | |
732 | iotg->hsm.b_sess_vld = 1; | |
733 | if (val32 & OTGSC_ASV) | |
734 | iotg->hsm.a_sess_vld = 1; | |
735 | if (val32 & OTGSC_AVV) | |
736 | iotg->hsm.a_vbus_vld = 1; | |
737 | ||
738 | /* defautly power the bus */ | |
739 | iotg->hsm.a_bus_req = 1; | |
740 | iotg->hsm.a_bus_drop = 0; | |
741 | /* defautly don't request bus as B device */ | |
742 | iotg->hsm.b_bus_req = 0; | |
743 | /* no system error */ | |
744 | iotg->hsm.a_clr_err = 0; | |
745 | ||
746 | langwell_otg_phy_low_power_wait(1); | |
747 | } | |
748 | ||
749 | static void update_hsm(void) | |
750 | { | |
751 | struct langwell_otg *lnw = the_transceiver; | |
752 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
753 | u32 val32; | |
754 | ||
755 | /* read OTGSC */ | |
756 | val32 = readl(lnw->iotg.base + CI_OTGSC); | |
757 | dev_dbg(lnw->dev, "%s: OTGSC value = 0x%x\n", __func__, val32); | |
758 | ||
759 | iotg->hsm.id = !!(val32 & OTGSC_ID); | |
760 | iotg->hsm.b_sess_end = !!(val32 & OTGSC_BSE); | |
761 | iotg->hsm.b_sess_vld = !!(val32 & OTGSC_BSV); | |
762 | iotg->hsm.a_sess_vld = !!(val32 & OTGSC_ASV); | |
763 | iotg->hsm.a_vbus_vld = !!(val32 & OTGSC_AVV); | |
764 | } | |
765 | ||
766 | static irqreturn_t otg_dummy_irq(int irq, void *_dev) | |
767 | { | |
768 | struct langwell_otg *lnw = the_transceiver; | |
769 | void __iomem *reg_base = _dev; | |
770 | u32 val; | |
771 | u32 int_mask = 0; | |
772 | ||
773 | val = readl(reg_base + CI_USBMODE); | |
774 | if ((val & USBMODE_CM) != USBMODE_DEVICE) | |
775 | return IRQ_NONE; | |
776 | ||
777 | val = readl(reg_base + CI_USBSTS); | |
778 | int_mask = val & INTR_DUMMY_MASK; | |
779 | ||
780 | if (int_mask == 0) | |
781 | return IRQ_NONE; | |
782 | ||
783 | /* clear hsm.b_conn here since host driver can't detect it | |
784 | * otg_dummy_irq called means B-disconnect happened. | |
785 | */ | |
786 | if (lnw->iotg.hsm.b_conn) { | |
787 | lnw->iotg.hsm.b_conn = 0; | |
788 | if (spin_trylock(&lnw->wq_lock)) { | |
789 | langwell_update_transceiver(); | |
790 | spin_unlock(&lnw->wq_lock); | |
791 | } | |
792 | } | |
793 | ||
794 | /* Clear interrupts */ | |
795 | writel(int_mask, reg_base + CI_USBSTS); | |
796 | return IRQ_HANDLED; | |
797 | } | |
798 | ||
799 | static irqreturn_t otg_irq(int irq, void *_dev) | |
800 | { | |
801 | struct langwell_otg *lnw = _dev; | |
802 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
803 | u32 int_sts, int_en; | |
804 | u32 int_mask = 0; | |
805 | int flag = 0; | |
806 | ||
807 | int_sts = readl(lnw->iotg.base + CI_OTGSC); | |
808 | int_en = (int_sts & OTGSC_INTEN_MASK) >> 8; | |
809 | int_mask = int_sts & int_en; | |
810 | if (int_mask == 0) | |
811 | return IRQ_NONE; | |
812 | ||
813 | if (int_mask & OTGSC_IDIS) { | |
814 | dev_dbg(lnw->dev, "%s: id change int\n", __func__); | |
815 | iotg->hsm.id = (int_sts & OTGSC_ID) ? 1 : 0; | |
816 | dev_dbg(lnw->dev, "id = %d\n", iotg->hsm.id); | |
817 | flag = 1; | |
818 | } | |
819 | if (int_mask & OTGSC_DPIS) { | |
820 | dev_dbg(lnw->dev, "%s: data pulse int\n", __func__); | |
821 | iotg->hsm.a_srp_det = (int_sts & OTGSC_DPS) ? 1 : 0; | |
822 | dev_dbg(lnw->dev, "data pulse = %d\n", iotg->hsm.a_srp_det); | |
823 | flag = 1; | |
824 | } | |
825 | if (int_mask & OTGSC_BSEIS) { | |
826 | dev_dbg(lnw->dev, "%s: b session end int\n", __func__); | |
827 | iotg->hsm.b_sess_end = (int_sts & OTGSC_BSE) ? 1 : 0; | |
828 | dev_dbg(lnw->dev, "b_sess_end = %d\n", iotg->hsm.b_sess_end); | |
829 | flag = 1; | |
830 | } | |
831 | if (int_mask & OTGSC_BSVIS) { | |
832 | dev_dbg(lnw->dev, "%s: b session valid int\n", __func__); | |
833 | iotg->hsm.b_sess_vld = (int_sts & OTGSC_BSV) ? 1 : 0; | |
834 | dev_dbg(lnw->dev, "b_sess_vld = %d\n", iotg->hsm.b_sess_end); | |
835 | flag = 1; | |
836 | } | |
837 | if (int_mask & OTGSC_ASVIS) { | |
838 | dev_dbg(lnw->dev, "%s: a session valid int\n", __func__); | |
839 | iotg->hsm.a_sess_vld = (int_sts & OTGSC_ASV) ? 1 : 0; | |
840 | dev_dbg(lnw->dev, "a_sess_vld = %d\n", iotg->hsm.a_sess_vld); | |
841 | flag = 1; | |
842 | } | |
843 | if (int_mask & OTGSC_AVVIS) { | |
844 | dev_dbg(lnw->dev, "%s: a vbus valid int\n", __func__); | |
845 | iotg->hsm.a_vbus_vld = (int_sts & OTGSC_AVV) ? 1 : 0; | |
846 | dev_dbg(lnw->dev, "a_vbus_vld = %d\n", iotg->hsm.a_vbus_vld); | |
847 | flag = 1; | |
848 | } | |
849 | ||
850 | if (int_mask & OTGSC_1MSS) { | |
851 | /* need to schedule otg_work if any timer is expired */ | |
852 | if (langwell_otg_tick_timer(&int_sts)) | |
853 | flag = 1; | |
854 | } | |
855 | ||
856 | writel((int_sts & ~OTGSC_INTSTS_MASK) | int_mask, | |
857 | lnw->iotg.base + CI_OTGSC); | |
858 | if (flag) | |
859 | langwell_update_transceiver(); | |
860 | ||
861 | return IRQ_HANDLED; | |
862 | } | |
863 | ||
864 | static int langwell_otg_iotg_notify(struct notifier_block *nb, | |
865 | unsigned long action, void *data) | |
866 | { | |
867 | struct langwell_otg *lnw = the_transceiver; | |
868 | struct intel_mid_otg_xceiv *iotg = data; | |
869 | int flag = 0; | |
870 | ||
871 | if (iotg == NULL) | |
872 | return NOTIFY_BAD; | |
873 | ||
874 | if (lnw == NULL) | |
875 | return NOTIFY_BAD; | |
876 | ||
877 | switch (action) { | |
878 | case MID_OTG_NOTIFY_CONNECT: | |
879 | dev_dbg(lnw->dev, "Lnw OTG Notify Connect Event\n"); | |
880 | if (iotg->otg.default_a == 1) | |
881 | iotg->hsm.b_conn = 1; | |
882 | else | |
883 | iotg->hsm.a_conn = 1; | |
884 | flag = 1; | |
885 | break; | |
886 | case MID_OTG_NOTIFY_DISCONN: | |
887 | dev_dbg(lnw->dev, "Lnw OTG Notify Disconnect Event\n"); | |
888 | if (iotg->otg.default_a == 1) | |
889 | iotg->hsm.b_conn = 0; | |
890 | else | |
891 | iotg->hsm.a_conn = 0; | |
892 | flag = 1; | |
893 | break; | |
894 | case MID_OTG_NOTIFY_HSUSPEND: | |
895 | dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus suspend Event\n"); | |
896 | if (iotg->otg.default_a == 1) | |
897 | iotg->hsm.a_suspend_req = 1; | |
898 | else | |
899 | iotg->hsm.b_bus_req = 0; | |
900 | flag = 1; | |
901 | break; | |
902 | case MID_OTG_NOTIFY_HRESUME: | |
903 | dev_dbg(lnw->dev, "Lnw OTG Notify Host Bus resume Event\n"); | |
904 | if (iotg->otg.default_a == 1) | |
905 | iotg->hsm.b_bus_resume = 1; | |
906 | flag = 1; | |
907 | break; | |
908 | case MID_OTG_NOTIFY_CSUSPEND: | |
909 | dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus suspend Event\n"); | |
910 | if (iotg->otg.default_a == 1) { | |
911 | if (iotg->hsm.b_bus_suspend_vld == 2) { | |
912 | iotg->hsm.b_bus_suspend = 1; | |
913 | iotg->hsm.b_bus_suspend_vld = 0; | |
914 | flag = 1; | |
915 | } else { | |
916 | iotg->hsm.b_bus_suspend_vld++; | |
917 | flag = 0; | |
918 | } | |
919 | } else { | |
920 | if (iotg->hsm.a_bus_suspend == 0) { | |
921 | iotg->hsm.a_bus_suspend = 1; | |
922 | flag = 1; | |
923 | } | |
924 | } | |
925 | break; | |
926 | case MID_OTG_NOTIFY_CRESUME: | |
927 | dev_dbg(lnw->dev, "Lnw OTG Notify Client Bus resume Event\n"); | |
928 | if (iotg->otg.default_a == 0) | |
929 | iotg->hsm.a_bus_suspend = 0; | |
930 | flag = 0; | |
931 | break; | |
932 | case MID_OTG_NOTIFY_HOSTADD: | |
933 | dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver Add\n"); | |
934 | flag = 1; | |
935 | break; | |
936 | case MID_OTG_NOTIFY_HOSTREMOVE: | |
937 | dev_dbg(lnw->dev, "Lnw OTG Nofity Host Driver remove\n"); | |
938 | flag = 1; | |
939 | break; | |
940 | case MID_OTG_NOTIFY_CLIENTADD: | |
941 | dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver Add\n"); | |
942 | flag = 1; | |
943 | break; | |
944 | case MID_OTG_NOTIFY_CLIENTREMOVE: | |
945 | dev_dbg(lnw->dev, "Lnw OTG Nofity Client Driver remove\n"); | |
946 | flag = 1; | |
947 | break; | |
948 | default: | |
949 | dev_dbg(lnw->dev, "Lnw OTG Nofity unknown notify message\n"); | |
950 | return NOTIFY_DONE; | |
951 | } | |
952 | ||
953 | if (flag) | |
954 | langwell_update_transceiver(); | |
955 | ||
956 | return NOTIFY_OK; | |
957 | } | |
958 | ||
959 | static void langwell_otg_work(struct work_struct *work) | |
960 | { | |
961 | struct langwell_otg *lnw; | |
962 | struct intel_mid_otg_xceiv *iotg; | |
963 | int retval; | |
964 | struct pci_dev *pdev; | |
965 | ||
966 | lnw = container_of(work, struct langwell_otg, work); | |
967 | iotg = &lnw->iotg; | |
968 | pdev = to_pci_dev(lnw->dev); | |
969 | ||
970 | dev_dbg(lnw->dev, "%s: old state = %s\n", __func__, | |
971 | state_string(iotg->otg.state)); | |
972 | ||
973 | switch (iotg->otg.state) { | |
974 | case OTG_STATE_UNDEFINED: | |
975 | case OTG_STATE_B_IDLE: | |
976 | if (!iotg->hsm.id) { | |
977 | langwell_otg_del_timer(b_srp_init_tmr); | |
978 | del_timer_sync(&lnw->hsm_timer); | |
979 | ||
980 | iotg->otg.default_a = 1; | |
981 | iotg->hsm.a_srp_det = 0; | |
982 | ||
983 | langwell_otg_chrg_vbus(0); | |
984 | set_host_mode(); | |
985 | langwell_otg_phy_low_power(1); | |
986 | ||
987 | iotg->otg.state = OTG_STATE_A_IDLE; | |
988 | langwell_update_transceiver(); | |
989 | } else if (iotg->hsm.b_sess_vld) { | |
990 | langwell_otg_del_timer(b_srp_init_tmr); | |
991 | del_timer_sync(&lnw->hsm_timer); | |
992 | iotg->hsm.b_sess_end = 0; | |
993 | iotg->hsm.a_bus_suspend = 0; | |
994 | langwell_otg_chrg_vbus(0); | |
995 | ||
996 | if (lnw->iotg.start_peripheral) { | |
997 | lnw->iotg.start_peripheral(&lnw->iotg); | |
998 | iotg->otg.state = OTG_STATE_B_PERIPHERAL; | |
999 | } else | |
1000 | dev_dbg(lnw->dev, "client driver not loaded\n"); | |
1001 | ||
1002 | } else if (iotg->hsm.b_srp_init_tmout) { | |
1003 | iotg->hsm.b_srp_init_tmout = 0; | |
1004 | dev_warn(lnw->dev, "SRP init timeout\n"); | |
1005 | } else if (iotg->hsm.b_srp_fail_tmout) { | |
1006 | iotg->hsm.b_srp_fail_tmout = 0; | |
1007 | iotg->hsm.b_bus_req = 0; | |
1008 | ||
1009 | /* No silence failure */ | |
1010 | langwell_otg_nsf_msg(6); | |
1011 | } else if (iotg->hsm.b_bus_req && iotg->hsm.b_sess_end) { | |
1012 | del_timer_sync(&lnw->hsm_timer); | |
1013 | /* workaround for b_se0_srp detection */ | |
1014 | retval = langwell_otg_check_se0_srp(0); | |
1015 | if (retval) { | |
1016 | iotg->hsm.b_bus_req = 0; | |
1017 | dev_dbg(lnw->dev, "LS isn't SE0, try later\n"); | |
1018 | } else { | |
1019 | /* clear the PHCD before start srp */ | |
1020 | langwell_otg_phy_low_power(0); | |
1021 | ||
1022 | /* Start SRP */ | |
1023 | langwell_otg_add_timer(b_srp_init_tmr); | |
1024 | iotg->otg.start_srp(&iotg->otg); | |
1025 | langwell_otg_del_timer(b_srp_init_tmr); | |
1026 | langwell_otg_add_ktimer(TB_SRP_FAIL_TMR); | |
1027 | ||
1028 | /* reset PHY low power mode here */ | |
1029 | langwell_otg_phy_low_power_wait(1); | |
1030 | } | |
1031 | } | |
1032 | break; | |
1033 | case OTG_STATE_B_SRP_INIT: | |
1034 | if (!iotg->hsm.id) { | |
1035 | iotg->otg.default_a = 1; | |
1036 | iotg->hsm.a_srp_det = 0; | |
1037 | ||
1038 | /* Turn off VBus */ | |
1039 | iotg->otg.set_vbus(&iotg->otg, false); | |
1040 | langwell_otg_chrg_vbus(0); | |
1041 | set_host_mode(); | |
1042 | langwell_otg_phy_low_power(1); | |
1043 | iotg->otg.state = OTG_STATE_A_IDLE; | |
1044 | langwell_update_transceiver(); | |
1045 | } else if (iotg->hsm.b_sess_vld) { | |
1046 | langwell_otg_chrg_vbus(0); | |
1047 | if (lnw->iotg.start_peripheral) { | |
1048 | lnw->iotg.start_peripheral(&lnw->iotg); | |
1049 | iotg->otg.state = OTG_STATE_B_PERIPHERAL; | |
1050 | } else | |
1051 | dev_dbg(lnw->dev, "client driver not loaded\n"); | |
1052 | } | |
1053 | break; | |
1054 | case OTG_STATE_B_PERIPHERAL: | |
1055 | if (!iotg->hsm.id) { | |
1056 | iotg->otg.default_a = 1; | |
1057 | iotg->hsm.a_srp_det = 0; | |
1058 | ||
1059 | langwell_otg_chrg_vbus(0); | |
1060 | ||
1061 | if (lnw->iotg.stop_peripheral) | |
1062 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1063 | else | |
1064 | dev_dbg(lnw->dev, | |
1065 | "client driver has been removed.\n"); | |
1066 | ||
1067 | set_host_mode(); | |
1068 | langwell_otg_phy_low_power(1); | |
1069 | iotg->otg.state = OTG_STATE_A_IDLE; | |
1070 | langwell_update_transceiver(); | |
1071 | } else if (!iotg->hsm.b_sess_vld) { | |
1072 | iotg->hsm.b_hnp_enable = 0; | |
1073 | ||
1074 | if (lnw->iotg.stop_peripheral) | |
1075 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1076 | else | |
1077 | dev_dbg(lnw->dev, | |
1078 | "client driver has been removed.\n"); | |
1079 | ||
1080 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1081 | } else if (iotg->hsm.b_bus_req && iotg->otg.gadget && | |
1082 | iotg->otg.gadget->b_hnp_enable && | |
1083 | iotg->hsm.a_bus_suspend) { | |
1084 | ||
1085 | if (lnw->iotg.stop_peripheral) | |
1086 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1087 | else | |
1088 | dev_dbg(lnw->dev, | |
1089 | "client driver has been removed.\n"); | |
1090 | ||
1091 | langwell_otg_HAAR(1); | |
1092 | iotg->hsm.a_conn = 0; | |
1093 | ||
1094 | if (lnw->iotg.start_host) { | |
1095 | lnw->iotg.start_host(&lnw->iotg); | |
1096 | iotg->otg.state = OTG_STATE_B_WAIT_ACON; | |
1097 | } else | |
1098 | dev_dbg(lnw->dev, | |
1099 | "host driver not loaded.\n"); | |
1100 | ||
1101 | iotg->hsm.a_bus_resume = 0; | |
1102 | langwell_otg_add_ktimer(TB_ASE0_BRST_TMR); | |
1103 | } | |
1104 | break; | |
1105 | ||
1106 | case OTG_STATE_B_WAIT_ACON: | |
1107 | if (!iotg->hsm.id) { | |
1108 | /* delete hsm timer for b_ase0_brst_tmr */ | |
1109 | del_timer_sync(&lnw->hsm_timer); | |
1110 | ||
1111 | iotg->otg.default_a = 1; | |
1112 | iotg->hsm.a_srp_det = 0; | |
1113 | ||
1114 | langwell_otg_chrg_vbus(0); | |
1115 | ||
1116 | langwell_otg_HAAR(0); | |
1117 | if (lnw->iotg.stop_host) | |
1118 | lnw->iotg.stop_host(&lnw->iotg); | |
1119 | else | |
1120 | dev_dbg(lnw->dev, | |
1121 | "host driver has been removed.\n"); | |
1122 | ||
1123 | set_host_mode(); | |
1124 | langwell_otg_phy_low_power(1); | |
1125 | iotg->otg.state = OTG_STATE_A_IDLE; | |
1126 | langwell_update_transceiver(); | |
1127 | } else if (!iotg->hsm.b_sess_vld) { | |
1128 | /* delete hsm timer for b_ase0_brst_tmr */ | |
1129 | del_timer_sync(&lnw->hsm_timer); | |
1130 | ||
1131 | iotg->hsm.b_hnp_enable = 0; | |
1132 | iotg->hsm.b_bus_req = 0; | |
1133 | ||
1134 | langwell_otg_chrg_vbus(0); | |
1135 | langwell_otg_HAAR(0); | |
1136 | ||
1137 | if (lnw->iotg.stop_host) | |
1138 | lnw->iotg.stop_host(&lnw->iotg); | |
1139 | else | |
1140 | dev_dbg(lnw->dev, | |
1141 | "host driver has been removed.\n"); | |
1142 | ||
1143 | set_client_mode(); | |
1144 | langwell_otg_phy_low_power(1); | |
1145 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1146 | } else if (iotg->hsm.a_conn) { | |
1147 | /* delete hsm timer for b_ase0_brst_tmr */ | |
1148 | del_timer_sync(&lnw->hsm_timer); | |
1149 | ||
1150 | langwell_otg_HAAR(0); | |
1151 | iotg->otg.state = OTG_STATE_B_HOST; | |
1152 | langwell_update_transceiver(); | |
1153 | } else if (iotg->hsm.a_bus_resume || | |
1154 | iotg->hsm.b_ase0_brst_tmout) { | |
1155 | /* delete hsm timer for b_ase0_brst_tmr */ | |
1156 | del_timer_sync(&lnw->hsm_timer); | |
1157 | ||
1158 | langwell_otg_HAAR(0); | |
1159 | langwell_otg_nsf_msg(7); | |
1160 | ||
1161 | if (lnw->iotg.stop_host) | |
1162 | lnw->iotg.stop_host(&lnw->iotg); | |
1163 | else | |
1164 | dev_dbg(lnw->dev, | |
1165 | "host driver has been removed.\n"); | |
1166 | ||
1167 | iotg->hsm.a_bus_suspend = 0; | |
1168 | iotg->hsm.b_bus_req = 0; | |
1169 | ||
1170 | if (lnw->iotg.start_peripheral) | |
1171 | lnw->iotg.start_peripheral(&lnw->iotg); | |
1172 | else | |
1173 | dev_dbg(lnw->dev, | |
1174 | "client driver not loaded.\n"); | |
1175 | ||
1176 | iotg->otg.state = OTG_STATE_B_PERIPHERAL; | |
1177 | } | |
1178 | break; | |
1179 | ||
1180 | case OTG_STATE_B_HOST: | |
1181 | if (!iotg->hsm.id) { | |
1182 | iotg->otg.default_a = 1; | |
1183 | iotg->hsm.a_srp_det = 0; | |
1184 | ||
1185 | langwell_otg_chrg_vbus(0); | |
1186 | ||
1187 | if (lnw->iotg.stop_host) | |
1188 | lnw->iotg.stop_host(&lnw->iotg); | |
1189 | else | |
1190 | dev_dbg(lnw->dev, | |
1191 | "host driver has been removed.\n"); | |
1192 | ||
1193 | set_host_mode(); | |
1194 | langwell_otg_phy_low_power(1); | |
1195 | iotg->otg.state = OTG_STATE_A_IDLE; | |
1196 | langwell_update_transceiver(); | |
1197 | } else if (!iotg->hsm.b_sess_vld) { | |
1198 | iotg->hsm.b_hnp_enable = 0; | |
1199 | iotg->hsm.b_bus_req = 0; | |
1200 | ||
1201 | langwell_otg_chrg_vbus(0); | |
1202 | if (lnw->iotg.stop_host) | |
1203 | lnw->iotg.stop_host(&lnw->iotg); | |
1204 | else | |
1205 | dev_dbg(lnw->dev, | |
1206 | "host driver has been removed.\n"); | |
1207 | ||
1208 | set_client_mode(); | |
1209 | langwell_otg_phy_low_power(1); | |
1210 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1211 | } else if ((!iotg->hsm.b_bus_req) || | |
1212 | (!iotg->hsm.a_conn)) { | |
1213 | iotg->hsm.b_bus_req = 0; | |
1214 | langwell_otg_loc_sof(0); | |
1215 | ||
1216 | if (lnw->iotg.stop_host) | |
1217 | lnw->iotg.stop_host(&lnw->iotg); | |
1218 | else | |
1219 | dev_dbg(lnw->dev, | |
1220 | "host driver has been removed.\n"); | |
1221 | ||
1222 | iotg->hsm.a_bus_suspend = 0; | |
1223 | ||
1224 | if (lnw->iotg.start_peripheral) | |
1225 | lnw->iotg.start_peripheral(&lnw->iotg); | |
1226 | else | |
1227 | dev_dbg(lnw->dev, | |
1228 | "client driver not loaded.\n"); | |
1229 | ||
1230 | iotg->otg.state = OTG_STATE_B_PERIPHERAL; | |
1231 | } | |
1232 | break; | |
1233 | ||
1234 | case OTG_STATE_A_IDLE: | |
1235 | iotg->otg.default_a = 1; | |
1236 | if (iotg->hsm.id) { | |
1237 | iotg->otg.default_a = 0; | |
1238 | iotg->hsm.b_bus_req = 0; | |
1239 | iotg->hsm.vbus_srp_up = 0; | |
1240 | ||
1241 | langwell_otg_chrg_vbus(0); | |
1242 | set_client_mode(); | |
1243 | langwell_otg_phy_low_power(1); | |
1244 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1245 | langwell_update_transceiver(); | |
1246 | } else if (!iotg->hsm.a_bus_drop && | |
1247 | (iotg->hsm.a_srp_det || iotg->hsm.a_bus_req)) { | |
1248 | langwell_otg_phy_low_power(0); | |
1249 | ||
1250 | /* Turn on VBus */ | |
1251 | iotg->otg.set_vbus(&iotg->otg, true); | |
1252 | ||
1253 | iotg->hsm.vbus_srp_up = 0; | |
1254 | iotg->hsm.a_wait_vrise_tmout = 0; | |
1255 | langwell_otg_add_timer(a_wait_vrise_tmr); | |
1256 | iotg->otg.state = OTG_STATE_A_WAIT_VRISE; | |
1257 | langwell_update_transceiver(); | |
1258 | } else if (!iotg->hsm.a_bus_drop && iotg->hsm.a_sess_vld) { | |
1259 | iotg->hsm.vbus_srp_up = 1; | |
1260 | } else if (!iotg->hsm.a_sess_vld && iotg->hsm.vbus_srp_up) { | |
1261 | msleep(10); | |
1262 | langwell_otg_phy_low_power(0); | |
1263 | ||
1264 | /* Turn on VBus */ | |
1265 | iotg->otg.set_vbus(&iotg->otg, true); | |
1266 | iotg->hsm.a_srp_det = 1; | |
1267 | iotg->hsm.vbus_srp_up = 0; | |
1268 | iotg->hsm.a_wait_vrise_tmout = 0; | |
1269 | langwell_otg_add_timer(a_wait_vrise_tmr); | |
1270 | iotg->otg.state = OTG_STATE_A_WAIT_VRISE; | |
1271 | langwell_update_transceiver(); | |
1272 | } else if (!iotg->hsm.a_sess_vld && | |
1273 | !iotg->hsm.vbus_srp_up) { | |
1274 | langwell_otg_phy_low_power(1); | |
1275 | } | |
1276 | break; | |
1277 | case OTG_STATE_A_WAIT_VRISE: | |
1278 | if (iotg->hsm.id) { | |
1279 | langwell_otg_del_timer(a_wait_vrise_tmr); | |
1280 | iotg->hsm.b_bus_req = 0; | |
1281 | iotg->otg.default_a = 0; | |
1282 | ||
1283 | /* Turn off VBus */ | |
1284 | iotg->otg.set_vbus(&iotg->otg, false); | |
1285 | set_client_mode(); | |
1286 | langwell_otg_phy_low_power_wait(1); | |
1287 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1288 | } else if (iotg->hsm.a_vbus_vld) { | |
1289 | langwell_otg_del_timer(a_wait_vrise_tmr); | |
1290 | iotg->hsm.b_conn = 0; | |
1291 | if (lnw->iotg.start_host) | |
1292 | lnw->iotg.start_host(&lnw->iotg); | |
1293 | else { | |
1294 | dev_dbg(lnw->dev, "host driver not loaded.\n"); | |
1295 | break; | |
1296 | } | |
1297 | ||
1298 | langwell_otg_add_ktimer(TA_WAIT_BCON_TMR); | |
1299 | iotg->otg.state = OTG_STATE_A_WAIT_BCON; | |
1300 | } else if (iotg->hsm.a_wait_vrise_tmout) { | |
1301 | iotg->hsm.b_conn = 0; | |
1302 | if (iotg->hsm.a_vbus_vld) { | |
1303 | if (lnw->iotg.start_host) | |
1304 | lnw->iotg.start_host(&lnw->iotg); | |
1305 | else { | |
1306 | dev_dbg(lnw->dev, | |
1307 | "host driver not loaded.\n"); | |
1308 | break; | |
1309 | } | |
1310 | langwell_otg_add_ktimer(TA_WAIT_BCON_TMR); | |
1311 | iotg->otg.state = OTG_STATE_A_WAIT_BCON; | |
1312 | } else { | |
1313 | ||
1314 | /* Turn off VBus */ | |
1315 | iotg->otg.set_vbus(&iotg->otg, false); | |
1316 | langwell_otg_phy_low_power_wait(1); | |
1317 | iotg->otg.state = OTG_STATE_A_VBUS_ERR; | |
1318 | } | |
1319 | } | |
1320 | break; | |
1321 | case OTG_STATE_A_WAIT_BCON: | |
1322 | if (iotg->hsm.id) { | |
1323 | /* delete hsm timer for a_wait_bcon_tmr */ | |
1324 | del_timer_sync(&lnw->hsm_timer); | |
1325 | ||
1326 | iotg->otg.default_a = 0; | |
1327 | iotg->hsm.b_bus_req = 0; | |
1328 | ||
1329 | if (lnw->iotg.stop_host) | |
1330 | lnw->iotg.stop_host(&lnw->iotg); | |
1331 | else | |
1332 | dev_dbg(lnw->dev, | |
1333 | "host driver has been removed.\n"); | |
1334 | ||
1335 | /* Turn off VBus */ | |
1336 | iotg->otg.set_vbus(&iotg->otg, false); | |
1337 | set_client_mode(); | |
1338 | langwell_otg_phy_low_power_wait(1); | |
1339 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1340 | langwell_update_transceiver(); | |
1341 | } else if (!iotg->hsm.a_vbus_vld) { | |
1342 | /* delete hsm timer for a_wait_bcon_tmr */ | |
1343 | del_timer_sync(&lnw->hsm_timer); | |
1344 | ||
1345 | if (lnw->iotg.stop_host) | |
1346 | lnw->iotg.stop_host(&lnw->iotg); | |
1347 | else | |
1348 | dev_dbg(lnw->dev, | |
1349 | "host driver has been removed.\n"); | |
1350 | ||
1351 | /* Turn off VBus */ | |
1352 | iotg->otg.set_vbus(&iotg->otg, false); | |
1353 | langwell_otg_phy_low_power_wait(1); | |
1354 | iotg->otg.state = OTG_STATE_A_VBUS_ERR; | |
1355 | } else if (iotg->hsm.a_bus_drop || | |
1356 | (iotg->hsm.a_wait_bcon_tmout && | |
1357 | !iotg->hsm.a_bus_req)) { | |
1358 | /* delete hsm timer for a_wait_bcon_tmr */ | |
1359 | del_timer_sync(&lnw->hsm_timer); | |
1360 | ||
1361 | if (lnw->iotg.stop_host) | |
1362 | lnw->iotg.stop_host(&lnw->iotg); | |
1363 | else | |
1364 | dev_dbg(lnw->dev, | |
1365 | "host driver has been removed.\n"); | |
1366 | ||
1367 | /* Turn off VBus */ | |
1368 | iotg->otg.set_vbus(&iotg->otg, false); | |
1369 | iotg->otg.state = OTG_STATE_A_WAIT_VFALL; | |
1370 | } else if (iotg->hsm.b_conn) { | |
1371 | /* delete hsm timer for a_wait_bcon_tmr */ | |
1372 | del_timer_sync(&lnw->hsm_timer); | |
1373 | ||
1374 | iotg->hsm.a_suspend_req = 0; | |
1375 | iotg->otg.state = OTG_STATE_A_HOST; | |
1376 | if (iotg->hsm.a_srp_det && iotg->otg.host && | |
1377 | !iotg->otg.host->b_hnp_enable) { | |
1378 | /* SRP capable peripheral-only device */ | |
1379 | iotg->hsm.a_bus_req = 1; | |
1380 | iotg->hsm.a_srp_det = 0; | |
1381 | } else if (!iotg->hsm.a_bus_req && iotg->otg.host && | |
1382 | iotg->otg.host->b_hnp_enable) { | |
1383 | /* It is not safe enough to do a fast | |
1384 | * transistion from A_WAIT_BCON to | |
1385 | * A_SUSPEND */ | |
1386 | msleep(10000); | |
1387 | if (iotg->hsm.a_bus_req) | |
1388 | break; | |
1389 | ||
1390 | if (request_irq(pdev->irq, | |
1391 | otg_dummy_irq, IRQF_SHARED, | |
1392 | driver_name, iotg->base) != 0) { | |
1393 | dev_dbg(lnw->dev, | |
1394 | "request interrupt %d fail\n", | |
1395 | pdev->irq); | |
1396 | } | |
1397 | ||
1398 | langwell_otg_HABA(1); | |
1399 | iotg->hsm.b_bus_resume = 0; | |
1400 | iotg->hsm.a_aidl_bdis_tmout = 0; | |
1401 | ||
1402 | langwell_otg_loc_sof(0); | |
1403 | /* clear PHCD to enable HW timer */ | |
1404 | langwell_otg_phy_low_power(0); | |
1405 | langwell_otg_add_timer(a_aidl_bdis_tmr); | |
1406 | iotg->otg.state = OTG_STATE_A_SUSPEND; | |
1407 | } else if (!iotg->hsm.a_bus_req && iotg->otg.host && | |
1408 | !iotg->otg.host->b_hnp_enable) { | |
1409 | if (lnw->iotg.stop_host) | |
1410 | lnw->iotg.stop_host(&lnw->iotg); | |
1411 | else | |
1412 | dev_dbg(lnw->dev, | |
1413 | "host driver removed.\n"); | |
1414 | ||
1415 | /* Turn off VBus */ | |
1416 | iotg->otg.set_vbus(&iotg->otg, false); | |
1417 | iotg->otg.state = OTG_STATE_A_WAIT_VFALL; | |
1418 | } | |
1419 | } | |
1420 | break; | |
1421 | case OTG_STATE_A_HOST: | |
1422 | if (iotg->hsm.id) { | |
1423 | iotg->otg.default_a = 0; | |
1424 | iotg->hsm.b_bus_req = 0; | |
1425 | ||
1426 | if (lnw->iotg.stop_host) | |
1427 | lnw->iotg.stop_host(&lnw->iotg); | |
1428 | else | |
1429 | dev_dbg(lnw->dev, | |
1430 | "host driver has been removed.\n"); | |
1431 | ||
1432 | /* Turn off VBus */ | |
1433 | iotg->otg.set_vbus(&iotg->otg, false); | |
1434 | set_client_mode(); | |
1435 | langwell_otg_phy_low_power_wait(1); | |
1436 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1437 | langwell_update_transceiver(); | |
1438 | } else if (iotg->hsm.a_bus_drop || | |
1439 | (iotg->otg.host && | |
1440 | !iotg->otg.host->b_hnp_enable && | |
1441 | !iotg->hsm.a_bus_req)) { | |
1442 | if (lnw->iotg.stop_host) | |
1443 | lnw->iotg.stop_host(&lnw->iotg); | |
1444 | else | |
1445 | dev_dbg(lnw->dev, | |
1446 | "host driver has been removed.\n"); | |
1447 | ||
1448 | /* Turn off VBus */ | |
1449 | iotg->otg.set_vbus(&iotg->otg, false); | |
1450 | iotg->otg.state = OTG_STATE_A_WAIT_VFALL; | |
1451 | } else if (!iotg->hsm.a_vbus_vld) { | |
1452 | if (lnw->iotg.stop_host) | |
1453 | lnw->iotg.stop_host(&lnw->iotg); | |
1454 | else | |
1455 | dev_dbg(lnw->dev, | |
1456 | "host driver has been removed.\n"); | |
1457 | ||
1458 | /* Turn off VBus */ | |
1459 | iotg->otg.set_vbus(&iotg->otg, false); | |
1460 | langwell_otg_phy_low_power_wait(1); | |
1461 | iotg->otg.state = OTG_STATE_A_VBUS_ERR; | |
1462 | } else if (iotg->otg.host && | |
1463 | iotg->otg.host->b_hnp_enable && | |
1464 | !iotg->hsm.a_bus_req) { | |
1465 | /* Set HABA to enable hardware assistance to signal | |
1466 | * A-connect after receiver B-disconnect. Hardware | |
1467 | * will then set client mode and enable URE, SLE and | |
1468 | * PCE after the assistance. otg_dummy_irq is used to | |
1469 | * clean these ints when client driver is not resumed. | |
1470 | */ | |
1471 | if (request_irq(pdev->irq, otg_dummy_irq, IRQF_SHARED, | |
1472 | driver_name, iotg->base) != 0) { | |
1473 | dev_dbg(lnw->dev, | |
1474 | "request interrupt %d failed\n", | |
1475 | pdev->irq); | |
1476 | } | |
1477 | ||
1478 | /* set HABA */ | |
1479 | langwell_otg_HABA(1); | |
1480 | iotg->hsm.b_bus_resume = 0; | |
1481 | iotg->hsm.a_aidl_bdis_tmout = 0; | |
1482 | langwell_otg_loc_sof(0); | |
1483 | /* clear PHCD to enable HW timer */ | |
1484 | langwell_otg_phy_low_power(0); | |
1485 | langwell_otg_add_timer(a_aidl_bdis_tmr); | |
1486 | iotg->otg.state = OTG_STATE_A_SUSPEND; | |
1487 | } else if (!iotg->hsm.b_conn || !iotg->hsm.a_bus_req) { | |
1488 | langwell_otg_add_ktimer(TA_WAIT_BCON_TMR); | |
1489 | iotg->otg.state = OTG_STATE_A_WAIT_BCON; | |
1490 | } | |
1491 | break; | |
1492 | case OTG_STATE_A_SUSPEND: | |
1493 | if (iotg->hsm.id) { | |
1494 | langwell_otg_del_timer(a_aidl_bdis_tmr); | |
1495 | langwell_otg_HABA(0); | |
1496 | free_irq(pdev->irq, iotg->base); | |
1497 | iotg->otg.default_a = 0; | |
1498 | iotg->hsm.b_bus_req = 0; | |
1499 | ||
1500 | if (lnw->iotg.stop_host) | |
1501 | lnw->iotg.stop_host(&lnw->iotg); | |
1502 | else | |
1503 | dev_dbg(lnw->dev, | |
1504 | "host driver has been removed.\n"); | |
1505 | ||
1506 | /* Turn off VBus */ | |
1507 | iotg->otg.set_vbus(&iotg->otg, false); | |
1508 | set_client_mode(); | |
1509 | langwell_otg_phy_low_power(1); | |
1510 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1511 | langwell_update_transceiver(); | |
1512 | } else if (iotg->hsm.a_bus_req || | |
1513 | iotg->hsm.b_bus_resume) { | |
1514 | langwell_otg_del_timer(a_aidl_bdis_tmr); | |
1515 | langwell_otg_HABA(0); | |
1516 | free_irq(pdev->irq, iotg->base); | |
1517 | iotg->hsm.a_suspend_req = 0; | |
1518 | langwell_otg_loc_sof(1); | |
1519 | iotg->otg.state = OTG_STATE_A_HOST; | |
1520 | } else if (iotg->hsm.a_aidl_bdis_tmout || | |
1521 | iotg->hsm.a_bus_drop) { | |
1522 | langwell_otg_del_timer(a_aidl_bdis_tmr); | |
1523 | langwell_otg_HABA(0); | |
1524 | free_irq(pdev->irq, iotg->base); | |
1525 | if (lnw->iotg.stop_host) | |
1526 | lnw->iotg.stop_host(&lnw->iotg); | |
1527 | else | |
1528 | dev_dbg(lnw->dev, | |
1529 | "host driver has been removed.\n"); | |
1530 | ||
1531 | /* Turn off VBus */ | |
1532 | iotg->otg.set_vbus(&iotg->otg, false); | |
1533 | iotg->otg.state = OTG_STATE_A_WAIT_VFALL; | |
1534 | } else if (!iotg->hsm.b_conn && iotg->otg.host && | |
1535 | iotg->otg.host->b_hnp_enable) { | |
1536 | langwell_otg_del_timer(a_aidl_bdis_tmr); | |
1537 | langwell_otg_HABA(0); | |
1538 | free_irq(pdev->irq, iotg->base); | |
1539 | ||
1540 | if (lnw->iotg.stop_host) | |
1541 | lnw->iotg.stop_host(&lnw->iotg); | |
1542 | else | |
1543 | dev_dbg(lnw->dev, | |
1544 | "host driver has been removed.\n"); | |
1545 | ||
1546 | iotg->hsm.b_bus_suspend = 0; | |
1547 | iotg->hsm.b_bus_suspend_vld = 0; | |
1548 | ||
1549 | /* msleep(200); */ | |
1550 | if (lnw->iotg.start_peripheral) | |
1551 | lnw->iotg.start_peripheral(&lnw->iotg); | |
1552 | else | |
1553 | dev_dbg(lnw->dev, | |
1554 | "client driver not loaded.\n"); | |
1555 | ||
1556 | langwell_otg_add_ktimer(TB_BUS_SUSPEND_TMR); | |
1557 | iotg->otg.state = OTG_STATE_A_PERIPHERAL; | |
1558 | break; | |
1559 | } else if (!iotg->hsm.a_vbus_vld) { | |
1560 | langwell_otg_del_timer(a_aidl_bdis_tmr); | |
1561 | langwell_otg_HABA(0); | |
1562 | free_irq(pdev->irq, iotg->base); | |
1563 | if (lnw->iotg.stop_host) | |
1564 | lnw->iotg.stop_host(&lnw->iotg); | |
1565 | else | |
1566 | dev_dbg(lnw->dev, | |
1567 | "host driver has been removed.\n"); | |
1568 | ||
1569 | /* Turn off VBus */ | |
1570 | iotg->otg.set_vbus(&iotg->otg, false); | |
1571 | langwell_otg_phy_low_power_wait(1); | |
1572 | iotg->otg.state = OTG_STATE_A_VBUS_ERR; | |
1573 | } | |
1574 | break; | |
1575 | case OTG_STATE_A_PERIPHERAL: | |
1576 | if (iotg->hsm.id) { | |
1577 | /* delete hsm timer for b_bus_suspend_tmr */ | |
1578 | del_timer_sync(&lnw->hsm_timer); | |
1579 | iotg->otg.default_a = 0; | |
1580 | iotg->hsm.b_bus_req = 0; | |
1581 | if (lnw->iotg.stop_peripheral) | |
1582 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1583 | else | |
1584 | dev_dbg(lnw->dev, | |
1585 | "client driver has been removed.\n"); | |
1586 | ||
1587 | /* Turn off VBus */ | |
1588 | iotg->otg.set_vbus(&iotg->otg, false); | |
1589 | set_client_mode(); | |
1590 | langwell_otg_phy_low_power_wait(1); | |
1591 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1592 | langwell_update_transceiver(); | |
1593 | } else if (!iotg->hsm.a_vbus_vld) { | |
1594 | /* delete hsm timer for b_bus_suspend_tmr */ | |
1595 | del_timer_sync(&lnw->hsm_timer); | |
1596 | ||
1597 | if (lnw->iotg.stop_peripheral) | |
1598 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1599 | else | |
1600 | dev_dbg(lnw->dev, | |
1601 | "client driver has been removed.\n"); | |
1602 | ||
1603 | /* Turn off VBus */ | |
1604 | iotg->otg.set_vbus(&iotg->otg, false); | |
1605 | langwell_otg_phy_low_power_wait(1); | |
1606 | iotg->otg.state = OTG_STATE_A_VBUS_ERR; | |
1607 | } else if (iotg->hsm.a_bus_drop) { | |
1608 | /* delete hsm timer for b_bus_suspend_tmr */ | |
1609 | del_timer_sync(&lnw->hsm_timer); | |
1610 | ||
1611 | if (lnw->iotg.stop_peripheral) | |
1612 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1613 | else | |
1614 | dev_dbg(lnw->dev, | |
1615 | "client driver has been removed.\n"); | |
1616 | ||
1617 | /* Turn off VBus */ | |
1618 | iotg->otg.set_vbus(&iotg->otg, false); | |
1619 | iotg->otg.state = OTG_STATE_A_WAIT_VFALL; | |
1620 | } else if (iotg->hsm.b_bus_suspend) { | |
1621 | /* delete hsm timer for b_bus_suspend_tmr */ | |
1622 | del_timer_sync(&lnw->hsm_timer); | |
1623 | ||
1624 | if (lnw->iotg.stop_peripheral) | |
1625 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1626 | else | |
1627 | dev_dbg(lnw->dev, | |
1628 | "client driver has been removed.\n"); | |
1629 | ||
1630 | if (lnw->iotg.start_host) | |
1631 | lnw->iotg.start_host(&lnw->iotg); | |
1632 | else | |
1633 | dev_dbg(lnw->dev, | |
1634 | "host driver not loaded.\n"); | |
1635 | langwell_otg_add_ktimer(TA_WAIT_BCON_TMR); | |
1636 | iotg->otg.state = OTG_STATE_A_WAIT_BCON; | |
1637 | } else if (iotg->hsm.b_bus_suspend_tmout) { | |
1638 | u32 val; | |
1639 | val = readl(lnw->iotg.base + CI_PORTSC1); | |
1640 | if (!(val & PORTSC_SUSP)) | |
1641 | break; | |
1642 | ||
1643 | if (lnw->iotg.stop_peripheral) | |
1644 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
1645 | else | |
1646 | dev_dbg(lnw->dev, | |
1647 | "client driver has been removed.\n"); | |
1648 | ||
1649 | if (lnw->iotg.start_host) | |
1650 | lnw->iotg.start_host(&lnw->iotg); | |
1651 | else | |
1652 | dev_dbg(lnw->dev, | |
1653 | "host driver not loaded.\n"); | |
1654 | langwell_otg_add_ktimer(TA_WAIT_BCON_TMR); | |
1655 | iotg->otg.state = OTG_STATE_A_WAIT_BCON; | |
1656 | } | |
1657 | break; | |
1658 | case OTG_STATE_A_VBUS_ERR: | |
1659 | if (iotg->hsm.id) { | |
1660 | iotg->otg.default_a = 0; | |
1661 | iotg->hsm.a_clr_err = 0; | |
1662 | iotg->hsm.a_srp_det = 0; | |
1663 | set_client_mode(); | |
1664 | langwell_otg_phy_low_power(1); | |
1665 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1666 | langwell_update_transceiver(); | |
1667 | } else if (iotg->hsm.a_clr_err) { | |
1668 | iotg->hsm.a_clr_err = 0; | |
1669 | iotg->hsm.a_srp_det = 0; | |
1670 | reset_otg(); | |
1671 | init_hsm(); | |
1672 | if (iotg->otg.state == OTG_STATE_A_IDLE) | |
1673 | langwell_update_transceiver(); | |
1674 | } else { | |
1675 | /* FW will clear PHCD bit when any VBus | |
1676 | * event detected. Reset PHCD to 1 again */ | |
1677 | langwell_otg_phy_low_power(1); | |
1678 | } | |
1679 | break; | |
1680 | case OTG_STATE_A_WAIT_VFALL: | |
1681 | if (iotg->hsm.id) { | |
1682 | iotg->otg.default_a = 0; | |
1683 | set_client_mode(); | |
1684 | langwell_otg_phy_low_power(1); | |
1685 | iotg->otg.state = OTG_STATE_B_IDLE; | |
1686 | langwell_update_transceiver(); | |
1687 | } else if (iotg->hsm.a_bus_req) { | |
1688 | ||
1689 | /* Turn on VBus */ | |
1690 | iotg->otg.set_vbus(&iotg->otg, true); | |
1691 | iotg->hsm.a_wait_vrise_tmout = 0; | |
1692 | langwell_otg_add_timer(a_wait_vrise_tmr); | |
1693 | iotg->otg.state = OTG_STATE_A_WAIT_VRISE; | |
1694 | } else if (!iotg->hsm.a_sess_vld) { | |
1695 | iotg->hsm.a_srp_det = 0; | |
1696 | set_host_mode(); | |
1697 | langwell_otg_phy_low_power(1); | |
1698 | iotg->otg.state = OTG_STATE_A_IDLE; | |
1699 | } | |
1700 | break; | |
1701 | default: | |
1702 | ; | |
1703 | } | |
1704 | ||
1705 | dev_dbg(lnw->dev, "%s: new state = %s\n", __func__, | |
1706 | state_string(iotg->otg.state)); | |
1707 | } | |
1708 | ||
1709 | static ssize_t | |
1710 | show_registers(struct device *_dev, struct device_attribute *attr, char *buf) | |
1711 | { | |
1712 | struct langwell_otg *lnw = the_transceiver; | |
1713 | char *next; | |
1714 | unsigned size, t; | |
1715 | ||
1716 | next = buf; | |
1717 | size = PAGE_SIZE; | |
1718 | ||
1719 | t = scnprintf(next, size, | |
1720 | "\n" | |
1721 | "USBCMD = 0x%08x\n" | |
1722 | "USBSTS = 0x%08x\n" | |
1723 | "USBINTR = 0x%08x\n" | |
1724 | "ASYNCLISTADDR = 0x%08x\n" | |
1725 | "PORTSC1 = 0x%08x\n" | |
1726 | "HOSTPC1 = 0x%08x\n" | |
1727 | "OTGSC = 0x%08x\n" | |
1728 | "USBMODE = 0x%08x\n", | |
1729 | readl(lnw->iotg.base + 0x30), | |
1730 | readl(lnw->iotg.base + 0x34), | |
1731 | readl(lnw->iotg.base + 0x38), | |
1732 | readl(lnw->iotg.base + 0x48), | |
1733 | readl(lnw->iotg.base + 0x74), | |
1734 | readl(lnw->iotg.base + 0xb4), | |
1735 | readl(lnw->iotg.base + 0xf4), | |
1736 | readl(lnw->iotg.base + 0xf8) | |
1737 | ); | |
1738 | size -= t; | |
1739 | next += t; | |
1740 | ||
1741 | return PAGE_SIZE - size; | |
1742 | } | |
1743 | static DEVICE_ATTR(registers, S_IRUGO, show_registers, NULL); | |
1744 | ||
1745 | static ssize_t | |
1746 | show_hsm(struct device *_dev, struct device_attribute *attr, char *buf) | |
1747 | { | |
1748 | struct langwell_otg *lnw = the_transceiver; | |
1749 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
1750 | char *next; | |
1751 | unsigned size, t; | |
1752 | ||
1753 | next = buf; | |
1754 | size = PAGE_SIZE; | |
1755 | ||
1756 | if (iotg->otg.host) | |
1757 | iotg->hsm.a_set_b_hnp_en = iotg->otg.host->b_hnp_enable; | |
1758 | ||
1759 | if (iotg->otg.gadget) | |
1760 | iotg->hsm.b_hnp_enable = iotg->otg.gadget->b_hnp_enable; | |
1761 | ||
1762 | t = scnprintf(next, size, | |
1763 | "\n" | |
1764 | "current state = %s\n" | |
1765 | "a_bus_resume = \t%d\n" | |
1766 | "a_bus_suspend = \t%d\n" | |
1767 | "a_conn = \t%d\n" | |
1768 | "a_sess_vld = \t%d\n" | |
1769 | "a_srp_det = \t%d\n" | |
1770 | "a_vbus_vld = \t%d\n" | |
1771 | "b_bus_resume = \t%d\n" | |
1772 | "b_bus_suspend = \t%d\n" | |
1773 | "b_conn = \t%d\n" | |
1774 | "b_se0_srp = \t%d\n" | |
1775 | "b_sess_end = \t%d\n" | |
1776 | "b_sess_vld = \t%d\n" | |
1777 | "id = \t%d\n" | |
1778 | "a_set_b_hnp_en = \t%d\n" | |
1779 | "b_srp_done = \t%d\n" | |
1780 | "b_hnp_enable = \t%d\n" | |
1781 | "a_wait_vrise_tmout = \t%d\n" | |
1782 | "a_wait_bcon_tmout = \t%d\n" | |
1783 | "a_aidl_bdis_tmout = \t%d\n" | |
1784 | "b_ase0_brst_tmout = \t%d\n" | |
1785 | "a_bus_drop = \t%d\n" | |
1786 | "a_bus_req = \t%d\n" | |
1787 | "a_clr_err = \t%d\n" | |
1788 | "a_suspend_req = \t%d\n" | |
1789 | "b_bus_req = \t%d\n" | |
1790 | "b_bus_suspend_tmout = \t%d\n" | |
1791 | "b_bus_suspend_vld = \t%d\n", | |
1792 | state_string(iotg->otg.state), | |
1793 | iotg->hsm.a_bus_resume, | |
1794 | iotg->hsm.a_bus_suspend, | |
1795 | iotg->hsm.a_conn, | |
1796 | iotg->hsm.a_sess_vld, | |
1797 | iotg->hsm.a_srp_det, | |
1798 | iotg->hsm.a_vbus_vld, | |
1799 | iotg->hsm.b_bus_resume, | |
1800 | iotg->hsm.b_bus_suspend, | |
1801 | iotg->hsm.b_conn, | |
1802 | iotg->hsm.b_se0_srp, | |
1803 | iotg->hsm.b_sess_end, | |
1804 | iotg->hsm.b_sess_vld, | |
1805 | iotg->hsm.id, | |
1806 | iotg->hsm.a_set_b_hnp_en, | |
1807 | iotg->hsm.b_srp_done, | |
1808 | iotg->hsm.b_hnp_enable, | |
1809 | iotg->hsm.a_wait_vrise_tmout, | |
1810 | iotg->hsm.a_wait_bcon_tmout, | |
1811 | iotg->hsm.a_aidl_bdis_tmout, | |
1812 | iotg->hsm.b_ase0_brst_tmout, | |
1813 | iotg->hsm.a_bus_drop, | |
1814 | iotg->hsm.a_bus_req, | |
1815 | iotg->hsm.a_clr_err, | |
1816 | iotg->hsm.a_suspend_req, | |
1817 | iotg->hsm.b_bus_req, | |
1818 | iotg->hsm.b_bus_suspend_tmout, | |
1819 | iotg->hsm.b_bus_suspend_vld | |
1820 | ); | |
1821 | size -= t; | |
1822 | next += t; | |
1823 | ||
1824 | return PAGE_SIZE - size; | |
1825 | } | |
1826 | static DEVICE_ATTR(hsm, S_IRUGO, show_hsm, NULL); | |
1827 | ||
1828 | static ssize_t | |
1829 | get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf) | |
1830 | { | |
1831 | struct langwell_otg *lnw = the_transceiver; | |
1832 | char *next; | |
1833 | unsigned size, t; | |
1834 | ||
1835 | next = buf; | |
1836 | size = PAGE_SIZE; | |
1837 | ||
1838 | t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_req); | |
1839 | size -= t; | |
1840 | next += t; | |
1841 | ||
1842 | return PAGE_SIZE - size; | |
1843 | } | |
1844 | ||
1845 | static ssize_t | |
1846 | set_a_bus_req(struct device *dev, struct device_attribute *attr, | |
1847 | const char *buf, size_t count) | |
1848 | { | |
1849 | struct langwell_otg *lnw = the_transceiver; | |
1850 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
1851 | ||
1852 | if (!iotg->otg.default_a) | |
1853 | return -1; | |
1854 | if (count > 2) | |
1855 | return -1; | |
1856 | ||
1857 | if (buf[0] == '0') { | |
1858 | iotg->hsm.a_bus_req = 0; | |
1859 | dev_dbg(lnw->dev, "User request: a_bus_req = 0\n"); | |
1860 | } else if (buf[0] == '1') { | |
1861 | /* If a_bus_drop is TRUE, a_bus_req can't be set */ | |
1862 | if (iotg->hsm.a_bus_drop) | |
1863 | return -1; | |
1864 | iotg->hsm.a_bus_req = 1; | |
1865 | dev_dbg(lnw->dev, "User request: a_bus_req = 1\n"); | |
1866 | } | |
1867 | if (spin_trylock(&lnw->wq_lock)) { | |
1868 | langwell_update_transceiver(); | |
1869 | spin_unlock(&lnw->wq_lock); | |
1870 | } | |
1871 | return count; | |
1872 | } | |
3d965875 | 1873 | static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req); |
f0ae849d HW |
1874 | |
1875 | static ssize_t | |
1876 | get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf) | |
1877 | { | |
1878 | struct langwell_otg *lnw = the_transceiver; | |
1879 | char *next; | |
1880 | unsigned size, t; | |
1881 | ||
1882 | next = buf; | |
1883 | size = PAGE_SIZE; | |
1884 | ||
1885 | t = scnprintf(next, size, "%d", lnw->iotg.hsm.a_bus_drop); | |
1886 | size -= t; | |
1887 | next += t; | |
1888 | ||
1889 | return PAGE_SIZE - size; | |
1890 | } | |
1891 | ||
1892 | static ssize_t | |
1893 | set_a_bus_drop(struct device *dev, struct device_attribute *attr, | |
1894 | const char *buf, size_t count) | |
1895 | { | |
1896 | struct langwell_otg *lnw = the_transceiver; | |
1897 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
1898 | ||
1899 | if (!iotg->otg.default_a) | |
1900 | return -1; | |
1901 | if (count > 2) | |
1902 | return -1; | |
1903 | ||
1904 | if (buf[0] == '0') { | |
1905 | iotg->hsm.a_bus_drop = 0; | |
1906 | dev_dbg(lnw->dev, "User request: a_bus_drop = 0\n"); | |
1907 | } else if (buf[0] == '1') { | |
1908 | iotg->hsm.a_bus_drop = 1; | |
1909 | iotg->hsm.a_bus_req = 0; | |
1910 | dev_dbg(lnw->dev, "User request: a_bus_drop = 1\n"); | |
1911 | dev_dbg(lnw->dev, "User request: and a_bus_req = 0\n"); | |
1912 | } | |
1913 | if (spin_trylock(&lnw->wq_lock)) { | |
1914 | langwell_update_transceiver(); | |
1915 | spin_unlock(&lnw->wq_lock); | |
1916 | } | |
1917 | return count; | |
1918 | } | |
3d965875 | 1919 | static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop, set_a_bus_drop); |
f0ae849d HW |
1920 | |
1921 | static ssize_t | |
1922 | get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf) | |
1923 | { | |
1924 | struct langwell_otg *lnw = the_transceiver; | |
1925 | char *next; | |
1926 | unsigned size, t; | |
1927 | ||
1928 | next = buf; | |
1929 | size = PAGE_SIZE; | |
1930 | ||
1931 | t = scnprintf(next, size, "%d", lnw->iotg.hsm.b_bus_req); | |
1932 | size -= t; | |
1933 | next += t; | |
1934 | ||
1935 | return PAGE_SIZE - size; | |
1936 | } | |
1937 | ||
1938 | static ssize_t | |
1939 | set_b_bus_req(struct device *dev, struct device_attribute *attr, | |
1940 | const char *buf, size_t count) | |
1941 | { | |
1942 | struct langwell_otg *lnw = the_transceiver; | |
1943 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
1944 | ||
1945 | if (iotg->otg.default_a) | |
1946 | return -1; | |
1947 | ||
1948 | if (count > 2) | |
1949 | return -1; | |
1950 | ||
1951 | if (buf[0] == '0') { | |
1952 | iotg->hsm.b_bus_req = 0; | |
1953 | dev_dbg(lnw->dev, "User request: b_bus_req = 0\n"); | |
1954 | } else if (buf[0] == '1') { | |
1955 | iotg->hsm.b_bus_req = 1; | |
1956 | dev_dbg(lnw->dev, "User request: b_bus_req = 1\n"); | |
1957 | } | |
1958 | if (spin_trylock(&lnw->wq_lock)) { | |
1959 | langwell_update_transceiver(); | |
1960 | spin_unlock(&lnw->wq_lock); | |
1961 | } | |
1962 | return count; | |
1963 | } | |
3d965875 | 1964 | static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req); |
f0ae849d HW |
1965 | |
1966 | static ssize_t | |
1967 | set_a_clr_err(struct device *dev, struct device_attribute *attr, | |
1968 | const char *buf, size_t count) | |
1969 | { | |
1970 | struct langwell_otg *lnw = the_transceiver; | |
1971 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
1972 | ||
1973 | if (!iotg->otg.default_a) | |
1974 | return -1; | |
1975 | if (count > 2) | |
1976 | return -1; | |
1977 | ||
1978 | if (buf[0] == '1') { | |
1979 | iotg->hsm.a_clr_err = 1; | |
1980 | dev_dbg(lnw->dev, "User request: a_clr_err = 1\n"); | |
1981 | } | |
1982 | if (spin_trylock(&lnw->wq_lock)) { | |
1983 | langwell_update_transceiver(); | |
1984 | spin_unlock(&lnw->wq_lock); | |
1985 | } | |
1986 | return count; | |
1987 | } | |
3d965875 | 1988 | static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err); |
f0ae849d HW |
1989 | |
1990 | static struct attribute *inputs_attrs[] = { | |
1991 | &dev_attr_a_bus_req.attr, | |
1992 | &dev_attr_a_bus_drop.attr, | |
1993 | &dev_attr_b_bus_req.attr, | |
1994 | &dev_attr_a_clr_err.attr, | |
1995 | NULL, | |
1996 | }; | |
1997 | ||
1998 | static struct attribute_group debug_dev_attr_group = { | |
1999 | .name = "inputs", | |
2000 | .attrs = inputs_attrs, | |
2001 | }; | |
2002 | ||
2003 | static int langwell_otg_probe(struct pci_dev *pdev, | |
2004 | const struct pci_device_id *id) | |
2005 | { | |
2006 | unsigned long resource, len; | |
2007 | void __iomem *base = NULL; | |
2008 | int retval; | |
2009 | u32 val32; | |
2010 | struct langwell_otg *lnw; | |
2011 | char qname[] = "langwell_otg_queue"; | |
2012 | ||
2013 | retval = 0; | |
2014 | dev_dbg(&pdev->dev, "\notg controller is detected.\n"); | |
2015 | if (pci_enable_device(pdev) < 0) { | |
2016 | retval = -ENODEV; | |
2017 | goto done; | |
2018 | } | |
2019 | ||
2020 | lnw = kzalloc(sizeof *lnw, GFP_KERNEL); | |
2021 | if (lnw == NULL) { | |
2022 | retval = -ENOMEM; | |
2023 | goto done; | |
2024 | } | |
2025 | the_transceiver = lnw; | |
2026 | ||
2027 | /* control register: BAR 0 */ | |
2028 | resource = pci_resource_start(pdev, 0); | |
2029 | len = pci_resource_len(pdev, 0); | |
2030 | if (!request_mem_region(resource, len, driver_name)) { | |
2031 | retval = -EBUSY; | |
2032 | goto err; | |
2033 | } | |
2034 | lnw->region = 1; | |
2035 | ||
2036 | base = ioremap_nocache(resource, len); | |
2037 | if (base == NULL) { | |
2038 | retval = -EFAULT; | |
2039 | goto err; | |
2040 | } | |
2041 | lnw->iotg.base = base; | |
2042 | ||
2043 | if (!request_mem_region(USBCFG_ADDR, USBCFG_LEN, driver_name)) { | |
2044 | retval = -EBUSY; | |
2045 | goto err; | |
2046 | } | |
2047 | lnw->cfg_region = 1; | |
2048 | ||
2049 | /* For the SCCB.USBCFG register */ | |
2050 | base = ioremap_nocache(USBCFG_ADDR, USBCFG_LEN); | |
2051 | if (base == NULL) { | |
2052 | retval = -EFAULT; | |
2053 | goto err; | |
2054 | } | |
2055 | lnw->usbcfg = base; | |
2056 | ||
2057 | if (!pdev->irq) { | |
2058 | dev_dbg(&pdev->dev, "No IRQ.\n"); | |
2059 | retval = -ENODEV; | |
2060 | goto err; | |
2061 | } | |
2062 | ||
2063 | lnw->qwork = create_singlethread_workqueue(qname); | |
2064 | if (!lnw->qwork) { | |
2065 | dev_dbg(&pdev->dev, "cannot create workqueue %s\n", qname); | |
2066 | retval = -ENOMEM; | |
2067 | goto err; | |
2068 | } | |
2069 | INIT_WORK(&lnw->work, langwell_otg_work); | |
2070 | ||
2071 | /* OTG common part */ | |
2072 | lnw->dev = &pdev->dev; | |
2073 | lnw->iotg.otg.dev = lnw->dev; | |
2074 | lnw->iotg.otg.label = driver_name; | |
2075 | lnw->iotg.otg.set_host = langwell_otg_set_host; | |
2076 | lnw->iotg.otg.set_peripheral = langwell_otg_set_peripheral; | |
2077 | lnw->iotg.otg.set_power = langwell_otg_set_power; | |
2078 | lnw->iotg.otg.set_vbus = langwell_otg_set_vbus; | |
2079 | lnw->iotg.otg.start_srp = langwell_otg_start_srp; | |
2080 | lnw->iotg.otg.state = OTG_STATE_UNDEFINED; | |
2081 | ||
2082 | if (otg_set_transceiver(&lnw->iotg.otg)) { | |
2083 | dev_dbg(lnw->dev, "can't set transceiver\n"); | |
2084 | retval = -EBUSY; | |
2085 | goto err; | |
2086 | } | |
2087 | ||
2088 | reset_otg(); | |
2089 | init_hsm(); | |
2090 | ||
2091 | spin_lock_init(&lnw->lock); | |
2092 | spin_lock_init(&lnw->wq_lock); | |
2093 | INIT_LIST_HEAD(&active_timers); | |
2094 | retval = langwell_otg_init_timers(&lnw->iotg.hsm); | |
2095 | if (retval) { | |
2096 | dev_dbg(&pdev->dev, "Failed to init timers\n"); | |
2097 | goto err; | |
2098 | } | |
2099 | ||
2100 | init_timer(&lnw->hsm_timer); | |
2101 | ATOMIC_INIT_NOTIFIER_HEAD(&lnw->iotg.iotg_notifier); | |
2102 | ||
2103 | lnw->iotg_notifier.notifier_call = langwell_otg_iotg_notify; | |
2104 | ||
2105 | retval = intel_mid_otg_register_notifier(&lnw->iotg, | |
2106 | &lnw->iotg_notifier); | |
2107 | if (retval) { | |
2108 | dev_dbg(lnw->dev, "Failed to register notifier\n"); | |
2109 | goto err; | |
2110 | } | |
2111 | ||
2112 | if (request_irq(pdev->irq, otg_irq, IRQF_SHARED, | |
2113 | driver_name, lnw) != 0) { | |
2114 | dev_dbg(lnw->dev, "request interrupt %d failed\n", pdev->irq); | |
2115 | retval = -EBUSY; | |
2116 | goto err; | |
2117 | } | |
2118 | ||
2119 | /* enable OTGSC int */ | |
2120 | val32 = OTGSC_DPIE | OTGSC_BSEIE | OTGSC_BSVIE | | |
2121 | OTGSC_ASVIE | OTGSC_AVVIE | OTGSC_IDIE | OTGSC_IDPU; | |
2122 | writel(val32, lnw->iotg.base + CI_OTGSC); | |
2123 | ||
2124 | retval = device_create_file(&pdev->dev, &dev_attr_registers); | |
2125 | if (retval < 0) { | |
2126 | dev_dbg(lnw->dev, | |
2127 | "Can't register sysfs attribute: %d\n", retval); | |
2128 | goto err; | |
2129 | } | |
2130 | ||
2131 | retval = device_create_file(&pdev->dev, &dev_attr_hsm); | |
2132 | if (retval < 0) { | |
2133 | dev_dbg(lnw->dev, "Can't hsm sysfs attribute: %d\n", retval); | |
2134 | goto err; | |
2135 | } | |
2136 | ||
2137 | retval = sysfs_create_group(&pdev->dev.kobj, &debug_dev_attr_group); | |
2138 | if (retval < 0) { | |
2139 | dev_dbg(lnw->dev, | |
2140 | "Can't register sysfs attr group: %d\n", retval); | |
2141 | goto err; | |
2142 | } | |
2143 | ||
2144 | if (lnw->iotg.otg.state == OTG_STATE_A_IDLE) | |
2145 | langwell_update_transceiver(); | |
2146 | ||
2147 | return 0; | |
2148 | ||
2149 | err: | |
2150 | if (the_transceiver) | |
2151 | langwell_otg_remove(pdev); | |
2152 | done: | |
2153 | return retval; | |
2154 | } | |
2155 | ||
2156 | static void langwell_otg_remove(struct pci_dev *pdev) | |
2157 | { | |
2158 | struct langwell_otg *lnw = the_transceiver; | |
2159 | ||
2160 | if (lnw->qwork) { | |
2161 | flush_workqueue(lnw->qwork); | |
2162 | destroy_workqueue(lnw->qwork); | |
2163 | } | |
2164 | intel_mid_otg_unregister_notifier(&lnw->iotg, &lnw->iotg_notifier); | |
2165 | langwell_otg_free_timers(); | |
2166 | ||
2167 | /* disable OTGSC interrupt as OTGSC doesn't change in reset */ | |
2168 | writel(0, lnw->iotg.base + CI_OTGSC); | |
2169 | ||
2170 | if (pdev->irq) | |
2171 | free_irq(pdev->irq, lnw); | |
2172 | if (lnw->usbcfg) | |
2173 | iounmap(lnw->usbcfg); | |
2174 | if (lnw->cfg_region) | |
2175 | release_mem_region(USBCFG_ADDR, USBCFG_LEN); | |
2176 | if (lnw->iotg.base) | |
2177 | iounmap(lnw->iotg.base); | |
2178 | if (lnw->region) | |
2179 | release_mem_region(pci_resource_start(pdev, 0), | |
2180 | pci_resource_len(pdev, 0)); | |
2181 | ||
2182 | otg_set_transceiver(NULL); | |
2183 | pci_disable_device(pdev); | |
2184 | sysfs_remove_group(&pdev->dev.kobj, &debug_dev_attr_group); | |
2185 | device_remove_file(&pdev->dev, &dev_attr_hsm); | |
2186 | device_remove_file(&pdev->dev, &dev_attr_registers); | |
2187 | kfree(lnw); | |
2188 | lnw = NULL; | |
2189 | } | |
2190 | ||
2191 | static void transceiver_suspend(struct pci_dev *pdev) | |
2192 | { | |
2193 | pci_save_state(pdev); | |
2194 | pci_set_power_state(pdev, PCI_D3hot); | |
2195 | langwell_otg_phy_low_power(1); | |
2196 | } | |
2197 | ||
2198 | static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message) | |
2199 | { | |
2200 | struct langwell_otg *lnw = the_transceiver; | |
2201 | struct intel_mid_otg_xceiv *iotg = &lnw->iotg; | |
2202 | int ret = 0; | |
2203 | ||
2204 | /* Disbale OTG interrupts */ | |
2205 | langwell_otg_intr(0); | |
2206 | ||
2207 | if (pdev->irq) | |
2208 | free_irq(pdev->irq, lnw); | |
2209 | ||
2210 | /* Prevent more otg_work */ | |
2211 | flush_workqueue(lnw->qwork); | |
2212 | destroy_workqueue(lnw->qwork); | |
2213 | lnw->qwork = NULL; | |
2214 | ||
2215 | /* start actions */ | |
2216 | switch (iotg->otg.state) { | |
2217 | case OTG_STATE_A_WAIT_VFALL: | |
2218 | iotg->otg.state = OTG_STATE_A_IDLE; | |
2219 | case OTG_STATE_A_IDLE: | |
2220 | case OTG_STATE_B_IDLE: | |
2221 | case OTG_STATE_A_VBUS_ERR: | |
2222 | transceiver_suspend(pdev); | |
2223 | break; | |
2224 | case OTG_STATE_A_WAIT_VRISE: | |
2225 | langwell_otg_del_timer(a_wait_vrise_tmr); | |
2226 | iotg->hsm.a_srp_det = 0; | |
2227 | ||
2228 | /* Turn off VBus */ | |
2229 | iotg->otg.set_vbus(&iotg->otg, false); | |
2230 | iotg->otg.state = OTG_STATE_A_IDLE; | |
2231 | transceiver_suspend(pdev); | |
2232 | break; | |
2233 | case OTG_STATE_A_WAIT_BCON: | |
2234 | del_timer_sync(&lnw->hsm_timer); | |
2235 | if (lnw->iotg.stop_host) | |
2236 | lnw->iotg.stop_host(&lnw->iotg); | |
2237 | else | |
2238 | dev_dbg(&pdev->dev, "host driver has been removed.\n"); | |
2239 | ||
2240 | iotg->hsm.a_srp_det = 0; | |
2241 | ||
2242 | /* Turn off VBus */ | |
2243 | iotg->otg.set_vbus(&iotg->otg, false); | |
2244 | iotg->otg.state = OTG_STATE_A_IDLE; | |
2245 | transceiver_suspend(pdev); | |
2246 | break; | |
2247 | case OTG_STATE_A_HOST: | |
2248 | if (lnw->iotg.stop_host) | |
2249 | lnw->iotg.stop_host(&lnw->iotg); | |
2250 | else | |
2251 | dev_dbg(&pdev->dev, "host driver has been removed.\n"); | |
2252 | ||
2253 | iotg->hsm.a_srp_det = 0; | |
2254 | ||
2255 | /* Turn off VBus */ | |
2256 | iotg->otg.set_vbus(&iotg->otg, false); | |
2257 | ||
2258 | iotg->otg.state = OTG_STATE_A_IDLE; | |
2259 | transceiver_suspend(pdev); | |
2260 | break; | |
2261 | case OTG_STATE_A_SUSPEND: | |
2262 | langwell_otg_del_timer(a_aidl_bdis_tmr); | |
2263 | langwell_otg_HABA(0); | |
2264 | if (lnw->iotg.stop_host) | |
2265 | lnw->iotg.stop_host(&lnw->iotg); | |
2266 | else | |
2267 | dev_dbg(lnw->dev, "host driver has been removed.\n"); | |
2268 | iotg->hsm.a_srp_det = 0; | |
2269 | ||
2270 | /* Turn off VBus */ | |
2271 | iotg->otg.set_vbus(&iotg->otg, false); | |
2272 | iotg->otg.state = OTG_STATE_A_IDLE; | |
2273 | transceiver_suspend(pdev); | |
2274 | break; | |
2275 | case OTG_STATE_A_PERIPHERAL: | |
2276 | del_timer_sync(&lnw->hsm_timer); | |
2277 | ||
2278 | if (lnw->iotg.stop_peripheral) | |
2279 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
2280 | else | |
2281 | dev_dbg(&pdev->dev, | |
2282 | "client driver has been removed.\n"); | |
2283 | iotg->hsm.a_srp_det = 0; | |
2284 | ||
2285 | /* Turn off VBus */ | |
2286 | iotg->otg.set_vbus(&iotg->otg, false); | |
2287 | iotg->otg.state = OTG_STATE_A_IDLE; | |
2288 | transceiver_suspend(pdev); | |
2289 | break; | |
2290 | case OTG_STATE_B_HOST: | |
2291 | if (lnw->iotg.stop_host) | |
2292 | lnw->iotg.stop_host(&lnw->iotg); | |
2293 | else | |
2294 | dev_dbg(&pdev->dev, "host driver has been removed.\n"); | |
2295 | iotg->hsm.b_bus_req = 0; | |
2296 | iotg->otg.state = OTG_STATE_B_IDLE; | |
2297 | transceiver_suspend(pdev); | |
2298 | break; | |
2299 | case OTG_STATE_B_PERIPHERAL: | |
2300 | if (lnw->iotg.stop_peripheral) | |
2301 | lnw->iotg.stop_peripheral(&lnw->iotg); | |
2302 | else | |
2303 | dev_dbg(&pdev->dev, | |
2304 | "client driver has been removed.\n"); | |
2305 | iotg->otg.state = OTG_STATE_B_IDLE; | |
2306 | transceiver_suspend(pdev); | |
2307 | break; | |
2308 | case OTG_STATE_B_WAIT_ACON: | |
2309 | /* delete hsm timer for b_ase0_brst_tmr */ | |
2310 | del_timer_sync(&lnw->hsm_timer); | |
2311 | ||
2312 | langwell_otg_HAAR(0); | |
2313 | ||
2314 | if (lnw->iotg.stop_host) | |
2315 | lnw->iotg.stop_host(&lnw->iotg); | |
2316 | else | |
2317 | dev_dbg(&pdev->dev, "host driver has been removed.\n"); | |
2318 | iotg->hsm.b_bus_req = 0; | |
2319 | iotg->otg.state = OTG_STATE_B_IDLE; | |
2320 | transceiver_suspend(pdev); | |
2321 | break; | |
2322 | default: | |
2323 | dev_dbg(lnw->dev, "error state before suspend\n"); | |
2324 | break; | |
2325 | } | |
2326 | ||
2327 | return ret; | |
2328 | } | |
2329 | ||
2330 | static void transceiver_resume(struct pci_dev *pdev) | |
2331 | { | |
2332 | pci_restore_state(pdev); | |
2333 | pci_set_power_state(pdev, PCI_D0); | |
2334 | } | |
2335 | ||
2336 | static int langwell_otg_resume(struct pci_dev *pdev) | |
2337 | { | |
2338 | struct langwell_otg *lnw = the_transceiver; | |
2339 | int ret = 0; | |
2340 | ||
2341 | transceiver_resume(pdev); | |
2342 | ||
2343 | lnw->qwork = create_singlethread_workqueue("langwell_otg_queue"); | |
2344 | if (!lnw->qwork) { | |
2345 | dev_dbg(&pdev->dev, "cannot create langwell otg workqueuen"); | |
2346 | ret = -ENOMEM; | |
2347 | goto error; | |
2348 | } | |
2349 | ||
2350 | if (request_irq(pdev->irq, otg_irq, IRQF_SHARED, | |
2351 | driver_name, lnw) != 0) { | |
2352 | dev_dbg(&pdev->dev, "request interrupt %d failed\n", pdev->irq); | |
2353 | ret = -EBUSY; | |
2354 | goto error; | |
2355 | } | |
2356 | ||
2357 | /* enable OTG interrupts */ | |
2358 | langwell_otg_intr(1); | |
2359 | ||
2360 | update_hsm(); | |
2361 | ||
2362 | langwell_update_transceiver(); | |
2363 | ||
2364 | return ret; | |
2365 | error: | |
2366 | langwell_otg_intr(0); | |
2367 | transceiver_suspend(pdev); | |
2368 | return ret; | |
2369 | } | |
2370 | ||
2371 | static int __init langwell_otg_init(void) | |
2372 | { | |
2373 | return pci_register_driver(&otg_pci_driver); | |
2374 | } | |
2375 | module_init(langwell_otg_init); | |
2376 | ||
2377 | static void __exit langwell_otg_cleanup(void) | |
2378 | { | |
2379 | pci_unregister_driver(&otg_pci_driver); | |
2380 | } | |
2381 | module_exit(langwell_otg_cleanup); |