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1 | /* |
2 | * Copyright (C) 2011 Marvell International Ltd. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | */ | |
9 | ||
10 | #ifndef __MV_USB_OTG_CONTROLLER__ | |
11 | #define __MV_USB_OTG_CONTROLLER__ | |
12 | ||
13 | #include <linux/types.h> | |
14 | ||
15 | /* Command Register Bit Masks */ | |
16 | #define USBCMD_RUN_STOP (0x00000001) | |
17 | #define USBCMD_CTRL_RESET (0x00000002) | |
18 | ||
19 | /* otgsc Register Bit Masks */ | |
20 | #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 | |
21 | #define OTGSC_CTRL_VUSB_CHARGE 0x00000002 | |
22 | #define OTGSC_CTRL_OTG_TERM 0x00000008 | |
23 | #define OTGSC_CTRL_DATA_PULSING 0x00000010 | |
24 | #define OTGSC_STS_USB_ID 0x00000100 | |
25 | #define OTGSC_STS_A_VBUS_VALID 0x00000200 | |
26 | #define OTGSC_STS_A_SESSION_VALID 0x00000400 | |
27 | #define OTGSC_STS_B_SESSION_VALID 0x00000800 | |
28 | #define OTGSC_STS_B_SESSION_END 0x00001000 | |
29 | #define OTGSC_STS_1MS_TOGGLE 0x00002000 | |
30 | #define OTGSC_STS_DATA_PULSING 0x00004000 | |
31 | #define OTGSC_INTSTS_USB_ID 0x00010000 | |
32 | #define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 | |
33 | #define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 | |
34 | #define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 | |
35 | #define OTGSC_INTSTS_B_SESSION_END 0x00100000 | |
36 | #define OTGSC_INTSTS_1MS 0x00200000 | |
37 | #define OTGSC_INTSTS_DATA_PULSING 0x00400000 | |
38 | #define OTGSC_INTR_USB_ID 0x01000000 | |
39 | #define OTGSC_INTR_A_VBUS_VALID 0x02000000 | |
40 | #define OTGSC_INTR_A_SESSION_VALID 0x04000000 | |
41 | #define OTGSC_INTR_B_SESSION_VALID 0x08000000 | |
42 | #define OTGSC_INTR_B_SESSION_END 0x10000000 | |
43 | #define OTGSC_INTR_1MS_TIMER 0x20000000 | |
44 | #define OTGSC_INTR_DATA_PULSING 0x40000000 | |
45 | ||
46 | #define CAPLENGTH_MASK (0xff) | |
47 | ||
48 | /* Timer's interval, unit 10ms */ | |
49 | #define T_A_WAIT_VRISE 100 | |
50 | #define T_A_WAIT_BCON 2000 | |
51 | #define T_A_AIDL_BDIS 100 | |
52 | #define T_A_BIDL_ADIS 20 | |
53 | #define T_B_ASE0_BRST 400 | |
54 | #define T_B_SE0_SRP 300 | |
55 | #define T_B_SRP_FAIL 2000 | |
56 | #define T_B_DATA_PLS 10 | |
57 | #define T_B_SRP_INIT 100 | |
58 | #define T_A_SRP_RSPNS 10 | |
59 | #define T_A_DRV_RSM 5 | |
60 | ||
61 | enum otg_function { | |
62 | OTG_B_DEVICE = 0, | |
63 | OTG_A_DEVICE | |
64 | }; | |
65 | ||
66 | enum mv_otg_timer { | |
67 | A_WAIT_BCON_TIMER = 0, | |
68 | OTG_TIMER_NUM | |
69 | }; | |
70 | ||
71 | /* PXA OTG state machine */ | |
72 | struct mv_otg_ctrl { | |
73 | /* internal variables */ | |
74 | u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */ | |
75 | u8 b_srp_done; | |
76 | u8 b_hnp_en; | |
77 | ||
78 | /* OTG inputs */ | |
79 | u8 a_bus_drop; | |
80 | u8 a_bus_req; | |
81 | u8 a_clr_err; | |
82 | u8 a_bus_resume; | |
83 | u8 a_bus_suspend; | |
84 | u8 a_conn; | |
85 | u8 a_sess_vld; | |
86 | u8 a_srp_det; | |
87 | u8 a_vbus_vld; | |
88 | u8 b_bus_req; /* B-Device Require Bus */ | |
89 | u8 b_bus_resume; | |
90 | u8 b_bus_suspend; | |
91 | u8 b_conn; | |
92 | u8 b_se0_srp; | |
93 | u8 b_sess_end; | |
94 | u8 b_sess_vld; | |
95 | u8 id; | |
96 | u8 a_suspend_req; | |
97 | ||
98 | /*Timer event */ | |
99 | u8 a_aidl_bdis_timeout; | |
100 | u8 b_ase0_brst_timeout; | |
101 | u8 a_bidl_adis_timeout; | |
102 | u8 a_wait_bcon_timeout; | |
103 | ||
104 | struct timer_list timer[OTG_TIMER_NUM]; | |
105 | }; | |
106 | ||
107 | #define VUSBHS_MAX_PORTS 8 | |
108 | ||
109 | struct mv_otg_regs { | |
110 | u32 usbcmd; /* Command register */ | |
111 | u32 usbsts; /* Status register */ | |
112 | u32 usbintr; /* Interrupt enable */ | |
113 | u32 frindex; /* Frame index */ | |
114 | u32 reserved1[1]; | |
115 | u32 deviceaddr; /* Device Address */ | |
116 | u32 eplistaddr; /* Endpoint List Address */ | |
117 | u32 ttctrl; /* HOST TT status and control */ | |
118 | u32 burstsize; /* Programmable Burst Size */ | |
119 | u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */ | |
120 | u32 reserved[4]; | |
121 | u32 epnak; /* Endpoint NAK */ | |
122 | u32 epnaken; /* Endpoint NAK Enable */ | |
123 | u32 configflag; /* Configured Flag register */ | |
124 | u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */ | |
125 | u32 otgsc; | |
126 | u32 usbmode; /* USB Host/Device mode */ | |
127 | u32 epsetupstat; /* Endpoint Setup Status */ | |
128 | u32 epprime; /* Endpoint Initialize */ | |
129 | u32 epflush; /* Endpoint De-initialize */ | |
130 | u32 epstatus; /* Endpoint Status */ | |
131 | u32 epcomplete; /* Endpoint Interrupt On Complete */ | |
132 | u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */ | |
133 | u32 mcr; /* Mux Control */ | |
134 | u32 isr; /* Interrupt Status */ | |
135 | u32 ier; /* Interrupt Enable */ | |
136 | }; | |
137 | ||
138 | struct mv_otg { | |
b1c711d6 | 139 | struct usb_phy phy; |
277164f0 NZ |
140 | struct mv_otg_ctrl otg_ctrl; |
141 | ||
142 | /* base address */ | |
143 | void __iomem *phy_regs; | |
144 | void __iomem *cap_regs; | |
145 | struct mv_otg_regs __iomem *op_regs; | |
146 | ||
147 | struct platform_device *pdev; | |
148 | int irq; | |
149 | u32 irq_status; | |
150 | u32 irq_en; | |
151 | ||
152 | struct delayed_work work; | |
153 | struct workqueue_struct *qwork; | |
154 | ||
155 | spinlock_t wq_lock; | |
156 | ||
157 | struct mv_usb_platform_data *pdata; | |
158 | ||
159 | unsigned int active; | |
160 | unsigned int clock_gating; | |
161 | unsigned int clknum; | |
162 | struct clk *clk[0]; | |
163 | }; | |
164 | ||
165 | #endif |