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9ebd9616 DB |
1 | /* |
2 | * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller | |
3 | * | |
4 | * Copyright (C) 2004-2007 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * Current status: | |
23 | * - HS USB ULPI mode works. | |
24 | * - 3-pin mode support may be added in future. | |
25 | */ | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/workqueue.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/usb/otg.h> | |
b07682b6 | 36 | #include <linux/i2c/twl.h> |
66760169 JH |
37 | #include <linux/regulator/consumer.h> |
38 | #include <linux/err.h> | |
d1b5b5c0 | 39 | #include <linux/notifier.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
9ebd9616 DB |
41 | |
42 | /* Register defines */ | |
43 | ||
44 | #define VENDOR_ID_LO 0x00 | |
45 | #define VENDOR_ID_HI 0x01 | |
46 | #define PRODUCT_ID_LO 0x02 | |
47 | #define PRODUCT_ID_HI 0x03 | |
48 | ||
49 | #define FUNC_CTRL 0x04 | |
50 | #define FUNC_CTRL_SET 0x05 | |
51 | #define FUNC_CTRL_CLR 0x06 | |
52 | #define FUNC_CTRL_SUSPENDM (1 << 6) | |
53 | #define FUNC_CTRL_RESET (1 << 5) | |
54 | #define FUNC_CTRL_OPMODE_MASK (3 << 3) /* bits 3 and 4 */ | |
55 | #define FUNC_CTRL_OPMODE_NORMAL (0 << 3) | |
56 | #define FUNC_CTRL_OPMODE_NONDRIVING (1 << 3) | |
57 | #define FUNC_CTRL_OPMODE_DISABLE_BIT_NRZI (2 << 3) | |
58 | #define FUNC_CTRL_TERMSELECT (1 << 2) | |
59 | #define FUNC_CTRL_XCVRSELECT_MASK (3 << 0) /* bits 0 and 1 */ | |
60 | #define FUNC_CTRL_XCVRSELECT_HS (0 << 0) | |
61 | #define FUNC_CTRL_XCVRSELECT_FS (1 << 0) | |
62 | #define FUNC_CTRL_XCVRSELECT_LS (2 << 0) | |
63 | #define FUNC_CTRL_XCVRSELECT_FS4LS (3 << 0) | |
64 | ||
65 | #define IFC_CTRL 0x07 | |
66 | #define IFC_CTRL_SET 0x08 | |
67 | #define IFC_CTRL_CLR 0x09 | |
68 | #define IFC_CTRL_INTERFACE_PROTECT_DISABLE (1 << 7) | |
69 | #define IFC_CTRL_AUTORESUME (1 << 4) | |
70 | #define IFC_CTRL_CLOCKSUSPENDM (1 << 3) | |
71 | #define IFC_CTRL_CARKITMODE (1 << 2) | |
72 | #define IFC_CTRL_FSLSSERIALMODE_3PIN (1 << 1) | |
73 | ||
74 | #define TWL4030_OTG_CTRL 0x0A | |
75 | #define TWL4030_OTG_CTRL_SET 0x0B | |
76 | #define TWL4030_OTG_CTRL_CLR 0x0C | |
77 | #define TWL4030_OTG_CTRL_DRVVBUS (1 << 5) | |
78 | #define TWL4030_OTG_CTRL_CHRGVBUS (1 << 4) | |
79 | #define TWL4030_OTG_CTRL_DISCHRGVBUS (1 << 3) | |
80 | #define TWL4030_OTG_CTRL_DMPULLDOWN (1 << 2) | |
81 | #define TWL4030_OTG_CTRL_DPPULLDOWN (1 << 1) | |
82 | #define TWL4030_OTG_CTRL_IDPULLUP (1 << 0) | |
83 | ||
84 | #define USB_INT_EN_RISE 0x0D | |
85 | #define USB_INT_EN_RISE_SET 0x0E | |
86 | #define USB_INT_EN_RISE_CLR 0x0F | |
87 | #define USB_INT_EN_FALL 0x10 | |
88 | #define USB_INT_EN_FALL_SET 0x11 | |
89 | #define USB_INT_EN_FALL_CLR 0x12 | |
90 | #define USB_INT_STS 0x13 | |
91 | #define USB_INT_LATCH 0x14 | |
92 | #define USB_INT_IDGND (1 << 4) | |
93 | #define USB_INT_SESSEND (1 << 3) | |
94 | #define USB_INT_SESSVALID (1 << 2) | |
95 | #define USB_INT_VBUSVALID (1 << 1) | |
96 | #define USB_INT_HOSTDISCONNECT (1 << 0) | |
97 | ||
98 | #define CARKIT_CTRL 0x19 | |
99 | #define CARKIT_CTRL_SET 0x1A | |
100 | #define CARKIT_CTRL_CLR 0x1B | |
101 | #define CARKIT_CTRL_MICEN (1 << 6) | |
102 | #define CARKIT_CTRL_SPKRIGHTEN (1 << 5) | |
103 | #define CARKIT_CTRL_SPKLEFTEN (1 << 4) | |
104 | #define CARKIT_CTRL_RXDEN (1 << 3) | |
105 | #define CARKIT_CTRL_TXDEN (1 << 2) | |
106 | #define CARKIT_CTRL_IDGNDDRV (1 << 1) | |
107 | #define CARKIT_CTRL_CARKITPWR (1 << 0) | |
108 | #define CARKIT_PLS_CTRL 0x22 | |
109 | #define CARKIT_PLS_CTRL_SET 0x23 | |
110 | #define CARKIT_PLS_CTRL_CLR 0x24 | |
111 | #define CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN (1 << 3) | |
112 | #define CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2) | |
113 | #define CARKIT_PLS_CTRL_RXPLSEN (1 << 1) | |
114 | #define CARKIT_PLS_CTRL_TXPLSEN (1 << 0) | |
115 | ||
116 | #define MCPC_CTRL 0x30 | |
117 | #define MCPC_CTRL_SET 0x31 | |
118 | #define MCPC_CTRL_CLR 0x32 | |
119 | #define MCPC_CTRL_RTSOL (1 << 7) | |
120 | #define MCPC_CTRL_EXTSWR (1 << 6) | |
121 | #define MCPC_CTRL_EXTSWC (1 << 5) | |
122 | #define MCPC_CTRL_VOICESW (1 << 4) | |
123 | #define MCPC_CTRL_OUT64K (1 << 3) | |
124 | #define MCPC_CTRL_RTSCTSSW (1 << 2) | |
125 | #define MCPC_CTRL_HS_UART (1 << 0) | |
126 | ||
127 | #define MCPC_IO_CTRL 0x33 | |
128 | #define MCPC_IO_CTRL_SET 0x34 | |
129 | #define MCPC_IO_CTRL_CLR 0x35 | |
130 | #define MCPC_IO_CTRL_MICBIASEN (1 << 5) | |
131 | #define MCPC_IO_CTRL_CTS_NPU (1 << 4) | |
132 | #define MCPC_IO_CTRL_RXD_PU (1 << 3) | |
133 | #define MCPC_IO_CTRL_TXDTYP (1 << 2) | |
134 | #define MCPC_IO_CTRL_CTSTYP (1 << 1) | |
135 | #define MCPC_IO_CTRL_RTSTYP (1 << 0) | |
136 | ||
137 | #define MCPC_CTRL2 0x36 | |
138 | #define MCPC_CTRL2_SET 0x37 | |
139 | #define MCPC_CTRL2_CLR 0x38 | |
140 | #define MCPC_CTRL2_MCPC_CK_EN (1 << 0) | |
141 | ||
142 | #define OTHER_FUNC_CTRL 0x80 | |
143 | #define OTHER_FUNC_CTRL_SET 0x81 | |
144 | #define OTHER_FUNC_CTRL_CLR 0x82 | |
145 | #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4) | |
146 | #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2) | |
147 | ||
148 | #define OTHER_IFC_CTRL 0x83 | |
149 | #define OTHER_IFC_CTRL_SET 0x84 | |
150 | #define OTHER_IFC_CTRL_CLR 0x85 | |
151 | #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6) | |
152 | #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5) | |
153 | #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4) | |
154 | #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3) | |
155 | #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2) | |
156 | #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0) | |
157 | ||
158 | #define OTHER_INT_EN_RISE 0x86 | |
159 | #define OTHER_INT_EN_RISE_SET 0x87 | |
160 | #define OTHER_INT_EN_RISE_CLR 0x88 | |
161 | #define OTHER_INT_EN_FALL 0x89 | |
162 | #define OTHER_INT_EN_FALL_SET 0x8A | |
163 | #define OTHER_INT_EN_FALL_CLR 0x8B | |
164 | #define OTHER_INT_STS 0x8C | |
165 | #define OTHER_INT_LATCH 0x8D | |
166 | #define OTHER_INT_VB_SESS_VLD (1 << 7) | |
167 | #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */ | |
168 | #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */ | |
169 | #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */ | |
170 | #define OTHER_INT_MANU (1 << 1) | |
171 | #define OTHER_INT_ABNORMAL_STRESS (1 << 0) | |
172 | ||
173 | #define ID_STATUS 0x96 | |
174 | #define ID_RES_FLOAT (1 << 4) | |
175 | #define ID_RES_440K (1 << 3) | |
176 | #define ID_RES_200K (1 << 2) | |
177 | #define ID_RES_102K (1 << 1) | |
178 | #define ID_RES_GND (1 << 0) | |
179 | ||
180 | #define POWER_CTRL 0xAC | |
181 | #define POWER_CTRL_SET 0xAD | |
182 | #define POWER_CTRL_CLR 0xAE | |
183 | #define POWER_CTRL_OTG_ENAB (1 << 5) | |
184 | ||
185 | #define OTHER_IFC_CTRL2 0xAF | |
186 | #define OTHER_IFC_CTRL2_SET 0xB0 | |
187 | #define OTHER_IFC_CTRL2_CLR 0xB1 | |
188 | #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4) | |
189 | #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3) | |
190 | #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2) | |
191 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */ | |
192 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0) | |
193 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0) | |
194 | ||
195 | #define REG_CTRL_EN 0xB2 | |
196 | #define REG_CTRL_EN_SET 0xB3 | |
197 | #define REG_CTRL_EN_CLR 0xB4 | |
198 | #define REG_CTRL_ERROR 0xB5 | |
199 | #define ULPI_I2C_CONFLICT_INTEN (1 << 0) | |
200 | ||
201 | #define OTHER_FUNC_CTRL2 0xB8 | |
202 | #define OTHER_FUNC_CTRL2_SET 0xB9 | |
203 | #define OTHER_FUNC_CTRL2_CLR 0xBA | |
204 | #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0) | |
205 | ||
206 | /* following registers do not have separate _clr and _set registers */ | |
207 | #define VBUS_DEBOUNCE 0xC0 | |
208 | #define ID_DEBOUNCE 0xC1 | |
209 | #define VBAT_TIMER 0xD3 | |
210 | #define PHY_PWR_CTRL 0xFD | |
211 | #define PHY_PWR_PHYPWD (1 << 0) | |
212 | #define PHY_CLK_CTRL 0xFE | |
213 | #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2) | |
214 | #define PHY_CLK_CTRL_CLK32K_EN (1 << 1) | |
215 | #define REQ_PHY_DPLL_CLK (1 << 0) | |
216 | #define PHY_CLK_CTRL_STS 0xFF | |
217 | #define PHY_DPLL_CLK (1 << 0) | |
218 | ||
219 | /* In module TWL4030_MODULE_PM_MASTER */ | |
220 | #define PROTECT_KEY 0x0E | |
def6f8b9 | 221 | #define STS_HW_CONDITIONS 0x0F |
9ebd9616 DB |
222 | |
223 | /* In module TWL4030_MODULE_PM_RECEIVER */ | |
224 | #define VUSB_DEDICATED1 0x7D | |
225 | #define VUSB_DEDICATED2 0x7E | |
226 | #define VUSB1V5_DEV_GRP 0x71 | |
227 | #define VUSB1V5_TYPE 0x72 | |
228 | #define VUSB1V5_REMAP 0x73 | |
229 | #define VUSB1V8_DEV_GRP 0x74 | |
230 | #define VUSB1V8_TYPE 0x75 | |
231 | #define VUSB1V8_REMAP 0x76 | |
232 | #define VUSB3V1_DEV_GRP 0x77 | |
233 | #define VUSB3V1_TYPE 0x78 | |
234 | #define VUSB3V1_REMAP 0x79 | |
235 | ||
236 | /* In module TWL4030_MODULE_INTBR */ | |
237 | #define PMBR1 0x0D | |
238 | #define GPIO_USB_4PIN_ULPI_2430C (3 << 0) | |
239 | ||
9ebd9616 DB |
240 | struct twl4030_usb { |
241 | struct otg_transceiver otg; | |
242 | struct device *dev; | |
243 | ||
66760169 JH |
244 | /* TWL4030 internal USB regulator supplies */ |
245 | struct regulator *usb1v5; | |
246 | struct regulator *usb1v8; | |
247 | struct regulator *usb3v1; | |
248 | ||
9ebd9616 DB |
249 | /* for vbus reporting with irqs disabled */ |
250 | spinlock_t lock; | |
251 | ||
252 | /* pin configuration */ | |
253 | enum twl4030_usb_mode usb_mode; | |
254 | ||
255 | int irq; | |
256 | u8 linkstat; | |
257 | u8 asleep; | |
258 | bool irq_enabled; | |
259 | }; | |
260 | ||
261 | /* internal define on top of container_of */ | |
262 | #define xceiv_to_twl(x) container_of((x), struct twl4030_usb, otg); | |
263 | ||
264 | /*-------------------------------------------------------------------------*/ | |
265 | ||
266 | static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl, | |
267 | u8 module, u8 data, u8 address) | |
268 | { | |
269 | u8 check; | |
270 | ||
fc7b92fc B |
271 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
272 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
273 | (check == data)) |
274 | return 0; | |
275 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
276 | 1, module, address, check, data); | |
277 | ||
278 | /* Failed once: Try again */ | |
fc7b92fc B |
279 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
280 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
281 | (check == data)) |
282 | return 0; | |
283 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
284 | 2, module, address, check, data); | |
285 | ||
286 | /* Failed again: Return error */ | |
287 | return -EBUSY; | |
288 | } | |
289 | ||
290 | #define twl4030_usb_write_verify(twl, address, data) \ | |
291 | twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address)) | |
292 | ||
293 | static inline int twl4030_usb_write(struct twl4030_usb *twl, | |
294 | u8 address, u8 data) | |
295 | { | |
296 | int ret = 0; | |
297 | ||
fc7b92fc | 298 | ret = twl_i2c_write_u8(TWL4030_MODULE_USB, data, address); |
9ebd9616 DB |
299 | if (ret < 0) |
300 | dev_dbg(twl->dev, | |
301 | "TWL4030:USB:Write[0x%x] Error %d\n", address, ret); | |
302 | return ret; | |
303 | } | |
304 | ||
305 | static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address) | |
306 | { | |
307 | u8 data; | |
308 | int ret = 0; | |
309 | ||
fc7b92fc | 310 | ret = twl_i2c_read_u8(module, &data, address); |
9ebd9616 DB |
311 | if (ret >= 0) |
312 | ret = data; | |
313 | else | |
314 | dev_dbg(twl->dev, | |
315 | "TWL4030:readb[0x%x,0x%x] Error %d\n", | |
316 | module, address, ret); | |
317 | ||
318 | return ret; | |
319 | } | |
320 | ||
321 | static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address) | |
322 | { | |
323 | return twl4030_readb(twl, TWL4030_MODULE_USB, address); | |
324 | } | |
325 | ||
326 | /*-------------------------------------------------------------------------*/ | |
327 | ||
328 | static inline int | |
329 | twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
330 | { | |
331 | return twl4030_usb_write(twl, reg + 1, bits); | |
332 | } | |
333 | ||
334 | static inline int | |
335 | twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
336 | { | |
337 | return twl4030_usb_write(twl, reg + 2, bits); | |
338 | } | |
339 | ||
340 | /*-------------------------------------------------------------------------*/ | |
341 | ||
d1b5b5c0 | 342 | static enum usb_xceiv_events twl4030_usb_linkstat(struct twl4030_usb *twl) |
9ebd9616 DB |
343 | { |
344 | int status; | |
d1b5b5c0 | 345 | int linkstat = USB_EVENT_NONE; |
9ebd9616 | 346 | |
def6f8b9 DB |
347 | /* |
348 | * For ID/VBUS sensing, see manual section 15.4.8 ... | |
349 | * except when using only battery backup power, two | |
350 | * comparators produce VBUS_PRES and ID_PRES signals, | |
351 | * which don't match docs elsewhere. But ... BIT(7) | |
352 | * and BIT(2) of STS_HW_CONDITIONS, respectively, do | |
353 | * seem to match up. If either is true the USB_PRES | |
354 | * signal is active, the OTG module is activated, and | |
355 | * its interrupt may be raised (may wake the system). | |
356 | */ | |
357 | status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER, | |
358 | STS_HW_CONDITIONS); | |
9ebd9616 DB |
359 | if (status < 0) |
360 | dev_err(twl->dev, "USB link status err %d\n", status); | |
def6f8b9 DB |
361 | else if (status & (BIT(7) | BIT(2))) { |
362 | if (status & BIT(2)) | |
d1b5b5c0 | 363 | linkstat = USB_EVENT_ID; |
def6f8b9 | 364 | else |
d1b5b5c0 | 365 | linkstat = USB_EVENT_VBUS; |
def6f8b9 | 366 | } else |
d1b5b5c0 | 367 | linkstat = USB_EVENT_NONE; |
9ebd9616 DB |
368 | |
369 | dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n", | |
370 | status, status, linkstat); | |
371 | ||
372 | /* REVISIT this assumes host and peripheral controllers | |
373 | * are registered, and that both are active... | |
374 | */ | |
375 | ||
376 | spin_lock_irq(&twl->lock); | |
377 | twl->linkstat = linkstat; | |
d1b5b5c0 | 378 | if (linkstat == USB_EVENT_ID) { |
9ebd9616 DB |
379 | twl->otg.default_a = true; |
380 | twl->otg.state = OTG_STATE_A_IDLE; | |
381 | } else { | |
382 | twl->otg.default_a = false; | |
383 | twl->otg.state = OTG_STATE_B_IDLE; | |
384 | } | |
385 | spin_unlock_irq(&twl->lock); | |
386 | ||
387 | return linkstat; | |
388 | } | |
389 | ||
390 | static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode) | |
391 | { | |
392 | twl->usb_mode = mode; | |
393 | ||
394 | switch (mode) { | |
395 | case T2_USB_MODE_ULPI: | |
396 | twl4030_usb_clear_bits(twl, IFC_CTRL, IFC_CTRL_CARKITMODE); | |
397 | twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); | |
398 | twl4030_usb_clear_bits(twl, FUNC_CTRL, | |
399 | FUNC_CTRL_XCVRSELECT_MASK | | |
400 | FUNC_CTRL_OPMODE_MASK); | |
401 | break; | |
402 | case -1: | |
403 | /* FIXME: power on defaults */ | |
404 | break; | |
405 | default: | |
406 | dev_err(twl->dev, "unsupported T2 transceiver mode %d\n", | |
407 | mode); | |
408 | break; | |
409 | }; | |
410 | } | |
411 | ||
412 | static void twl4030_i2c_access(struct twl4030_usb *twl, int on) | |
413 | { | |
414 | unsigned long timeout; | |
415 | int val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
416 | ||
417 | if (val >= 0) { | |
418 | if (on) { | |
419 | /* enable DPLL to access PHY registers over I2C */ | |
420 | val |= REQ_PHY_DPLL_CLK; | |
421 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
422 | (u8)val) < 0); | |
423 | ||
424 | timeout = jiffies + HZ; | |
425 | while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
426 | PHY_DPLL_CLK) | |
427 | && time_before(jiffies, timeout)) | |
428 | udelay(10); | |
429 | if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
430 | PHY_DPLL_CLK)) | |
431 | dev_err(twl->dev, "Timeout setting T2 HSUSB " | |
432 | "PHY DPLL clock\n"); | |
433 | } else { | |
434 | /* let ULPI control the DPLL clock */ | |
435 | val &= ~REQ_PHY_DPLL_CLK; | |
436 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
437 | (u8)val) < 0); | |
438 | } | |
439 | } | |
440 | } | |
441 | ||
442 | static void twl4030_phy_power(struct twl4030_usb *twl, int on) | |
443 | { | |
444 | u8 pwr; | |
445 | ||
446 | pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); | |
447 | if (on) { | |
66760169 JH |
448 | regulator_enable(twl->usb3v1); |
449 | regulator_enable(twl->usb1v8); | |
450 | /* | |
451 | * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP | |
452 | * in twl4030) resets the VUSB_DEDICATED2 register. This reset | |
453 | * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to | |
454 | * SLEEP. We work around this by clearing the bit after usv3v1 | |
455 | * is re-activated. This ensures that VUSB3V1 is really active. | |
456 | */ | |
fc7b92fc | 457 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, |
66760169 JH |
458 | VUSB_DEDICATED2); |
459 | regulator_enable(twl->usb1v5); | |
9ebd9616 DB |
460 | pwr &= ~PHY_PWR_PHYPWD; |
461 | WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); | |
462 | twl4030_usb_write(twl, PHY_CLK_CTRL, | |
463 | twl4030_usb_read(twl, PHY_CLK_CTRL) | | |
464 | (PHY_CLK_CTRL_CLOCKGATING_EN | | |
465 | PHY_CLK_CTRL_CLK32K_EN)); | |
466 | } else { | |
467 | pwr |= PHY_PWR_PHYPWD; | |
468 | WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); | |
66760169 JH |
469 | regulator_disable(twl->usb1v5); |
470 | regulator_disable(twl->usb1v8); | |
471 | regulator_disable(twl->usb3v1); | |
9ebd9616 DB |
472 | } |
473 | } | |
474 | ||
475 | static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off) | |
476 | { | |
477 | if (twl->asleep) | |
478 | return; | |
479 | ||
480 | twl4030_phy_power(twl, 0); | |
481 | twl->asleep = 1; | |
482 | } | |
483 | ||
484 | static void twl4030_phy_resume(struct twl4030_usb *twl) | |
485 | { | |
486 | if (!twl->asleep) | |
487 | return; | |
488 | ||
489 | twl4030_phy_power(twl, 1); | |
490 | twl4030_i2c_access(twl, 1); | |
491 | twl4030_usb_set_mode(twl, twl->usb_mode); | |
492 | if (twl->usb_mode == T2_USB_MODE_ULPI) | |
493 | twl4030_i2c_access(twl, 0); | |
494 | twl->asleep = 0; | |
495 | } | |
496 | ||
66760169 | 497 | static int twl4030_usb_ldo_init(struct twl4030_usb *twl) |
9ebd9616 DB |
498 | { |
499 | /* Enable writing to power configuration registers */ | |
fc7b92fc B |
500 | twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0xC0, PROTECT_KEY); |
501 | twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x0C, PROTECT_KEY); | |
9ebd9616 DB |
502 | |
503 | /* put VUSB3V1 LDO in active state */ | |
fc7b92fc | 504 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); |
9ebd9616 DB |
505 | |
506 | /* input to VUSB3V1 LDO is from VBAT, not VBUS */ | |
fc7b92fc | 507 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1); |
9ebd9616 | 508 | |
66760169 | 509 | /* Initialize 3.1V regulator */ |
fc7b92fc | 510 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP); |
66760169 JH |
511 | |
512 | twl->usb3v1 = regulator_get(twl->dev, "usb3v1"); | |
513 | if (IS_ERR(twl->usb3v1)) | |
514 | return -ENODEV; | |
515 | ||
fc7b92fc | 516 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE); |
9ebd9616 | 517 | |
66760169 | 518 | /* Initialize 1.5V regulator */ |
fc7b92fc | 519 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP); |
66760169 JH |
520 | |
521 | twl->usb1v5 = regulator_get(twl->dev, "usb1v5"); | |
522 | if (IS_ERR(twl->usb1v5)) | |
523 | goto fail1; | |
524 | ||
fc7b92fc | 525 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE); |
9ebd9616 | 526 | |
66760169 | 527 | /* Initialize 1.8V regulator */ |
fc7b92fc | 528 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP); |
66760169 JH |
529 | |
530 | twl->usb1v8 = regulator_get(twl->dev, "usb1v8"); | |
531 | if (IS_ERR(twl->usb1v8)) | |
532 | goto fail2; | |
533 | ||
fc7b92fc | 534 | twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE); |
9ebd9616 DB |
535 | |
536 | /* disable access to power configuration registers */ | |
fc7b92fc | 537 | twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, PROTECT_KEY); |
66760169 JH |
538 | |
539 | return 0; | |
540 | ||
541 | fail2: | |
542 | regulator_put(twl->usb1v5); | |
543 | twl->usb1v5 = NULL; | |
544 | fail1: | |
545 | regulator_put(twl->usb3v1); | |
546 | twl->usb3v1 = NULL; | |
547 | return -ENODEV; | |
9ebd9616 DB |
548 | } |
549 | ||
550 | static ssize_t twl4030_usb_vbus_show(struct device *dev, | |
551 | struct device_attribute *attr, char *buf) | |
552 | { | |
553 | struct twl4030_usb *twl = dev_get_drvdata(dev); | |
554 | unsigned long flags; | |
555 | int ret = -EINVAL; | |
556 | ||
557 | spin_lock_irqsave(&twl->lock, flags); | |
558 | ret = sprintf(buf, "%s\n", | |
d1b5b5c0 | 559 | (twl->linkstat == USB_EVENT_VBUS) ? "on" : "off"); |
9ebd9616 DB |
560 | spin_unlock_irqrestore(&twl->lock, flags); |
561 | ||
562 | return ret; | |
563 | } | |
564 | static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL); | |
565 | ||
566 | static irqreturn_t twl4030_usb_irq(int irq, void *_twl) | |
567 | { | |
568 | struct twl4030_usb *twl = _twl; | |
569 | int status; | |
570 | ||
9ebd9616 | 571 | status = twl4030_usb_linkstat(twl); |
d1b5b5c0 | 572 | if (status >= 0) { |
9ebd9616 DB |
573 | /* FIXME add a set_power() method so that B-devices can |
574 | * configure the charger appropriately. It's not always | |
575 | * correct to consume VBUS power, and how much current to | |
576 | * consume is a function of the USB configuration chosen | |
577 | * by the host. | |
578 | * | |
579 | * REVISIT usb_gadget_vbus_connect(...) as needed, ditto | |
580 | * its disconnect() sibling, when changing to/from the | |
581 | * USB_LINK_VBUS state. musb_hdrc won't care until it | |
582 | * starts to handle softconnect right. | |
583 | */ | |
d1b5b5c0 | 584 | if (status == USB_EVENT_NONE) |
9ebd9616 DB |
585 | twl4030_phy_suspend(twl, 0); |
586 | else | |
587 | twl4030_phy_resume(twl); | |
be30fc4b | 588 | |
d1b5b5c0 FB |
589 | blocking_notifier_call_chain(&twl->otg.notifier, status, |
590 | twl->otg.gadget); | |
9ebd9616 DB |
591 | } |
592 | sysfs_notify(&twl->dev->kobj, NULL, "vbus"); | |
593 | ||
594 | return IRQ_HANDLED; | |
595 | } | |
596 | ||
597 | static int twl4030_set_suspend(struct otg_transceiver *x, int suspend) | |
598 | { | |
599 | struct twl4030_usb *twl = xceiv_to_twl(x); | |
600 | ||
601 | if (suspend) | |
602 | twl4030_phy_suspend(twl, 1); | |
603 | else | |
604 | twl4030_phy_resume(twl); | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | static int twl4030_set_peripheral(struct otg_transceiver *x, | |
610 | struct usb_gadget *gadget) | |
611 | { | |
612 | struct twl4030_usb *twl; | |
613 | ||
614 | if (!x) | |
615 | return -ENODEV; | |
616 | ||
617 | twl = xceiv_to_twl(x); | |
618 | twl->otg.gadget = gadget; | |
619 | if (!gadget) | |
620 | twl->otg.state = OTG_STATE_UNDEFINED; | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
625 | static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host) | |
626 | { | |
627 | struct twl4030_usb *twl; | |
628 | ||
629 | if (!x) | |
630 | return -ENODEV; | |
631 | ||
632 | twl = xceiv_to_twl(x); | |
633 | twl->otg.host = host; | |
634 | if (!host) | |
635 | twl->otg.state = OTG_STATE_UNDEFINED; | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
d8b175e7 | 640 | static int __devinit twl4030_usb_probe(struct platform_device *pdev) |
9ebd9616 DB |
641 | { |
642 | struct twl4030_usb_data *pdata = pdev->dev.platform_data; | |
643 | struct twl4030_usb *twl; | |
66760169 | 644 | int status, err; |
9ebd9616 DB |
645 | |
646 | if (!pdata) { | |
647 | dev_dbg(&pdev->dev, "platform_data not available\n"); | |
648 | return -EINVAL; | |
649 | } | |
650 | ||
651 | twl = kzalloc(sizeof *twl, GFP_KERNEL); | |
652 | if (!twl) | |
653 | return -ENOMEM; | |
654 | ||
655 | twl->dev = &pdev->dev; | |
656 | twl->irq = platform_get_irq(pdev, 0); | |
657 | twl->otg.dev = twl->dev; | |
658 | twl->otg.label = "twl4030"; | |
659 | twl->otg.set_host = twl4030_set_host; | |
660 | twl->otg.set_peripheral = twl4030_set_peripheral; | |
661 | twl->otg.set_suspend = twl4030_set_suspend; | |
662 | twl->usb_mode = pdata->usb_mode; | |
663 | twl->asleep = 1; | |
664 | ||
665 | /* init spinlock for workqueue */ | |
666 | spin_lock_init(&twl->lock); | |
667 | ||
66760169 JH |
668 | err = twl4030_usb_ldo_init(twl); |
669 | if (err) { | |
670 | dev_err(&pdev->dev, "ldo init failed\n"); | |
671 | kfree(twl); | |
672 | return err; | |
673 | } | |
9ebd9616 DB |
674 | otg_set_transceiver(&twl->otg); |
675 | ||
676 | platform_set_drvdata(pdev, twl); | |
677 | if (device_create_file(&pdev->dev, &dev_attr_vbus)) | |
678 | dev_warn(&pdev->dev, "could not create sysfs file\n"); | |
679 | ||
d1b5b5c0 FB |
680 | BLOCKING_INIT_NOTIFIER_HEAD(&twl->otg.notifier); |
681 | ||
9ebd9616 DB |
682 | /* Our job is to use irqs and status from the power module |
683 | * to keep the transceiver disabled when nothing's connected. | |
684 | * | |
685 | * FIXME we actually shouldn't start enabling it until the | |
686 | * USB controller drivers have said they're ready, by calling | |
687 | * set_host() and/or set_peripheral() ... OTG_capable boards | |
688 | * need both handles, otherwise just one suffices. | |
689 | */ | |
690 | twl->irq_enabled = true; | |
8f20960c | 691 | status = request_threaded_irq(twl->irq, NULL, twl4030_usb_irq, |
9ebd9616 DB |
692 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, |
693 | "twl4030_usb", twl); | |
694 | if (status < 0) { | |
695 | dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n", | |
696 | twl->irq, status); | |
697 | kfree(twl); | |
698 | return status; | |
699 | } | |
700 | ||
701 | /* The IRQ handler just handles changes from the previous states | |
702 | * of the ID and VBUS pins ... in probe() we must initialize that | |
703 | * previous state. The easy way: fake an IRQ. | |
704 | * | |
705 | * REVISIT: a real IRQ might have happened already, if PREEMPT is | |
706 | * enabled. Else the IRQ may not yet be configured or enabled, | |
707 | * because of scheduling delays. | |
708 | */ | |
709 | twl4030_usb_irq(twl->irq, twl); | |
710 | ||
711 | dev_info(&pdev->dev, "Initialized TWL4030 USB module\n"); | |
712 | return 0; | |
713 | } | |
714 | ||
715 | static int __exit twl4030_usb_remove(struct platform_device *pdev) | |
716 | { | |
717 | struct twl4030_usb *twl = platform_get_drvdata(pdev); | |
718 | int val; | |
719 | ||
720 | free_irq(twl->irq, twl); | |
721 | device_remove_file(twl->dev, &dev_attr_vbus); | |
722 | ||
723 | /* set transceiver mode to power on defaults */ | |
724 | twl4030_usb_set_mode(twl, -1); | |
725 | ||
726 | /* autogate 60MHz ULPI clock, | |
727 | * clear dpll clock request for i2c access, | |
728 | * disable 32KHz | |
729 | */ | |
730 | val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
731 | if (val >= 0) { | |
732 | val |= PHY_CLK_CTRL_CLOCKGATING_EN; | |
733 | val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK); | |
734 | twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val); | |
735 | } | |
736 | ||
737 | /* disable complete OTG block */ | |
738 | twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); | |
739 | ||
740 | twl4030_phy_power(twl, 0); | |
66760169 JH |
741 | regulator_put(twl->usb1v5); |
742 | regulator_put(twl->usb1v8); | |
743 | regulator_put(twl->usb3v1); | |
9ebd9616 DB |
744 | |
745 | kfree(twl); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | static struct platform_driver twl4030_usb_driver = { | |
751 | .probe = twl4030_usb_probe, | |
752 | .remove = __exit_p(twl4030_usb_remove), | |
753 | .driver = { | |
754 | .name = "twl4030_usb", | |
755 | .owner = THIS_MODULE, | |
756 | }, | |
757 | }; | |
758 | ||
759 | static int __init twl4030_usb_init(void) | |
760 | { | |
761 | return platform_driver_register(&twl4030_usb_driver); | |
762 | } | |
763 | subsys_initcall(twl4030_usb_init); | |
764 | ||
765 | static void __exit twl4030_usb_exit(void) | |
766 | { | |
767 | platform_driver_unregister(&twl4030_usb_driver); | |
768 | } | |
769 | module_exit(twl4030_usb_exit); | |
770 | ||
771 | MODULE_ALIAS("platform:twl4030_usb"); | |
772 | MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation"); | |
773 | MODULE_DESCRIPTION("TWL4030 USB transceiver driver"); | |
774 | MODULE_LICENSE("GPL"); |