Commit | Line | Data |
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d860852e | 1 | /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. |
e0c201f3 PK |
2 | * |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/uaccess.h> | |
30 | #include <linux/debugfs.h> | |
31 | #include <linux/seq_file.h> | |
87c0104a | 32 | #include <linux/pm_runtime.h> |
e0c201f3 PK |
33 | |
34 | #include <linux/usb.h> | |
35 | #include <linux/usb/otg.h> | |
36 | #include <linux/usb/ulpi.h> | |
37 | #include <linux/usb/gadget.h> | |
38 | #include <linux/usb/hcd.h> | |
39 | #include <linux/usb/msm_hsusb.h> | |
40 | #include <linux/usb/msm_hsusb_hw.h> | |
11aa5c47 | 41 | #include <linux/regulator/consumer.h> |
e0c201f3 | 42 | |
e0c201f3 PK |
43 | #define MSM_USB_BASE (motg->regs) |
44 | #define DRIVER_NAME "msm_otg" | |
45 | ||
46 | #define ULPI_IO_TIMEOUT_USEC (10 * 1000) | |
11aa5c47 A |
47 | |
48 | #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */ | |
49 | #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */ | |
50 | #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */ | |
51 | #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */ | |
52 | ||
53 | #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */ | |
54 | #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */ | |
55 | #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */ | |
56 | #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */ | |
57 | ||
58 | #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */ | |
59 | #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */ | |
60 | ||
61 | static struct regulator *hsusb_3p3; | |
62 | static struct regulator *hsusb_1p8; | |
63 | static struct regulator *hsusb_vddcx; | |
64 | ||
65 | static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init) | |
66 | { | |
67 | int ret = 0; | |
68 | ||
69 | if (init) { | |
1d4c9293 | 70 | hsusb_vddcx = regulator_get(motg->phy.dev, "HSUSB_VDDCX"); |
11aa5c47 | 71 | if (IS_ERR(hsusb_vddcx)) { |
1d4c9293 | 72 | dev_err(motg->phy.dev, "unable to get hsusb vddcx\n"); |
11aa5c47 A |
73 | return PTR_ERR(hsusb_vddcx); |
74 | } | |
75 | ||
76 | ret = regulator_set_voltage(hsusb_vddcx, | |
77 | USB_PHY_VDD_DIG_VOL_MIN, | |
78 | USB_PHY_VDD_DIG_VOL_MAX); | |
79 | if (ret) { | |
1d4c9293 | 80 | dev_err(motg->phy.dev, "unable to set the voltage " |
11aa5c47 A |
81 | "for hsusb vddcx\n"); |
82 | regulator_put(hsusb_vddcx); | |
83 | return ret; | |
84 | } | |
85 | ||
86 | ret = regulator_enable(hsusb_vddcx); | |
87 | if (ret) { | |
1d4c9293 | 88 | dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n"); |
11aa5c47 A |
89 | regulator_put(hsusb_vddcx); |
90 | } | |
91 | } else { | |
92 | ret = regulator_set_voltage(hsusb_vddcx, 0, | |
7b521fcb | 93 | USB_PHY_VDD_DIG_VOL_MAX); |
e99c4309 | 94 | if (ret) |
1d4c9293 | 95 | dev_err(motg->phy.dev, "unable to set the voltage " |
11aa5c47 | 96 | "for hsusb vddcx\n"); |
11aa5c47 A |
97 | ret = regulator_disable(hsusb_vddcx); |
98 | if (ret) | |
1d4c9293 | 99 | dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n"); |
11aa5c47 A |
100 | |
101 | regulator_put(hsusb_vddcx); | |
102 | } | |
103 | ||
104 | return ret; | |
105 | } | |
106 | ||
107 | static int msm_hsusb_ldo_init(struct msm_otg *motg, int init) | |
108 | { | |
109 | int rc = 0; | |
110 | ||
111 | if (init) { | |
1d4c9293 | 112 | hsusb_3p3 = regulator_get(motg->phy.dev, "HSUSB_3p3"); |
11aa5c47 | 113 | if (IS_ERR(hsusb_3p3)) { |
1d4c9293 | 114 | dev_err(motg->phy.dev, "unable to get hsusb 3p3\n"); |
11aa5c47 A |
115 | return PTR_ERR(hsusb_3p3); |
116 | } | |
117 | ||
118 | rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN, | |
119 | USB_PHY_3P3_VOL_MAX); | |
120 | if (rc) { | |
1d4c9293 | 121 | dev_err(motg->phy.dev, "unable to set voltage level " |
11aa5c47 A |
122 | "for hsusb 3p3\n"); |
123 | goto put_3p3; | |
124 | } | |
125 | rc = regulator_enable(hsusb_3p3); | |
126 | if (rc) { | |
1d4c9293 | 127 | dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n"); |
11aa5c47 A |
128 | goto put_3p3; |
129 | } | |
1d4c9293 | 130 | hsusb_1p8 = regulator_get(motg->phy.dev, "HSUSB_1p8"); |
11aa5c47 | 131 | if (IS_ERR(hsusb_1p8)) { |
1d4c9293 | 132 | dev_err(motg->phy.dev, "unable to get hsusb 1p8\n"); |
11aa5c47 A |
133 | rc = PTR_ERR(hsusb_1p8); |
134 | goto disable_3p3; | |
135 | } | |
136 | rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN, | |
137 | USB_PHY_1P8_VOL_MAX); | |
138 | if (rc) { | |
1d4c9293 | 139 | dev_err(motg->phy.dev, "unable to set voltage level " |
11aa5c47 A |
140 | "for hsusb 1p8\n"); |
141 | goto put_1p8; | |
142 | } | |
143 | rc = regulator_enable(hsusb_1p8); | |
144 | if (rc) { | |
1d4c9293 | 145 | dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n"); |
11aa5c47 A |
146 | goto put_1p8; |
147 | } | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | regulator_disable(hsusb_1p8); | |
153 | put_1p8: | |
154 | regulator_put(hsusb_1p8); | |
155 | disable_3p3: | |
156 | regulator_disable(hsusb_3p3); | |
157 | put_3p3: | |
158 | regulator_put(hsusb_3p3); | |
159 | return rc; | |
160 | } | |
161 | ||
162 | static int msm_hsusb_ldo_set_mode(int on) | |
163 | { | |
164 | int ret = 0; | |
165 | ||
166 | if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) { | |
167 | pr_err("%s: HSUSB_1p8 is not initialized\n", __func__); | |
168 | return -ENODEV; | |
169 | } | |
170 | ||
171 | if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) { | |
172 | pr_err("%s: HSUSB_3p3 is not initialized\n", __func__); | |
173 | return -ENODEV; | |
174 | } | |
175 | ||
176 | if (on) { | |
177 | ret = regulator_set_optimum_mode(hsusb_1p8, | |
178 | USB_PHY_1P8_HPM_LOAD); | |
179 | if (ret < 0) { | |
180 | pr_err("%s: Unable to set HPM of the regulator " | |
181 | "HSUSB_1p8\n", __func__); | |
182 | return ret; | |
183 | } | |
184 | ret = regulator_set_optimum_mode(hsusb_3p3, | |
185 | USB_PHY_3P3_HPM_LOAD); | |
186 | if (ret < 0) { | |
187 | pr_err("%s: Unable to set HPM of the regulator " | |
188 | "HSUSB_3p3\n", __func__); | |
189 | regulator_set_optimum_mode(hsusb_1p8, | |
190 | USB_PHY_1P8_LPM_LOAD); | |
191 | return ret; | |
192 | } | |
193 | } else { | |
194 | ret = regulator_set_optimum_mode(hsusb_1p8, | |
195 | USB_PHY_1P8_LPM_LOAD); | |
196 | if (ret < 0) | |
197 | pr_err("%s: Unable to set LPM of the regulator " | |
198 | "HSUSB_1p8\n", __func__); | |
199 | ret = regulator_set_optimum_mode(hsusb_3p3, | |
200 | USB_PHY_3P3_LPM_LOAD); | |
201 | if (ret < 0) | |
202 | pr_err("%s: Unable to set LPM of the regulator " | |
203 | "HSUSB_3p3\n", __func__); | |
204 | } | |
205 | ||
206 | pr_debug("reg (%s)\n", on ? "HPM" : "LPM"); | |
207 | return ret < 0 ? ret : 0; | |
208 | } | |
209 | ||
1d4c9293 | 210 | static int ulpi_read(struct usb_phy *phy, u32 reg) |
e0c201f3 | 211 | { |
1d4c9293 | 212 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
213 | int cnt = 0; |
214 | ||
215 | /* initiate read operation */ | |
216 | writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg), | |
217 | USB_ULPI_VIEWPORT); | |
218 | ||
219 | /* wait for completion */ | |
220 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
221 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
222 | break; | |
223 | udelay(1); | |
224 | cnt++; | |
225 | } | |
226 | ||
227 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 228 | dev_err(phy->dev, "ulpi_read: timeout %08x\n", |
e0c201f3 PK |
229 | readl(USB_ULPI_VIEWPORT)); |
230 | return -ETIMEDOUT; | |
231 | } | |
232 | return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT)); | |
233 | } | |
234 | ||
1d4c9293 | 235 | static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
e0c201f3 | 236 | { |
1d4c9293 | 237 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
238 | int cnt = 0; |
239 | ||
240 | /* initiate write operation */ | |
241 | writel(ULPI_RUN | ULPI_WRITE | | |
242 | ULPI_ADDR(reg) | ULPI_DATA(val), | |
243 | USB_ULPI_VIEWPORT); | |
244 | ||
245 | /* wait for completion */ | |
246 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
247 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
248 | break; | |
249 | udelay(1); | |
250 | cnt++; | |
251 | } | |
252 | ||
253 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 254 | dev_err(phy->dev, "ulpi_write: timeout\n"); |
e0c201f3 PK |
255 | return -ETIMEDOUT; |
256 | } | |
257 | return 0; | |
258 | } | |
259 | ||
1d4c9293 | 260 | static struct usb_phy_io_ops msm_otg_io_ops = { |
e0c201f3 PK |
261 | .read = ulpi_read, |
262 | .write = ulpi_write, | |
263 | }; | |
264 | ||
265 | static void ulpi_init(struct msm_otg *motg) | |
266 | { | |
267 | struct msm_otg_platform_data *pdata = motg->pdata; | |
268 | int *seq = pdata->phy_init_seq; | |
269 | ||
270 | if (!seq) | |
271 | return; | |
272 | ||
273 | while (seq[0] >= 0) { | |
1d4c9293 | 274 | dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n", |
e0c201f3 | 275 | seq[0], seq[1]); |
1d4c9293 | 276 | ulpi_write(&motg->phy, seq[0], seq[1]); |
e0c201f3 PK |
277 | seq += 2; |
278 | } | |
279 | } | |
280 | ||
281 | static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) | |
282 | { | |
5146d771 II |
283 | int ret = 0; |
284 | ||
285 | if (!motg->pdata->link_clk_reset) | |
286 | return ret; | |
287 | ||
288 | ret = motg->pdata->link_clk_reset(motg->clk, assert); | |
289 | if (ret) | |
290 | dev_err(motg->phy.dev, "usb link clk reset %s failed\n", | |
291 | assert ? "assert" : "deassert"); | |
e0c201f3 | 292 | |
e0c201f3 PK |
293 | return ret; |
294 | } | |
295 | ||
296 | static int msm_otg_phy_clk_reset(struct msm_otg *motg) | |
297 | { | |
5146d771 | 298 | int ret = 0; |
e0c201f3 | 299 | |
5146d771 | 300 | if (!motg->pdata->phy_clk_reset) |
e0c201f3 | 301 | return ret; |
5146d771 II |
302 | |
303 | ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk); | |
e0c201f3 | 304 | if (ret) |
5146d771 II |
305 | dev_err(motg->phy.dev, "usb phy clk reset failed\n"); |
306 | ||
e0c201f3 PK |
307 | return ret; |
308 | } | |
309 | ||
310 | static int msm_otg_phy_reset(struct msm_otg *motg) | |
311 | { | |
312 | u32 val; | |
313 | int ret; | |
314 | int retries; | |
315 | ||
316 | ret = msm_otg_link_clk_reset(motg, 1); | |
317 | if (ret) | |
318 | return ret; | |
319 | ret = msm_otg_phy_clk_reset(motg); | |
320 | if (ret) | |
321 | return ret; | |
322 | ret = msm_otg_link_clk_reset(motg, 0); | |
323 | if (ret) | |
324 | return ret; | |
325 | ||
326 | val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK; | |
327 | writel(val | PORTSC_PTS_ULPI, USB_PORTSC); | |
328 | ||
329 | for (retries = 3; retries > 0; retries--) { | |
1d4c9293 | 330 | ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM, |
e0c201f3 PK |
331 | ULPI_CLR(ULPI_FUNC_CTRL)); |
332 | if (!ret) | |
333 | break; | |
334 | ret = msm_otg_phy_clk_reset(motg); | |
335 | if (ret) | |
336 | return ret; | |
337 | } | |
338 | if (!retries) | |
339 | return -ETIMEDOUT; | |
340 | ||
341 | /* This reset calibrates the phy, if the above write succeeded */ | |
342 | ret = msm_otg_phy_clk_reset(motg); | |
343 | if (ret) | |
344 | return ret; | |
345 | ||
346 | for (retries = 3; retries > 0; retries--) { | |
1d4c9293 | 347 | ret = ulpi_read(&motg->phy, ULPI_DEBUG); |
e0c201f3 PK |
348 | if (ret != -ETIMEDOUT) |
349 | break; | |
350 | ret = msm_otg_phy_clk_reset(motg); | |
351 | if (ret) | |
352 | return ret; | |
353 | } | |
354 | if (!retries) | |
355 | return -ETIMEDOUT; | |
356 | ||
1d4c9293 | 357 | dev_info(motg->phy.dev, "phy_reset: success\n"); |
e0c201f3 PK |
358 | return 0; |
359 | } | |
360 | ||
361 | #define LINK_RESET_TIMEOUT_USEC (250 * 1000) | |
1d4c9293 | 362 | static int msm_otg_reset(struct usb_phy *phy) |
e0c201f3 | 363 | { |
1d4c9293 | 364 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
365 | struct msm_otg_platform_data *pdata = motg->pdata; |
366 | int cnt = 0; | |
367 | int ret; | |
368 | u32 val = 0; | |
369 | u32 ulpi_val = 0; | |
370 | ||
371 | ret = msm_otg_phy_reset(motg); | |
372 | if (ret) { | |
1d4c9293 | 373 | dev_err(phy->dev, "phy_reset failed\n"); |
e0c201f3 PK |
374 | return ret; |
375 | } | |
376 | ||
377 | ulpi_init(motg); | |
378 | ||
379 | writel(USBCMD_RESET, USB_USBCMD); | |
380 | while (cnt < LINK_RESET_TIMEOUT_USEC) { | |
381 | if (!(readl(USB_USBCMD) & USBCMD_RESET)) | |
382 | break; | |
383 | udelay(1); | |
384 | cnt++; | |
385 | } | |
386 | if (cnt >= LINK_RESET_TIMEOUT_USEC) | |
387 | return -ETIMEDOUT; | |
388 | ||
389 | /* select ULPI phy */ | |
390 | writel(0x80000000, USB_PORTSC); | |
391 | ||
392 | msleep(100); | |
393 | ||
394 | writel(0x0, USB_AHBBURST); | |
395 | writel(0x00, USB_AHBMODE); | |
396 | ||
397 | if (pdata->otg_control == OTG_PHY_CONTROL) { | |
398 | val = readl(USB_OTGSC); | |
399 | if (pdata->mode == USB_OTG) { | |
400 | ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; | |
401 | val |= OTGSC_IDIE | OTGSC_BSVIE; | |
402 | } else if (pdata->mode == USB_PERIPHERAL) { | |
403 | ulpi_val = ULPI_INT_SESS_VALID; | |
404 | val |= OTGSC_BSVIE; | |
405 | } | |
406 | writel(val, USB_OTGSC); | |
1d4c9293 HK |
407 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE); |
408 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); | |
e0c201f3 PK |
409 | } |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
87c0104a | 414 | #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000) |
7018773a PK |
415 | #define PHY_RESUME_TIMEOUT_USEC (100 * 1000) |
416 | ||
e7d613d1 JC |
417 | #ifdef CONFIG_PM |
418 | ||
419 | #define USB_PHY_SUSP_DIG_VOL 500000 | |
420 | static int msm_hsusb_config_vddcx(int high) | |
421 | { | |
422 | int max_vol = USB_PHY_VDD_DIG_VOL_MAX; | |
423 | int min_vol; | |
424 | int ret; | |
425 | ||
426 | if (high) | |
427 | min_vol = USB_PHY_VDD_DIG_VOL_MIN; | |
428 | else | |
429 | min_vol = USB_PHY_SUSP_DIG_VOL; | |
430 | ||
431 | ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol); | |
432 | if (ret) { | |
433 | pr_err("%s: unable to set the voltage for regulator " | |
434 | "HSUSB_VDDCX\n", __func__); | |
435 | return ret; | |
436 | } | |
437 | ||
438 | pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol); | |
439 | ||
440 | return ret; | |
441 | } | |
442 | ||
87c0104a PK |
443 | static int msm_otg_suspend(struct msm_otg *motg) |
444 | { | |
1d4c9293 HK |
445 | struct usb_phy *phy = &motg->phy; |
446 | struct usb_bus *bus = phy->otg->host; | |
87c0104a PK |
447 | struct msm_otg_platform_data *pdata = motg->pdata; |
448 | int cnt = 0; | |
449 | ||
450 | if (atomic_read(&motg->in_lpm)) | |
451 | return 0; | |
452 | ||
453 | disable_irq(motg->irq); | |
454 | /* | |
04aebcbb PK |
455 | * Chipidea 45-nm PHY suspend sequence: |
456 | * | |
87c0104a PK |
457 | * Interrupt Latch Register auto-clear feature is not present |
458 | * in all PHY versions. Latch register is clear on read type. | |
459 | * Clear latch register to avoid spurious wakeup from | |
460 | * low power mode (LPM). | |
04aebcbb | 461 | * |
87c0104a PK |
462 | * PHY comparators are disabled when PHY enters into low power |
463 | * mode (LPM). Keep PHY comparators ON in LPM only when we expect | |
464 | * VBUS/Id notifications from USB PHY. Otherwise turn off USB | |
465 | * PHY comparators. This save significant amount of power. | |
04aebcbb | 466 | * |
87c0104a PK |
467 | * PLL is not turned off when PHY enters into low power mode (LPM). |
468 | * Disable PLL for maximum power savings. | |
469 | */ | |
04aebcbb PK |
470 | |
471 | if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) { | |
1d4c9293 | 472 | ulpi_read(phy, 0x14); |
04aebcbb | 473 | if (pdata->otg_control == OTG_PHY_CONTROL) |
1d4c9293 HK |
474 | ulpi_write(phy, 0x01, 0x30); |
475 | ulpi_write(phy, 0x08, 0x09); | |
04aebcbb | 476 | } |
87c0104a PK |
477 | |
478 | /* | |
479 | * PHY may take some time or even fail to enter into low power | |
480 | * mode (LPM). Hence poll for 500 msec and reset the PHY and link | |
481 | * in failure case. | |
482 | */ | |
483 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
484 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
485 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
486 | break; | |
487 | udelay(1); | |
488 | cnt++; | |
489 | } | |
490 | ||
491 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) { | |
1d4c9293 HK |
492 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
493 | msm_otg_reset(phy); | |
87c0104a PK |
494 | enable_irq(motg->irq); |
495 | return -ETIMEDOUT; | |
496 | } | |
497 | ||
498 | /* | |
499 | * PHY has capability to generate interrupt asynchronously in low | |
500 | * power mode (LPM). This interrupt is level triggered. So USB IRQ | |
501 | * line must be disabled till async interrupt enable bit is cleared | |
502 | * in USBCMD register. Assert STP (ULPI interface STOP signal) to | |
503 | * block data communication from PHY. | |
504 | */ | |
505 | writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD); | |
506 | ||
04aebcbb PK |
507 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
508 | motg->pdata->otg_control == OTG_PMIC_CONTROL) | |
509 | writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL); | |
510 | ||
b99a8f62 SB |
511 | clk_disable_unprepare(motg->pclk); |
512 | clk_disable_unprepare(motg->clk); | |
87c0104a | 513 | if (motg->core_clk) |
b99a8f62 | 514 | clk_disable_unprepare(motg->core_clk); |
87c0104a | 515 | |
0f73cac8 | 516 | if (!IS_ERR(motg->pclk_src)) |
b99a8f62 | 517 | clk_disable_unprepare(motg->pclk_src); |
0f73cac8 | 518 | |
04aebcbb PK |
519 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
520 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
521 | msm_hsusb_ldo_set_mode(0); | |
522 | msm_hsusb_config_vddcx(0); | |
523 | } | |
524 | ||
1d4c9293 | 525 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
526 | enable_irq_wake(motg->irq); |
527 | if (bus) | |
528 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
529 | ||
530 | atomic_set(&motg->in_lpm, 1); | |
531 | enable_irq(motg->irq); | |
532 | ||
1d4c9293 | 533 | dev_info(phy->dev, "USB in low power mode\n"); |
87c0104a PK |
534 | |
535 | return 0; | |
536 | } | |
537 | ||
87c0104a PK |
538 | static int msm_otg_resume(struct msm_otg *motg) |
539 | { | |
1d4c9293 HK |
540 | struct usb_phy *phy = &motg->phy; |
541 | struct usb_bus *bus = phy->otg->host; | |
87c0104a PK |
542 | int cnt = 0; |
543 | unsigned temp; | |
544 | ||
545 | if (!atomic_read(&motg->in_lpm)) | |
546 | return 0; | |
547 | ||
0f73cac8 | 548 | if (!IS_ERR(motg->pclk_src)) |
b99a8f62 | 549 | clk_prepare_enable(motg->pclk_src); |
0f73cac8 | 550 | |
b99a8f62 SB |
551 | clk_prepare_enable(motg->pclk); |
552 | clk_prepare_enable(motg->clk); | |
87c0104a | 553 | if (motg->core_clk) |
b99a8f62 | 554 | clk_prepare_enable(motg->core_clk); |
87c0104a | 555 | |
04aebcbb PK |
556 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
557 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
558 | msm_hsusb_ldo_set_mode(1); | |
559 | msm_hsusb_config_vddcx(1); | |
560 | writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL); | |
561 | } | |
562 | ||
87c0104a PK |
563 | temp = readl(USB_USBCMD); |
564 | temp &= ~ASYNC_INTR_CTRL; | |
565 | temp &= ~ULPI_STP_CTRL; | |
566 | writel(temp, USB_USBCMD); | |
567 | ||
568 | /* | |
569 | * PHY comes out of low power mode (LPM) in case of wakeup | |
570 | * from asynchronous interrupt. | |
571 | */ | |
572 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
573 | goto skip_phy_resume; | |
574 | ||
575 | writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC); | |
576 | while (cnt < PHY_RESUME_TIMEOUT_USEC) { | |
577 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
578 | break; | |
579 | udelay(1); | |
580 | cnt++; | |
581 | } | |
582 | ||
583 | if (cnt >= PHY_RESUME_TIMEOUT_USEC) { | |
584 | /* | |
585 | * This is a fatal error. Reset the link and | |
586 | * PHY. USB state can not be restored. Re-insertion | |
587 | * of USB cable is the only way to get USB working. | |
588 | */ | |
1d4c9293 | 589 | dev_err(phy->dev, "Unable to resume USB." |
87c0104a | 590 | "Re-plugin the cable\n"); |
1d4c9293 | 591 | msm_otg_reset(phy); |
87c0104a PK |
592 | } |
593 | ||
594 | skip_phy_resume: | |
1d4c9293 | 595 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
596 | disable_irq_wake(motg->irq); |
597 | if (bus) | |
598 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
599 | ||
2ce2c3ac PK |
600 | atomic_set(&motg->in_lpm, 0); |
601 | ||
87c0104a PK |
602 | if (motg->async_int) { |
603 | motg->async_int = 0; | |
1d4c9293 | 604 | pm_runtime_put(phy->dev); |
87c0104a PK |
605 | enable_irq(motg->irq); |
606 | } | |
607 | ||
1d4c9293 | 608 | dev_info(phy->dev, "USB exited from low power mode\n"); |
87c0104a PK |
609 | |
610 | return 0; | |
611 | } | |
7018773a | 612 | #endif |
87c0104a | 613 | |
d860852e PK |
614 | static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA) |
615 | { | |
616 | if (motg->cur_power == mA) | |
617 | return; | |
618 | ||
619 | /* TODO: Notify PMIC about available current */ | |
1d4c9293 | 620 | dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA); |
d860852e PK |
621 | motg->cur_power = mA; |
622 | } | |
623 | ||
1d4c9293 | 624 | static int msm_otg_set_power(struct usb_phy *phy, unsigned mA) |
d860852e | 625 | { |
1d4c9293 | 626 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
d860852e PK |
627 | |
628 | /* | |
629 | * Gadget driver uses set_power method to notify about the | |
630 | * available current based on suspend/configured states. | |
631 | * | |
632 | * IDEV_CHG can be drawn irrespective of suspend/un-configured | |
633 | * states when CDP/ACA is connected. | |
634 | */ | |
635 | if (motg->chg_type == USB_SDP_CHARGER) | |
636 | msm_otg_notify_charger(motg, mA); | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
1d4c9293 | 641 | static void msm_otg_start_host(struct usb_phy *phy, int on) |
e0c201f3 | 642 | { |
1d4c9293 | 643 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
644 | struct msm_otg_platform_data *pdata = motg->pdata; |
645 | struct usb_hcd *hcd; | |
646 | ||
1d4c9293 | 647 | if (!phy->otg->host) |
e0c201f3 PK |
648 | return; |
649 | ||
1d4c9293 | 650 | hcd = bus_to_hcd(phy->otg->host); |
e0c201f3 PK |
651 | |
652 | if (on) { | |
1d4c9293 | 653 | dev_dbg(phy->dev, "host on\n"); |
e0c201f3 PK |
654 | |
655 | if (pdata->vbus_power) | |
656 | pdata->vbus_power(1); | |
657 | /* | |
658 | * Some boards have a switch cotrolled by gpio | |
659 | * to enable/disable internal HUB. Enable internal | |
660 | * HUB before kicking the host. | |
661 | */ | |
662 | if (pdata->setup_gpio) | |
663 | pdata->setup_gpio(OTG_STATE_A_HOST); | |
664 | #ifdef CONFIG_USB | |
665 | usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); | |
3c9740a1 | 666 | device_wakeup_enable(hcd->self.controller); |
e0c201f3 PK |
667 | #endif |
668 | } else { | |
1d4c9293 | 669 | dev_dbg(phy->dev, "host off\n"); |
e0c201f3 PK |
670 | |
671 | #ifdef CONFIG_USB | |
672 | usb_remove_hcd(hcd); | |
673 | #endif | |
674 | if (pdata->setup_gpio) | |
675 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
676 | if (pdata->vbus_power) | |
677 | pdata->vbus_power(0); | |
678 | } | |
679 | } | |
680 | ||
1d4c9293 | 681 | static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) |
e0c201f3 | 682 | { |
1d4c9293 | 683 | struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy); |
e0c201f3 PK |
684 | struct usb_hcd *hcd; |
685 | ||
686 | /* | |
687 | * Fail host registration if this board can support | |
688 | * only peripheral configuration. | |
689 | */ | |
690 | if (motg->pdata->mode == USB_PERIPHERAL) { | |
1d4c9293 | 691 | dev_info(otg->phy->dev, "Host mode is not supported\n"); |
e0c201f3 PK |
692 | return -ENODEV; |
693 | } | |
694 | ||
695 | if (!host) { | |
1d4c9293 HK |
696 | if (otg->phy->state == OTG_STATE_A_HOST) { |
697 | pm_runtime_get_sync(otg->phy->dev); | |
698 | msm_otg_start_host(otg->phy, 0); | |
e0c201f3 | 699 | otg->host = NULL; |
1d4c9293 | 700 | otg->phy->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
701 | schedule_work(&motg->sm_work); |
702 | } else { | |
703 | otg->host = NULL; | |
704 | } | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | hcd = bus_to_hcd(host); | |
710 | hcd->power_budget = motg->pdata->power_budget; | |
711 | ||
712 | otg->host = host; | |
1d4c9293 | 713 | dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n"); |
e0c201f3 PK |
714 | |
715 | /* | |
716 | * Kick the state machine work, if peripheral is not supported | |
717 | * or peripheral is already registered with us. | |
718 | */ | |
87c0104a | 719 | if (motg->pdata->mode == USB_HOST || otg->gadget) { |
1d4c9293 | 720 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 | 721 | schedule_work(&motg->sm_work); |
87c0104a | 722 | } |
e0c201f3 PK |
723 | |
724 | return 0; | |
725 | } | |
726 | ||
1d4c9293 | 727 | static void msm_otg_start_peripheral(struct usb_phy *phy, int on) |
e0c201f3 | 728 | { |
1d4c9293 | 729 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
730 | struct msm_otg_platform_data *pdata = motg->pdata; |
731 | ||
1d4c9293 | 732 | if (!phy->otg->gadget) |
e0c201f3 PK |
733 | return; |
734 | ||
735 | if (on) { | |
1d4c9293 | 736 | dev_dbg(phy->dev, "gadget on\n"); |
e0c201f3 PK |
737 | /* |
738 | * Some boards have a switch cotrolled by gpio | |
739 | * to enable/disable internal HUB. Disable internal | |
740 | * HUB before kicking the gadget. | |
741 | */ | |
742 | if (pdata->setup_gpio) | |
743 | pdata->setup_gpio(OTG_STATE_B_PERIPHERAL); | |
1d4c9293 | 744 | usb_gadget_vbus_connect(phy->otg->gadget); |
e0c201f3 | 745 | } else { |
1d4c9293 HK |
746 | dev_dbg(phy->dev, "gadget off\n"); |
747 | usb_gadget_vbus_disconnect(phy->otg->gadget); | |
e0c201f3 PK |
748 | if (pdata->setup_gpio) |
749 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
750 | } | |
751 | ||
752 | } | |
753 | ||
1d4c9293 HK |
754 | static int msm_otg_set_peripheral(struct usb_otg *otg, |
755 | struct usb_gadget *gadget) | |
e0c201f3 | 756 | { |
1d4c9293 | 757 | struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy); |
e0c201f3 PK |
758 | |
759 | /* | |
760 | * Fail peripheral registration if this board can support | |
761 | * only host configuration. | |
762 | */ | |
763 | if (motg->pdata->mode == USB_HOST) { | |
1d4c9293 | 764 | dev_info(otg->phy->dev, "Peripheral mode is not supported\n"); |
e0c201f3 PK |
765 | return -ENODEV; |
766 | } | |
767 | ||
768 | if (!gadget) { | |
1d4c9293 HK |
769 | if (otg->phy->state == OTG_STATE_B_PERIPHERAL) { |
770 | pm_runtime_get_sync(otg->phy->dev); | |
771 | msm_otg_start_peripheral(otg->phy, 0); | |
e0c201f3 | 772 | otg->gadget = NULL; |
1d4c9293 | 773 | otg->phy->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
774 | schedule_work(&motg->sm_work); |
775 | } else { | |
776 | otg->gadget = NULL; | |
777 | } | |
778 | ||
779 | return 0; | |
780 | } | |
781 | otg->gadget = gadget; | |
1d4c9293 | 782 | dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n"); |
e0c201f3 PK |
783 | |
784 | /* | |
785 | * Kick the state machine work, if host is not supported | |
786 | * or host is already registered with us. | |
787 | */ | |
87c0104a | 788 | if (motg->pdata->mode == USB_PERIPHERAL || otg->host) { |
1d4c9293 | 789 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 | 790 | schedule_work(&motg->sm_work); |
87c0104a | 791 | } |
e0c201f3 PK |
792 | |
793 | return 0; | |
794 | } | |
795 | ||
d860852e PK |
796 | static bool msm_chg_check_secondary_det(struct msm_otg *motg) |
797 | { | |
1d4c9293 | 798 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
799 | u32 chg_det; |
800 | bool ret = false; | |
801 | ||
802 | switch (motg->pdata->phy_type) { | |
803 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 804 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
805 | ret = chg_det & (1 << 4); |
806 | break; | |
807 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 808 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
809 | ret = chg_det & 1; |
810 | break; | |
811 | default: | |
812 | break; | |
813 | } | |
814 | return ret; | |
815 | } | |
816 | ||
817 | static void msm_chg_enable_secondary_det(struct msm_otg *motg) | |
818 | { | |
1d4c9293 | 819 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
820 | u32 chg_det; |
821 | ||
822 | switch (motg->pdata->phy_type) { | |
823 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 824 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
825 | /* Turn off charger block */ |
826 | chg_det |= ~(1 << 1); | |
1d4c9293 | 827 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
828 | udelay(20); |
829 | /* control chg block via ULPI */ | |
830 | chg_det &= ~(1 << 3); | |
1d4c9293 | 831 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
832 | /* put it in host mode for enabling D- source */ |
833 | chg_det &= ~(1 << 2); | |
1d4c9293 | 834 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
835 | /* Turn on chg detect block */ |
836 | chg_det &= ~(1 << 1); | |
1d4c9293 | 837 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
838 | udelay(20); |
839 | /* enable chg detection */ | |
840 | chg_det &= ~(1 << 0); | |
1d4c9293 | 841 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
842 | break; |
843 | case SNPS_28NM_INTEGRATED_PHY: | |
844 | /* | |
845 | * Configure DM as current source, DP as current sink | |
846 | * and enable battery charging comparators. | |
847 | */ | |
1d4c9293 HK |
848 | ulpi_write(phy, 0x8, 0x85); |
849 | ulpi_write(phy, 0x2, 0x85); | |
850 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
851 | break; |
852 | default: | |
853 | break; | |
854 | } | |
855 | } | |
856 | ||
857 | static bool msm_chg_check_primary_det(struct msm_otg *motg) | |
858 | { | |
1d4c9293 | 859 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
860 | u32 chg_det; |
861 | bool ret = false; | |
862 | ||
863 | switch (motg->pdata->phy_type) { | |
864 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 865 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
866 | ret = chg_det & (1 << 4); |
867 | break; | |
868 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 869 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
870 | ret = chg_det & 1; |
871 | break; | |
872 | default: | |
873 | break; | |
874 | } | |
875 | return ret; | |
876 | } | |
877 | ||
878 | static void msm_chg_enable_primary_det(struct msm_otg *motg) | |
879 | { | |
1d4c9293 | 880 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
881 | u32 chg_det; |
882 | ||
883 | switch (motg->pdata->phy_type) { | |
884 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 885 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
886 | /* enable chg detection */ |
887 | chg_det &= ~(1 << 0); | |
1d4c9293 | 888 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
889 | break; |
890 | case SNPS_28NM_INTEGRATED_PHY: | |
891 | /* | |
892 | * Configure DP as current source, DM as current sink | |
893 | * and enable battery charging comparators. | |
894 | */ | |
1d4c9293 HK |
895 | ulpi_write(phy, 0x2, 0x85); |
896 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
897 | break; |
898 | default: | |
899 | break; | |
900 | } | |
901 | } | |
902 | ||
903 | static bool msm_chg_check_dcd(struct msm_otg *motg) | |
904 | { | |
1d4c9293 | 905 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
906 | u32 line_state; |
907 | bool ret = false; | |
908 | ||
909 | switch (motg->pdata->phy_type) { | |
910 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 911 | line_state = ulpi_read(phy, 0x15); |
d860852e PK |
912 | ret = !(line_state & 1); |
913 | break; | |
914 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 915 | line_state = ulpi_read(phy, 0x87); |
d860852e PK |
916 | ret = line_state & 2; |
917 | break; | |
918 | default: | |
919 | break; | |
920 | } | |
921 | return ret; | |
922 | } | |
923 | ||
924 | static void msm_chg_disable_dcd(struct msm_otg *motg) | |
925 | { | |
1d4c9293 | 926 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
927 | u32 chg_det; |
928 | ||
929 | switch (motg->pdata->phy_type) { | |
930 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 931 | chg_det = ulpi_read(phy, 0x34); |
d860852e | 932 | chg_det &= ~(1 << 5); |
1d4c9293 | 933 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
934 | break; |
935 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 936 | ulpi_write(phy, 0x10, 0x86); |
d860852e PK |
937 | break; |
938 | default: | |
939 | break; | |
940 | } | |
941 | } | |
942 | ||
943 | static void msm_chg_enable_dcd(struct msm_otg *motg) | |
944 | { | |
1d4c9293 | 945 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
946 | u32 chg_det; |
947 | ||
948 | switch (motg->pdata->phy_type) { | |
949 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 950 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
951 | /* Turn on D+ current source */ |
952 | chg_det |= (1 << 5); | |
1d4c9293 | 953 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
954 | break; |
955 | case SNPS_28NM_INTEGRATED_PHY: | |
956 | /* Data contact detection enable */ | |
1d4c9293 | 957 | ulpi_write(phy, 0x10, 0x85); |
d860852e PK |
958 | break; |
959 | default: | |
960 | break; | |
961 | } | |
962 | } | |
963 | ||
964 | static void msm_chg_block_on(struct msm_otg *motg) | |
965 | { | |
1d4c9293 | 966 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
967 | u32 func_ctrl, chg_det; |
968 | ||
969 | /* put the controller in non-driving mode */ | |
1d4c9293 | 970 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
971 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
972 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; | |
1d4c9293 | 973 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
974 | |
975 | switch (motg->pdata->phy_type) { | |
976 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 977 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
978 | /* control chg block via ULPI */ |
979 | chg_det &= ~(1 << 3); | |
1d4c9293 | 980 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
981 | /* Turn on chg detect block */ |
982 | chg_det &= ~(1 << 1); | |
1d4c9293 | 983 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
984 | udelay(20); |
985 | break; | |
986 | case SNPS_28NM_INTEGRATED_PHY: | |
987 | /* Clear charger detecting control bits */ | |
1d4c9293 | 988 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 989 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
990 | ulpi_write(phy, 0x1F, 0x92); |
991 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
992 | udelay(100); |
993 | break; | |
994 | default: | |
995 | break; | |
996 | } | |
997 | } | |
998 | ||
999 | static void msm_chg_block_off(struct msm_otg *motg) | |
1000 | { | |
1d4c9293 | 1001 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1002 | u32 func_ctrl, chg_det; |
1003 | ||
1004 | switch (motg->pdata->phy_type) { | |
1005 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1006 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1007 | /* Turn off charger block */ |
1008 | chg_det |= ~(1 << 1); | |
1d4c9293 | 1009 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1010 | break; |
1011 | case SNPS_28NM_INTEGRATED_PHY: | |
1012 | /* Clear charger detecting control bits */ | |
1d4c9293 | 1013 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 1014 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
1015 | ulpi_write(phy, 0x1F, 0x92); |
1016 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
1017 | break; |
1018 | default: | |
1019 | break; | |
1020 | } | |
1021 | ||
1022 | /* put the controller in normal mode */ | |
1d4c9293 | 1023 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
1024 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
1025 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL; | |
1d4c9293 | 1026 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
1027 | } |
1028 | ||
1029 | #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */ | |
1030 | #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */ | |
1031 | #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */ | |
1032 | #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */ | |
1033 | static void msm_chg_detect_work(struct work_struct *w) | |
1034 | { | |
1035 | struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work); | |
1d4c9293 | 1036 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1037 | bool is_dcd, tmout, vout; |
1038 | unsigned long delay; | |
1039 | ||
1d4c9293 | 1040 | dev_dbg(phy->dev, "chg detection work\n"); |
d860852e PK |
1041 | switch (motg->chg_state) { |
1042 | case USB_CHG_STATE_UNDEFINED: | |
1d4c9293 | 1043 | pm_runtime_get_sync(phy->dev); |
d860852e PK |
1044 | msm_chg_block_on(motg); |
1045 | msm_chg_enable_dcd(motg); | |
1046 | motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; | |
1047 | motg->dcd_retries = 0; | |
1048 | delay = MSM_CHG_DCD_POLL_TIME; | |
1049 | break; | |
1050 | case USB_CHG_STATE_WAIT_FOR_DCD: | |
1051 | is_dcd = msm_chg_check_dcd(motg); | |
1052 | tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES; | |
1053 | if (is_dcd || tmout) { | |
1054 | msm_chg_disable_dcd(motg); | |
1055 | msm_chg_enable_primary_det(motg); | |
1056 | delay = MSM_CHG_PRIMARY_DET_TIME; | |
1057 | motg->chg_state = USB_CHG_STATE_DCD_DONE; | |
1058 | } else { | |
1059 | delay = MSM_CHG_DCD_POLL_TIME; | |
1060 | } | |
1061 | break; | |
1062 | case USB_CHG_STATE_DCD_DONE: | |
1063 | vout = msm_chg_check_primary_det(motg); | |
1064 | if (vout) { | |
1065 | msm_chg_enable_secondary_det(motg); | |
1066 | delay = MSM_CHG_SECONDARY_DET_TIME; | |
1067 | motg->chg_state = USB_CHG_STATE_PRIMARY_DONE; | |
1068 | } else { | |
1069 | motg->chg_type = USB_SDP_CHARGER; | |
1070 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1071 | delay = 0; | |
1072 | } | |
1073 | break; | |
1074 | case USB_CHG_STATE_PRIMARY_DONE: | |
1075 | vout = msm_chg_check_secondary_det(motg); | |
1076 | if (vout) | |
1077 | motg->chg_type = USB_DCP_CHARGER; | |
1078 | else | |
1079 | motg->chg_type = USB_CDP_CHARGER; | |
1080 | motg->chg_state = USB_CHG_STATE_SECONDARY_DONE; | |
1081 | /* fall through */ | |
1082 | case USB_CHG_STATE_SECONDARY_DONE: | |
1083 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1084 | case USB_CHG_STATE_DETECTED: | |
1085 | msm_chg_block_off(motg); | |
1d4c9293 | 1086 | dev_dbg(phy->dev, "charger = %d\n", motg->chg_type); |
d860852e PK |
1087 | schedule_work(&motg->sm_work); |
1088 | return; | |
1089 | default: | |
1090 | return; | |
1091 | } | |
1092 | ||
1093 | schedule_delayed_work(&motg->chg_work, delay); | |
1094 | } | |
1095 | ||
e0c201f3 PK |
1096 | /* |
1097 | * We support OTG, Peripheral only and Host only configurations. In case | |
1098 | * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen | |
1099 | * via Id pin status or user request (debugfs). Id/BSV interrupts are not | |
1100 | * enabled when switch is controlled by user and default mode is supplied | |
1101 | * by board file, which can be changed by userspace later. | |
1102 | */ | |
1103 | static void msm_otg_init_sm(struct msm_otg *motg) | |
1104 | { | |
1105 | struct msm_otg_platform_data *pdata = motg->pdata; | |
1106 | u32 otgsc = readl(USB_OTGSC); | |
1107 | ||
1108 | switch (pdata->mode) { | |
1109 | case USB_OTG: | |
1110 | if (pdata->otg_control == OTG_PHY_CONTROL) { | |
1111 | if (otgsc & OTGSC_ID) | |
1112 | set_bit(ID, &motg->inputs); | |
1113 | else | |
1114 | clear_bit(ID, &motg->inputs); | |
1115 | ||
1116 | if (otgsc & OTGSC_BSV) | |
1117 | set_bit(B_SESS_VLD, &motg->inputs); | |
1118 | else | |
1119 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1120 | } else if (pdata->otg_control == OTG_USER_CONTROL) { | |
1121 | if (pdata->default_mode == USB_HOST) { | |
1122 | clear_bit(ID, &motg->inputs); | |
1123 | } else if (pdata->default_mode == USB_PERIPHERAL) { | |
1124 | set_bit(ID, &motg->inputs); | |
1125 | set_bit(B_SESS_VLD, &motg->inputs); | |
1126 | } else { | |
1127 | set_bit(ID, &motg->inputs); | |
1128 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1129 | } | |
1130 | } | |
1131 | break; | |
1132 | case USB_HOST: | |
1133 | clear_bit(ID, &motg->inputs); | |
1134 | break; | |
1135 | case USB_PERIPHERAL: | |
1136 | set_bit(ID, &motg->inputs); | |
1137 | if (otgsc & OTGSC_BSV) | |
1138 | set_bit(B_SESS_VLD, &motg->inputs); | |
1139 | else | |
1140 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1141 | break; | |
1142 | default: | |
1143 | break; | |
1144 | } | |
1145 | } | |
1146 | ||
1147 | static void msm_otg_sm_work(struct work_struct *w) | |
1148 | { | |
1149 | struct msm_otg *motg = container_of(w, struct msm_otg, sm_work); | |
1d4c9293 | 1150 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1151 | |
1d4c9293 | 1152 | switch (otg->phy->state) { |
e0c201f3 | 1153 | case OTG_STATE_UNDEFINED: |
1d4c9293 HK |
1154 | dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n"); |
1155 | msm_otg_reset(otg->phy); | |
e0c201f3 | 1156 | msm_otg_init_sm(motg); |
1d4c9293 | 1157 | otg->phy->state = OTG_STATE_B_IDLE; |
e0c201f3 PK |
1158 | /* FALL THROUGH */ |
1159 | case OTG_STATE_B_IDLE: | |
1d4c9293 | 1160 | dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n"); |
e0c201f3 PK |
1161 | if (!test_bit(ID, &motg->inputs) && otg->host) { |
1162 | /* disable BSV bit */ | |
1163 | writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC); | |
1d4c9293 HK |
1164 | msm_otg_start_host(otg->phy, 1); |
1165 | otg->phy->state = OTG_STATE_A_HOST; | |
d860852e PK |
1166 | } else if (test_bit(B_SESS_VLD, &motg->inputs)) { |
1167 | switch (motg->chg_state) { | |
1168 | case USB_CHG_STATE_UNDEFINED: | |
1169 | msm_chg_detect_work(&motg->chg_work.work); | |
1170 | break; | |
1171 | case USB_CHG_STATE_DETECTED: | |
1172 | switch (motg->chg_type) { | |
1173 | case USB_DCP_CHARGER: | |
1174 | msm_otg_notify_charger(motg, | |
1175 | IDEV_CHG_MAX); | |
1176 | break; | |
1177 | case USB_CDP_CHARGER: | |
1178 | msm_otg_notify_charger(motg, | |
1179 | IDEV_CHG_MAX); | |
1d4c9293 HK |
1180 | msm_otg_start_peripheral(otg->phy, 1); |
1181 | otg->phy->state | |
1182 | = OTG_STATE_B_PERIPHERAL; | |
d860852e PK |
1183 | break; |
1184 | case USB_SDP_CHARGER: | |
1185 | msm_otg_notify_charger(motg, IUNIT); | |
1d4c9293 HK |
1186 | msm_otg_start_peripheral(otg->phy, 1); |
1187 | otg->phy->state | |
1188 | = OTG_STATE_B_PERIPHERAL; | |
d860852e PK |
1189 | break; |
1190 | default: | |
1191 | break; | |
1192 | } | |
1193 | break; | |
1194 | default: | |
1195 | break; | |
1196 | } | |
1197 | } else { | |
1198 | /* | |
1199 | * If charger detection work is pending, decrement | |
1200 | * the pm usage counter to balance with the one that | |
1201 | * is incremented in charger detection work. | |
1202 | */ | |
1203 | if (cancel_delayed_work_sync(&motg->chg_work)) { | |
1d4c9293 HK |
1204 | pm_runtime_put_sync(otg->phy->dev); |
1205 | msm_otg_reset(otg->phy); | |
d860852e PK |
1206 | } |
1207 | msm_otg_notify_charger(motg, 0); | |
1208 | motg->chg_state = USB_CHG_STATE_UNDEFINED; | |
1209 | motg->chg_type = USB_INVALID_CHARGER; | |
e0c201f3 | 1210 | } |
1d4c9293 | 1211 | pm_runtime_put_sync(otg->phy->dev); |
e0c201f3 PK |
1212 | break; |
1213 | case OTG_STATE_B_PERIPHERAL: | |
1d4c9293 | 1214 | dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n"); |
e0c201f3 PK |
1215 | if (!test_bit(B_SESS_VLD, &motg->inputs) || |
1216 | !test_bit(ID, &motg->inputs)) { | |
d860852e | 1217 | msm_otg_notify_charger(motg, 0); |
1d4c9293 | 1218 | msm_otg_start_peripheral(otg->phy, 0); |
d860852e PK |
1219 | motg->chg_state = USB_CHG_STATE_UNDEFINED; |
1220 | motg->chg_type = USB_INVALID_CHARGER; | |
1d4c9293 HK |
1221 | otg->phy->state = OTG_STATE_B_IDLE; |
1222 | msm_otg_reset(otg->phy); | |
e0c201f3 PK |
1223 | schedule_work(w); |
1224 | } | |
1225 | break; | |
1226 | case OTG_STATE_A_HOST: | |
1d4c9293 | 1227 | dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n"); |
e0c201f3 | 1228 | if (test_bit(ID, &motg->inputs)) { |
1d4c9293 HK |
1229 | msm_otg_start_host(otg->phy, 0); |
1230 | otg->phy->state = OTG_STATE_B_IDLE; | |
1231 | msm_otg_reset(otg->phy); | |
e0c201f3 PK |
1232 | schedule_work(w); |
1233 | } | |
1234 | break; | |
1235 | default: | |
1236 | break; | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | static irqreturn_t msm_otg_irq(int irq, void *data) | |
1241 | { | |
1242 | struct msm_otg *motg = data; | |
1d4c9293 | 1243 | struct usb_phy *phy = &motg->phy; |
e0c201f3 PK |
1244 | u32 otgsc = 0; |
1245 | ||
87c0104a PK |
1246 | if (atomic_read(&motg->in_lpm)) { |
1247 | disable_irq_nosync(irq); | |
1248 | motg->async_int = 1; | |
1d4c9293 | 1249 | pm_runtime_get(phy->dev); |
87c0104a PK |
1250 | return IRQ_HANDLED; |
1251 | } | |
1252 | ||
e0c201f3 PK |
1253 | otgsc = readl(USB_OTGSC); |
1254 | if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS))) | |
1255 | return IRQ_NONE; | |
1256 | ||
1257 | if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) { | |
1258 | if (otgsc & OTGSC_ID) | |
1259 | set_bit(ID, &motg->inputs); | |
1260 | else | |
1261 | clear_bit(ID, &motg->inputs); | |
1d4c9293 HK |
1262 | dev_dbg(phy->dev, "ID set/clear\n"); |
1263 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1264 | } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) { |
1265 | if (otgsc & OTGSC_BSV) | |
1266 | set_bit(B_SESS_VLD, &motg->inputs); | |
1267 | else | |
1268 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1d4c9293 HK |
1269 | dev_dbg(phy->dev, "BSV set/clear\n"); |
1270 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1271 | } |
1272 | ||
1273 | writel(otgsc, USB_OTGSC); | |
1274 | schedule_work(&motg->sm_work); | |
1275 | return IRQ_HANDLED; | |
1276 | } | |
1277 | ||
1278 | static int msm_otg_mode_show(struct seq_file *s, void *unused) | |
1279 | { | |
1280 | struct msm_otg *motg = s->private; | |
1d4c9293 | 1281 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1282 | |
1d4c9293 | 1283 | switch (otg->phy->state) { |
e0c201f3 PK |
1284 | case OTG_STATE_A_HOST: |
1285 | seq_printf(s, "host\n"); | |
1286 | break; | |
1287 | case OTG_STATE_B_PERIPHERAL: | |
1288 | seq_printf(s, "peripheral\n"); | |
1289 | break; | |
1290 | default: | |
1291 | seq_printf(s, "none\n"); | |
1292 | break; | |
1293 | } | |
1294 | ||
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | static int msm_otg_mode_open(struct inode *inode, struct file *file) | |
1299 | { | |
1300 | return single_open(file, msm_otg_mode_show, inode->i_private); | |
1301 | } | |
1302 | ||
1303 | static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, | |
1304 | size_t count, loff_t *ppos) | |
1305 | { | |
e2904ee4 PK |
1306 | struct seq_file *s = file->private_data; |
1307 | struct msm_otg *motg = s->private; | |
e0c201f3 | 1308 | char buf[16]; |
1d4c9293 | 1309 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 PK |
1310 | int status = count; |
1311 | enum usb_mode_type req_mode; | |
1312 | ||
1313 | memset(buf, 0x00, sizeof(buf)); | |
1314 | ||
1315 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) { | |
1316 | status = -EFAULT; | |
1317 | goto out; | |
1318 | } | |
1319 | ||
1320 | if (!strncmp(buf, "host", 4)) { | |
1321 | req_mode = USB_HOST; | |
1322 | } else if (!strncmp(buf, "peripheral", 10)) { | |
1323 | req_mode = USB_PERIPHERAL; | |
1324 | } else if (!strncmp(buf, "none", 4)) { | |
1325 | req_mode = USB_NONE; | |
1326 | } else { | |
1327 | status = -EINVAL; | |
1328 | goto out; | |
1329 | } | |
1330 | ||
1331 | switch (req_mode) { | |
1332 | case USB_NONE: | |
1d4c9293 | 1333 | switch (otg->phy->state) { |
e0c201f3 PK |
1334 | case OTG_STATE_A_HOST: |
1335 | case OTG_STATE_B_PERIPHERAL: | |
1336 | set_bit(ID, &motg->inputs); | |
1337 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1338 | break; | |
1339 | default: | |
1340 | goto out; | |
1341 | } | |
1342 | break; | |
1343 | case USB_PERIPHERAL: | |
1d4c9293 | 1344 | switch (otg->phy->state) { |
e0c201f3 PK |
1345 | case OTG_STATE_B_IDLE: |
1346 | case OTG_STATE_A_HOST: | |
1347 | set_bit(ID, &motg->inputs); | |
1348 | set_bit(B_SESS_VLD, &motg->inputs); | |
1349 | break; | |
1350 | default: | |
1351 | goto out; | |
1352 | } | |
1353 | break; | |
1354 | case USB_HOST: | |
1d4c9293 | 1355 | switch (otg->phy->state) { |
e0c201f3 PK |
1356 | case OTG_STATE_B_IDLE: |
1357 | case OTG_STATE_B_PERIPHERAL: | |
1358 | clear_bit(ID, &motg->inputs); | |
1359 | break; | |
1360 | default: | |
1361 | goto out; | |
1362 | } | |
1363 | break; | |
1364 | default: | |
1365 | goto out; | |
1366 | } | |
1367 | ||
1d4c9293 | 1368 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 PK |
1369 | schedule_work(&motg->sm_work); |
1370 | out: | |
1371 | return status; | |
1372 | } | |
1373 | ||
1374 | const struct file_operations msm_otg_mode_fops = { | |
1375 | .open = msm_otg_mode_open, | |
1376 | .read = seq_read, | |
1377 | .write = msm_otg_mode_write, | |
1378 | .llseek = seq_lseek, | |
1379 | .release = single_release, | |
1380 | }; | |
1381 | ||
1382 | static struct dentry *msm_otg_dbg_root; | |
1383 | static struct dentry *msm_otg_dbg_mode; | |
1384 | ||
1385 | static int msm_otg_debugfs_init(struct msm_otg *motg) | |
1386 | { | |
1387 | msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL); | |
1388 | ||
1389 | if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root)) | |
1390 | return -ENODEV; | |
1391 | ||
1392 | msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR, | |
1393 | msm_otg_dbg_root, motg, &msm_otg_mode_fops); | |
1394 | if (!msm_otg_dbg_mode) { | |
1395 | debugfs_remove(msm_otg_dbg_root); | |
1396 | msm_otg_dbg_root = NULL; | |
1397 | return -ENODEV; | |
1398 | } | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
1403 | static void msm_otg_debugfs_cleanup(void) | |
1404 | { | |
1405 | debugfs_remove(msm_otg_dbg_mode); | |
1406 | debugfs_remove(msm_otg_dbg_root); | |
1407 | } | |
1408 | ||
1409 | static int __init msm_otg_probe(struct platform_device *pdev) | |
1410 | { | |
1411 | int ret = 0; | |
1412 | struct resource *res; | |
1413 | struct msm_otg *motg; | |
1d4c9293 | 1414 | struct usb_phy *phy; |
e0c201f3 PK |
1415 | |
1416 | dev_info(&pdev->dev, "msm_otg probe\n"); | |
19f9e188 | 1417 | if (!dev_get_platdata(&pdev->dev)) { |
e0c201f3 PK |
1418 | dev_err(&pdev->dev, "No platform data given. Bailing out\n"); |
1419 | return -ENODEV; | |
1420 | } | |
1421 | ||
1422 | motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL); | |
1423 | if (!motg) { | |
1424 | dev_err(&pdev->dev, "unable to allocate msm_otg\n"); | |
1425 | return -ENOMEM; | |
1426 | } | |
1427 | ||
1d4c9293 HK |
1428 | motg->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); |
1429 | if (!motg->phy.otg) { | |
1430 | dev_err(&pdev->dev, "unable to allocate msm_otg\n"); | |
5c73e740 DC |
1431 | ret = -ENOMEM; |
1432 | goto free_motg; | |
1d4c9293 HK |
1433 | } |
1434 | ||
19f9e188 | 1435 | motg->pdata = dev_get_platdata(&pdev->dev); |
1d4c9293 HK |
1436 | phy = &motg->phy; |
1437 | phy->dev = &pdev->dev; | |
e0c201f3 PK |
1438 | |
1439 | motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk"); | |
1440 | if (IS_ERR(motg->phy_reset_clk)) { | |
1441 | dev_err(&pdev->dev, "failed to get usb_phy_clk\n"); | |
1442 | ret = PTR_ERR(motg->phy_reset_clk); | |
1443 | goto free_motg; | |
1444 | } | |
1445 | ||
1446 | motg->clk = clk_get(&pdev->dev, "usb_hs_clk"); | |
1447 | if (IS_ERR(motg->clk)) { | |
1448 | dev_err(&pdev->dev, "failed to get usb_hs_clk\n"); | |
1449 | ret = PTR_ERR(motg->clk); | |
1450 | goto put_phy_reset_clk; | |
1451 | } | |
0f73cac8 A |
1452 | clk_set_rate(motg->clk, 60000000); |
1453 | ||
1454 | /* | |
1455 | * If USB Core is running its protocol engine based on CORE CLK, | |
1456 | * CORE CLK must be running at >55Mhz for correct HSUSB | |
1457 | * operation and USB core cannot tolerate frequency changes on | |
1458 | * CORE CLK. For such USB cores, vote for maximum clk frequency | |
1459 | * on pclk source | |
1460 | */ | |
1461 | if (motg->pdata->pclk_src_name) { | |
1462 | motg->pclk_src = clk_get(&pdev->dev, | |
1463 | motg->pdata->pclk_src_name); | |
1464 | if (IS_ERR(motg->pclk_src)) | |
1465 | goto put_clk; | |
1466 | clk_set_rate(motg->pclk_src, INT_MAX); | |
b99a8f62 | 1467 | clk_prepare_enable(motg->pclk_src); |
0f73cac8 A |
1468 | } else |
1469 | motg->pclk_src = ERR_PTR(-ENOENT); | |
1470 | ||
e0c201f3 PK |
1471 | |
1472 | motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk"); | |
1473 | if (IS_ERR(motg->pclk)) { | |
1474 | dev_err(&pdev->dev, "failed to get usb_hs_pclk\n"); | |
1475 | ret = PTR_ERR(motg->pclk); | |
0f73cac8 | 1476 | goto put_pclk_src; |
e0c201f3 PK |
1477 | } |
1478 | ||
1479 | /* | |
1480 | * USB core clock is not present on all MSM chips. This | |
1481 | * clock is introduced to remove the dependency on AXI | |
1482 | * bus frequency. | |
1483 | */ | |
1484 | motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk"); | |
1485 | if (IS_ERR(motg->core_clk)) | |
1486 | motg->core_clk = NULL; | |
1487 | ||
1488 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1489 | if (!res) { | |
1490 | dev_err(&pdev->dev, "failed to get platform resource mem\n"); | |
1491 | ret = -ENODEV; | |
1492 | goto put_core_clk; | |
1493 | } | |
1494 | ||
1495 | motg->regs = ioremap(res->start, resource_size(res)); | |
1496 | if (!motg->regs) { | |
1497 | dev_err(&pdev->dev, "ioremap failed\n"); | |
1498 | ret = -ENOMEM; | |
1499 | goto put_core_clk; | |
1500 | } | |
1501 | dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); | |
1502 | ||
1503 | motg->irq = platform_get_irq(pdev, 0); | |
1504 | if (!motg->irq) { | |
1505 | dev_err(&pdev->dev, "platform_get_irq failed\n"); | |
1506 | ret = -ENODEV; | |
1507 | goto free_regs; | |
1508 | } | |
1509 | ||
b99a8f62 SB |
1510 | clk_prepare_enable(motg->clk); |
1511 | clk_prepare_enable(motg->pclk); | |
11aa5c47 A |
1512 | |
1513 | ret = msm_hsusb_init_vddcx(motg, 1); | |
1514 | if (ret) { | |
1515 | dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); | |
1516 | goto free_regs; | |
1517 | } | |
1518 | ||
1519 | ret = msm_hsusb_ldo_init(motg, 1); | |
1520 | if (ret) { | |
1521 | dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); | |
1522 | goto vddcx_exit; | |
1523 | } | |
1524 | ret = msm_hsusb_ldo_set_mode(1); | |
1525 | if (ret) { | |
1526 | dev_err(&pdev->dev, "hsusb vreg enable failed\n"); | |
1527 | goto ldo_exit; | |
1528 | } | |
1529 | ||
e0c201f3 | 1530 | if (motg->core_clk) |
b99a8f62 | 1531 | clk_prepare_enable(motg->core_clk); |
e0c201f3 PK |
1532 | |
1533 | writel(0, USB_USBINTR); | |
1534 | writel(0, USB_OTGSC); | |
1535 | ||
1536 | INIT_WORK(&motg->sm_work, msm_otg_sm_work); | |
d860852e | 1537 | INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work); |
e0c201f3 PK |
1538 | ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED, |
1539 | "msm_otg", motg); | |
1540 | if (ret) { | |
1541 | dev_err(&pdev->dev, "request irq failed\n"); | |
1542 | goto disable_clks; | |
1543 | } | |
1544 | ||
1d4c9293 HK |
1545 | phy->init = msm_otg_reset; |
1546 | phy->set_power = msm_otg_set_power; | |
1547 | ||
1548 | phy->io_ops = &msm_otg_io_ops; | |
e0c201f3 | 1549 | |
1d4c9293 HK |
1550 | phy->otg->phy = &motg->phy; |
1551 | phy->otg->set_host = msm_otg_set_host; | |
1552 | phy->otg->set_peripheral = msm_otg_set_peripheral; | |
e0c201f3 | 1553 | |
662dca54 | 1554 | ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2); |
e0c201f3 | 1555 | if (ret) { |
721002ec | 1556 | dev_err(&pdev->dev, "usb_add_phy failed\n"); |
e0c201f3 PK |
1557 | goto free_irq; |
1558 | } | |
1559 | ||
1560 | platform_set_drvdata(pdev, motg); | |
1561 | device_init_wakeup(&pdev->dev, 1); | |
1562 | ||
1563 | if (motg->pdata->mode == USB_OTG && | |
1564 | motg->pdata->otg_control == OTG_USER_CONTROL) { | |
1565 | ret = msm_otg_debugfs_init(motg); | |
1566 | if (ret) | |
1567 | dev_dbg(&pdev->dev, "mode debugfs file is" | |
1568 | "not available\n"); | |
1569 | } | |
1570 | ||
87c0104a PK |
1571 | pm_runtime_set_active(&pdev->dev); |
1572 | pm_runtime_enable(&pdev->dev); | |
e0c201f3 | 1573 | |
87c0104a | 1574 | return 0; |
e0c201f3 PK |
1575 | free_irq: |
1576 | free_irq(motg->irq, motg); | |
1577 | disable_clks: | |
b99a8f62 SB |
1578 | clk_disable_unprepare(motg->pclk); |
1579 | clk_disable_unprepare(motg->clk); | |
11aa5c47 A |
1580 | ldo_exit: |
1581 | msm_hsusb_ldo_init(motg, 0); | |
1582 | vddcx_exit: | |
1583 | msm_hsusb_init_vddcx(motg, 0); | |
e0c201f3 PK |
1584 | free_regs: |
1585 | iounmap(motg->regs); | |
1586 | put_core_clk: | |
1587 | if (motg->core_clk) | |
1588 | clk_put(motg->core_clk); | |
1589 | clk_put(motg->pclk); | |
0f73cac8 A |
1590 | put_pclk_src: |
1591 | if (!IS_ERR(motg->pclk_src)) { | |
b99a8f62 | 1592 | clk_disable_unprepare(motg->pclk_src); |
0f73cac8 A |
1593 | clk_put(motg->pclk_src); |
1594 | } | |
e0c201f3 PK |
1595 | put_clk: |
1596 | clk_put(motg->clk); | |
1597 | put_phy_reset_clk: | |
1598 | clk_put(motg->phy_reset_clk); | |
1599 | free_motg: | |
1d4c9293 | 1600 | kfree(motg->phy.otg); |
e0c201f3 PK |
1601 | kfree(motg); |
1602 | return ret; | |
1603 | } | |
1604 | ||
fb4e98ab | 1605 | static int msm_otg_remove(struct platform_device *pdev) |
e0c201f3 PK |
1606 | { |
1607 | struct msm_otg *motg = platform_get_drvdata(pdev); | |
1d4c9293 | 1608 | struct usb_phy *phy = &motg->phy; |
87c0104a | 1609 | int cnt = 0; |
e0c201f3 | 1610 | |
1d4c9293 | 1611 | if (phy->otg->host || phy->otg->gadget) |
e0c201f3 PK |
1612 | return -EBUSY; |
1613 | ||
1614 | msm_otg_debugfs_cleanup(); | |
d860852e | 1615 | cancel_delayed_work_sync(&motg->chg_work); |
e0c201f3 | 1616 | cancel_work_sync(&motg->sm_work); |
87c0104a | 1617 | |
7018773a | 1618 | pm_runtime_resume(&pdev->dev); |
87c0104a | 1619 | |
e0c201f3 | 1620 | device_init_wakeup(&pdev->dev, 0); |
87c0104a | 1621 | pm_runtime_disable(&pdev->dev); |
e0c201f3 | 1622 | |
662dca54 | 1623 | usb_remove_phy(phy); |
e0c201f3 PK |
1624 | free_irq(motg->irq, motg); |
1625 | ||
87c0104a PK |
1626 | /* |
1627 | * Put PHY in low power mode. | |
1628 | */ | |
1d4c9293 HK |
1629 | ulpi_read(phy, 0x14); |
1630 | ulpi_write(phy, 0x08, 0x09); | |
87c0104a PK |
1631 | |
1632 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
1633 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
1634 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
1635 | break; | |
1636 | udelay(1); | |
1637 | cnt++; | |
1638 | } | |
1639 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) | |
1d4c9293 | 1640 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
87c0104a | 1641 | |
b99a8f62 SB |
1642 | clk_disable_unprepare(motg->pclk); |
1643 | clk_disable_unprepare(motg->clk); | |
e0c201f3 | 1644 | if (motg->core_clk) |
b99a8f62 | 1645 | clk_disable_unprepare(motg->core_clk); |
0f73cac8 | 1646 | if (!IS_ERR(motg->pclk_src)) { |
b99a8f62 | 1647 | clk_disable_unprepare(motg->pclk_src); |
0f73cac8 A |
1648 | clk_put(motg->pclk_src); |
1649 | } | |
11aa5c47 | 1650 | msm_hsusb_ldo_init(motg, 0); |
e0c201f3 PK |
1651 | |
1652 | iounmap(motg->regs); | |
87c0104a | 1653 | pm_runtime_set_suspended(&pdev->dev); |
e0c201f3 PK |
1654 | |
1655 | clk_put(motg->phy_reset_clk); | |
1656 | clk_put(motg->pclk); | |
1657 | clk_put(motg->clk); | |
1658 | if (motg->core_clk) | |
1659 | clk_put(motg->core_clk); | |
1660 | ||
1d4c9293 | 1661 | kfree(motg->phy.otg); |
e0c201f3 PK |
1662 | kfree(motg); |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
87c0104a PK |
1667 | #ifdef CONFIG_PM_RUNTIME |
1668 | static int msm_otg_runtime_idle(struct device *dev) | |
1669 | { | |
1670 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1d4c9293 | 1671 | struct usb_otg *otg = motg->phy.otg; |
87c0104a PK |
1672 | |
1673 | dev_dbg(dev, "OTG runtime idle\n"); | |
1674 | ||
1675 | /* | |
1676 | * It is observed some times that a spurious interrupt | |
1677 | * comes when PHY is put into LPM immediately after PHY reset. | |
1678 | * This 1 sec delay also prevents entering into LPM immediately | |
1679 | * after asynchronous interrupt. | |
1680 | */ | |
1d4c9293 | 1681 | if (otg->phy->state != OTG_STATE_UNDEFINED) |
87c0104a PK |
1682 | pm_schedule_suspend(dev, 1000); |
1683 | ||
1684 | return -EAGAIN; | |
1685 | } | |
1686 | ||
1687 | static int msm_otg_runtime_suspend(struct device *dev) | |
1688 | { | |
1689 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1690 | ||
1691 | dev_dbg(dev, "OTG runtime suspend\n"); | |
1692 | return msm_otg_suspend(motg); | |
1693 | } | |
1694 | ||
1695 | static int msm_otg_runtime_resume(struct device *dev) | |
1696 | { | |
1697 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1698 | ||
1699 | dev_dbg(dev, "OTG runtime resume\n"); | |
1700 | return msm_otg_resume(motg); | |
1701 | } | |
87c0104a PK |
1702 | #endif |
1703 | ||
7018773a | 1704 | #ifdef CONFIG_PM_SLEEP |
87c0104a PK |
1705 | static int msm_otg_pm_suspend(struct device *dev) |
1706 | { | |
1707 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1708 | ||
1709 | dev_dbg(dev, "OTG PM suspend\n"); | |
1710 | return msm_otg_suspend(motg); | |
1711 | } | |
1712 | ||
1713 | static int msm_otg_pm_resume(struct device *dev) | |
1714 | { | |
1715 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1716 | int ret; | |
1717 | ||
1718 | dev_dbg(dev, "OTG PM resume\n"); | |
1719 | ||
1720 | ret = msm_otg_resume(motg); | |
1721 | if (ret) | |
1722 | return ret; | |
1723 | ||
1724 | /* | |
1725 | * Runtime PM Documentation recommends bringing the | |
1726 | * device to full powered state upon resume. | |
1727 | */ | |
1728 | pm_runtime_disable(dev); | |
1729 | pm_runtime_set_active(dev); | |
1730 | pm_runtime_enable(dev); | |
1731 | ||
1732 | return 0; | |
1733 | } | |
87c0104a PK |
1734 | #endif |
1735 | ||
1736 | static const struct dev_pm_ops msm_otg_dev_pm_ops = { | |
7018773a PK |
1737 | SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume) |
1738 | SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume, | |
1739 | msm_otg_runtime_idle) | |
87c0104a PK |
1740 | }; |
1741 | ||
e0c201f3 | 1742 | static struct platform_driver msm_otg_driver = { |
7690417d | 1743 | .remove = msm_otg_remove, |
e0c201f3 PK |
1744 | .driver = { |
1745 | .name = DRIVER_NAME, | |
1746 | .owner = THIS_MODULE, | |
87c0104a | 1747 | .pm = &msm_otg_dev_pm_ops, |
e0c201f3 PK |
1748 | }, |
1749 | }; | |
1750 | ||
52f7a82b | 1751 | module_platform_driver_probe(msm_otg_driver, msm_otg_probe); |
e0c201f3 PK |
1752 | |
1753 | MODULE_LICENSE("GPL v2"); | |
1754 | MODULE_DESCRIPTION("MSM USB transceiver driver"); |