Commit | Line | Data |
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d860852e | 1 | /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. |
e0c201f3 PK |
2 | * |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/uaccess.h> | |
30 | #include <linux/debugfs.h> | |
31 | #include <linux/seq_file.h> | |
87c0104a | 32 | #include <linux/pm_runtime.h> |
8364f9af II |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
e0c201f3 PK |
35 | |
36 | #include <linux/usb.h> | |
37 | #include <linux/usb/otg.h> | |
8364f9af | 38 | #include <linux/usb/of.h> |
e0c201f3 PK |
39 | #include <linux/usb/ulpi.h> |
40 | #include <linux/usb/gadget.h> | |
41 | #include <linux/usb/hcd.h> | |
42 | #include <linux/usb/msm_hsusb.h> | |
43 | #include <linux/usb/msm_hsusb_hw.h> | |
11aa5c47 | 44 | #include <linux/regulator/consumer.h> |
e0c201f3 | 45 | |
e0c201f3 PK |
46 | #define MSM_USB_BASE (motg->regs) |
47 | #define DRIVER_NAME "msm_otg" | |
48 | ||
49 | #define ULPI_IO_TIMEOUT_USEC (10 * 1000) | |
11aa5c47 A |
50 | |
51 | #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */ | |
52 | #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */ | |
53 | #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */ | |
54 | #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */ | |
55 | ||
56 | #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */ | |
57 | #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */ | |
58 | #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */ | |
59 | #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */ | |
60 | ||
61 | #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */ | |
62 | #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */ | |
63 | ||
11aa5c47 A |
64 | static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init) |
65 | { | |
66 | int ret = 0; | |
67 | ||
68 | if (init) { | |
37cfdaf7 | 69 | ret = regulator_set_voltage(motg->vddcx, |
11aa5c47 A |
70 | USB_PHY_VDD_DIG_VOL_MIN, |
71 | USB_PHY_VDD_DIG_VOL_MAX); | |
72 | if (ret) { | |
3aca0fa9 | 73 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
11aa5c47 A |
74 | return ret; |
75 | } | |
76 | ||
37cfdaf7 | 77 | ret = regulator_enable(motg->vddcx); |
6b99c68e | 78 | if (ret) |
1d4c9293 | 79 | dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n"); |
11aa5c47 | 80 | } else { |
37cfdaf7 | 81 | ret = regulator_set_voltage(motg->vddcx, 0, |
7b521fcb | 82 | USB_PHY_VDD_DIG_VOL_MAX); |
e99c4309 | 83 | if (ret) |
3aca0fa9 | 84 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
37cfdaf7 | 85 | ret = regulator_disable(motg->vddcx); |
11aa5c47 | 86 | if (ret) |
1d4c9293 | 87 | dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n"); |
11aa5c47 A |
88 | } |
89 | ||
90 | return ret; | |
91 | } | |
92 | ||
93 | static int msm_hsusb_ldo_init(struct msm_otg *motg, int init) | |
94 | { | |
95 | int rc = 0; | |
96 | ||
97 | if (init) { | |
37cfdaf7 | 98 | rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN, |
11aa5c47 A |
99 | USB_PHY_3P3_VOL_MAX); |
100 | if (rc) { | |
3aca0fa9 | 101 | dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n"); |
6b99c68e | 102 | goto exit; |
11aa5c47 | 103 | } |
37cfdaf7 | 104 | rc = regulator_enable(motg->v3p3); |
11aa5c47 | 105 | if (rc) { |
1d4c9293 | 106 | dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n"); |
6b99c68e | 107 | goto exit; |
11aa5c47 | 108 | } |
37cfdaf7 | 109 | rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN, |
11aa5c47 A |
110 | USB_PHY_1P8_VOL_MAX); |
111 | if (rc) { | |
3aca0fa9 | 112 | dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n"); |
6b99c68e | 113 | goto disable_3p3; |
11aa5c47 | 114 | } |
37cfdaf7 | 115 | rc = regulator_enable(motg->v1p8); |
11aa5c47 | 116 | if (rc) { |
1d4c9293 | 117 | dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n"); |
6b99c68e | 118 | goto disable_3p3; |
11aa5c47 A |
119 | } |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
37cfdaf7 | 124 | regulator_disable(motg->v1p8); |
11aa5c47 | 125 | disable_3p3: |
37cfdaf7 | 126 | regulator_disable(motg->v3p3); |
6b99c68e | 127 | exit: |
11aa5c47 A |
128 | return rc; |
129 | } | |
130 | ||
37cfdaf7 | 131 | static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on) |
11aa5c47 A |
132 | { |
133 | int ret = 0; | |
134 | ||
11aa5c47 | 135 | if (on) { |
37cfdaf7 | 136 | ret = regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
137 | USB_PHY_1P8_HPM_LOAD); |
138 | if (ret < 0) { | |
3aca0fa9 | 139 | pr_err("Could not set HPM for v1p8\n"); |
11aa5c47 A |
140 | return ret; |
141 | } | |
37cfdaf7 | 142 | ret = regulator_set_optimum_mode(motg->v3p3, |
11aa5c47 A |
143 | USB_PHY_3P3_HPM_LOAD); |
144 | if (ret < 0) { | |
3aca0fa9 | 145 | pr_err("Could not set HPM for v3p3\n"); |
37cfdaf7 | 146 | regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
147 | USB_PHY_1P8_LPM_LOAD); |
148 | return ret; | |
149 | } | |
150 | } else { | |
37cfdaf7 | 151 | ret = regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
152 | USB_PHY_1P8_LPM_LOAD); |
153 | if (ret < 0) | |
3aca0fa9 | 154 | pr_err("Could not set LPM for v1p8\n"); |
37cfdaf7 | 155 | ret = regulator_set_optimum_mode(motg->v3p3, |
11aa5c47 A |
156 | USB_PHY_3P3_LPM_LOAD); |
157 | if (ret < 0) | |
3aca0fa9 | 158 | pr_err("Could not set LPM for v3p3\n"); |
11aa5c47 A |
159 | } |
160 | ||
161 | pr_debug("reg (%s)\n", on ? "HPM" : "LPM"); | |
162 | return ret < 0 ? ret : 0; | |
163 | } | |
164 | ||
1d4c9293 | 165 | static int ulpi_read(struct usb_phy *phy, u32 reg) |
e0c201f3 | 166 | { |
1d4c9293 | 167 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
168 | int cnt = 0; |
169 | ||
170 | /* initiate read operation */ | |
171 | writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg), | |
172 | USB_ULPI_VIEWPORT); | |
173 | ||
174 | /* wait for completion */ | |
175 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
176 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
177 | break; | |
178 | udelay(1); | |
179 | cnt++; | |
180 | } | |
181 | ||
182 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 183 | dev_err(phy->dev, "ulpi_read: timeout %08x\n", |
e0c201f3 PK |
184 | readl(USB_ULPI_VIEWPORT)); |
185 | return -ETIMEDOUT; | |
186 | } | |
187 | return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT)); | |
188 | } | |
189 | ||
1d4c9293 | 190 | static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
e0c201f3 | 191 | { |
1d4c9293 | 192 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
193 | int cnt = 0; |
194 | ||
195 | /* initiate write operation */ | |
196 | writel(ULPI_RUN | ULPI_WRITE | | |
197 | ULPI_ADDR(reg) | ULPI_DATA(val), | |
198 | USB_ULPI_VIEWPORT); | |
199 | ||
200 | /* wait for completion */ | |
201 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
202 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
203 | break; | |
204 | udelay(1); | |
205 | cnt++; | |
206 | } | |
207 | ||
208 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 209 | dev_err(phy->dev, "ulpi_write: timeout\n"); |
e0c201f3 PK |
210 | return -ETIMEDOUT; |
211 | } | |
212 | return 0; | |
213 | } | |
214 | ||
1d4c9293 | 215 | static struct usb_phy_io_ops msm_otg_io_ops = { |
e0c201f3 PK |
216 | .read = ulpi_read, |
217 | .write = ulpi_write, | |
218 | }; | |
219 | ||
220 | static void ulpi_init(struct msm_otg *motg) | |
221 | { | |
222 | struct msm_otg_platform_data *pdata = motg->pdata; | |
8364f9af II |
223 | int *seq = pdata->phy_init_seq, idx; |
224 | u32 addr = ULPI_EXT_VENDOR_SPECIFIC; | |
e0c201f3 | 225 | |
8364f9af II |
226 | for (idx = 0; idx < pdata->phy_init_sz; idx++) { |
227 | if (seq[idx] == -1) | |
228 | continue; | |
e0c201f3 | 229 | |
1d4c9293 | 230 | dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n", |
8364f9af II |
231 | seq[idx], addr + idx); |
232 | ulpi_write(&motg->phy, seq[idx], addr + idx); | |
e0c201f3 PK |
233 | } |
234 | } | |
235 | ||
236 | static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) | |
237 | { | |
5146d771 II |
238 | int ret = 0; |
239 | ||
240 | if (!motg->pdata->link_clk_reset) | |
241 | return ret; | |
242 | ||
243 | ret = motg->pdata->link_clk_reset(motg->clk, assert); | |
244 | if (ret) | |
245 | dev_err(motg->phy.dev, "usb link clk reset %s failed\n", | |
246 | assert ? "assert" : "deassert"); | |
e0c201f3 | 247 | |
e0c201f3 PK |
248 | return ret; |
249 | } | |
250 | ||
251 | static int msm_otg_phy_clk_reset(struct msm_otg *motg) | |
252 | { | |
5146d771 | 253 | int ret = 0; |
e0c201f3 | 254 | |
5146d771 | 255 | if (!motg->pdata->phy_clk_reset) |
e0c201f3 | 256 | return ret; |
5146d771 II |
257 | |
258 | ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk); | |
e0c201f3 | 259 | if (ret) |
5146d771 II |
260 | dev_err(motg->phy.dev, "usb phy clk reset failed\n"); |
261 | ||
e0c201f3 PK |
262 | return ret; |
263 | } | |
264 | ||
265 | static int msm_otg_phy_reset(struct msm_otg *motg) | |
266 | { | |
267 | u32 val; | |
268 | int ret; | |
269 | int retries; | |
270 | ||
271 | ret = msm_otg_link_clk_reset(motg, 1); | |
272 | if (ret) | |
273 | return ret; | |
274 | ret = msm_otg_phy_clk_reset(motg); | |
275 | if (ret) | |
276 | return ret; | |
277 | ret = msm_otg_link_clk_reset(motg, 0); | |
278 | if (ret) | |
279 | return ret; | |
280 | ||
281 | val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK; | |
282 | writel(val | PORTSC_PTS_ULPI, USB_PORTSC); | |
283 | ||
284 | for (retries = 3; retries > 0; retries--) { | |
1d4c9293 | 285 | ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM, |
e0c201f3 PK |
286 | ULPI_CLR(ULPI_FUNC_CTRL)); |
287 | if (!ret) | |
288 | break; | |
289 | ret = msm_otg_phy_clk_reset(motg); | |
290 | if (ret) | |
291 | return ret; | |
292 | } | |
293 | if (!retries) | |
294 | return -ETIMEDOUT; | |
295 | ||
296 | /* This reset calibrates the phy, if the above write succeeded */ | |
297 | ret = msm_otg_phy_clk_reset(motg); | |
298 | if (ret) | |
299 | return ret; | |
300 | ||
301 | for (retries = 3; retries > 0; retries--) { | |
1d4c9293 | 302 | ret = ulpi_read(&motg->phy, ULPI_DEBUG); |
e0c201f3 PK |
303 | if (ret != -ETIMEDOUT) |
304 | break; | |
305 | ret = msm_otg_phy_clk_reset(motg); | |
306 | if (ret) | |
307 | return ret; | |
308 | } | |
309 | if (!retries) | |
310 | return -ETIMEDOUT; | |
311 | ||
1d4c9293 | 312 | dev_info(motg->phy.dev, "phy_reset: success\n"); |
e0c201f3 PK |
313 | return 0; |
314 | } | |
315 | ||
316 | #define LINK_RESET_TIMEOUT_USEC (250 * 1000) | |
1d4c9293 | 317 | static int msm_otg_reset(struct usb_phy *phy) |
e0c201f3 | 318 | { |
1d4c9293 | 319 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
320 | struct msm_otg_platform_data *pdata = motg->pdata; |
321 | int cnt = 0; | |
322 | int ret; | |
323 | u32 val = 0; | |
324 | u32 ulpi_val = 0; | |
325 | ||
326 | ret = msm_otg_phy_reset(motg); | |
327 | if (ret) { | |
1d4c9293 | 328 | dev_err(phy->dev, "phy_reset failed\n"); |
e0c201f3 PK |
329 | return ret; |
330 | } | |
331 | ||
332 | ulpi_init(motg); | |
333 | ||
334 | writel(USBCMD_RESET, USB_USBCMD); | |
335 | while (cnt < LINK_RESET_TIMEOUT_USEC) { | |
336 | if (!(readl(USB_USBCMD) & USBCMD_RESET)) | |
337 | break; | |
338 | udelay(1); | |
339 | cnt++; | |
340 | } | |
341 | if (cnt >= LINK_RESET_TIMEOUT_USEC) | |
342 | return -ETIMEDOUT; | |
343 | ||
344 | /* select ULPI phy */ | |
345 | writel(0x80000000, USB_PORTSC); | |
346 | ||
347 | msleep(100); | |
348 | ||
349 | writel(0x0, USB_AHBBURST); | |
350 | writel(0x00, USB_AHBMODE); | |
351 | ||
352 | if (pdata->otg_control == OTG_PHY_CONTROL) { | |
353 | val = readl(USB_OTGSC); | |
971232cf | 354 | if (pdata->mode == USB_DR_MODE_OTG) { |
e0c201f3 PK |
355 | ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; |
356 | val |= OTGSC_IDIE | OTGSC_BSVIE; | |
971232cf | 357 | } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) { |
e0c201f3 PK |
358 | ulpi_val = ULPI_INT_SESS_VALID; |
359 | val |= OTGSC_BSVIE; | |
360 | } | |
361 | writel(val, USB_OTGSC); | |
1d4c9293 HK |
362 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE); |
363 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); | |
e0c201f3 PK |
364 | } |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
87c0104a | 369 | #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000) |
7018773a PK |
370 | #define PHY_RESUME_TIMEOUT_USEC (100 * 1000) |
371 | ||
e7d613d1 JC |
372 | #ifdef CONFIG_PM |
373 | ||
374 | #define USB_PHY_SUSP_DIG_VOL 500000 | |
37cfdaf7 | 375 | static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high) |
e7d613d1 JC |
376 | { |
377 | int max_vol = USB_PHY_VDD_DIG_VOL_MAX; | |
378 | int min_vol; | |
379 | int ret; | |
380 | ||
381 | if (high) | |
382 | min_vol = USB_PHY_VDD_DIG_VOL_MIN; | |
383 | else | |
384 | min_vol = USB_PHY_SUSP_DIG_VOL; | |
385 | ||
37cfdaf7 | 386 | ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol); |
e7d613d1 | 387 | if (ret) { |
3aca0fa9 | 388 | pr_err("Cannot set vddcx voltage\n"); |
e7d613d1 JC |
389 | return ret; |
390 | } | |
391 | ||
392 | pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol); | |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
87c0104a PK |
397 | static int msm_otg_suspend(struct msm_otg *motg) |
398 | { | |
1d4c9293 HK |
399 | struct usb_phy *phy = &motg->phy; |
400 | struct usb_bus *bus = phy->otg->host; | |
87c0104a PK |
401 | struct msm_otg_platform_data *pdata = motg->pdata; |
402 | int cnt = 0; | |
403 | ||
404 | if (atomic_read(&motg->in_lpm)) | |
405 | return 0; | |
406 | ||
407 | disable_irq(motg->irq); | |
408 | /* | |
04aebcbb PK |
409 | * Chipidea 45-nm PHY suspend sequence: |
410 | * | |
87c0104a PK |
411 | * Interrupt Latch Register auto-clear feature is not present |
412 | * in all PHY versions. Latch register is clear on read type. | |
413 | * Clear latch register to avoid spurious wakeup from | |
414 | * low power mode (LPM). | |
04aebcbb | 415 | * |
87c0104a PK |
416 | * PHY comparators are disabled when PHY enters into low power |
417 | * mode (LPM). Keep PHY comparators ON in LPM only when we expect | |
418 | * VBUS/Id notifications from USB PHY. Otherwise turn off USB | |
419 | * PHY comparators. This save significant amount of power. | |
04aebcbb | 420 | * |
87c0104a PK |
421 | * PLL is not turned off when PHY enters into low power mode (LPM). |
422 | * Disable PLL for maximum power savings. | |
423 | */ | |
04aebcbb PK |
424 | |
425 | if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) { | |
1d4c9293 | 426 | ulpi_read(phy, 0x14); |
04aebcbb | 427 | if (pdata->otg_control == OTG_PHY_CONTROL) |
1d4c9293 HK |
428 | ulpi_write(phy, 0x01, 0x30); |
429 | ulpi_write(phy, 0x08, 0x09); | |
04aebcbb | 430 | } |
87c0104a PK |
431 | |
432 | /* | |
433 | * PHY may take some time or even fail to enter into low power | |
434 | * mode (LPM). Hence poll for 500 msec and reset the PHY and link | |
435 | * in failure case. | |
436 | */ | |
437 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
438 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
439 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
440 | break; | |
441 | udelay(1); | |
442 | cnt++; | |
443 | } | |
444 | ||
445 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) { | |
1d4c9293 HK |
446 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
447 | msm_otg_reset(phy); | |
87c0104a PK |
448 | enable_irq(motg->irq); |
449 | return -ETIMEDOUT; | |
450 | } | |
451 | ||
452 | /* | |
453 | * PHY has capability to generate interrupt asynchronously in low | |
454 | * power mode (LPM). This interrupt is level triggered. So USB IRQ | |
455 | * line must be disabled till async interrupt enable bit is cleared | |
456 | * in USBCMD register. Assert STP (ULPI interface STOP signal) to | |
457 | * block data communication from PHY. | |
458 | */ | |
459 | writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD); | |
460 | ||
04aebcbb PK |
461 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
462 | motg->pdata->otg_control == OTG_PMIC_CONTROL) | |
463 | writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL); | |
464 | ||
b99a8f62 SB |
465 | clk_disable_unprepare(motg->pclk); |
466 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 467 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 468 | clk_disable_unprepare(motg->core_clk); |
87c0104a | 469 | |
04aebcbb PK |
470 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
471 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
37cfdaf7 II |
472 | msm_hsusb_ldo_set_mode(motg, 0); |
473 | msm_hsusb_config_vddcx(motg, 0); | |
04aebcbb PK |
474 | } |
475 | ||
1d4c9293 | 476 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
477 | enable_irq_wake(motg->irq); |
478 | if (bus) | |
479 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
480 | ||
481 | atomic_set(&motg->in_lpm, 1); | |
482 | enable_irq(motg->irq); | |
483 | ||
1d4c9293 | 484 | dev_info(phy->dev, "USB in low power mode\n"); |
87c0104a PK |
485 | |
486 | return 0; | |
487 | } | |
488 | ||
87c0104a PK |
489 | static int msm_otg_resume(struct msm_otg *motg) |
490 | { | |
1d4c9293 HK |
491 | struct usb_phy *phy = &motg->phy; |
492 | struct usb_bus *bus = phy->otg->host; | |
87c0104a PK |
493 | int cnt = 0; |
494 | unsigned temp; | |
495 | ||
496 | if (!atomic_read(&motg->in_lpm)) | |
497 | return 0; | |
498 | ||
b99a8f62 SB |
499 | clk_prepare_enable(motg->pclk); |
500 | clk_prepare_enable(motg->clk); | |
6b99c68e | 501 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 502 | clk_prepare_enable(motg->core_clk); |
87c0104a | 503 | |
04aebcbb PK |
504 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
505 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
37cfdaf7 II |
506 | msm_hsusb_ldo_set_mode(motg, 1); |
507 | msm_hsusb_config_vddcx(motg, 1); | |
04aebcbb PK |
508 | writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL); |
509 | } | |
510 | ||
87c0104a PK |
511 | temp = readl(USB_USBCMD); |
512 | temp &= ~ASYNC_INTR_CTRL; | |
513 | temp &= ~ULPI_STP_CTRL; | |
514 | writel(temp, USB_USBCMD); | |
515 | ||
516 | /* | |
517 | * PHY comes out of low power mode (LPM) in case of wakeup | |
518 | * from asynchronous interrupt. | |
519 | */ | |
520 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
521 | goto skip_phy_resume; | |
522 | ||
523 | writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC); | |
524 | while (cnt < PHY_RESUME_TIMEOUT_USEC) { | |
525 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
526 | break; | |
527 | udelay(1); | |
528 | cnt++; | |
529 | } | |
530 | ||
531 | if (cnt >= PHY_RESUME_TIMEOUT_USEC) { | |
532 | /* | |
533 | * This is a fatal error. Reset the link and | |
534 | * PHY. USB state can not be restored. Re-insertion | |
535 | * of USB cable is the only way to get USB working. | |
536 | */ | |
3aca0fa9 | 537 | dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n"); |
1d4c9293 | 538 | msm_otg_reset(phy); |
87c0104a PK |
539 | } |
540 | ||
541 | skip_phy_resume: | |
1d4c9293 | 542 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
543 | disable_irq_wake(motg->irq); |
544 | if (bus) | |
545 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
546 | ||
2ce2c3ac PK |
547 | atomic_set(&motg->in_lpm, 0); |
548 | ||
87c0104a PK |
549 | if (motg->async_int) { |
550 | motg->async_int = 0; | |
1d4c9293 | 551 | pm_runtime_put(phy->dev); |
87c0104a PK |
552 | enable_irq(motg->irq); |
553 | } | |
554 | ||
1d4c9293 | 555 | dev_info(phy->dev, "USB exited from low power mode\n"); |
87c0104a PK |
556 | |
557 | return 0; | |
558 | } | |
7018773a | 559 | #endif |
87c0104a | 560 | |
d860852e PK |
561 | static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA) |
562 | { | |
563 | if (motg->cur_power == mA) | |
564 | return; | |
565 | ||
566 | /* TODO: Notify PMIC about available current */ | |
1d4c9293 | 567 | dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA); |
d860852e PK |
568 | motg->cur_power = mA; |
569 | } | |
570 | ||
1d4c9293 | 571 | static int msm_otg_set_power(struct usb_phy *phy, unsigned mA) |
d860852e | 572 | { |
1d4c9293 | 573 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
d860852e PK |
574 | |
575 | /* | |
576 | * Gadget driver uses set_power method to notify about the | |
577 | * available current based on suspend/configured states. | |
578 | * | |
579 | * IDEV_CHG can be drawn irrespective of suspend/un-configured | |
580 | * states when CDP/ACA is connected. | |
581 | */ | |
582 | if (motg->chg_type == USB_SDP_CHARGER) | |
583 | msm_otg_notify_charger(motg, mA); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
1d4c9293 | 588 | static void msm_otg_start_host(struct usb_phy *phy, int on) |
e0c201f3 | 589 | { |
1d4c9293 | 590 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
591 | struct msm_otg_platform_data *pdata = motg->pdata; |
592 | struct usb_hcd *hcd; | |
593 | ||
1d4c9293 | 594 | if (!phy->otg->host) |
e0c201f3 PK |
595 | return; |
596 | ||
1d4c9293 | 597 | hcd = bus_to_hcd(phy->otg->host); |
e0c201f3 PK |
598 | |
599 | if (on) { | |
1d4c9293 | 600 | dev_dbg(phy->dev, "host on\n"); |
e0c201f3 PK |
601 | |
602 | if (pdata->vbus_power) | |
603 | pdata->vbus_power(1); | |
604 | /* | |
605 | * Some boards have a switch cotrolled by gpio | |
606 | * to enable/disable internal HUB. Enable internal | |
607 | * HUB before kicking the host. | |
608 | */ | |
609 | if (pdata->setup_gpio) | |
610 | pdata->setup_gpio(OTG_STATE_A_HOST); | |
611 | #ifdef CONFIG_USB | |
612 | usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); | |
3c9740a1 | 613 | device_wakeup_enable(hcd->self.controller); |
e0c201f3 PK |
614 | #endif |
615 | } else { | |
1d4c9293 | 616 | dev_dbg(phy->dev, "host off\n"); |
e0c201f3 PK |
617 | |
618 | #ifdef CONFIG_USB | |
619 | usb_remove_hcd(hcd); | |
620 | #endif | |
621 | if (pdata->setup_gpio) | |
622 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
623 | if (pdata->vbus_power) | |
624 | pdata->vbus_power(0); | |
625 | } | |
626 | } | |
627 | ||
1d4c9293 | 628 | static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) |
e0c201f3 | 629 | { |
1d4c9293 | 630 | struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy); |
e0c201f3 PK |
631 | struct usb_hcd *hcd; |
632 | ||
633 | /* | |
634 | * Fail host registration if this board can support | |
635 | * only peripheral configuration. | |
636 | */ | |
971232cf | 637 | if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) { |
1d4c9293 | 638 | dev_info(otg->phy->dev, "Host mode is not supported\n"); |
e0c201f3 PK |
639 | return -ENODEV; |
640 | } | |
641 | ||
642 | if (!host) { | |
1d4c9293 HK |
643 | if (otg->phy->state == OTG_STATE_A_HOST) { |
644 | pm_runtime_get_sync(otg->phy->dev); | |
645 | msm_otg_start_host(otg->phy, 0); | |
e0c201f3 | 646 | otg->host = NULL; |
1d4c9293 | 647 | otg->phy->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
648 | schedule_work(&motg->sm_work); |
649 | } else { | |
650 | otg->host = NULL; | |
651 | } | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | hcd = bus_to_hcd(host); | |
657 | hcd->power_budget = motg->pdata->power_budget; | |
658 | ||
659 | otg->host = host; | |
1d4c9293 | 660 | dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n"); |
e0c201f3 PK |
661 | |
662 | /* | |
663 | * Kick the state machine work, if peripheral is not supported | |
664 | * or peripheral is already registered with us. | |
665 | */ | |
971232cf | 666 | if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) { |
1d4c9293 | 667 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 | 668 | schedule_work(&motg->sm_work); |
87c0104a | 669 | } |
e0c201f3 PK |
670 | |
671 | return 0; | |
672 | } | |
673 | ||
1d4c9293 | 674 | static void msm_otg_start_peripheral(struct usb_phy *phy, int on) |
e0c201f3 | 675 | { |
1d4c9293 | 676 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
677 | struct msm_otg_platform_data *pdata = motg->pdata; |
678 | ||
1d4c9293 | 679 | if (!phy->otg->gadget) |
e0c201f3 PK |
680 | return; |
681 | ||
682 | if (on) { | |
1d4c9293 | 683 | dev_dbg(phy->dev, "gadget on\n"); |
e0c201f3 PK |
684 | /* |
685 | * Some boards have a switch cotrolled by gpio | |
686 | * to enable/disable internal HUB. Disable internal | |
687 | * HUB before kicking the gadget. | |
688 | */ | |
689 | if (pdata->setup_gpio) | |
690 | pdata->setup_gpio(OTG_STATE_B_PERIPHERAL); | |
1d4c9293 | 691 | usb_gadget_vbus_connect(phy->otg->gadget); |
e0c201f3 | 692 | } else { |
1d4c9293 HK |
693 | dev_dbg(phy->dev, "gadget off\n"); |
694 | usb_gadget_vbus_disconnect(phy->otg->gadget); | |
e0c201f3 PK |
695 | if (pdata->setup_gpio) |
696 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
697 | } | |
698 | ||
699 | } | |
700 | ||
1d4c9293 HK |
701 | static int msm_otg_set_peripheral(struct usb_otg *otg, |
702 | struct usb_gadget *gadget) | |
e0c201f3 | 703 | { |
1d4c9293 | 704 | struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy); |
e0c201f3 PK |
705 | |
706 | /* | |
707 | * Fail peripheral registration if this board can support | |
708 | * only host configuration. | |
709 | */ | |
971232cf | 710 | if (motg->pdata->mode == USB_DR_MODE_HOST) { |
1d4c9293 | 711 | dev_info(otg->phy->dev, "Peripheral mode is not supported\n"); |
e0c201f3 PK |
712 | return -ENODEV; |
713 | } | |
714 | ||
715 | if (!gadget) { | |
1d4c9293 HK |
716 | if (otg->phy->state == OTG_STATE_B_PERIPHERAL) { |
717 | pm_runtime_get_sync(otg->phy->dev); | |
718 | msm_otg_start_peripheral(otg->phy, 0); | |
e0c201f3 | 719 | otg->gadget = NULL; |
1d4c9293 | 720 | otg->phy->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
721 | schedule_work(&motg->sm_work); |
722 | } else { | |
723 | otg->gadget = NULL; | |
724 | } | |
725 | ||
726 | return 0; | |
727 | } | |
728 | otg->gadget = gadget; | |
1d4c9293 | 729 | dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n"); |
e0c201f3 PK |
730 | |
731 | /* | |
732 | * Kick the state machine work, if host is not supported | |
733 | * or host is already registered with us. | |
734 | */ | |
971232cf | 735 | if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) { |
1d4c9293 | 736 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 | 737 | schedule_work(&motg->sm_work); |
87c0104a | 738 | } |
e0c201f3 PK |
739 | |
740 | return 0; | |
741 | } | |
742 | ||
d860852e PK |
743 | static bool msm_chg_check_secondary_det(struct msm_otg *motg) |
744 | { | |
1d4c9293 | 745 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
746 | u32 chg_det; |
747 | bool ret = false; | |
748 | ||
749 | switch (motg->pdata->phy_type) { | |
750 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 751 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
752 | ret = chg_det & (1 << 4); |
753 | break; | |
754 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 755 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
756 | ret = chg_det & 1; |
757 | break; | |
758 | default: | |
759 | break; | |
760 | } | |
761 | return ret; | |
762 | } | |
763 | ||
764 | static void msm_chg_enable_secondary_det(struct msm_otg *motg) | |
765 | { | |
1d4c9293 | 766 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
767 | u32 chg_det; |
768 | ||
769 | switch (motg->pdata->phy_type) { | |
770 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 771 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
772 | /* Turn off charger block */ |
773 | chg_det |= ~(1 << 1); | |
1d4c9293 | 774 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
775 | udelay(20); |
776 | /* control chg block via ULPI */ | |
777 | chg_det &= ~(1 << 3); | |
1d4c9293 | 778 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
779 | /* put it in host mode for enabling D- source */ |
780 | chg_det &= ~(1 << 2); | |
1d4c9293 | 781 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
782 | /* Turn on chg detect block */ |
783 | chg_det &= ~(1 << 1); | |
1d4c9293 | 784 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
785 | udelay(20); |
786 | /* enable chg detection */ | |
787 | chg_det &= ~(1 << 0); | |
1d4c9293 | 788 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
789 | break; |
790 | case SNPS_28NM_INTEGRATED_PHY: | |
791 | /* | |
792 | * Configure DM as current source, DP as current sink | |
793 | * and enable battery charging comparators. | |
794 | */ | |
1d4c9293 HK |
795 | ulpi_write(phy, 0x8, 0x85); |
796 | ulpi_write(phy, 0x2, 0x85); | |
797 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
798 | break; |
799 | default: | |
800 | break; | |
801 | } | |
802 | } | |
803 | ||
804 | static bool msm_chg_check_primary_det(struct msm_otg *motg) | |
805 | { | |
1d4c9293 | 806 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
807 | u32 chg_det; |
808 | bool ret = false; | |
809 | ||
810 | switch (motg->pdata->phy_type) { | |
811 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 812 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
813 | ret = chg_det & (1 << 4); |
814 | break; | |
815 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 816 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
817 | ret = chg_det & 1; |
818 | break; | |
819 | default: | |
820 | break; | |
821 | } | |
822 | return ret; | |
823 | } | |
824 | ||
825 | static void msm_chg_enable_primary_det(struct msm_otg *motg) | |
826 | { | |
1d4c9293 | 827 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
828 | u32 chg_det; |
829 | ||
830 | switch (motg->pdata->phy_type) { | |
831 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 832 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
833 | /* enable chg detection */ |
834 | chg_det &= ~(1 << 0); | |
1d4c9293 | 835 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
836 | break; |
837 | case SNPS_28NM_INTEGRATED_PHY: | |
838 | /* | |
839 | * Configure DP as current source, DM as current sink | |
840 | * and enable battery charging comparators. | |
841 | */ | |
1d4c9293 HK |
842 | ulpi_write(phy, 0x2, 0x85); |
843 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
844 | break; |
845 | default: | |
846 | break; | |
847 | } | |
848 | } | |
849 | ||
850 | static bool msm_chg_check_dcd(struct msm_otg *motg) | |
851 | { | |
1d4c9293 | 852 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
853 | u32 line_state; |
854 | bool ret = false; | |
855 | ||
856 | switch (motg->pdata->phy_type) { | |
857 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 858 | line_state = ulpi_read(phy, 0x15); |
d860852e PK |
859 | ret = !(line_state & 1); |
860 | break; | |
861 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 862 | line_state = ulpi_read(phy, 0x87); |
d860852e PK |
863 | ret = line_state & 2; |
864 | break; | |
865 | default: | |
866 | break; | |
867 | } | |
868 | return ret; | |
869 | } | |
870 | ||
871 | static void msm_chg_disable_dcd(struct msm_otg *motg) | |
872 | { | |
1d4c9293 | 873 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
874 | u32 chg_det; |
875 | ||
876 | switch (motg->pdata->phy_type) { | |
877 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 878 | chg_det = ulpi_read(phy, 0x34); |
d860852e | 879 | chg_det &= ~(1 << 5); |
1d4c9293 | 880 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
881 | break; |
882 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 883 | ulpi_write(phy, 0x10, 0x86); |
d860852e PK |
884 | break; |
885 | default: | |
886 | break; | |
887 | } | |
888 | } | |
889 | ||
890 | static void msm_chg_enable_dcd(struct msm_otg *motg) | |
891 | { | |
1d4c9293 | 892 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
893 | u32 chg_det; |
894 | ||
895 | switch (motg->pdata->phy_type) { | |
896 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 897 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
898 | /* Turn on D+ current source */ |
899 | chg_det |= (1 << 5); | |
1d4c9293 | 900 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
901 | break; |
902 | case SNPS_28NM_INTEGRATED_PHY: | |
903 | /* Data contact detection enable */ | |
1d4c9293 | 904 | ulpi_write(phy, 0x10, 0x85); |
d860852e PK |
905 | break; |
906 | default: | |
907 | break; | |
908 | } | |
909 | } | |
910 | ||
911 | static void msm_chg_block_on(struct msm_otg *motg) | |
912 | { | |
1d4c9293 | 913 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
914 | u32 func_ctrl, chg_det; |
915 | ||
916 | /* put the controller in non-driving mode */ | |
1d4c9293 | 917 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
918 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
919 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; | |
1d4c9293 | 920 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
921 | |
922 | switch (motg->pdata->phy_type) { | |
923 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 924 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
925 | /* control chg block via ULPI */ |
926 | chg_det &= ~(1 << 3); | |
1d4c9293 | 927 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
928 | /* Turn on chg detect block */ |
929 | chg_det &= ~(1 << 1); | |
1d4c9293 | 930 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
931 | udelay(20); |
932 | break; | |
933 | case SNPS_28NM_INTEGRATED_PHY: | |
934 | /* Clear charger detecting control bits */ | |
1d4c9293 | 935 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 936 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
937 | ulpi_write(phy, 0x1F, 0x92); |
938 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
939 | udelay(100); |
940 | break; | |
941 | default: | |
942 | break; | |
943 | } | |
944 | } | |
945 | ||
946 | static void msm_chg_block_off(struct msm_otg *motg) | |
947 | { | |
1d4c9293 | 948 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
949 | u32 func_ctrl, chg_det; |
950 | ||
951 | switch (motg->pdata->phy_type) { | |
952 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 953 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
954 | /* Turn off charger block */ |
955 | chg_det |= ~(1 << 1); | |
1d4c9293 | 956 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
957 | break; |
958 | case SNPS_28NM_INTEGRATED_PHY: | |
959 | /* Clear charger detecting control bits */ | |
1d4c9293 | 960 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 961 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
962 | ulpi_write(phy, 0x1F, 0x92); |
963 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
964 | break; |
965 | default: | |
966 | break; | |
967 | } | |
968 | ||
969 | /* put the controller in normal mode */ | |
1d4c9293 | 970 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
971 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
972 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL; | |
1d4c9293 | 973 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
974 | } |
975 | ||
976 | #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */ | |
977 | #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */ | |
978 | #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */ | |
979 | #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */ | |
980 | static void msm_chg_detect_work(struct work_struct *w) | |
981 | { | |
982 | struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work); | |
1d4c9293 | 983 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
984 | bool is_dcd, tmout, vout; |
985 | unsigned long delay; | |
986 | ||
1d4c9293 | 987 | dev_dbg(phy->dev, "chg detection work\n"); |
d860852e PK |
988 | switch (motg->chg_state) { |
989 | case USB_CHG_STATE_UNDEFINED: | |
1d4c9293 | 990 | pm_runtime_get_sync(phy->dev); |
d860852e PK |
991 | msm_chg_block_on(motg); |
992 | msm_chg_enable_dcd(motg); | |
993 | motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; | |
994 | motg->dcd_retries = 0; | |
995 | delay = MSM_CHG_DCD_POLL_TIME; | |
996 | break; | |
997 | case USB_CHG_STATE_WAIT_FOR_DCD: | |
998 | is_dcd = msm_chg_check_dcd(motg); | |
999 | tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES; | |
1000 | if (is_dcd || tmout) { | |
1001 | msm_chg_disable_dcd(motg); | |
1002 | msm_chg_enable_primary_det(motg); | |
1003 | delay = MSM_CHG_PRIMARY_DET_TIME; | |
1004 | motg->chg_state = USB_CHG_STATE_DCD_DONE; | |
1005 | } else { | |
1006 | delay = MSM_CHG_DCD_POLL_TIME; | |
1007 | } | |
1008 | break; | |
1009 | case USB_CHG_STATE_DCD_DONE: | |
1010 | vout = msm_chg_check_primary_det(motg); | |
1011 | if (vout) { | |
1012 | msm_chg_enable_secondary_det(motg); | |
1013 | delay = MSM_CHG_SECONDARY_DET_TIME; | |
1014 | motg->chg_state = USB_CHG_STATE_PRIMARY_DONE; | |
1015 | } else { | |
1016 | motg->chg_type = USB_SDP_CHARGER; | |
1017 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1018 | delay = 0; | |
1019 | } | |
1020 | break; | |
1021 | case USB_CHG_STATE_PRIMARY_DONE: | |
1022 | vout = msm_chg_check_secondary_det(motg); | |
1023 | if (vout) | |
1024 | motg->chg_type = USB_DCP_CHARGER; | |
1025 | else | |
1026 | motg->chg_type = USB_CDP_CHARGER; | |
1027 | motg->chg_state = USB_CHG_STATE_SECONDARY_DONE; | |
1028 | /* fall through */ | |
1029 | case USB_CHG_STATE_SECONDARY_DONE: | |
1030 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1031 | case USB_CHG_STATE_DETECTED: | |
1032 | msm_chg_block_off(motg); | |
1d4c9293 | 1033 | dev_dbg(phy->dev, "charger = %d\n", motg->chg_type); |
d860852e PK |
1034 | schedule_work(&motg->sm_work); |
1035 | return; | |
1036 | default: | |
1037 | return; | |
1038 | } | |
1039 | ||
1040 | schedule_delayed_work(&motg->chg_work, delay); | |
1041 | } | |
1042 | ||
e0c201f3 PK |
1043 | /* |
1044 | * We support OTG, Peripheral only and Host only configurations. In case | |
1045 | * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen | |
1046 | * via Id pin status or user request (debugfs). Id/BSV interrupts are not | |
1047 | * enabled when switch is controlled by user and default mode is supplied | |
1048 | * by board file, which can be changed by userspace later. | |
1049 | */ | |
1050 | static void msm_otg_init_sm(struct msm_otg *motg) | |
1051 | { | |
1052 | struct msm_otg_platform_data *pdata = motg->pdata; | |
1053 | u32 otgsc = readl(USB_OTGSC); | |
1054 | ||
1055 | switch (pdata->mode) { | |
971232cf | 1056 | case USB_DR_MODE_OTG: |
e0c201f3 PK |
1057 | if (pdata->otg_control == OTG_PHY_CONTROL) { |
1058 | if (otgsc & OTGSC_ID) | |
1059 | set_bit(ID, &motg->inputs); | |
1060 | else | |
1061 | clear_bit(ID, &motg->inputs); | |
1062 | ||
1063 | if (otgsc & OTGSC_BSV) | |
1064 | set_bit(B_SESS_VLD, &motg->inputs); | |
1065 | else | |
1066 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1067 | } else if (pdata->otg_control == OTG_USER_CONTROL) { | |
e0c201f3 PK |
1068 | set_bit(ID, &motg->inputs); |
1069 | clear_bit(B_SESS_VLD, &motg->inputs); | |
e0c201f3 PK |
1070 | } |
1071 | break; | |
971232cf | 1072 | case USB_DR_MODE_HOST: |
e0c201f3 PK |
1073 | clear_bit(ID, &motg->inputs); |
1074 | break; | |
971232cf | 1075 | case USB_DR_MODE_PERIPHERAL: |
e0c201f3 PK |
1076 | set_bit(ID, &motg->inputs); |
1077 | if (otgsc & OTGSC_BSV) | |
1078 | set_bit(B_SESS_VLD, &motg->inputs); | |
1079 | else | |
1080 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1081 | break; | |
1082 | default: | |
1083 | break; | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | static void msm_otg_sm_work(struct work_struct *w) | |
1088 | { | |
1089 | struct msm_otg *motg = container_of(w, struct msm_otg, sm_work); | |
1d4c9293 | 1090 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1091 | |
1d4c9293 | 1092 | switch (otg->phy->state) { |
e0c201f3 | 1093 | case OTG_STATE_UNDEFINED: |
1d4c9293 HK |
1094 | dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n"); |
1095 | msm_otg_reset(otg->phy); | |
e0c201f3 | 1096 | msm_otg_init_sm(motg); |
1d4c9293 | 1097 | otg->phy->state = OTG_STATE_B_IDLE; |
e0c201f3 PK |
1098 | /* FALL THROUGH */ |
1099 | case OTG_STATE_B_IDLE: | |
1d4c9293 | 1100 | dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n"); |
e0c201f3 PK |
1101 | if (!test_bit(ID, &motg->inputs) && otg->host) { |
1102 | /* disable BSV bit */ | |
1103 | writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC); | |
1d4c9293 HK |
1104 | msm_otg_start_host(otg->phy, 1); |
1105 | otg->phy->state = OTG_STATE_A_HOST; | |
d860852e PK |
1106 | } else if (test_bit(B_SESS_VLD, &motg->inputs)) { |
1107 | switch (motg->chg_state) { | |
1108 | case USB_CHG_STATE_UNDEFINED: | |
1109 | msm_chg_detect_work(&motg->chg_work.work); | |
1110 | break; | |
1111 | case USB_CHG_STATE_DETECTED: | |
1112 | switch (motg->chg_type) { | |
1113 | case USB_DCP_CHARGER: | |
1114 | msm_otg_notify_charger(motg, | |
1115 | IDEV_CHG_MAX); | |
1116 | break; | |
1117 | case USB_CDP_CHARGER: | |
1118 | msm_otg_notify_charger(motg, | |
1119 | IDEV_CHG_MAX); | |
1d4c9293 HK |
1120 | msm_otg_start_peripheral(otg->phy, 1); |
1121 | otg->phy->state | |
1122 | = OTG_STATE_B_PERIPHERAL; | |
d860852e PK |
1123 | break; |
1124 | case USB_SDP_CHARGER: | |
1125 | msm_otg_notify_charger(motg, IUNIT); | |
1d4c9293 HK |
1126 | msm_otg_start_peripheral(otg->phy, 1); |
1127 | otg->phy->state | |
1128 | = OTG_STATE_B_PERIPHERAL; | |
d860852e PK |
1129 | break; |
1130 | default: | |
1131 | break; | |
1132 | } | |
1133 | break; | |
1134 | default: | |
1135 | break; | |
1136 | } | |
1137 | } else { | |
1138 | /* | |
1139 | * If charger detection work is pending, decrement | |
1140 | * the pm usage counter to balance with the one that | |
1141 | * is incremented in charger detection work. | |
1142 | */ | |
1143 | if (cancel_delayed_work_sync(&motg->chg_work)) { | |
1d4c9293 HK |
1144 | pm_runtime_put_sync(otg->phy->dev); |
1145 | msm_otg_reset(otg->phy); | |
d860852e PK |
1146 | } |
1147 | msm_otg_notify_charger(motg, 0); | |
1148 | motg->chg_state = USB_CHG_STATE_UNDEFINED; | |
1149 | motg->chg_type = USB_INVALID_CHARGER; | |
e0c201f3 | 1150 | } |
1d4c9293 | 1151 | pm_runtime_put_sync(otg->phy->dev); |
e0c201f3 PK |
1152 | break; |
1153 | case OTG_STATE_B_PERIPHERAL: | |
1d4c9293 | 1154 | dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n"); |
e0c201f3 PK |
1155 | if (!test_bit(B_SESS_VLD, &motg->inputs) || |
1156 | !test_bit(ID, &motg->inputs)) { | |
d860852e | 1157 | msm_otg_notify_charger(motg, 0); |
1d4c9293 | 1158 | msm_otg_start_peripheral(otg->phy, 0); |
d860852e PK |
1159 | motg->chg_state = USB_CHG_STATE_UNDEFINED; |
1160 | motg->chg_type = USB_INVALID_CHARGER; | |
1d4c9293 HK |
1161 | otg->phy->state = OTG_STATE_B_IDLE; |
1162 | msm_otg_reset(otg->phy); | |
e0c201f3 PK |
1163 | schedule_work(w); |
1164 | } | |
1165 | break; | |
1166 | case OTG_STATE_A_HOST: | |
1d4c9293 | 1167 | dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n"); |
e0c201f3 | 1168 | if (test_bit(ID, &motg->inputs)) { |
1d4c9293 HK |
1169 | msm_otg_start_host(otg->phy, 0); |
1170 | otg->phy->state = OTG_STATE_B_IDLE; | |
1171 | msm_otg_reset(otg->phy); | |
e0c201f3 PK |
1172 | schedule_work(w); |
1173 | } | |
1174 | break; | |
1175 | default: | |
1176 | break; | |
1177 | } | |
1178 | } | |
1179 | ||
1180 | static irqreturn_t msm_otg_irq(int irq, void *data) | |
1181 | { | |
1182 | struct msm_otg *motg = data; | |
1d4c9293 | 1183 | struct usb_phy *phy = &motg->phy; |
e0c201f3 PK |
1184 | u32 otgsc = 0; |
1185 | ||
87c0104a PK |
1186 | if (atomic_read(&motg->in_lpm)) { |
1187 | disable_irq_nosync(irq); | |
1188 | motg->async_int = 1; | |
1d4c9293 | 1189 | pm_runtime_get(phy->dev); |
87c0104a PK |
1190 | return IRQ_HANDLED; |
1191 | } | |
1192 | ||
e0c201f3 PK |
1193 | otgsc = readl(USB_OTGSC); |
1194 | if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS))) | |
1195 | return IRQ_NONE; | |
1196 | ||
1197 | if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) { | |
1198 | if (otgsc & OTGSC_ID) | |
1199 | set_bit(ID, &motg->inputs); | |
1200 | else | |
1201 | clear_bit(ID, &motg->inputs); | |
1d4c9293 HK |
1202 | dev_dbg(phy->dev, "ID set/clear\n"); |
1203 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1204 | } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) { |
1205 | if (otgsc & OTGSC_BSV) | |
1206 | set_bit(B_SESS_VLD, &motg->inputs); | |
1207 | else | |
1208 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1d4c9293 HK |
1209 | dev_dbg(phy->dev, "BSV set/clear\n"); |
1210 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1211 | } |
1212 | ||
1213 | writel(otgsc, USB_OTGSC); | |
1214 | schedule_work(&motg->sm_work); | |
1215 | return IRQ_HANDLED; | |
1216 | } | |
1217 | ||
1218 | static int msm_otg_mode_show(struct seq_file *s, void *unused) | |
1219 | { | |
1220 | struct msm_otg *motg = s->private; | |
1d4c9293 | 1221 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1222 | |
1d4c9293 | 1223 | switch (otg->phy->state) { |
e0c201f3 | 1224 | case OTG_STATE_A_HOST: |
3aca0fa9 | 1225 | seq_puts(s, "host\n"); |
e0c201f3 PK |
1226 | break; |
1227 | case OTG_STATE_B_PERIPHERAL: | |
3aca0fa9 | 1228 | seq_puts(s, "peripheral\n"); |
e0c201f3 PK |
1229 | break; |
1230 | default: | |
3aca0fa9 | 1231 | seq_puts(s, "none\n"); |
e0c201f3 PK |
1232 | break; |
1233 | } | |
1234 | ||
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | static int msm_otg_mode_open(struct inode *inode, struct file *file) | |
1239 | { | |
1240 | return single_open(file, msm_otg_mode_show, inode->i_private); | |
1241 | } | |
1242 | ||
1243 | static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, | |
1244 | size_t count, loff_t *ppos) | |
1245 | { | |
e2904ee4 PK |
1246 | struct seq_file *s = file->private_data; |
1247 | struct msm_otg *motg = s->private; | |
e0c201f3 | 1248 | char buf[16]; |
1d4c9293 | 1249 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1250 | int status = count; |
971232cf | 1251 | enum usb_dr_mode req_mode; |
e0c201f3 PK |
1252 | |
1253 | memset(buf, 0x00, sizeof(buf)); | |
1254 | ||
1255 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) { | |
1256 | status = -EFAULT; | |
1257 | goto out; | |
1258 | } | |
1259 | ||
1260 | if (!strncmp(buf, "host", 4)) { | |
971232cf | 1261 | req_mode = USB_DR_MODE_HOST; |
e0c201f3 | 1262 | } else if (!strncmp(buf, "peripheral", 10)) { |
971232cf | 1263 | req_mode = USB_DR_MODE_PERIPHERAL; |
e0c201f3 | 1264 | } else if (!strncmp(buf, "none", 4)) { |
971232cf | 1265 | req_mode = USB_DR_MODE_UNKNOWN; |
e0c201f3 PK |
1266 | } else { |
1267 | status = -EINVAL; | |
1268 | goto out; | |
1269 | } | |
1270 | ||
1271 | switch (req_mode) { | |
971232cf | 1272 | case USB_DR_MODE_UNKNOWN: |
1d4c9293 | 1273 | switch (otg->phy->state) { |
e0c201f3 PK |
1274 | case OTG_STATE_A_HOST: |
1275 | case OTG_STATE_B_PERIPHERAL: | |
1276 | set_bit(ID, &motg->inputs); | |
1277 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1278 | break; | |
1279 | default: | |
1280 | goto out; | |
1281 | } | |
1282 | break; | |
971232cf | 1283 | case USB_DR_MODE_PERIPHERAL: |
1d4c9293 | 1284 | switch (otg->phy->state) { |
e0c201f3 PK |
1285 | case OTG_STATE_B_IDLE: |
1286 | case OTG_STATE_A_HOST: | |
1287 | set_bit(ID, &motg->inputs); | |
1288 | set_bit(B_SESS_VLD, &motg->inputs); | |
1289 | break; | |
1290 | default: | |
1291 | goto out; | |
1292 | } | |
1293 | break; | |
971232cf | 1294 | case USB_DR_MODE_HOST: |
1d4c9293 | 1295 | switch (otg->phy->state) { |
e0c201f3 PK |
1296 | case OTG_STATE_B_IDLE: |
1297 | case OTG_STATE_B_PERIPHERAL: | |
1298 | clear_bit(ID, &motg->inputs); | |
1299 | break; | |
1300 | default: | |
1301 | goto out; | |
1302 | } | |
1303 | break; | |
1304 | default: | |
1305 | goto out; | |
1306 | } | |
1307 | ||
1d4c9293 | 1308 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 PK |
1309 | schedule_work(&motg->sm_work); |
1310 | out: | |
1311 | return status; | |
1312 | } | |
1313 | ||
1314 | const struct file_operations msm_otg_mode_fops = { | |
1315 | .open = msm_otg_mode_open, | |
1316 | .read = seq_read, | |
1317 | .write = msm_otg_mode_write, | |
1318 | .llseek = seq_lseek, | |
1319 | .release = single_release, | |
1320 | }; | |
1321 | ||
1322 | static struct dentry *msm_otg_dbg_root; | |
1323 | static struct dentry *msm_otg_dbg_mode; | |
1324 | ||
1325 | static int msm_otg_debugfs_init(struct msm_otg *motg) | |
1326 | { | |
1327 | msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL); | |
1328 | ||
1329 | if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root)) | |
1330 | return -ENODEV; | |
1331 | ||
1332 | msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR, | |
1333 | msm_otg_dbg_root, motg, &msm_otg_mode_fops); | |
1334 | if (!msm_otg_dbg_mode) { | |
1335 | debugfs_remove(msm_otg_dbg_root); | |
1336 | msm_otg_dbg_root = NULL; | |
1337 | return -ENODEV; | |
1338 | } | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static void msm_otg_debugfs_cleanup(void) | |
1344 | { | |
1345 | debugfs_remove(msm_otg_dbg_mode); | |
1346 | debugfs_remove(msm_otg_dbg_root); | |
1347 | } | |
1348 | ||
8364f9af II |
1349 | static struct of_device_id msm_otg_dt_match[] = { |
1350 | { | |
1351 | .compatible = "qcom,usb-otg-ci", | |
1352 | .data = (void *) CI_45NM_INTEGRATED_PHY | |
1353 | }, | |
1354 | { | |
1355 | .compatible = "qcom,usb-otg-snps", | |
1356 | .data = (void *) SNPS_28NM_INTEGRATED_PHY | |
1357 | }, | |
1358 | { } | |
1359 | }; | |
1360 | MODULE_DEVICE_TABLE(of, msm_otg_dt_match); | |
1361 | ||
1362 | static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) | |
1363 | { | |
1364 | struct msm_otg_platform_data *pdata; | |
1365 | const struct of_device_id *id; | |
1366 | struct device_node *node = pdev->dev.of_node; | |
1367 | struct property *prop; | |
1368 | int len, ret, words; | |
1369 | u32 val; | |
1370 | ||
1371 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1372 | if (!pdata) | |
1373 | return -ENOMEM; | |
1374 | ||
1375 | motg->pdata = pdata; | |
1376 | ||
1377 | id = of_match_device(msm_otg_dt_match, &pdev->dev); | |
1378 | pdata->phy_type = (int) id->data; | |
1379 | ||
1380 | pdata->mode = of_usb_get_dr_mode(node); | |
1381 | if (pdata->mode == USB_DR_MODE_UNKNOWN) | |
1382 | pdata->mode = USB_DR_MODE_OTG; | |
1383 | ||
1384 | pdata->otg_control = OTG_PHY_CONTROL; | |
1385 | if (!of_property_read_u32(node, "qcom,otg-control", &val)) | |
1386 | if (val == OTG_PMIC_CONTROL) | |
1387 | pdata->otg_control = val; | |
1388 | ||
1389 | prop = of_find_property(node, "qcom,phy-init-sequence", &len); | |
1390 | if (!prop || !len) | |
1391 | return 0; | |
1392 | ||
1393 | words = len / sizeof(u32); | |
1394 | ||
1395 | if (words >= ULPI_EXT_VENDOR_SPECIFIC) { | |
1396 | dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words); | |
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); | |
1401 | if (!pdata->phy_init_seq) { | |
1402 | dev_warn(&pdev->dev, "No space for PHY init sequence\n"); | |
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | ret = of_property_read_u32_array(node, "qcom,phy-init-sequence", | |
1407 | pdata->phy_init_seq, words); | |
1408 | if (!ret) | |
1409 | pdata->phy_init_sz = words; | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
06a6ec44 | 1414 | static int msm_otg_probe(struct platform_device *pdev) |
e0c201f3 | 1415 | { |
6b99c68e | 1416 | struct regulator_bulk_data regs[3]; |
e0c201f3 | 1417 | int ret = 0; |
8364f9af II |
1418 | struct device_node *np = pdev->dev.of_node; |
1419 | struct msm_otg_platform_data *pdata; | |
e0c201f3 PK |
1420 | struct resource *res; |
1421 | struct msm_otg *motg; | |
1d4c9293 | 1422 | struct usb_phy *phy; |
e0c201f3 | 1423 | |
6b99c68e | 1424 | motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL); |
e0c201f3 PK |
1425 | if (!motg) { |
1426 | dev_err(&pdev->dev, "unable to allocate msm_otg\n"); | |
1427 | return -ENOMEM; | |
1428 | } | |
1429 | ||
8364f9af II |
1430 | pdata = dev_get_platdata(&pdev->dev); |
1431 | if (!pdata) { | |
1432 | if (!np) | |
1433 | return -ENXIO; | |
1434 | ret = msm_otg_read_dt(pdev, motg); | |
1435 | if (ret) | |
1436 | return ret; | |
1437 | } | |
1438 | ||
6b99c68e II |
1439 | motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
1440 | GFP_KERNEL); | |
1d4c9293 HK |
1441 | if (!motg->phy.otg) { |
1442 | dev_err(&pdev->dev, "unable to allocate msm_otg\n"); | |
6b99c68e | 1443 | return -ENOMEM; |
1d4c9293 HK |
1444 | } |
1445 | ||
1d4c9293 HK |
1446 | phy = &motg->phy; |
1447 | phy->dev = &pdev->dev; | |
e0c201f3 | 1448 | |
8364f9af II |
1449 | motg->phy_reset_clk = devm_clk_get(&pdev->dev, |
1450 | np ? "phy" : "usb_phy_clk"); | |
e0c201f3 PK |
1451 | if (IS_ERR(motg->phy_reset_clk)) { |
1452 | dev_err(&pdev->dev, "failed to get usb_phy_clk\n"); | |
6b99c68e | 1453 | return PTR_ERR(motg->phy_reset_clk); |
e0c201f3 PK |
1454 | } |
1455 | ||
8364f9af | 1456 | motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk"); |
e0c201f3 PK |
1457 | if (IS_ERR(motg->clk)) { |
1458 | dev_err(&pdev->dev, "failed to get usb_hs_clk\n"); | |
6b99c68e | 1459 | return PTR_ERR(motg->clk); |
e0c201f3 | 1460 | } |
0f73cac8 A |
1461 | |
1462 | /* | |
1463 | * If USB Core is running its protocol engine based on CORE CLK, | |
1464 | * CORE CLK must be running at >55Mhz for correct HSUSB | |
1465 | * operation and USB core cannot tolerate frequency changes on | |
ff0e4a68 | 1466 | * CORE CLK. |
0f73cac8 | 1467 | */ |
8364f9af | 1468 | motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk"); |
e0c201f3 PK |
1469 | if (IS_ERR(motg->pclk)) { |
1470 | dev_err(&pdev->dev, "failed to get usb_hs_pclk\n"); | |
6b99c68e | 1471 | return PTR_ERR(motg->pclk); |
e0c201f3 PK |
1472 | } |
1473 | ||
1474 | /* | |
1475 | * USB core clock is not present on all MSM chips. This | |
1476 | * clock is introduced to remove the dependency on AXI | |
1477 | * bus frequency. | |
1478 | */ | |
8364f9af II |
1479 | motg->core_clk = devm_clk_get(&pdev->dev, |
1480 | np ? "alt_core" : "usb_hs_core_clk"); | |
e0c201f3 PK |
1481 | |
1482 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6b99c68e II |
1483 | motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
1484 | if (IS_ERR(motg->regs)) | |
1485 | return PTR_ERR(motg->regs); | |
e0c201f3 | 1486 | |
e0c201f3 PK |
1487 | dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); |
1488 | ||
1489 | motg->irq = platform_get_irq(pdev, 0); | |
f60c114a | 1490 | if (motg->irq < 0) { |
e0c201f3 | 1491 | dev_err(&pdev->dev, "platform_get_irq failed\n"); |
6b99c68e II |
1492 | return motg->irq; |
1493 | } | |
1494 | ||
f5ef2372 II |
1495 | regs[0].supply = "vddcx"; |
1496 | regs[1].supply = "v3p3"; | |
1497 | regs[2].supply = "v1p8"; | |
6b99c68e II |
1498 | |
1499 | ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs); | |
1500 | if (ret) | |
1501 | return ret; | |
1502 | ||
1503 | motg->vddcx = regs[0].consumer; | |
1504 | motg->v3p3 = regs[1].consumer; | |
1505 | motg->v1p8 = regs[2].consumer; | |
1506 | ||
1507 | clk_set_rate(motg->clk, 60000000); | |
e0c201f3 | 1508 | |
b99a8f62 SB |
1509 | clk_prepare_enable(motg->clk); |
1510 | clk_prepare_enable(motg->pclk); | |
11aa5c47 | 1511 | |
6b99c68e II |
1512 | if (!IS_ERR(motg->core_clk)) |
1513 | clk_prepare_enable(motg->core_clk); | |
1514 | ||
11aa5c47 A |
1515 | ret = msm_hsusb_init_vddcx(motg, 1); |
1516 | if (ret) { | |
1517 | dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); | |
6b99c68e | 1518 | goto disable_clks; |
11aa5c47 A |
1519 | } |
1520 | ||
1521 | ret = msm_hsusb_ldo_init(motg, 1); | |
1522 | if (ret) { | |
1523 | dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); | |
6b99c68e | 1524 | goto disable_vddcx; |
11aa5c47 | 1525 | } |
37cfdaf7 | 1526 | ret = msm_hsusb_ldo_set_mode(motg, 1); |
11aa5c47 A |
1527 | if (ret) { |
1528 | dev_err(&pdev->dev, "hsusb vreg enable failed\n"); | |
6b99c68e | 1529 | goto disable_ldo; |
11aa5c47 A |
1530 | } |
1531 | ||
e0c201f3 PK |
1532 | writel(0, USB_USBINTR); |
1533 | writel(0, USB_OTGSC); | |
1534 | ||
1535 | INIT_WORK(&motg->sm_work, msm_otg_sm_work); | |
d860852e | 1536 | INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work); |
6b99c68e | 1537 | ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED, |
e0c201f3 PK |
1538 | "msm_otg", motg); |
1539 | if (ret) { | |
1540 | dev_err(&pdev->dev, "request irq failed\n"); | |
6b99c68e | 1541 | goto disable_ldo; |
e0c201f3 PK |
1542 | } |
1543 | ||
1d4c9293 HK |
1544 | phy->init = msm_otg_reset; |
1545 | phy->set_power = msm_otg_set_power; | |
1546 | ||
1547 | phy->io_ops = &msm_otg_io_ops; | |
e0c201f3 | 1548 | |
1d4c9293 HK |
1549 | phy->otg->phy = &motg->phy; |
1550 | phy->otg->set_host = msm_otg_set_host; | |
1551 | phy->otg->set_peripheral = msm_otg_set_peripheral; | |
e0c201f3 | 1552 | |
662dca54 | 1553 | ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2); |
e0c201f3 | 1554 | if (ret) { |
721002ec | 1555 | dev_err(&pdev->dev, "usb_add_phy failed\n"); |
6b99c68e | 1556 | goto disable_ldo; |
e0c201f3 PK |
1557 | } |
1558 | ||
1559 | platform_set_drvdata(pdev, motg); | |
1560 | device_init_wakeup(&pdev->dev, 1); | |
1561 | ||
971232cf | 1562 | if (motg->pdata->mode == USB_DR_MODE_OTG && |
8364f9af | 1563 | motg->pdata->otg_control == OTG_USER_CONTROL) { |
e0c201f3 PK |
1564 | ret = msm_otg_debugfs_init(motg); |
1565 | if (ret) | |
3aca0fa9 | 1566 | dev_dbg(&pdev->dev, "Can not create mode change file\n"); |
e0c201f3 PK |
1567 | } |
1568 | ||
87c0104a PK |
1569 | pm_runtime_set_active(&pdev->dev); |
1570 | pm_runtime_enable(&pdev->dev); | |
e0c201f3 | 1571 | |
87c0104a | 1572 | return 0; |
6b99c68e II |
1573 | |
1574 | disable_ldo: | |
1575 | msm_hsusb_ldo_init(motg, 0); | |
1576 | disable_vddcx: | |
1577 | msm_hsusb_init_vddcx(motg, 0); | |
e0c201f3 | 1578 | disable_clks: |
b99a8f62 SB |
1579 | clk_disable_unprepare(motg->pclk); |
1580 | clk_disable_unprepare(motg->clk); | |
6b99c68e II |
1581 | if (!IS_ERR(motg->core_clk)) |
1582 | clk_disable_unprepare(motg->core_clk); | |
e0c201f3 PK |
1583 | return ret; |
1584 | } | |
1585 | ||
fb4e98ab | 1586 | static int msm_otg_remove(struct platform_device *pdev) |
e0c201f3 PK |
1587 | { |
1588 | struct msm_otg *motg = platform_get_drvdata(pdev); | |
1d4c9293 | 1589 | struct usb_phy *phy = &motg->phy; |
87c0104a | 1590 | int cnt = 0; |
e0c201f3 | 1591 | |
1d4c9293 | 1592 | if (phy->otg->host || phy->otg->gadget) |
e0c201f3 PK |
1593 | return -EBUSY; |
1594 | ||
1595 | msm_otg_debugfs_cleanup(); | |
d860852e | 1596 | cancel_delayed_work_sync(&motg->chg_work); |
e0c201f3 | 1597 | cancel_work_sync(&motg->sm_work); |
87c0104a | 1598 | |
7018773a | 1599 | pm_runtime_resume(&pdev->dev); |
87c0104a | 1600 | |
e0c201f3 | 1601 | device_init_wakeup(&pdev->dev, 0); |
87c0104a | 1602 | pm_runtime_disable(&pdev->dev); |
e0c201f3 | 1603 | |
662dca54 | 1604 | usb_remove_phy(phy); |
6b99c68e | 1605 | disable_irq(motg->irq); |
e0c201f3 | 1606 | |
87c0104a PK |
1607 | /* |
1608 | * Put PHY in low power mode. | |
1609 | */ | |
1d4c9293 HK |
1610 | ulpi_read(phy, 0x14); |
1611 | ulpi_write(phy, 0x08, 0x09); | |
87c0104a PK |
1612 | |
1613 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
1614 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
1615 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
1616 | break; | |
1617 | udelay(1); | |
1618 | cnt++; | |
1619 | } | |
1620 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) | |
1d4c9293 | 1621 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
87c0104a | 1622 | |
b99a8f62 SB |
1623 | clk_disable_unprepare(motg->pclk); |
1624 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 1625 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 1626 | clk_disable_unprepare(motg->core_clk); |
11aa5c47 | 1627 | msm_hsusb_ldo_init(motg, 0); |
e0c201f3 | 1628 | |
87c0104a | 1629 | pm_runtime_set_suspended(&pdev->dev); |
e0c201f3 | 1630 | |
e0c201f3 PK |
1631 | return 0; |
1632 | } | |
1633 | ||
87c0104a PK |
1634 | #ifdef CONFIG_PM_RUNTIME |
1635 | static int msm_otg_runtime_idle(struct device *dev) | |
1636 | { | |
1637 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1d4c9293 | 1638 | struct usb_otg *otg = motg->phy.otg; |
87c0104a PK |
1639 | |
1640 | dev_dbg(dev, "OTG runtime idle\n"); | |
1641 | ||
1642 | /* | |
1643 | * It is observed some times that a spurious interrupt | |
1644 | * comes when PHY is put into LPM immediately after PHY reset. | |
1645 | * This 1 sec delay also prevents entering into LPM immediately | |
1646 | * after asynchronous interrupt. | |
1647 | */ | |
1d4c9293 | 1648 | if (otg->phy->state != OTG_STATE_UNDEFINED) |
87c0104a PK |
1649 | pm_schedule_suspend(dev, 1000); |
1650 | ||
1651 | return -EAGAIN; | |
1652 | } | |
1653 | ||
1654 | static int msm_otg_runtime_suspend(struct device *dev) | |
1655 | { | |
1656 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1657 | ||
1658 | dev_dbg(dev, "OTG runtime suspend\n"); | |
1659 | return msm_otg_suspend(motg); | |
1660 | } | |
1661 | ||
1662 | static int msm_otg_runtime_resume(struct device *dev) | |
1663 | { | |
1664 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1665 | ||
1666 | dev_dbg(dev, "OTG runtime resume\n"); | |
1667 | return msm_otg_resume(motg); | |
1668 | } | |
87c0104a PK |
1669 | #endif |
1670 | ||
7018773a | 1671 | #ifdef CONFIG_PM_SLEEP |
87c0104a PK |
1672 | static int msm_otg_pm_suspend(struct device *dev) |
1673 | { | |
1674 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1675 | ||
1676 | dev_dbg(dev, "OTG PM suspend\n"); | |
1677 | return msm_otg_suspend(motg); | |
1678 | } | |
1679 | ||
1680 | static int msm_otg_pm_resume(struct device *dev) | |
1681 | { | |
1682 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1683 | int ret; | |
1684 | ||
1685 | dev_dbg(dev, "OTG PM resume\n"); | |
1686 | ||
1687 | ret = msm_otg_resume(motg); | |
1688 | if (ret) | |
1689 | return ret; | |
1690 | ||
1691 | /* | |
1692 | * Runtime PM Documentation recommends bringing the | |
1693 | * device to full powered state upon resume. | |
1694 | */ | |
1695 | pm_runtime_disable(dev); | |
1696 | pm_runtime_set_active(dev); | |
1697 | pm_runtime_enable(dev); | |
1698 | ||
1699 | return 0; | |
1700 | } | |
87c0104a PK |
1701 | #endif |
1702 | ||
1703 | static const struct dev_pm_ops msm_otg_dev_pm_ops = { | |
7018773a PK |
1704 | SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume) |
1705 | SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume, | |
1706 | msm_otg_runtime_idle) | |
87c0104a PK |
1707 | }; |
1708 | ||
e0c201f3 | 1709 | static struct platform_driver msm_otg_driver = { |
06a6ec44 | 1710 | .probe = msm_otg_probe, |
7690417d | 1711 | .remove = msm_otg_remove, |
e0c201f3 PK |
1712 | .driver = { |
1713 | .name = DRIVER_NAME, | |
1714 | .owner = THIS_MODULE, | |
87c0104a | 1715 | .pm = &msm_otg_dev_pm_ops, |
8364f9af | 1716 | .of_match_table = msm_otg_dt_match, |
e0c201f3 PK |
1717 | }, |
1718 | }; | |
1719 | ||
06a6ec44 | 1720 | module_platform_driver(msm_otg_driver); |
e0c201f3 PK |
1721 | |
1722 | MODULE_LICENSE("GPL v2"); | |
1723 | MODULE_DESCRIPTION("MSM USB transceiver driver"); |