Commit | Line | Data |
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b3d99681 | 1 | /* |
43f3634f | 2 | * Copyright 2012-2014 Freescale Semiconductor, Inc. |
b3d99681 RZ |
3 | * Copyright (C) 2012 Marek Vasut <marex@denx.de> |
4 | * on behalf of DENX Software Engineering GmbH | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/usb/otg.h> | |
19 | #include <linux/stmp_device.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/io.h> | |
2400780e | 23 | #include <linux/of_device.h> |
0d896538 PC |
24 | #include <linux/regmap.h> |
25 | #include <linux/mfd/syscon.h> | |
b3d99681 RZ |
26 | |
27 | #define DRIVER_NAME "mxs_phy" | |
28 | ||
29 | #define HW_USBPHY_PWD 0x00 | |
30 | #define HW_USBPHY_CTRL 0x30 | |
31 | #define HW_USBPHY_CTRL_SET 0x34 | |
32 | #define HW_USBPHY_CTRL_CLR 0x38 | |
33 | ||
3f126505 PC |
34 | #define HW_USBPHY_DEBUG_SET 0x54 |
35 | #define HW_USBPHY_DEBUG_CLR 0x58 | |
36 | ||
22db05ec PC |
37 | #define HW_USBPHY_IP 0x90 |
38 | #define HW_USBPHY_IP_SET 0x94 | |
39 | #define HW_USBPHY_IP_CLR 0x98 | |
40 | ||
b3d99681 RZ |
41 | #define BM_USBPHY_CTRL_SFTRST BIT(31) |
42 | #define BM_USBPHY_CTRL_CLKGATE BIT(30) | |
13644144 PC |
43 | #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) |
44 | #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) | |
3f126505 PC |
45 | #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) |
46 | #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) | |
47 | #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) | |
13644144 PC |
48 | #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) |
49 | #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) | |
50 | #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) | |
b3d99681 RZ |
51 | #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) |
52 | #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) | |
53 | #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) | |
54 | ||
22db05ec PC |
55 | #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) |
56 | ||
3f126505 PC |
57 | #define BM_USBPHY_DEBUG_CLKGATE BIT(30) |
58 | ||
59 | /* Anatop Registers */ | |
bf783438 PC |
60 | #define ANADIG_ANA_MISC0 0x150 |
61 | #define ANADIG_ANA_MISC0_SET 0x154 | |
62 | #define ANADIG_ANA_MISC0_CLR 0x158 | |
63 | ||
3f126505 PC |
64 | #define ANADIG_USB1_VBUS_DET_STAT 0x1c0 |
65 | #define ANADIG_USB2_VBUS_DET_STAT 0x220 | |
66 | ||
67 | #define ANADIG_USB1_LOOPBACK_SET 0x1e4 | |
68 | #define ANADIG_USB1_LOOPBACK_CLR 0x1e8 | |
69 | #define ANADIG_USB2_LOOPBACK_SET 0x244 | |
70 | #define ANADIG_USB2_LOOPBACK_CLR 0x248 | |
71 | ||
bf783438 PC |
72 | #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) |
73 | #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) | |
74 | ||
3f126505 PC |
75 | #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) |
76 | #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) | |
77 | ||
78 | #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) | |
79 | #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) | |
80 | #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) | |
81 | #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) | |
82 | ||
2400780e PC |
83 | #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) |
84 | ||
85 | /* Do disconnection between PHY and controller without vbus */ | |
86 | #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) | |
87 | ||
88 | /* | |
89 | * The PHY will be in messy if there is a wakeup after putting | |
90 | * bus to suspend (set portsc.suspendM) but before setting PHY to low | |
91 | * power mode (set portsc.phcd). | |
92 | */ | |
93 | #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) | |
94 | ||
95 | /* | |
96 | * The SOF sends too fast after resuming, it will cause disconnection | |
97 | * between host and high speed device. | |
98 | */ | |
99 | #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) | |
100 | ||
22db05ec PC |
101 | /* |
102 | * IC has bug fixes logic, they include | |
103 | * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST | |
104 | * which are described at above flags, the RTL will handle it | |
105 | * according to different versions. | |
106 | */ | |
107 | #define MXS_PHY_NEED_IP_FIX BIT(3) | |
108 | ||
2400780e PC |
109 | struct mxs_phy_data { |
110 | unsigned int flags; | |
111 | }; | |
112 | ||
113 | static const struct mxs_phy_data imx23_phy_data = { | |
114 | .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, | |
115 | }; | |
116 | ||
117 | static const struct mxs_phy_data imx6q_phy_data = { | |
118 | .flags = MXS_PHY_SENDING_SOF_TOO_FAST | | |
22db05ec PC |
119 | MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | |
120 | MXS_PHY_NEED_IP_FIX, | |
2400780e PC |
121 | }; |
122 | ||
123 | static const struct mxs_phy_data imx6sl_phy_data = { | |
22db05ec PC |
124 | .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | |
125 | MXS_PHY_NEED_IP_FIX, | |
2400780e PC |
126 | }; |
127 | ||
d0ee68b5 SA |
128 | static const struct mxs_phy_data vf610_phy_data = { |
129 | .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | | |
130 | MXS_PHY_NEED_IP_FIX, | |
131 | }; | |
132 | ||
43f3634f PC |
133 | static const struct mxs_phy_data imx6sx_phy_data = { |
134 | .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | | |
135 | MXS_PHY_NEED_IP_FIX, | |
136 | }; | |
137 | ||
2400780e | 138 | static const struct of_device_id mxs_phy_dt_ids[] = { |
43f3634f | 139 | { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, |
2400780e PC |
140 | { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, |
141 | { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, | |
142 | { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, | |
d0ee68b5 | 143 | { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, }, |
2400780e PC |
144 | { /* sentinel */ } |
145 | }; | |
146 | MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); | |
147 | ||
b3d99681 RZ |
148 | struct mxs_phy { |
149 | struct usb_phy phy; | |
150 | struct clk *clk; | |
2400780e | 151 | const struct mxs_phy_data *data; |
0d896538 | 152 | struct regmap *regmap_anatop; |
83be181b | 153 | int port_id; |
b3d99681 RZ |
154 | }; |
155 | ||
bf783438 PC |
156 | static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy) |
157 | { | |
158 | return mxs_phy->data == &imx6q_phy_data; | |
159 | } | |
160 | ||
161 | static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) | |
162 | { | |
163 | return mxs_phy->data == &imx6sl_phy_data; | |
164 | } | |
165 | ||
47d1845f PC |
166 | /* |
167 | * PHY needs some 32K cycles to switch from 32K clock to | |
168 | * bus (such as AHB/AXI, etc) clock. | |
169 | */ | |
170 | static void mxs_phy_clock_switch_delay(void) | |
171 | { | |
172 | usleep_range(300, 400); | |
173 | } | |
174 | ||
51e563e3 | 175 | static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) |
b3d99681 | 176 | { |
51e563e3 | 177 | int ret; |
b3d99681 RZ |
178 | void __iomem *base = mxs_phy->phy.io_priv; |
179 | ||
51e563e3 FE |
180 | ret = stmp_reset_block(base + HW_USBPHY_CTRL); |
181 | if (ret) | |
182 | return ret; | |
b3d99681 RZ |
183 | |
184 | /* Power up the PHY */ | |
b5a726b3 | 185 | writel(0, base + HW_USBPHY_PWD); |
b3d99681 | 186 | |
13644144 PC |
187 | /* |
188 | * USB PHY Ctrl Setting | |
189 | * - Auto clock/power on | |
190 | * - Enable full/low speed support | |
191 | */ | |
192 | writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | | |
193 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | | |
194 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | | |
195 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | | |
196 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | | |
197 | BM_USBPHY_CTRL_ENUTMILEVEL2 | | |
198 | BM_USBPHY_CTRL_ENUTMILEVEL3, | |
b5a726b3 | 199 | base + HW_USBPHY_CTRL_SET); |
51e563e3 | 200 | |
22db05ec PC |
201 | if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) |
202 | writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); | |
203 | ||
51e563e3 | 204 | return 0; |
b3d99681 RZ |
205 | } |
206 | ||
3f126505 PC |
207 | /* Return true if the vbus is there */ |
208 | static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy) | |
209 | { | |
210 | unsigned int vbus_value; | |
211 | ||
212 | if (mxs_phy->port_id == 0) | |
213 | regmap_read(mxs_phy->regmap_anatop, | |
214 | ANADIG_USB1_VBUS_DET_STAT, | |
215 | &vbus_value); | |
216 | else if (mxs_phy->port_id == 1) | |
217 | regmap_read(mxs_phy->regmap_anatop, | |
218 | ANADIG_USB2_VBUS_DET_STAT, | |
219 | &vbus_value); | |
220 | ||
221 | if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID) | |
222 | return true; | |
223 | else | |
224 | return false; | |
225 | } | |
226 | ||
227 | static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) | |
228 | { | |
229 | void __iomem *base = mxs_phy->phy.io_priv; | |
230 | u32 reg; | |
231 | ||
232 | if (disconnect) | |
233 | writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, | |
234 | base + HW_USBPHY_DEBUG_CLR); | |
235 | ||
236 | if (mxs_phy->port_id == 0) { | |
237 | reg = disconnect ? ANADIG_USB1_LOOPBACK_SET | |
238 | : ANADIG_USB1_LOOPBACK_CLR; | |
239 | regmap_write(mxs_phy->regmap_anatop, reg, | |
240 | BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 | | |
241 | BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN); | |
242 | } else if (mxs_phy->port_id == 1) { | |
243 | reg = disconnect ? ANADIG_USB2_LOOPBACK_SET | |
244 | : ANADIG_USB2_LOOPBACK_CLR; | |
245 | regmap_write(mxs_phy->regmap_anatop, reg, | |
246 | BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 | | |
247 | BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN); | |
248 | } | |
249 | ||
250 | if (!disconnect) | |
251 | writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, | |
252 | base + HW_USBPHY_DEBUG_SET); | |
253 | ||
254 | /* Delay some time, and let Linestate be SE0 for controller */ | |
255 | if (disconnect) | |
256 | usleep_range(500, 1000); | |
257 | } | |
258 | ||
259 | static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) | |
260 | { | |
261 | bool vbus_is_on = false; | |
262 | ||
263 | /* If the SoCs don't need to disconnect line without vbus, quit */ | |
264 | if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) | |
265 | return; | |
266 | ||
267 | /* If the SoCs don't have anatop, quit */ | |
268 | if (!mxs_phy->regmap_anatop) | |
269 | return; | |
270 | ||
271 | vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); | |
272 | ||
273 | if (on && !vbus_is_on) | |
274 | __mxs_phy_disconnect_line(mxs_phy, true); | |
275 | else | |
276 | __mxs_phy_disconnect_line(mxs_phy, false); | |
277 | ||
278 | } | |
279 | ||
b3d99681 RZ |
280 | static int mxs_phy_init(struct usb_phy *phy) |
281 | { | |
67c21fc8 | 282 | int ret; |
b3d99681 RZ |
283 | struct mxs_phy *mxs_phy = to_mxs_phy(phy); |
284 | ||
47d1845f | 285 | mxs_phy_clock_switch_delay(); |
67c21fc8 FE |
286 | ret = clk_prepare_enable(mxs_phy->clk); |
287 | if (ret) | |
288 | return ret; | |
289 | ||
51e563e3 | 290 | return mxs_phy_hw_init(mxs_phy); |
b3d99681 RZ |
291 | } |
292 | ||
293 | static void mxs_phy_shutdown(struct usb_phy *phy) | |
294 | { | |
295 | struct mxs_phy *mxs_phy = to_mxs_phy(phy); | |
fdf80e78 PC |
296 | u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | |
297 | BM_USBPHY_CTRL_ENDPDMCHG_WKUP | | |
298 | BM_USBPHY_CTRL_ENIDCHG_WKUP | | |
299 | BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | | |
300 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | | |
301 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | | |
302 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | | |
303 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL; | |
304 | ||
305 | writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); | |
306 | writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); | |
b3d99681 | 307 | |
b5a726b3 MKB |
308 | writel(BM_USBPHY_CTRL_CLKGATE, |
309 | phy->io_priv + HW_USBPHY_CTRL_SET); | |
b3d99681 RZ |
310 | |
311 | clk_disable_unprepare(mxs_phy->clk); | |
312 | } | |
313 | ||
04a6221c PC |
314 | static int mxs_phy_suspend(struct usb_phy *x, int suspend) |
315 | { | |
67c21fc8 | 316 | int ret; |
04a6221c PC |
317 | struct mxs_phy *mxs_phy = to_mxs_phy(x); |
318 | ||
319 | if (suspend) { | |
b5a726b3 MKB |
320 | writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); |
321 | writel(BM_USBPHY_CTRL_CLKGATE, | |
322 | x->io_priv + HW_USBPHY_CTRL_SET); | |
04a6221c PC |
323 | clk_disable_unprepare(mxs_phy->clk); |
324 | } else { | |
47d1845f | 325 | mxs_phy_clock_switch_delay(); |
67c21fc8 FE |
326 | ret = clk_prepare_enable(mxs_phy->clk); |
327 | if (ret) | |
328 | return ret; | |
b5a726b3 MKB |
329 | writel(BM_USBPHY_CTRL_CLKGATE, |
330 | x->io_priv + HW_USBPHY_CTRL_CLR); | |
331 | writel(0, x->io_priv + HW_USBPHY_PWD); | |
04a6221c PC |
332 | } |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
3f126505 PC |
337 | static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled) |
338 | { | |
339 | struct mxs_phy *mxs_phy = to_mxs_phy(x); | |
340 | u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | | |
341 | BM_USBPHY_CTRL_ENDPDMCHG_WKUP | | |
342 | BM_USBPHY_CTRL_ENIDCHG_WKUP; | |
343 | if (enabled) { | |
344 | mxs_phy_disconnect_line(mxs_phy, true); | |
345 | writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); | |
346 | } else { | |
347 | writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); | |
348 | mxs_phy_disconnect_line(mxs_phy, false); | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
ac96511b PC |
354 | static int mxs_phy_on_connect(struct usb_phy *phy, |
355 | enum usb_device_speed speed) | |
b3d99681 | 356 | { |
f6a15824 PC |
357 | dev_dbg(phy->dev, "%s device has connected\n", |
358 | (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); | |
b3d99681 | 359 | |
ac96511b | 360 | if (speed == USB_SPEED_HIGH) |
b5a726b3 MKB |
361 | writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, |
362 | phy->io_priv + HW_USBPHY_CTRL_SET); | |
b3d99681 RZ |
363 | |
364 | return 0; | |
365 | } | |
366 | ||
ac96511b PC |
367 | static int mxs_phy_on_disconnect(struct usb_phy *phy, |
368 | enum usb_device_speed speed) | |
b3d99681 | 369 | { |
f6a15824 PC |
370 | dev_dbg(phy->dev, "%s device has disconnected\n", |
371 | (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); | |
b3d99681 | 372 | |
f78c0957 PC |
373 | /* Sometimes, the speed is not high speed when the error occurs */ |
374 | if (readl(phy->io_priv + HW_USBPHY_CTRL) & | |
375 | BM_USBPHY_CTRL_ENHOSTDISCONDETECT) | |
b5a726b3 MKB |
376 | writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, |
377 | phy->io_priv + HW_USBPHY_CTRL_CLR); | |
b3d99681 RZ |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
382 | static int mxs_phy_probe(struct platform_device *pdev) | |
383 | { | |
384 | struct resource *res; | |
385 | void __iomem *base; | |
386 | struct clk *clk; | |
387 | struct mxs_phy *mxs_phy; | |
25df6397 | 388 | int ret; |
2400780e PC |
389 | const struct of_device_id *of_id = |
390 | of_match_device(mxs_phy_dt_ids, &pdev->dev); | |
0d896538 | 391 | struct device_node *np = pdev->dev.of_node; |
b3d99681 RZ |
392 | |
393 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
148e1134 TR |
394 | base = devm_ioremap_resource(&pdev->dev, res); |
395 | if (IS_ERR(base)) | |
396 | return PTR_ERR(base); | |
b3d99681 RZ |
397 | |
398 | clk = devm_clk_get(&pdev->dev, NULL); | |
399 | if (IS_ERR(clk)) { | |
400 | dev_err(&pdev->dev, | |
401 | "can't get the clock, err=%ld", PTR_ERR(clk)); | |
402 | return PTR_ERR(clk); | |
403 | } | |
404 | ||
405 | mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); | |
c62fe556 | 406 | if (!mxs_phy) |
b3d99681 | 407 | return -ENOMEM; |
b3d99681 | 408 | |
0d896538 PC |
409 | /* Some SoCs don't have anatop registers */ |
410 | if (of_get_property(np, "fsl,anatop", NULL)) { | |
411 | mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle | |
412 | (np, "fsl,anatop"); | |
413 | if (IS_ERR(mxs_phy->regmap_anatop)) { | |
414 | dev_dbg(&pdev->dev, | |
415 | "failed to find regmap for anatop\n"); | |
416 | return PTR_ERR(mxs_phy->regmap_anatop); | |
417 | } | |
418 | } | |
419 | ||
83be181b PC |
420 | ret = of_alias_get_id(np, "usbphy"); |
421 | if (ret < 0) | |
422 | dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
423 | mxs_phy->port_id = ret; | |
424 | ||
b3d99681 RZ |
425 | mxs_phy->phy.io_priv = base; |
426 | mxs_phy->phy.dev = &pdev->dev; | |
427 | mxs_phy->phy.label = DRIVER_NAME; | |
428 | mxs_phy->phy.init = mxs_phy_init; | |
429 | mxs_phy->phy.shutdown = mxs_phy_shutdown; | |
04a6221c | 430 | mxs_phy->phy.set_suspend = mxs_phy_suspend; |
b3d99681 RZ |
431 | mxs_phy->phy.notify_connect = mxs_phy_on_connect; |
432 | mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; | |
4e0aa635 | 433 | mxs_phy->phy.type = USB_PHY_TYPE_USB2; |
3f126505 | 434 | mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; |
b3d99681 | 435 | |
b3d99681 | 436 | mxs_phy->clk = clk; |
2400780e | 437 | mxs_phy->data = of_id->data; |
b3d99681 | 438 | |
97a27f73 | 439 | platform_set_drvdata(pdev, mxs_phy); |
b3d99681 | 440 | |
bf783438 PC |
441 | device_set_wakeup_capable(&pdev->dev, true); |
442 | ||
25df6397 SH |
443 | ret = usb_add_phy_dev(&mxs_phy->phy); |
444 | if (ret) | |
445 | return ret; | |
446 | ||
b3d99681 RZ |
447 | return 0; |
448 | } | |
449 | ||
fb4e98ab | 450 | static int mxs_phy_remove(struct platform_device *pdev) |
b3d99681 | 451 | { |
25df6397 SH |
452 | struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); |
453 | ||
454 | usb_remove_phy(&mxs_phy->phy); | |
455 | ||
b3d99681 RZ |
456 | return 0; |
457 | } | |
458 | ||
bf783438 PC |
459 | #ifdef CONFIG_PM_SLEEP |
460 | static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on) | |
461 | { | |
462 | unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; | |
463 | ||
464 | /* If the SoCs don't have anatop, quit */ | |
465 | if (!mxs_phy->regmap_anatop) | |
466 | return; | |
467 | ||
468 | if (is_imx6q_phy(mxs_phy)) | |
469 | regmap_write(mxs_phy->regmap_anatop, reg, | |
470 | BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG); | |
471 | else if (is_imx6sl_phy(mxs_phy)) | |
472 | regmap_write(mxs_phy->regmap_anatop, | |
473 | reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); | |
474 | } | |
475 | ||
476 | static int mxs_phy_system_suspend(struct device *dev) | |
477 | { | |
478 | struct mxs_phy *mxs_phy = dev_get_drvdata(dev); | |
479 | ||
480 | if (device_may_wakeup(dev)) | |
481 | mxs_phy_enable_ldo_in_suspend(mxs_phy, true); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int mxs_phy_system_resume(struct device *dev) | |
487 | { | |
488 | struct mxs_phy *mxs_phy = dev_get_drvdata(dev); | |
489 | ||
490 | if (device_may_wakeup(dev)) | |
491 | mxs_phy_enable_ldo_in_suspend(mxs_phy, false); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | #endif /* CONFIG_PM_SLEEP */ | |
496 | ||
497 | static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, | |
498 | mxs_phy_system_resume); | |
499 | ||
b3d99681 RZ |
500 | static struct platform_driver mxs_phy_driver = { |
501 | .probe = mxs_phy_probe, | |
7690417d | 502 | .remove = mxs_phy_remove, |
b3d99681 RZ |
503 | .driver = { |
504 | .name = DRIVER_NAME, | |
b3d99681 | 505 | .of_match_table = mxs_phy_dt_ids, |
bf783438 | 506 | .pm = &mxs_phy_pm, |
b3d99681 RZ |
507 | }, |
508 | }; | |
509 | ||
510 | static int __init mxs_phy_module_init(void) | |
511 | { | |
512 | return platform_driver_register(&mxs_phy_driver); | |
513 | } | |
514 | postcore_initcall(mxs_phy_module_init); | |
515 | ||
516 | static void __exit mxs_phy_module_exit(void) | |
517 | { | |
518 | platform_driver_unregister(&mxs_phy_driver); | |
519 | } | |
520 | module_exit(mxs_phy_module_exit); | |
521 | ||
522 | MODULE_ALIAS("platform:mxs-usb-phy"); | |
523 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
524 | MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); | |
525 | MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); | |
526 | MODULE_LICENSE("GPL"); |