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91525d08 | 1 | /* |
91525d08 | 2 | * Copyright (C) 2010 Google, Inc. |
2d22b42d | 3 | * Copyright (C) 2013 NVIDIA Corporation |
91525d08 BG |
4 | * |
5 | * Author: | |
6 | * Erik Gilling <konkers@google.com> | |
7 | * Benoit Goby <benoit@android.com> | |
2d22b42d | 8 | * Venu Byravarasu <vbyravarasu@nvidia.com> |
91525d08 BG |
9 | * |
10 | * This software is licensed under the terms of the GNU General Public | |
11 | * License version 2, as published by the Free Software Foundation, and | |
12 | * may be copied, distributed, and modified under those terms. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/resource.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/err.h> | |
4265cbfd | 25 | #include <linux/export.h> |
587376a1 | 26 | #include <linux/module.h> |
91525d08 BG |
27 | #include <linux/platform_device.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/gpio.h> | |
3a55c6a8 | 30 | #include <linux/of.h> |
3e635202 | 31 | #include <linux/of_device.h> |
aa607ebf | 32 | #include <linux/of_gpio.h> |
91525d08 BG |
33 | #include <linux/usb/otg.h> |
34 | #include <linux/usb/ulpi.h> | |
9fdb07f7 | 35 | #include <linux/usb/of.h> |
91a687d8 | 36 | #include <linux/usb/ehci_def.h> |
1ba8216f | 37 | #include <linux/usb/tegra_usb_phy.h> |
f5b8c8b6 | 38 | #include <linux/regulator/consumer.h> |
91525d08 BG |
39 | |
40 | #define ULPI_VIEWPORT 0x170 | |
41 | ||
3e635202 | 42 | /* PORTSC PTS/PHCD bits, Tegra20 only */ |
91a687d8 SW |
43 | #define TEGRA_USB_PORTSC1 0x184 |
44 | #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) | |
45 | #define TEGRA_USB_PORTSC1_PHCD (1 << 23) | |
46 | ||
3e635202 TT |
47 | /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */ |
48 | #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 | |
49 | #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) | |
50 | #define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22) | |
51 | ||
91a687d8 SW |
52 | /* Bits of PORTSC1, which will get cleared by writing 1 into them */ |
53 | #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) | |
54 | ||
91525d08 BG |
55 | #define USB_SUSP_CTRL 0x400 |
56 | #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) | |
57 | #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) | |
58 | #define USB_SUSP_CLR (1 << 5) | |
59 | #define USB_PHY_CLK_VALID (1 << 7) | |
60 | #define UTMIP_RESET (1 << 11) | |
61 | #define UHSIC_RESET (1 << 11) | |
62 | #define UTMIP_PHY_ENABLE (1 << 12) | |
63 | #define ULPI_PHY_ENABLE (1 << 13) | |
64 | #define USB_SUSP_SET (1 << 14) | |
65 | #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) | |
66 | ||
67 | #define USB1_LEGACY_CTRL 0x410 | |
68 | #define USB1_NO_LEGACY_MODE (1 << 0) | |
69 | #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) | |
70 | #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) | |
71 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ | |
72 | (1 << 1) | |
73 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) | |
74 | #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) | |
75 | ||
76 | #define ULPI_TIMING_CTRL_0 0x424 | |
77 | #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) | |
78 | #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) | |
79 | ||
80 | #define ULPI_TIMING_CTRL_1 0x428 | |
81 | #define ULPI_DATA_TRIMMER_LOAD (1 << 0) | |
82 | #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) | |
83 | #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) | |
84 | #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) | |
85 | #define ULPI_DIR_TRIMMER_LOAD (1 << 24) | |
86 | #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) | |
87 | ||
88 | #define UTMIP_PLL_CFG1 0x804 | |
89 | #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
90 | #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
91 | ||
92 | #define UTMIP_XCVR_CFG0 0x808 | |
93 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) | |
f5833a0b | 94 | #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) |
91525d08 BG |
95 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) |
96 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) | |
97 | #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) | |
98 | #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) | |
99 | #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) | |
f5833a0b | 100 | #define UTMIP_XCVR_LSBIAS_SEL (1 << 21) |
e497a24d TT |
101 | #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) |
102 | #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) | |
91525d08 BG |
103 | |
104 | #define UTMIP_BIAS_CFG0 0x80c | |
105 | #define UTMIP_OTGPD (1 << 11) | |
106 | #define UTMIP_BIASPD (1 << 10) | |
e497a24d TT |
107 | #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) |
108 | #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) | |
109 | #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) | |
91525d08 BG |
110 | |
111 | #define UTMIP_HSRX_CFG0 0x810 | |
112 | #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) | |
113 | #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) | |
114 | ||
115 | #define UTMIP_HSRX_CFG1 0x814 | |
116 | #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) | |
117 | ||
118 | #define UTMIP_TX_CFG0 0x820 | |
119 | #define UTMIP_FS_PREABMLE_J (1 << 19) | |
120 | #define UTMIP_HS_DISCON_DISABLE (1 << 8) | |
121 | ||
122 | #define UTMIP_MISC_CFG0 0x824 | |
123 | #define UTMIP_DPDM_OBSERVE (1 << 26) | |
124 | #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) | |
125 | #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) | |
126 | #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) | |
127 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) | |
128 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) | |
129 | #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) | |
130 | ||
131 | #define UTMIP_MISC_CFG1 0x828 | |
132 | #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) | |
133 | #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
134 | ||
135 | #define UTMIP_DEBOUNCE_CFG0 0x82c | |
136 | #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) | |
137 | ||
138 | #define UTMIP_BAT_CHRG_CFG0 0x830 | |
139 | #define UTMIP_PD_CHRG (1 << 0) | |
140 | ||
141 | #define UTMIP_SPARE_CFG0 0x834 | |
142 | #define FUSE_SETUP_SEL (1 << 3) | |
143 | ||
144 | #define UTMIP_XCVR_CFG1 0x838 | |
145 | #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) | |
146 | #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) | |
147 | #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) | |
148 | #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) | |
149 | ||
150 | #define UTMIP_BIAS_CFG1 0x83c | |
151 | #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) | |
152 | ||
3e635202 TT |
153 | /* For Tegra30 and above only, the address is different in Tegra20 */ |
154 | #define USB_USBMODE 0x1f8 | |
155 | #define USB_USBMODE_MASK (3 << 0) | |
156 | #define USB_USBMODE_HOST (3 << 0) | |
157 | #define USB_USBMODE_DEVICE (2 << 0) | |
158 | ||
91525d08 BG |
159 | static DEFINE_SPINLOCK(utmip_pad_lock); |
160 | static int utmip_pad_count; | |
161 | ||
162 | struct tegra_xtal_freq { | |
163 | int freq; | |
164 | u8 enable_delay; | |
165 | u8 stable_count; | |
166 | u8 active_delay; | |
167 | u8 xtal_freq_count; | |
168 | u16 debounce; | |
169 | }; | |
170 | ||
171 | static const struct tegra_xtal_freq tegra_freq_table[] = { | |
172 | { | |
173 | .freq = 12000000, | |
174 | .enable_delay = 0x02, | |
175 | .stable_count = 0x2F, | |
176 | .active_delay = 0x04, | |
177 | .xtal_freq_count = 0x76, | |
178 | .debounce = 0x7530, | |
179 | }, | |
180 | { | |
181 | .freq = 13000000, | |
182 | .enable_delay = 0x02, | |
183 | .stable_count = 0x33, | |
184 | .active_delay = 0x05, | |
185 | .xtal_freq_count = 0x7F, | |
186 | .debounce = 0x7EF4, | |
187 | }, | |
188 | { | |
189 | .freq = 19200000, | |
190 | .enable_delay = 0x03, | |
191 | .stable_count = 0x4B, | |
192 | .active_delay = 0x06, | |
193 | .xtal_freq_count = 0xBB, | |
194 | .debounce = 0xBB80, | |
195 | }, | |
196 | { | |
197 | .freq = 26000000, | |
198 | .enable_delay = 0x04, | |
199 | .stable_count = 0x66, | |
200 | .active_delay = 0x09, | |
201 | .xtal_freq_count = 0xFE, | |
202 | .debounce = 0xFDE8, | |
203 | }, | |
204 | }; | |
205 | ||
91a687d8 SW |
206 | static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) |
207 | { | |
208 | void __iomem *base = phy->regs; | |
209 | unsigned long val; | |
210 | ||
3e635202 TT |
211 | if (phy->soc_config->has_hostpc) { |
212 | val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); | |
213 | val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); | |
214 | val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); | |
215 | writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); | |
216 | } else { | |
217 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
218 | val &= ~TEGRA_USB_PORTSC1_PTS(~0); | |
219 | val |= TEGRA_USB_PORTSC1_PTS(pts_val); | |
220 | writel(val, base + TEGRA_USB_PORTSC1); | |
221 | } | |
91a687d8 SW |
222 | } |
223 | ||
224 | static void set_phcd(struct tegra_usb_phy *phy, bool enable) | |
225 | { | |
226 | void __iomem *base = phy->regs; | |
227 | unsigned long val; | |
228 | ||
3e635202 TT |
229 | if (phy->soc_config->has_hostpc) { |
230 | val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); | |
231 | if (enable) | |
232 | val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; | |
233 | else | |
234 | val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; | |
235 | writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); | |
236 | } else { | |
237 | val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; | |
238 | if (enable) | |
239 | val |= TEGRA_USB_PORTSC1_PHCD; | |
240 | else | |
241 | val &= ~TEGRA_USB_PORTSC1_PHCD; | |
242 | writel(val, base + TEGRA_USB_PORTSC1); | |
243 | } | |
91a687d8 SW |
244 | } |
245 | ||
91525d08 BG |
246 | static int utmip_pad_open(struct tegra_usb_phy *phy) |
247 | { | |
185d0fd5 | 248 | phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads"); |
91525d08 BG |
249 | if (IS_ERR(phy->pad_clk)) { |
250 | pr_err("%s: can't get utmip pad clock\n", __func__); | |
251 | return PTR_ERR(phy->pad_clk); | |
252 | } | |
253 | ||
91525d08 BG |
254 | return 0; |
255 | } | |
256 | ||
91525d08 BG |
257 | static void utmip_pad_power_on(struct tegra_usb_phy *phy) |
258 | { | |
259 | unsigned long val, flags; | |
260 | void __iomem *base = phy->pad_regs; | |
e497a24d | 261 | struct tegra_utmip_config *config = phy->config; |
91525d08 | 262 | |
6a5278d0 | 263 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
264 | |
265 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
266 | ||
267 | if (utmip_pad_count++ == 0) { | |
268 | val = readl(base + UTMIP_BIAS_CFG0); | |
269 | val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); | |
e497a24d TT |
270 | |
271 | if (phy->soc_config->requires_extra_tuning_parameters) { | |
272 | val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | | |
273 | UTMIP_HSDISCON_LEVEL(~0) | | |
274 | UTMIP_HSDISCON_LEVEL_MSB(~0)); | |
275 | ||
276 | val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); | |
277 | val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); | |
278 | val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); | |
279 | } | |
91525d08 BG |
280 | writel(val, base + UTMIP_BIAS_CFG0); |
281 | } | |
282 | ||
283 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
284 | ||
6a5278d0 | 285 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
286 | } |
287 | ||
288 | static int utmip_pad_power_off(struct tegra_usb_phy *phy) | |
289 | { | |
290 | unsigned long val, flags; | |
291 | void __iomem *base = phy->pad_regs; | |
292 | ||
293 | if (!utmip_pad_count) { | |
294 | pr_err("%s: utmip pad already powered off\n", __func__); | |
295 | return -EINVAL; | |
296 | } | |
297 | ||
6a5278d0 | 298 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
299 | |
300 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
301 | ||
302 | if (--utmip_pad_count == 0) { | |
303 | val = readl(base + UTMIP_BIAS_CFG0); | |
304 | val |= UTMIP_OTGPD | UTMIP_BIASPD; | |
305 | writel(val, base + UTMIP_BIAS_CFG0); | |
306 | } | |
307 | ||
308 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
309 | ||
6a5278d0 | 310 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
311 | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) | |
316 | { | |
317 | unsigned long timeout = 2000; | |
318 | do { | |
319 | if ((readl(reg) & mask) == result) | |
320 | return 0; | |
321 | udelay(1); | |
322 | timeout--; | |
323 | } while (timeout); | |
324 | return -1; | |
325 | } | |
326 | ||
327 | static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) | |
328 | { | |
329 | unsigned long val; | |
330 | void __iomem *base = phy->regs; | |
331 | ||
3a55c6a8 | 332 | if (phy->is_legacy_phy) { |
91525d08 BG |
333 | val = readl(base + USB_SUSP_CTRL); |
334 | val |= USB_SUSP_SET; | |
335 | writel(val, base + USB_SUSP_CTRL); | |
336 | ||
337 | udelay(10); | |
338 | ||
339 | val = readl(base + USB_SUSP_CTRL); | |
340 | val &= ~USB_SUSP_SET; | |
341 | writel(val, base + USB_SUSP_CTRL); | |
bbdabdb6 | 342 | } else |
91a687d8 | 343 | set_phcd(phy, true); |
91525d08 BG |
344 | |
345 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) | |
346 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
347 | } | |
348 | ||
349 | static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) | |
350 | { | |
351 | unsigned long val; | |
352 | void __iomem *base = phy->regs; | |
353 | ||
3a55c6a8 | 354 | if (phy->is_legacy_phy) { |
91525d08 BG |
355 | val = readl(base + USB_SUSP_CTRL); |
356 | val |= USB_SUSP_CLR; | |
357 | writel(val, base + USB_SUSP_CTRL); | |
358 | ||
359 | udelay(10); | |
360 | ||
361 | val = readl(base + USB_SUSP_CTRL); | |
362 | val &= ~USB_SUSP_CLR; | |
363 | writel(val, base + USB_SUSP_CTRL); | |
bbdabdb6 | 364 | } else |
91a687d8 | 365 | set_phcd(phy, false); |
91525d08 BG |
366 | |
367 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, | |
368 | USB_PHY_CLK_VALID)) | |
369 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
370 | } | |
371 | ||
372 | static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |
373 | { | |
374 | unsigned long val; | |
375 | void __iomem *base = phy->regs; | |
376 | struct tegra_utmip_config *config = phy->config; | |
377 | ||
378 | val = readl(base + USB_SUSP_CTRL); | |
379 | val |= UTMIP_RESET; | |
380 | writel(val, base + USB_SUSP_CTRL); | |
381 | ||
3a55c6a8 | 382 | if (phy->is_legacy_phy) { |
91525d08 BG |
383 | val = readl(base + USB1_LEGACY_CTRL); |
384 | val |= USB1_NO_LEGACY_MODE; | |
385 | writel(val, base + USB1_LEGACY_CTRL); | |
386 | } | |
387 | ||
388 | val = readl(base + UTMIP_TX_CFG0); | |
f5833a0b | 389 | val |= UTMIP_FS_PREABMLE_J; |
91525d08 BG |
390 | writel(val, base + UTMIP_TX_CFG0); |
391 | ||
392 | val = readl(base + UTMIP_HSRX_CFG0); | |
393 | val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); | |
394 | val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); | |
395 | val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); | |
396 | writel(val, base + UTMIP_HSRX_CFG0); | |
397 | ||
398 | val = readl(base + UTMIP_HSRX_CFG1); | |
399 | val &= ~UTMIP_HS_SYNC_START_DLY(~0); | |
400 | val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); | |
401 | writel(val, base + UTMIP_HSRX_CFG1); | |
402 | ||
403 | val = readl(base + UTMIP_DEBOUNCE_CFG0); | |
404 | val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); | |
405 | val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); | |
406 | writel(val, base + UTMIP_DEBOUNCE_CFG0); | |
407 | ||
408 | val = readl(base + UTMIP_MISC_CFG0); | |
409 | val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; | |
410 | writel(val, base + UTMIP_MISC_CFG0); | |
411 | ||
3e635202 TT |
412 | if (!phy->soc_config->utmi_pll_config_in_car_module) { |
413 | val = readl(base + UTMIP_MISC_CFG1); | |
414 | val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | | |
415 | UTMIP_PLLU_STABLE_COUNT(~0)); | |
416 | val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | | |
417 | UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); | |
418 | writel(val, base + UTMIP_MISC_CFG1); | |
419 | ||
420 | val = readl(base + UTMIP_PLL_CFG1); | |
421 | val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | | |
422 | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); | |
423 | val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | | |
424 | UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); | |
425 | writel(val, base + UTMIP_PLL_CFG1); | |
426 | } | |
91525d08 | 427 | |
6558d7ed | 428 | if (phy->mode == USB_DR_MODE_PERIPHERAL) { |
91525d08 BG |
429 | val = readl(base + USB_SUSP_CTRL); |
430 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); | |
431 | writel(val, base + USB_SUSP_CTRL); | |
f5833a0b TT |
432 | |
433 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
434 | val &= ~UTMIP_PD_CHRG; | |
435 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
436 | } else { | |
437 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
438 | val |= UTMIP_PD_CHRG; | |
439 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
91525d08 BG |
440 | } |
441 | ||
442 | utmip_pad_power_on(phy); | |
443 | ||
444 | val = readl(base + UTMIP_XCVR_CFG0); | |
445 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
f5833a0b TT |
446 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL | |
447 | UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) | | |
e497a24d TT |
448 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0)); |
449 | ||
450 | if (!config->xcvr_setup_use_fuses) { | |
451 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); | |
452 | val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); | |
453 | } | |
91525d08 BG |
454 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); |
455 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); | |
e497a24d TT |
456 | |
457 | if (phy->soc_config->requires_extra_tuning_parameters) { | |
458 | val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); | |
459 | val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); | |
460 | val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); | |
461 | } | |
91525d08 BG |
462 | writel(val, base + UTMIP_XCVR_CFG0); |
463 | ||
464 | val = readl(base + UTMIP_XCVR_CFG1); | |
465 | val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
466 | UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); | |
467 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); | |
468 | writel(val, base + UTMIP_XCVR_CFG1); | |
469 | ||
91525d08 BG |
470 | val = readl(base + UTMIP_BIAS_CFG1); |
471 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); | |
472 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); | |
473 | writel(val, base + UTMIP_BIAS_CFG1); | |
474 | ||
e497a24d TT |
475 | val = readl(base + UTMIP_SPARE_CFG0); |
476 | if (config->xcvr_setup_use_fuses) | |
477 | val |= FUSE_SETUP_SEL; | |
478 | else | |
479 | val &= ~FUSE_SETUP_SEL; | |
480 | writel(val, base + UTMIP_SPARE_CFG0); | |
481 | ||
482 | if (!phy->is_legacy_phy) { | |
91525d08 BG |
483 | val = readl(base + USB_SUSP_CTRL); |
484 | val |= UTMIP_PHY_ENABLE; | |
485 | writel(val, base + USB_SUSP_CTRL); | |
486 | } | |
487 | ||
488 | val = readl(base + USB_SUSP_CTRL); | |
489 | val &= ~UTMIP_RESET; | |
490 | writel(val, base + USB_SUSP_CTRL); | |
491 | ||
3a55c6a8 | 492 | if (phy->is_legacy_phy) { |
91525d08 BG |
493 | val = readl(base + USB1_LEGACY_CTRL); |
494 | val &= ~USB1_VBUS_SENSE_CTL_MASK; | |
495 | val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; | |
496 | writel(val, base + USB1_LEGACY_CTRL); | |
497 | ||
498 | val = readl(base + USB_SUSP_CTRL); | |
499 | val &= ~USB_SUSP_SET; | |
500 | writel(val, base + USB_SUSP_CTRL); | |
501 | } | |
502 | ||
503 | utmi_phy_clk_enable(phy); | |
504 | ||
3e635202 TT |
505 | if (phy->soc_config->requires_usbmode_setup) { |
506 | val = readl(base + USB_USBMODE); | |
507 | val &= ~USB_USBMODE_MASK; | |
508 | if (phy->mode == USB_DR_MODE_HOST) | |
509 | val |= USB_USBMODE_HOST; | |
510 | else | |
511 | val |= USB_USBMODE_DEVICE; | |
512 | writel(val, base + USB_USBMODE); | |
513 | } | |
514 | ||
bbdabdb6 | 515 | if (!phy->is_legacy_phy) |
91a687d8 | 516 | set_pts(phy, 0); |
91525d08 BG |
517 | |
518 | return 0; | |
519 | } | |
520 | ||
1ba8216f | 521 | static int utmi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 BG |
522 | { |
523 | unsigned long val; | |
524 | void __iomem *base = phy->regs; | |
525 | ||
526 | utmi_phy_clk_disable(phy); | |
527 | ||
6558d7ed | 528 | if (phy->mode == USB_DR_MODE_PERIPHERAL) { |
91525d08 BG |
529 | val = readl(base + USB_SUSP_CTRL); |
530 | val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); | |
531 | val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); | |
532 | writel(val, base + USB_SUSP_CTRL); | |
533 | } | |
534 | ||
535 | val = readl(base + USB_SUSP_CTRL); | |
536 | val |= UTMIP_RESET; | |
537 | writel(val, base + USB_SUSP_CTRL); | |
538 | ||
539 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
540 | val |= UTMIP_PD_CHRG; | |
541 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
542 | ||
543 | val = readl(base + UTMIP_XCVR_CFG0); | |
544 | val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
545 | UTMIP_FORCE_PDZI_POWERDOWN; | |
546 | writel(val, base + UTMIP_XCVR_CFG0); | |
547 | ||
548 | val = readl(base + UTMIP_XCVR_CFG1); | |
549 | val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
550 | UTMIP_FORCE_PDDR_POWERDOWN; | |
551 | writel(val, base + UTMIP_XCVR_CFG1); | |
552 | ||
1ba8216f | 553 | return utmip_pad_power_off(phy); |
91525d08 BG |
554 | } |
555 | ||
556 | static void utmi_phy_preresume(struct tegra_usb_phy *phy) | |
557 | { | |
558 | unsigned long val; | |
559 | void __iomem *base = phy->regs; | |
560 | ||
561 | val = readl(base + UTMIP_TX_CFG0); | |
562 | val |= UTMIP_HS_DISCON_DISABLE; | |
563 | writel(val, base + UTMIP_TX_CFG0); | |
564 | } | |
565 | ||
566 | static void utmi_phy_postresume(struct tegra_usb_phy *phy) | |
567 | { | |
568 | unsigned long val; | |
569 | void __iomem *base = phy->regs; | |
570 | ||
571 | val = readl(base + UTMIP_TX_CFG0); | |
572 | val &= ~UTMIP_HS_DISCON_DISABLE; | |
573 | writel(val, base + UTMIP_TX_CFG0); | |
574 | } | |
575 | ||
576 | static void utmi_phy_restore_start(struct tegra_usb_phy *phy, | |
577 | enum tegra_usb_phy_port_speed port_speed) | |
578 | { | |
579 | unsigned long val; | |
580 | void __iomem *base = phy->regs; | |
581 | ||
582 | val = readl(base + UTMIP_MISC_CFG0); | |
583 | val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); | |
584 | if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
585 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; | |
586 | else | |
587 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; | |
588 | writel(val, base + UTMIP_MISC_CFG0); | |
589 | udelay(1); | |
590 | ||
591 | val = readl(base + UTMIP_MISC_CFG0); | |
592 | val |= UTMIP_DPDM_OBSERVE; | |
593 | writel(val, base + UTMIP_MISC_CFG0); | |
594 | udelay(10); | |
595 | } | |
596 | ||
597 | static void utmi_phy_restore_end(struct tegra_usb_phy *phy) | |
598 | { | |
599 | unsigned long val; | |
600 | void __iomem *base = phy->regs; | |
601 | ||
602 | val = readl(base + UTMIP_MISC_CFG0); | |
603 | val &= ~UTMIP_DPDM_OBSERVE; | |
604 | writel(val, base + UTMIP_MISC_CFG0); | |
605 | udelay(10); | |
606 | } | |
607 | ||
608 | static int ulpi_phy_power_on(struct tegra_usb_phy *phy) | |
609 | { | |
610 | int ret; | |
611 | unsigned long val; | |
612 | void __iomem *base = phy->regs; | |
91525d08 | 613 | |
6829f92f VB |
614 | ret = gpio_direction_output(phy->reset_gpio, 0); |
615 | if (ret < 0) { | |
185d0fd5 TT |
616 | dev_err(phy->u_phy.dev, "gpio %d not set to 0\n", |
617 | phy->reset_gpio); | |
6829f92f VB |
618 | return ret; |
619 | } | |
91525d08 | 620 | msleep(5); |
6829f92f VB |
621 | ret = gpio_direction_output(phy->reset_gpio, 1); |
622 | if (ret < 0) { | |
185d0fd5 TT |
623 | dev_err(phy->u_phy.dev, "gpio %d not set to 1\n", |
624 | phy->reset_gpio); | |
6829f92f VB |
625 | return ret; |
626 | } | |
91525d08 | 627 | |
6a5278d0 | 628 | clk_prepare_enable(phy->clk); |
91525d08 BG |
629 | msleep(1); |
630 | ||
631 | val = readl(base + USB_SUSP_CTRL); | |
632 | val |= UHSIC_RESET; | |
633 | writel(val, base + USB_SUSP_CTRL); | |
634 | ||
635 | val = readl(base + ULPI_TIMING_CTRL_0); | |
636 | val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; | |
637 | writel(val, base + ULPI_TIMING_CTRL_0); | |
638 | ||
639 | val = readl(base + USB_SUSP_CTRL); | |
640 | val |= ULPI_PHY_ENABLE; | |
641 | writel(val, base + USB_SUSP_CTRL); | |
642 | ||
643 | val = 0; | |
644 | writel(val, base + ULPI_TIMING_CTRL_1); | |
645 | ||
646 | val |= ULPI_DATA_TRIMMER_SEL(4); | |
647 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); | |
648 | val |= ULPI_DIR_TRIMMER_SEL(4); | |
649 | writel(val, base + ULPI_TIMING_CTRL_1); | |
650 | udelay(10); | |
651 | ||
652 | val |= ULPI_DATA_TRIMMER_LOAD; | |
653 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; | |
654 | val |= ULPI_DIR_TRIMMER_LOAD; | |
655 | writel(val, base + ULPI_TIMING_CTRL_1); | |
656 | ||
657 | /* Fix VbusInvalid due to floating VBUS */ | |
b96d3b08 | 658 | ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); |
91525d08 BG |
659 | if (ret) { |
660 | pr_err("%s: ulpi write failed\n", __func__); | |
661 | return ret; | |
662 | } | |
663 | ||
b96d3b08 | 664 | ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); |
91525d08 BG |
665 | if (ret) { |
666 | pr_err("%s: ulpi write failed\n", __func__); | |
667 | return ret; | |
668 | } | |
669 | ||
91525d08 BG |
670 | val = readl(base + USB_SUSP_CTRL); |
671 | val |= USB_SUSP_CLR; | |
672 | writel(val, base + USB_SUSP_CTRL); | |
673 | udelay(100); | |
674 | ||
675 | val = readl(base + USB_SUSP_CTRL); | |
676 | val &= ~USB_SUSP_CLR; | |
677 | writel(val, base + USB_SUSP_CTRL); | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
1ba8216f | 682 | static int ulpi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 | 683 | { |
91525d08 | 684 | clk_disable(phy->clk); |
12ea18e4 | 685 | return gpio_direction_output(phy->reset_gpio, 0); |
1ba8216f VB |
686 | } |
687 | ||
3e346d41 | 688 | static void tegra_usb_phy_close(struct tegra_usb_phy *phy) |
1ba8216f | 689 | { |
f5b8c8b6 MP |
690 | if (!IS_ERR(phy->vbus)) |
691 | regulator_disable(phy->vbus); | |
692 | ||
1ba8216f | 693 | clk_disable_unprepare(phy->pll_u); |
1ba8216f VB |
694 | } |
695 | ||
696 | static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) | |
697 | { | |
3f9db1a1 | 698 | if (phy->is_ulpi_phy) |
1ba8216f VB |
699 | return ulpi_phy_power_on(phy); |
700 | else | |
701 | return utmi_phy_power_on(phy); | |
702 | } | |
703 | ||
704 | static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) | |
705 | { | |
3f9db1a1 | 706 | if (phy->is_ulpi_phy) |
1ba8216f VB |
707 | return ulpi_phy_power_off(phy); |
708 | else | |
709 | return utmi_phy_power_off(phy); | |
710 | } | |
711 | ||
712 | static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend) | |
713 | { | |
714 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
715 | if (suspend) | |
716 | return tegra_usb_phy_power_off(phy); | |
717 | else | |
718 | return tegra_usb_phy_power_on(phy); | |
91525d08 BG |
719 | } |
720 | ||
2d22b42d | 721 | static int ulpi_open(struct tegra_usb_phy *phy) |
91525d08 | 722 | { |
91525d08 BG |
723 | int err; |
724 | ||
185d0fd5 | 725 | phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link"); |
2d22b42d VB |
726 | if (IS_ERR(phy->clk)) { |
727 | pr_err("%s: can't get ulpi clock\n", __func__); | |
728 | return PTR_ERR(phy->clk); | |
729 | } | |
91525d08 | 730 | |
185d0fd5 TT |
731 | err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio, |
732 | "ulpi_phy_reset_b"); | |
2d22b42d | 733 | if (err < 0) { |
185d0fd5 | 734 | dev_err(phy->u_phy.dev, "request failed for gpio: %d\n", |
2d22b42d VB |
735 | phy->reset_gpio); |
736 | return err; | |
737 | } | |
91525d08 | 738 | |
2d22b42d | 739 | err = gpio_direction_output(phy->reset_gpio, 0); |
9cd9384c | 740 | if (err < 0) { |
185d0fd5 | 741 | dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n", |
2d22b42d VB |
742 | phy->reset_gpio); |
743 | return err; | |
744 | } | |
745 | ||
746 | phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); | |
747 | if (!phy->ulpi) { | |
185d0fd5 | 748 | dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n"); |
2d22b42d VB |
749 | err = -ENOMEM; |
750 | return err; | |
751 | } | |
752 | ||
753 | phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT; | |
754 | return 0; | |
755 | } | |
756 | ||
757 | static int tegra_usb_phy_init(struct tegra_usb_phy *phy) | |
758 | { | |
759 | unsigned long parent_rate; | |
760 | int i; | |
761 | int err; | |
762 | ||
185d0fd5 | 763 | phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u"); |
91525d08 BG |
764 | if (IS_ERR(phy->pll_u)) { |
765 | pr_err("Can't get pll_u clock\n"); | |
2d22b42d | 766 | return PTR_ERR(phy->pll_u); |
91525d08 | 767 | } |
2d22b42d VB |
768 | |
769 | err = clk_prepare_enable(phy->pll_u); | |
770 | if (err) | |
771 | return err; | |
91525d08 BG |
772 | |
773 | parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); | |
774 | for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { | |
775 | if (tegra_freq_table[i].freq == parent_rate) { | |
776 | phy->freq = &tegra_freq_table[i]; | |
777 | break; | |
778 | } | |
779 | } | |
780 | if (!phy->freq) { | |
781 | pr_err("invalid pll_u parent rate %ld\n", parent_rate); | |
782 | err = -EINVAL; | |
2d22b42d | 783 | goto fail; |
91525d08 BG |
784 | } |
785 | ||
f5b8c8b6 MP |
786 | if (!IS_ERR(phy->vbus)) { |
787 | err = regulator_enable(phy->vbus); | |
788 | if (err) { | |
185d0fd5 | 789 | dev_err(phy->u_phy.dev, |
f5b8c8b6 MP |
790 | "failed to enable usb vbus regulator: %d\n", |
791 | err); | |
792 | goto fail; | |
793 | } | |
794 | } | |
795 | ||
2d22b42d VB |
796 | if (phy->is_ulpi_phy) |
797 | err = ulpi_open(phy); | |
798 | else | |
799 | err = utmip_pad_open(phy); | |
800 | if (err < 0) | |
801 | goto fail; | |
91525d08 | 802 | |
2d22b42d | 803 | return 0; |
91525d08 | 804 | |
2d22b42d | 805 | fail: |
6a5278d0 | 806 | clk_disable_unprepare(phy->pll_u); |
2d22b42d | 807 | return err; |
91525d08 BG |
808 | } |
809 | ||
ab137d04 | 810 | void tegra_usb_phy_preresume(struct usb_phy *x) |
91525d08 | 811 | { |
ab137d04 VB |
812 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
813 | ||
3f9db1a1 | 814 | if (!phy->is_ulpi_phy) |
91525d08 BG |
815 | utmi_phy_preresume(phy); |
816 | } | |
4265cbfd | 817 | EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); |
91525d08 | 818 | |
ab137d04 | 819 | void tegra_usb_phy_postresume(struct usb_phy *x) |
91525d08 | 820 | { |
ab137d04 VB |
821 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
822 | ||
3f9db1a1 | 823 | if (!phy->is_ulpi_phy) |
91525d08 BG |
824 | utmi_phy_postresume(phy); |
825 | } | |
4265cbfd | 826 | EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); |
91525d08 | 827 | |
ab137d04 | 828 | void tegra_ehci_phy_restore_start(struct usb_phy *x, |
91525d08 BG |
829 | enum tegra_usb_phy_port_speed port_speed) |
830 | { | |
ab137d04 VB |
831 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
832 | ||
3f9db1a1 | 833 | if (!phy->is_ulpi_phy) |
91525d08 BG |
834 | utmi_phy_restore_start(phy, port_speed); |
835 | } | |
4265cbfd | 836 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); |
91525d08 | 837 | |
ab137d04 | 838 | void tegra_ehci_phy_restore_end(struct usb_phy *x) |
91525d08 | 839 | { |
ab137d04 VB |
840 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
841 | ||
3f9db1a1 | 842 | if (!phy->is_ulpi_phy) |
91525d08 BG |
843 | utmi_phy_restore_end(phy); |
844 | } | |
4265cbfd | 845 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); |
91525d08 | 846 | |
81d5dfe6 MP |
847 | static int read_utmi_param(struct platform_device *pdev, const char *param, |
848 | u8 *dest) | |
849 | { | |
850 | u32 value; | |
851 | int err = of_property_read_u32(pdev->dev.of_node, param, &value); | |
852 | *dest = (u8)value; | |
853 | if (err < 0) | |
854 | dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n", | |
855 | param, err); | |
856 | return err; | |
857 | } | |
858 | ||
859 | static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy, | |
860 | struct platform_device *pdev) | |
861 | { | |
862 | struct resource *res; | |
863 | int err; | |
864 | struct tegra_utmip_config *config; | |
865 | ||
866 | tegra_phy->is_ulpi_phy = false; | |
867 | ||
868 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
869 | if (!res) { | |
870 | dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n"); | |
871 | return -ENXIO; | |
872 | } | |
873 | ||
874 | tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start, | |
875 | resource_size(res)); | |
851dd02b | 876 | if (!tegra_phy->pad_regs) { |
81d5dfe6 MP |
877 | dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n"); |
878 | return -ENOMEM; | |
879 | } | |
880 | ||
881 | tegra_phy->config = devm_kzalloc(&pdev->dev, | |
882 | sizeof(*tegra_phy->config), GFP_KERNEL); | |
883 | if (!tegra_phy->config) { | |
884 | dev_err(&pdev->dev, | |
885 | "unable to allocate memory for USB UTMIP config\n"); | |
886 | return -ENOMEM; | |
887 | } | |
888 | ||
889 | config = tegra_phy->config; | |
890 | ||
891 | err = read_utmi_param(pdev, "nvidia,hssync-start-delay", | |
892 | &config->hssync_start_delay); | |
893 | if (err < 0) | |
894 | return err; | |
895 | ||
896 | err = read_utmi_param(pdev, "nvidia,elastic-limit", | |
897 | &config->elastic_limit); | |
898 | if (err < 0) | |
899 | return err; | |
900 | ||
901 | err = read_utmi_param(pdev, "nvidia,idle-wait-delay", | |
902 | &config->idle_wait_delay); | |
903 | if (err < 0) | |
904 | return err; | |
905 | ||
906 | err = read_utmi_param(pdev, "nvidia,term-range-adj", | |
907 | &config->term_range_adj); | |
908 | if (err < 0) | |
909 | return err; | |
910 | ||
81d5dfe6 MP |
911 | err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew", |
912 | &config->xcvr_lsfslew); | |
913 | if (err < 0) | |
914 | return err; | |
915 | ||
916 | err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew", | |
917 | &config->xcvr_lsrslew); | |
918 | if (err < 0) | |
919 | return err; | |
920 | ||
e497a24d TT |
921 | if (tegra_phy->soc_config->requires_extra_tuning_parameters) { |
922 | err = read_utmi_param(pdev, "nvidia,xcvr-hsslew", | |
923 | &config->xcvr_hsslew); | |
924 | if (err < 0) | |
925 | return err; | |
926 | ||
927 | err = read_utmi_param(pdev, "nvidia,hssquelch-level", | |
928 | &config->hssquelch_level); | |
929 | if (err < 0) | |
930 | return err; | |
931 | ||
932 | err = read_utmi_param(pdev, "nvidia,hsdiscon-level", | |
933 | &config->hsdiscon_level); | |
934 | if (err < 0) | |
935 | return err; | |
936 | } | |
937 | ||
938 | config->xcvr_setup_use_fuses = of_property_read_bool( | |
939 | pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses"); | |
940 | ||
941 | if (!config->xcvr_setup_use_fuses) { | |
942 | err = read_utmi_param(pdev, "nvidia,xcvr-setup", | |
943 | &config->xcvr_setup); | |
944 | if (err < 0) | |
945 | return err; | |
946 | } | |
947 | ||
81d5dfe6 MP |
948 | return 0; |
949 | } | |
950 | ||
3e635202 TT |
951 | static const struct tegra_phy_soc_config tegra20_soc_config = { |
952 | .utmi_pll_config_in_car_module = false, | |
953 | .has_hostpc = false, | |
954 | .requires_usbmode_setup = false, | |
955 | .requires_extra_tuning_parameters = false, | |
956 | }; | |
957 | ||
958 | static const struct tegra_phy_soc_config tegra30_soc_config = { | |
959 | .utmi_pll_config_in_car_module = true, | |
960 | .has_hostpc = true, | |
961 | .requires_usbmode_setup = true, | |
962 | .requires_extra_tuning_parameters = true, | |
963 | }; | |
964 | ||
0f0520ba | 965 | static const struct of_device_id tegra_usb_phy_id_table[] = { |
3e635202 TT |
966 | { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config }, |
967 | { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config }, | |
968 | { }, | |
969 | }; | |
970 | MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table); | |
971 | ||
2d22b42d VB |
972 | static int tegra_usb_phy_probe(struct platform_device *pdev) |
973 | { | |
3e635202 | 974 | const struct of_device_id *match; |
2d22b42d VB |
975 | struct resource *res; |
976 | struct tegra_usb_phy *tegra_phy = NULL; | |
977 | struct device_node *np = pdev->dev.of_node; | |
9fdb07f7 | 978 | enum usb_phy_interface phy_type; |
2d22b42d VB |
979 | int err; |
980 | ||
981 | tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL); | |
982 | if (!tegra_phy) { | |
983 | dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n"); | |
984 | return -ENOMEM; | |
985 | } | |
986 | ||
3e635202 TT |
987 | match = of_match_device(tegra_usb_phy_id_table, &pdev->dev); |
988 | if (!match) { | |
989 | dev_err(&pdev->dev, "Error: No device match found\n"); | |
990 | return -ENODEV; | |
991 | } | |
992 | tegra_phy->soc_config = match->data; | |
993 | ||
2d22b42d VB |
994 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
995 | if (!res) { | |
996 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
997 | return -ENXIO; | |
998 | } | |
999 | ||
1000 | tegra_phy->regs = devm_ioremap(&pdev->dev, res->start, | |
1001 | resource_size(res)); | |
1002 | if (!tegra_phy->regs) { | |
1003 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
1004 | return -ENOMEM; | |
1005 | } | |
1006 | ||
1007 | tegra_phy->is_legacy_phy = | |
1008 | of_property_read_bool(np, "nvidia,has-legacy-mode"); | |
1009 | ||
9fdb07f7 | 1010 | phy_type = of_usb_get_phy_mode(np); |
a554aea6 TT |
1011 | switch (phy_type) { |
1012 | case USBPHY_INTERFACE_MODE_UTMI: | |
81d5dfe6 MP |
1013 | err = utmi_phy_probe(tegra_phy, pdev); |
1014 | if (err < 0) | |
1015 | return err; | |
a554aea6 TT |
1016 | break; |
1017 | ||
1018 | case USBPHY_INTERFACE_MODE_ULPI: | |
2d22b42d VB |
1019 | tegra_phy->is_ulpi_phy = true; |
1020 | ||
1021 | tegra_phy->reset_gpio = | |
1022 | of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0); | |
1023 | if (!gpio_is_valid(tegra_phy->reset_gpio)) { | |
1024 | dev_err(&pdev->dev, "invalid gpio: %d\n", | |
1025 | tegra_phy->reset_gpio); | |
1026 | return tegra_phy->reset_gpio; | |
1027 | } | |
81d5dfe6 | 1028 | tegra_phy->config = NULL; |
a554aea6 TT |
1029 | break; |
1030 | ||
1031 | default: | |
9fdb07f7 TT |
1032 | dev_err(&pdev->dev, "phy_type is invalid or unsupported\n"); |
1033 | return -EINVAL; | |
2d22b42d VB |
1034 | } |
1035 | ||
6558d7ed TT |
1036 | if (of_find_property(np, "dr_mode", NULL)) |
1037 | tegra_phy->mode = of_usb_get_dr_mode(np); | |
1038 | else | |
1039 | tegra_phy->mode = USB_DR_MODE_HOST; | |
1040 | ||
1041 | if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) { | |
1042 | dev_err(&pdev->dev, "dr_mode is invalid\n"); | |
1043 | return -EINVAL; | |
1044 | } | |
2d22b42d | 1045 | |
f5b8c8b6 MP |
1046 | /* On some boards, the VBUS regulator doesn't need to be controlled */ |
1047 | if (of_find_property(np, "vbus-supply", NULL)) { | |
1048 | tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus"); | |
1049 | if (IS_ERR(tegra_phy->vbus)) | |
1050 | return PTR_ERR(tegra_phy->vbus); | |
1051 | } else { | |
1052 | dev_notice(&pdev->dev, "no vbus regulator"); | |
1053 | tegra_phy->vbus = ERR_PTR(-ENODEV); | |
1054 | } | |
1055 | ||
185d0fd5 | 1056 | tegra_phy->u_phy.dev = &pdev->dev; |
2d22b42d VB |
1057 | err = tegra_usb_phy_init(tegra_phy); |
1058 | if (err < 0) | |
1059 | return err; | |
1060 | ||
2d22b42d VB |
1061 | tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend; |
1062 | ||
72031b52 | 1063 | platform_set_drvdata(pdev, tegra_phy); |
0ee5b4ab TT |
1064 | |
1065 | err = usb_add_phy_dev(&tegra_phy->u_phy); | |
1066 | if (err < 0) { | |
3e346d41 | 1067 | tegra_usb_phy_close(tegra_phy); |
0ee5b4ab TT |
1068 | return err; |
1069 | } | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | static int tegra_usb_phy_remove(struct platform_device *pdev) | |
1075 | { | |
1076 | struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev); | |
1077 | ||
1078 | usb_remove_phy(&tegra_phy->u_phy); | |
3e346d41 | 1079 | tegra_usb_phy_close(tegra_phy); |
0ee5b4ab | 1080 | |
2d22b42d VB |
1081 | return 0; |
1082 | } | |
1083 | ||
2d22b42d VB |
1084 | static struct platform_driver tegra_usb_phy_driver = { |
1085 | .probe = tegra_usb_phy_probe, | |
0ee5b4ab | 1086 | .remove = tegra_usb_phy_remove, |
2d22b42d VB |
1087 | .driver = { |
1088 | .name = "tegra-phy", | |
1089 | .owner = THIS_MODULE, | |
78723920 | 1090 | .of_match_table = tegra_usb_phy_id_table, |
2d22b42d VB |
1091 | }, |
1092 | }; | |
1093 | module_platform_driver(tegra_usb_phy_driver); | |
1094 | ||
587376a1 SW |
1095 | MODULE_DESCRIPTION("Tegra USB PHY driver"); |
1096 | MODULE_LICENSE("GPL v2"); |