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91525d08 | 1 | /* |
91525d08 | 2 | * Copyright (C) 2010 Google, Inc. |
2d22b42d | 3 | * Copyright (C) 2013 NVIDIA Corporation |
91525d08 BG |
4 | * |
5 | * Author: | |
6 | * Erik Gilling <konkers@google.com> | |
7 | * Benoit Goby <benoit@android.com> | |
2d22b42d | 8 | * Venu Byravarasu <vbyravarasu@nvidia.com> |
91525d08 BG |
9 | * |
10 | * This software is licensed under the terms of the GNU General Public | |
11 | * License version 2, as published by the Free Software Foundation, and | |
12 | * may be copied, distributed, and modified under those terms. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/resource.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/err.h> | |
4265cbfd | 25 | #include <linux/export.h> |
587376a1 | 26 | #include <linux/module.h> |
91525d08 BG |
27 | #include <linux/platform_device.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/gpio.h> | |
3a55c6a8 | 30 | #include <linux/of.h> |
aa607ebf | 31 | #include <linux/of_gpio.h> |
91525d08 BG |
32 | #include <linux/usb/otg.h> |
33 | #include <linux/usb/ulpi.h> | |
34 | #include <asm/mach-types.h> | |
91a687d8 | 35 | #include <linux/usb/ehci_def.h> |
1ba8216f | 36 | #include <linux/usb/tegra_usb_phy.h> |
91525d08 BG |
37 | |
38 | #define ULPI_VIEWPORT 0x170 | |
39 | ||
91a687d8 SW |
40 | /* PORTSC registers */ |
41 | #define TEGRA_USB_PORTSC1 0x184 | |
42 | #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) | |
43 | #define TEGRA_USB_PORTSC1_PHCD (1 << 23) | |
44 | ||
45 | /* Bits of PORTSC1, which will get cleared by writing 1 into them */ | |
46 | #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) | |
47 | ||
91525d08 BG |
48 | #define USB_SUSP_CTRL 0x400 |
49 | #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) | |
50 | #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) | |
51 | #define USB_SUSP_CLR (1 << 5) | |
52 | #define USB_PHY_CLK_VALID (1 << 7) | |
53 | #define UTMIP_RESET (1 << 11) | |
54 | #define UHSIC_RESET (1 << 11) | |
55 | #define UTMIP_PHY_ENABLE (1 << 12) | |
56 | #define ULPI_PHY_ENABLE (1 << 13) | |
57 | #define USB_SUSP_SET (1 << 14) | |
58 | #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) | |
59 | ||
60 | #define USB1_LEGACY_CTRL 0x410 | |
61 | #define USB1_NO_LEGACY_MODE (1 << 0) | |
62 | #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) | |
63 | #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) | |
64 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ | |
65 | (1 << 1) | |
66 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) | |
67 | #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) | |
68 | ||
69 | #define ULPI_TIMING_CTRL_0 0x424 | |
70 | #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) | |
71 | #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) | |
72 | ||
73 | #define ULPI_TIMING_CTRL_1 0x428 | |
74 | #define ULPI_DATA_TRIMMER_LOAD (1 << 0) | |
75 | #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) | |
76 | #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) | |
77 | #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) | |
78 | #define ULPI_DIR_TRIMMER_LOAD (1 << 24) | |
79 | #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) | |
80 | ||
81 | #define UTMIP_PLL_CFG1 0x804 | |
82 | #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
83 | #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
84 | ||
85 | #define UTMIP_XCVR_CFG0 0x808 | |
86 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) | |
87 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) | |
88 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) | |
89 | #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) | |
90 | #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) | |
91 | #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) | |
92 | #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) | |
93 | ||
94 | #define UTMIP_BIAS_CFG0 0x80c | |
95 | #define UTMIP_OTGPD (1 << 11) | |
96 | #define UTMIP_BIASPD (1 << 10) | |
97 | ||
98 | #define UTMIP_HSRX_CFG0 0x810 | |
99 | #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) | |
100 | #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) | |
101 | ||
102 | #define UTMIP_HSRX_CFG1 0x814 | |
103 | #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) | |
104 | ||
105 | #define UTMIP_TX_CFG0 0x820 | |
106 | #define UTMIP_FS_PREABMLE_J (1 << 19) | |
107 | #define UTMIP_HS_DISCON_DISABLE (1 << 8) | |
108 | ||
109 | #define UTMIP_MISC_CFG0 0x824 | |
110 | #define UTMIP_DPDM_OBSERVE (1 << 26) | |
111 | #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) | |
112 | #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) | |
113 | #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) | |
114 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) | |
115 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) | |
116 | #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) | |
117 | ||
118 | #define UTMIP_MISC_CFG1 0x828 | |
119 | #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) | |
120 | #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
121 | ||
122 | #define UTMIP_DEBOUNCE_CFG0 0x82c | |
123 | #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) | |
124 | ||
125 | #define UTMIP_BAT_CHRG_CFG0 0x830 | |
126 | #define UTMIP_PD_CHRG (1 << 0) | |
127 | ||
128 | #define UTMIP_SPARE_CFG0 0x834 | |
129 | #define FUSE_SETUP_SEL (1 << 3) | |
130 | ||
131 | #define UTMIP_XCVR_CFG1 0x838 | |
132 | #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) | |
133 | #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) | |
134 | #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) | |
135 | #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) | |
136 | ||
137 | #define UTMIP_BIAS_CFG1 0x83c | |
138 | #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) | |
139 | ||
140 | static DEFINE_SPINLOCK(utmip_pad_lock); | |
141 | static int utmip_pad_count; | |
142 | ||
143 | struct tegra_xtal_freq { | |
144 | int freq; | |
145 | u8 enable_delay; | |
146 | u8 stable_count; | |
147 | u8 active_delay; | |
148 | u8 xtal_freq_count; | |
149 | u16 debounce; | |
150 | }; | |
151 | ||
152 | static const struct tegra_xtal_freq tegra_freq_table[] = { | |
153 | { | |
154 | .freq = 12000000, | |
155 | .enable_delay = 0x02, | |
156 | .stable_count = 0x2F, | |
157 | .active_delay = 0x04, | |
158 | .xtal_freq_count = 0x76, | |
159 | .debounce = 0x7530, | |
160 | }, | |
161 | { | |
162 | .freq = 13000000, | |
163 | .enable_delay = 0x02, | |
164 | .stable_count = 0x33, | |
165 | .active_delay = 0x05, | |
166 | .xtal_freq_count = 0x7F, | |
167 | .debounce = 0x7EF4, | |
168 | }, | |
169 | { | |
170 | .freq = 19200000, | |
171 | .enable_delay = 0x03, | |
172 | .stable_count = 0x4B, | |
173 | .active_delay = 0x06, | |
174 | .xtal_freq_count = 0xBB, | |
175 | .debounce = 0xBB80, | |
176 | }, | |
177 | { | |
178 | .freq = 26000000, | |
179 | .enable_delay = 0x04, | |
180 | .stable_count = 0x66, | |
181 | .active_delay = 0x09, | |
182 | .xtal_freq_count = 0xFE, | |
183 | .debounce = 0xFDE8, | |
184 | }, | |
185 | }; | |
186 | ||
91a687d8 SW |
187 | static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) |
188 | { | |
189 | void __iomem *base = phy->regs; | |
190 | unsigned long val; | |
191 | ||
192 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
193 | val &= ~TEGRA_USB_PORTSC1_PTS(3); | |
194 | val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3); | |
195 | writel(val, base + TEGRA_USB_PORTSC1); | |
196 | } | |
197 | ||
198 | static void set_phcd(struct tegra_usb_phy *phy, bool enable) | |
199 | { | |
200 | void __iomem *base = phy->regs; | |
201 | unsigned long val; | |
202 | ||
203 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
204 | if (enable) | |
205 | val |= TEGRA_USB_PORTSC1_PHCD; | |
206 | else | |
207 | val &= ~TEGRA_USB_PORTSC1_PHCD; | |
208 | writel(val, base + TEGRA_USB_PORTSC1); | |
209 | } | |
210 | ||
91525d08 BG |
211 | static int utmip_pad_open(struct tegra_usb_phy *phy) |
212 | { | |
2d22b42d | 213 | phy->pad_clk = devm_clk_get(phy->dev, "utmi-pads"); |
91525d08 BG |
214 | if (IS_ERR(phy->pad_clk)) { |
215 | pr_err("%s: can't get utmip pad clock\n", __func__); | |
216 | return PTR_ERR(phy->pad_clk); | |
217 | } | |
218 | ||
91525d08 BG |
219 | return 0; |
220 | } | |
221 | ||
91525d08 BG |
222 | static void utmip_pad_power_on(struct tegra_usb_phy *phy) |
223 | { | |
224 | unsigned long val, flags; | |
225 | void __iomem *base = phy->pad_regs; | |
226 | ||
6a5278d0 | 227 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
228 | |
229 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
230 | ||
231 | if (utmip_pad_count++ == 0) { | |
232 | val = readl(base + UTMIP_BIAS_CFG0); | |
233 | val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); | |
234 | writel(val, base + UTMIP_BIAS_CFG0); | |
235 | } | |
236 | ||
237 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
238 | ||
6a5278d0 | 239 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
240 | } |
241 | ||
242 | static int utmip_pad_power_off(struct tegra_usb_phy *phy) | |
243 | { | |
244 | unsigned long val, flags; | |
245 | void __iomem *base = phy->pad_regs; | |
246 | ||
247 | if (!utmip_pad_count) { | |
248 | pr_err("%s: utmip pad already powered off\n", __func__); | |
249 | return -EINVAL; | |
250 | } | |
251 | ||
6a5278d0 | 252 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
253 | |
254 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
255 | ||
256 | if (--utmip_pad_count == 0) { | |
257 | val = readl(base + UTMIP_BIAS_CFG0); | |
258 | val |= UTMIP_OTGPD | UTMIP_BIASPD; | |
259 | writel(val, base + UTMIP_BIAS_CFG0); | |
260 | } | |
261 | ||
262 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
263 | ||
6a5278d0 | 264 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
265 | |
266 | return 0; | |
267 | } | |
268 | ||
269 | static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) | |
270 | { | |
271 | unsigned long timeout = 2000; | |
272 | do { | |
273 | if ((readl(reg) & mask) == result) | |
274 | return 0; | |
275 | udelay(1); | |
276 | timeout--; | |
277 | } while (timeout); | |
278 | return -1; | |
279 | } | |
280 | ||
281 | static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) | |
282 | { | |
283 | unsigned long val; | |
284 | void __iomem *base = phy->regs; | |
285 | ||
3a55c6a8 | 286 | if (phy->is_legacy_phy) { |
91525d08 BG |
287 | val = readl(base + USB_SUSP_CTRL); |
288 | val |= USB_SUSP_SET; | |
289 | writel(val, base + USB_SUSP_CTRL); | |
290 | ||
291 | udelay(10); | |
292 | ||
293 | val = readl(base + USB_SUSP_CTRL); | |
294 | val &= ~USB_SUSP_SET; | |
295 | writel(val, base + USB_SUSP_CTRL); | |
bbdabdb6 | 296 | } else |
91a687d8 | 297 | set_phcd(phy, true); |
91525d08 BG |
298 | |
299 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) | |
300 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
301 | } | |
302 | ||
303 | static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) | |
304 | { | |
305 | unsigned long val; | |
306 | void __iomem *base = phy->regs; | |
307 | ||
3a55c6a8 | 308 | if (phy->is_legacy_phy) { |
91525d08 BG |
309 | val = readl(base + USB_SUSP_CTRL); |
310 | val |= USB_SUSP_CLR; | |
311 | writel(val, base + USB_SUSP_CTRL); | |
312 | ||
313 | udelay(10); | |
314 | ||
315 | val = readl(base + USB_SUSP_CTRL); | |
316 | val &= ~USB_SUSP_CLR; | |
317 | writel(val, base + USB_SUSP_CTRL); | |
bbdabdb6 | 318 | } else |
91a687d8 | 319 | set_phcd(phy, false); |
91525d08 BG |
320 | |
321 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, | |
322 | USB_PHY_CLK_VALID)) | |
323 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
324 | } | |
325 | ||
326 | static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |
327 | { | |
328 | unsigned long val; | |
329 | void __iomem *base = phy->regs; | |
330 | struct tegra_utmip_config *config = phy->config; | |
331 | ||
332 | val = readl(base + USB_SUSP_CTRL); | |
333 | val |= UTMIP_RESET; | |
334 | writel(val, base + USB_SUSP_CTRL); | |
335 | ||
3a55c6a8 | 336 | if (phy->is_legacy_phy) { |
91525d08 BG |
337 | val = readl(base + USB1_LEGACY_CTRL); |
338 | val |= USB1_NO_LEGACY_MODE; | |
339 | writel(val, base + USB1_LEGACY_CTRL); | |
340 | } | |
341 | ||
342 | val = readl(base + UTMIP_TX_CFG0); | |
343 | val &= ~UTMIP_FS_PREABMLE_J; | |
344 | writel(val, base + UTMIP_TX_CFG0); | |
345 | ||
346 | val = readl(base + UTMIP_HSRX_CFG0); | |
347 | val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); | |
348 | val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); | |
349 | val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); | |
350 | writel(val, base + UTMIP_HSRX_CFG0); | |
351 | ||
352 | val = readl(base + UTMIP_HSRX_CFG1); | |
353 | val &= ~UTMIP_HS_SYNC_START_DLY(~0); | |
354 | val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); | |
355 | writel(val, base + UTMIP_HSRX_CFG1); | |
356 | ||
357 | val = readl(base + UTMIP_DEBOUNCE_CFG0); | |
358 | val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); | |
359 | val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); | |
360 | writel(val, base + UTMIP_DEBOUNCE_CFG0); | |
361 | ||
362 | val = readl(base + UTMIP_MISC_CFG0); | |
363 | val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; | |
364 | writel(val, base + UTMIP_MISC_CFG0); | |
365 | ||
366 | val = readl(base + UTMIP_MISC_CFG1); | |
367 | val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0)); | |
368 | val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | | |
369 | UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); | |
370 | writel(val, base + UTMIP_MISC_CFG1); | |
371 | ||
372 | val = readl(base + UTMIP_PLL_CFG1); | |
373 | val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); | |
374 | val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | | |
375 | UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); | |
376 | writel(val, base + UTMIP_PLL_CFG1); | |
377 | ||
378 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { | |
379 | val = readl(base + USB_SUSP_CTRL); | |
380 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); | |
381 | writel(val, base + USB_SUSP_CTRL); | |
382 | } | |
383 | ||
384 | utmip_pad_power_on(phy); | |
385 | ||
386 | val = readl(base + UTMIP_XCVR_CFG0); | |
387 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
388 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | | |
389 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | | |
390 | UTMIP_XCVR_HSSLEW_MSB(~0)); | |
391 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); | |
392 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); | |
393 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); | |
394 | writel(val, base + UTMIP_XCVR_CFG0); | |
395 | ||
396 | val = readl(base + UTMIP_XCVR_CFG1); | |
397 | val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
398 | UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); | |
399 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); | |
400 | writel(val, base + UTMIP_XCVR_CFG1); | |
401 | ||
402 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
403 | val &= ~UTMIP_PD_CHRG; | |
404 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
405 | ||
406 | val = readl(base + UTMIP_BIAS_CFG1); | |
407 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); | |
408 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); | |
409 | writel(val, base + UTMIP_BIAS_CFG1); | |
410 | ||
3a55c6a8 | 411 | if (phy->is_legacy_phy) { |
91525d08 BG |
412 | val = readl(base + UTMIP_SPARE_CFG0); |
413 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) | |
414 | val &= ~FUSE_SETUP_SEL; | |
415 | else | |
416 | val |= FUSE_SETUP_SEL; | |
417 | writel(val, base + UTMIP_SPARE_CFG0); | |
3a55c6a8 | 418 | } else { |
91525d08 BG |
419 | val = readl(base + USB_SUSP_CTRL); |
420 | val |= UTMIP_PHY_ENABLE; | |
421 | writel(val, base + USB_SUSP_CTRL); | |
422 | } | |
423 | ||
424 | val = readl(base + USB_SUSP_CTRL); | |
425 | val &= ~UTMIP_RESET; | |
426 | writel(val, base + USB_SUSP_CTRL); | |
427 | ||
3a55c6a8 | 428 | if (phy->is_legacy_phy) { |
91525d08 BG |
429 | val = readl(base + USB1_LEGACY_CTRL); |
430 | val &= ~USB1_VBUS_SENSE_CTL_MASK; | |
431 | val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; | |
432 | writel(val, base + USB1_LEGACY_CTRL); | |
433 | ||
434 | val = readl(base + USB_SUSP_CTRL); | |
435 | val &= ~USB_SUSP_SET; | |
436 | writel(val, base + USB_SUSP_CTRL); | |
437 | } | |
438 | ||
439 | utmi_phy_clk_enable(phy); | |
440 | ||
bbdabdb6 | 441 | if (!phy->is_legacy_phy) |
91a687d8 | 442 | set_pts(phy, 0); |
91525d08 BG |
443 | |
444 | return 0; | |
445 | } | |
446 | ||
1ba8216f | 447 | static int utmi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 BG |
448 | { |
449 | unsigned long val; | |
450 | void __iomem *base = phy->regs; | |
451 | ||
452 | utmi_phy_clk_disable(phy); | |
453 | ||
454 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { | |
455 | val = readl(base + USB_SUSP_CTRL); | |
456 | val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); | |
457 | val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); | |
458 | writel(val, base + USB_SUSP_CTRL); | |
459 | } | |
460 | ||
461 | val = readl(base + USB_SUSP_CTRL); | |
462 | val |= UTMIP_RESET; | |
463 | writel(val, base + USB_SUSP_CTRL); | |
464 | ||
465 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
466 | val |= UTMIP_PD_CHRG; | |
467 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
468 | ||
469 | val = readl(base + UTMIP_XCVR_CFG0); | |
470 | val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
471 | UTMIP_FORCE_PDZI_POWERDOWN; | |
472 | writel(val, base + UTMIP_XCVR_CFG0); | |
473 | ||
474 | val = readl(base + UTMIP_XCVR_CFG1); | |
475 | val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
476 | UTMIP_FORCE_PDDR_POWERDOWN; | |
477 | writel(val, base + UTMIP_XCVR_CFG1); | |
478 | ||
1ba8216f | 479 | return utmip_pad_power_off(phy); |
91525d08 BG |
480 | } |
481 | ||
482 | static void utmi_phy_preresume(struct tegra_usb_phy *phy) | |
483 | { | |
484 | unsigned long val; | |
485 | void __iomem *base = phy->regs; | |
486 | ||
487 | val = readl(base + UTMIP_TX_CFG0); | |
488 | val |= UTMIP_HS_DISCON_DISABLE; | |
489 | writel(val, base + UTMIP_TX_CFG0); | |
490 | } | |
491 | ||
492 | static void utmi_phy_postresume(struct tegra_usb_phy *phy) | |
493 | { | |
494 | unsigned long val; | |
495 | void __iomem *base = phy->regs; | |
496 | ||
497 | val = readl(base + UTMIP_TX_CFG0); | |
498 | val &= ~UTMIP_HS_DISCON_DISABLE; | |
499 | writel(val, base + UTMIP_TX_CFG0); | |
500 | } | |
501 | ||
502 | static void utmi_phy_restore_start(struct tegra_usb_phy *phy, | |
503 | enum tegra_usb_phy_port_speed port_speed) | |
504 | { | |
505 | unsigned long val; | |
506 | void __iomem *base = phy->regs; | |
507 | ||
508 | val = readl(base + UTMIP_MISC_CFG0); | |
509 | val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); | |
510 | if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
511 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; | |
512 | else | |
513 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; | |
514 | writel(val, base + UTMIP_MISC_CFG0); | |
515 | udelay(1); | |
516 | ||
517 | val = readl(base + UTMIP_MISC_CFG0); | |
518 | val |= UTMIP_DPDM_OBSERVE; | |
519 | writel(val, base + UTMIP_MISC_CFG0); | |
520 | udelay(10); | |
521 | } | |
522 | ||
523 | static void utmi_phy_restore_end(struct tegra_usb_phy *phy) | |
524 | { | |
525 | unsigned long val; | |
526 | void __iomem *base = phy->regs; | |
527 | ||
528 | val = readl(base + UTMIP_MISC_CFG0); | |
529 | val &= ~UTMIP_DPDM_OBSERVE; | |
530 | writel(val, base + UTMIP_MISC_CFG0); | |
531 | udelay(10); | |
532 | } | |
533 | ||
534 | static int ulpi_phy_power_on(struct tegra_usb_phy *phy) | |
535 | { | |
536 | int ret; | |
537 | unsigned long val; | |
538 | void __iomem *base = phy->regs; | |
91525d08 | 539 | |
6829f92f VB |
540 | ret = gpio_direction_output(phy->reset_gpio, 0); |
541 | if (ret < 0) { | |
542 | dev_err(phy->dev, "gpio %d not set to 0\n", phy->reset_gpio); | |
543 | return ret; | |
544 | } | |
91525d08 | 545 | msleep(5); |
6829f92f VB |
546 | ret = gpio_direction_output(phy->reset_gpio, 1); |
547 | if (ret < 0) { | |
548 | dev_err(phy->dev, "gpio %d not set to 1\n", phy->reset_gpio); | |
549 | return ret; | |
550 | } | |
91525d08 | 551 | |
6a5278d0 | 552 | clk_prepare_enable(phy->clk); |
91525d08 BG |
553 | msleep(1); |
554 | ||
555 | val = readl(base + USB_SUSP_CTRL); | |
556 | val |= UHSIC_RESET; | |
557 | writel(val, base + USB_SUSP_CTRL); | |
558 | ||
559 | val = readl(base + ULPI_TIMING_CTRL_0); | |
560 | val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; | |
561 | writel(val, base + ULPI_TIMING_CTRL_0); | |
562 | ||
563 | val = readl(base + USB_SUSP_CTRL); | |
564 | val |= ULPI_PHY_ENABLE; | |
565 | writel(val, base + USB_SUSP_CTRL); | |
566 | ||
567 | val = 0; | |
568 | writel(val, base + ULPI_TIMING_CTRL_1); | |
569 | ||
570 | val |= ULPI_DATA_TRIMMER_SEL(4); | |
571 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); | |
572 | val |= ULPI_DIR_TRIMMER_SEL(4); | |
573 | writel(val, base + ULPI_TIMING_CTRL_1); | |
574 | udelay(10); | |
575 | ||
576 | val |= ULPI_DATA_TRIMMER_LOAD; | |
577 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; | |
578 | val |= ULPI_DIR_TRIMMER_LOAD; | |
579 | writel(val, base + ULPI_TIMING_CTRL_1); | |
580 | ||
581 | /* Fix VbusInvalid due to floating VBUS */ | |
b96d3b08 | 582 | ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); |
91525d08 BG |
583 | if (ret) { |
584 | pr_err("%s: ulpi write failed\n", __func__); | |
585 | return ret; | |
586 | } | |
587 | ||
b96d3b08 | 588 | ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); |
91525d08 BG |
589 | if (ret) { |
590 | pr_err("%s: ulpi write failed\n", __func__); | |
591 | return ret; | |
592 | } | |
593 | ||
91525d08 BG |
594 | val = readl(base + USB_SUSP_CTRL); |
595 | val |= USB_SUSP_CLR; | |
596 | writel(val, base + USB_SUSP_CTRL); | |
597 | udelay(100); | |
598 | ||
599 | val = readl(base + USB_SUSP_CTRL); | |
600 | val &= ~USB_SUSP_CLR; | |
601 | writel(val, base + USB_SUSP_CTRL); | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
1ba8216f | 606 | static int ulpi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 | 607 | { |
91525d08 | 608 | clk_disable(phy->clk); |
12ea18e4 | 609 | return gpio_direction_output(phy->reset_gpio, 0); |
1ba8216f VB |
610 | } |
611 | ||
1ba8216f VB |
612 | static void tegra_usb_phy_close(struct usb_phy *x) |
613 | { | |
614 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
615 | ||
1ba8216f | 616 | clk_disable_unprepare(phy->pll_u); |
1ba8216f VB |
617 | } |
618 | ||
619 | static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) | |
620 | { | |
3f9db1a1 | 621 | if (phy->is_ulpi_phy) |
1ba8216f VB |
622 | return ulpi_phy_power_on(phy); |
623 | else | |
624 | return utmi_phy_power_on(phy); | |
625 | } | |
626 | ||
627 | static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) | |
628 | { | |
3f9db1a1 | 629 | if (phy->is_ulpi_phy) |
1ba8216f VB |
630 | return ulpi_phy_power_off(phy); |
631 | else | |
632 | return utmi_phy_power_off(phy); | |
633 | } | |
634 | ||
635 | static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend) | |
636 | { | |
637 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
638 | if (suspend) | |
639 | return tegra_usb_phy_power_off(phy); | |
640 | else | |
641 | return tegra_usb_phy_power_on(phy); | |
91525d08 BG |
642 | } |
643 | ||
2d22b42d | 644 | static int ulpi_open(struct tegra_usb_phy *phy) |
91525d08 | 645 | { |
91525d08 BG |
646 | int err; |
647 | ||
2d22b42d VB |
648 | phy->clk = devm_clk_get(phy->dev, "ulpi-link"); |
649 | if (IS_ERR(phy->clk)) { | |
650 | pr_err("%s: can't get ulpi clock\n", __func__); | |
651 | return PTR_ERR(phy->clk); | |
652 | } | |
91525d08 | 653 | |
2d22b42d VB |
654 | err = devm_gpio_request(phy->dev, phy->reset_gpio, "ulpi_phy_reset_b"); |
655 | if (err < 0) { | |
656 | dev_err(phy->dev, "request failed for gpio: %d\n", | |
657 | phy->reset_gpio); | |
658 | return err; | |
659 | } | |
91525d08 | 660 | |
2d22b42d | 661 | err = gpio_direction_output(phy->reset_gpio, 0); |
9cd9384c | 662 | if (err < 0) { |
2d22b42d VB |
663 | dev_err(phy->dev, "gpio %d direction not set to output\n", |
664 | phy->reset_gpio); | |
665 | return err; | |
666 | } | |
667 | ||
668 | phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); | |
669 | if (!phy->ulpi) { | |
670 | dev_err(phy->dev, "otg_ulpi_create returned NULL\n"); | |
671 | err = -ENOMEM; | |
672 | return err; | |
673 | } | |
674 | ||
675 | phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT; | |
676 | return 0; | |
677 | } | |
678 | ||
679 | static int tegra_usb_phy_init(struct tegra_usb_phy *phy) | |
680 | { | |
681 | unsigned long parent_rate; | |
682 | int i; | |
683 | int err; | |
684 | ||
2d22b42d | 685 | phy->pll_u = devm_clk_get(phy->dev, "pll_u"); |
91525d08 BG |
686 | if (IS_ERR(phy->pll_u)) { |
687 | pr_err("Can't get pll_u clock\n"); | |
2d22b42d | 688 | return PTR_ERR(phy->pll_u); |
91525d08 | 689 | } |
2d22b42d VB |
690 | |
691 | err = clk_prepare_enable(phy->pll_u); | |
692 | if (err) | |
693 | return err; | |
91525d08 BG |
694 | |
695 | parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); | |
696 | for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { | |
697 | if (tegra_freq_table[i].freq == parent_rate) { | |
698 | phy->freq = &tegra_freq_table[i]; | |
699 | break; | |
700 | } | |
701 | } | |
702 | if (!phy->freq) { | |
703 | pr_err("invalid pll_u parent rate %ld\n", parent_rate); | |
704 | err = -EINVAL; | |
2d22b42d | 705 | goto fail; |
91525d08 BG |
706 | } |
707 | ||
2d22b42d VB |
708 | if (phy->is_ulpi_phy) |
709 | err = ulpi_open(phy); | |
710 | else | |
711 | err = utmip_pad_open(phy); | |
712 | if (err < 0) | |
713 | goto fail; | |
91525d08 | 714 | |
2d22b42d | 715 | return 0; |
91525d08 | 716 | |
2d22b42d | 717 | fail: |
6a5278d0 | 718 | clk_disable_unprepare(phy->pll_u); |
2d22b42d | 719 | return err; |
91525d08 BG |
720 | } |
721 | ||
ab137d04 | 722 | void tegra_usb_phy_preresume(struct usb_phy *x) |
91525d08 | 723 | { |
ab137d04 VB |
724 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
725 | ||
3f9db1a1 | 726 | if (!phy->is_ulpi_phy) |
91525d08 BG |
727 | utmi_phy_preresume(phy); |
728 | } | |
4265cbfd | 729 | EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); |
91525d08 | 730 | |
ab137d04 | 731 | void tegra_usb_phy_postresume(struct usb_phy *x) |
91525d08 | 732 | { |
ab137d04 VB |
733 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
734 | ||
3f9db1a1 | 735 | if (!phy->is_ulpi_phy) |
91525d08 BG |
736 | utmi_phy_postresume(phy); |
737 | } | |
4265cbfd | 738 | EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); |
91525d08 | 739 | |
ab137d04 | 740 | void tegra_ehci_phy_restore_start(struct usb_phy *x, |
91525d08 BG |
741 | enum tegra_usb_phy_port_speed port_speed) |
742 | { | |
ab137d04 VB |
743 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
744 | ||
3f9db1a1 | 745 | if (!phy->is_ulpi_phy) |
91525d08 BG |
746 | utmi_phy_restore_start(phy, port_speed); |
747 | } | |
4265cbfd | 748 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); |
91525d08 | 749 | |
ab137d04 | 750 | void tegra_ehci_phy_restore_end(struct usb_phy *x) |
91525d08 | 751 | { |
ab137d04 VB |
752 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
753 | ||
3f9db1a1 | 754 | if (!phy->is_ulpi_phy) |
91525d08 BG |
755 | utmi_phy_restore_end(phy); |
756 | } | |
4265cbfd | 757 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); |
91525d08 | 758 | |
81d5dfe6 MP |
759 | static int read_utmi_param(struct platform_device *pdev, const char *param, |
760 | u8 *dest) | |
761 | { | |
762 | u32 value; | |
763 | int err = of_property_read_u32(pdev->dev.of_node, param, &value); | |
764 | *dest = (u8)value; | |
765 | if (err < 0) | |
766 | dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n", | |
767 | param, err); | |
768 | return err; | |
769 | } | |
770 | ||
771 | static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy, | |
772 | struct platform_device *pdev) | |
773 | { | |
774 | struct resource *res; | |
775 | int err; | |
776 | struct tegra_utmip_config *config; | |
777 | ||
778 | tegra_phy->is_ulpi_phy = false; | |
779 | ||
780 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
781 | if (!res) { | |
782 | dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n"); | |
783 | return -ENXIO; | |
784 | } | |
785 | ||
786 | tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start, | |
787 | resource_size(res)); | |
788 | if (!tegra_phy->regs) { | |
789 | dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n"); | |
790 | return -ENOMEM; | |
791 | } | |
792 | ||
793 | tegra_phy->config = devm_kzalloc(&pdev->dev, | |
794 | sizeof(*tegra_phy->config), GFP_KERNEL); | |
795 | if (!tegra_phy->config) { | |
796 | dev_err(&pdev->dev, | |
797 | "unable to allocate memory for USB UTMIP config\n"); | |
798 | return -ENOMEM; | |
799 | } | |
800 | ||
801 | config = tegra_phy->config; | |
802 | ||
803 | err = read_utmi_param(pdev, "nvidia,hssync-start-delay", | |
804 | &config->hssync_start_delay); | |
805 | if (err < 0) | |
806 | return err; | |
807 | ||
808 | err = read_utmi_param(pdev, "nvidia,elastic-limit", | |
809 | &config->elastic_limit); | |
810 | if (err < 0) | |
811 | return err; | |
812 | ||
813 | err = read_utmi_param(pdev, "nvidia,idle-wait-delay", | |
814 | &config->idle_wait_delay); | |
815 | if (err < 0) | |
816 | return err; | |
817 | ||
818 | err = read_utmi_param(pdev, "nvidia,term-range-adj", | |
819 | &config->term_range_adj); | |
820 | if (err < 0) | |
821 | return err; | |
822 | ||
823 | err = read_utmi_param(pdev, "nvidia,xcvr-setup", | |
824 | &config->xcvr_setup); | |
825 | if (err < 0) | |
826 | return err; | |
827 | ||
828 | err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew", | |
829 | &config->xcvr_lsfslew); | |
830 | if (err < 0) | |
831 | return err; | |
832 | ||
833 | err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew", | |
834 | &config->xcvr_lsrslew); | |
835 | if (err < 0) | |
836 | return err; | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
2d22b42d VB |
841 | static int tegra_usb_phy_probe(struct platform_device *pdev) |
842 | { | |
843 | struct resource *res; | |
844 | struct tegra_usb_phy *tegra_phy = NULL; | |
845 | struct device_node *np = pdev->dev.of_node; | |
846 | int err; | |
847 | ||
848 | tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL); | |
849 | if (!tegra_phy) { | |
850 | dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n"); | |
851 | return -ENOMEM; | |
852 | } | |
853 | ||
854 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
855 | if (!res) { | |
856 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
857 | return -ENXIO; | |
858 | } | |
859 | ||
860 | tegra_phy->regs = devm_ioremap(&pdev->dev, res->start, | |
861 | resource_size(res)); | |
862 | if (!tegra_phy->regs) { | |
863 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
864 | return -ENOMEM; | |
865 | } | |
866 | ||
867 | tegra_phy->is_legacy_phy = | |
868 | of_property_read_bool(np, "nvidia,has-legacy-mode"); | |
869 | ||
870 | err = of_property_match_string(np, "phy_type", "ulpi"); | |
871 | if (err < 0) { | |
81d5dfe6 MP |
872 | err = utmi_phy_probe(tegra_phy, pdev); |
873 | if (err < 0) | |
874 | return err; | |
2d22b42d VB |
875 | } else { |
876 | tegra_phy->is_ulpi_phy = true; | |
877 | ||
878 | tegra_phy->reset_gpio = | |
879 | of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0); | |
880 | if (!gpio_is_valid(tegra_phy->reset_gpio)) { | |
881 | dev_err(&pdev->dev, "invalid gpio: %d\n", | |
882 | tegra_phy->reset_gpio); | |
883 | return tegra_phy->reset_gpio; | |
884 | } | |
81d5dfe6 MP |
885 | |
886 | tegra_phy->config = NULL; | |
2d22b42d VB |
887 | } |
888 | ||
889 | err = of_property_match_string(np, "dr_mode", "otg"); | |
890 | if (err < 0) { | |
891 | err = of_property_match_string(np, "dr_mode", "peripheral"); | |
892 | if (err < 0) | |
893 | tegra_phy->mode = TEGRA_USB_PHY_MODE_HOST; | |
894 | else | |
895 | tegra_phy->mode = TEGRA_USB_PHY_MODE_DEVICE; | |
896 | } else | |
897 | tegra_phy->mode = TEGRA_USB_PHY_MODE_OTG; | |
898 | ||
899 | tegra_phy->dev = &pdev->dev; | |
900 | err = tegra_usb_phy_init(tegra_phy); | |
901 | if (err < 0) | |
902 | return err; | |
903 | ||
904 | tegra_phy->u_phy.shutdown = tegra_usb_phy_close; | |
905 | tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend; | |
906 | ||
907 | dev_set_drvdata(&pdev->dev, tegra_phy); | |
908 | return 0; | |
909 | } | |
910 | ||
911 | static struct of_device_id tegra_usb_phy_id_table[] = { | |
912 | { .compatible = "nvidia,tegra20-usb-phy", }, | |
913 | { }, | |
914 | }; | |
915 | MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table); | |
916 | ||
917 | static struct platform_driver tegra_usb_phy_driver = { | |
918 | .probe = tegra_usb_phy_probe, | |
919 | .driver = { | |
920 | .name = "tegra-phy", | |
921 | .owner = THIS_MODULE, | |
922 | .of_match_table = of_match_ptr(tegra_usb_phy_id_table), | |
923 | }, | |
924 | }; | |
925 | module_platform_driver(tegra_usb_phy_driver); | |
926 | ||
927 | static int tegra_usb_phy_match(struct device *dev, void *data) | |
928 | { | |
929 | struct tegra_usb_phy *tegra_phy = dev_get_drvdata(dev); | |
930 | struct device_node *dn = data; | |
931 | ||
932 | return (tegra_phy->dev->of_node == dn) ? 1 : 0; | |
933 | } | |
934 | ||
935 | struct usb_phy *tegra_usb_get_phy(struct device_node *dn) | |
936 | { | |
937 | struct device *dev; | |
938 | struct tegra_usb_phy *tegra_phy; | |
939 | ||
940 | dev = driver_find_device(&tegra_usb_phy_driver.driver, NULL, dn, | |
941 | tegra_usb_phy_match); | |
942 | if (!dev) | |
943 | return ERR_PTR(-EPROBE_DEFER); | |
944 | ||
945 | tegra_phy = dev_get_drvdata(dev); | |
946 | ||
947 | return &tegra_phy->u_phy; | |
948 | } | |
949 | EXPORT_SYMBOL_GPL(tegra_usb_get_phy); | |
587376a1 SW |
950 | |
951 | MODULE_DESCRIPTION("Tegra USB PHY driver"); | |
952 | MODULE_LICENSE("GPL v2"); |