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b6e06983 IPG |
1 | /* |
2 | * Wireless Host Controller: Radio Control Interface (WHCI v0.95[2.3]) | |
3 | * Radio Control command/event transport to the UWB stack | |
4 | * | |
5 | * Copyright (C) 2005-2006 Intel Corporation | |
6 | * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License version | |
10 | * 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301, USA. | |
21 | * | |
22 | * | |
23 | * Initialize and hook up the Radio Control interface. | |
24 | * | |
25 | * For each device probed, creates an 'struct whcrc' which contains | |
26 | * just the representation of the UWB Radio Controller, and the logic | |
27 | * for reading notifications and passing them to the UWB Core. | |
28 | * | |
29 | * So we initialize all of those, register the UWB Radio Controller | |
30 | * and setup the notification/event handle to pipe the notifications | |
31 | * to the UWB management Daemon. | |
32 | * | |
33 | * Once uwb_rc_add() is called, the UWB stack takes control, resets | |
34 | * the radio and readies the device to take commands the UWB | |
35 | * API/user-space. | |
36 | * | |
37 | * Note this driver is just a transport driver; the commands are | |
38 | * formed at the UWB stack and given to this driver who will deliver | |
39 | * them to the hw and transfer the replies/notifications back to the | |
40 | * UWB stack through the UWB daemon (UWBD). | |
41 | */ | |
b6e06983 IPG |
42 | #include <linux/init.h> |
43 | #include <linux/module.h> | |
44 | #include <linux/pci.h> | |
45 | #include <linux/dma-mapping.h> | |
46 | #include <linux/interrupt.h> | |
47 | #include <linux/workqueue.h> | |
48 | #include <linux/uwb.h> | |
49 | #include <linux/uwb/whci.h> | |
50 | #include <linux/uwb/umc.h> | |
b6e06983 | 51 | |
bce83697 | 52 | #include "uwb-internal.h" |
b6e06983 IPG |
53 | |
54 | /** | |
55 | * Descriptor for an instance of the UWB Radio Control Driver that | |
56 | * attaches to the URC interface of the WHCI PCI card. | |
57 | * | |
58 | * Unless there is a lock specific to the 'data members', all access | |
59 | * is protected by uwb_rc->mutex. | |
60 | */ | |
61 | struct whcrc { | |
62 | struct umc_dev *umc_dev; | |
63 | struct uwb_rc *uwb_rc; /* UWB host controller */ | |
64 | ||
65 | unsigned long area; | |
66 | void __iomem *rc_base; | |
67 | size_t rc_len; | |
68 | spinlock_t irq_lock; | |
69 | ||
70 | void *evt_buf, *cmd_buf; | |
71 | dma_addr_t evt_dma_buf, cmd_dma_buf; | |
72 | wait_queue_head_t cmd_wq; | |
73 | struct work_struct event_work; | |
74 | }; | |
75 | ||
76 | /** | |
77 | * Execute an UWB RC command on WHCI/RC | |
78 | * | |
79 | * @rc: Instance of a Radio Controller that is a whcrc | |
80 | * @cmd: Buffer containing the RCCB and payload to execute | |
81 | * @cmd_size: Size of the command buffer. | |
82 | * | |
83 | * We copy the command into whcrc->cmd_buf (as it is pretty and | |
84 | * aligned`and physically contiguous) and then press the right keys in | |
85 | * the controller's URCCMD register to get it to read it. We might | |
86 | * have to wait for the cmd_sem to be open to us. | |
87 | * | |
88 | * NOTE: rc's mutex has to be locked | |
89 | */ | |
90 | static int whcrc_cmd(struct uwb_rc *uwb_rc, | |
91 | const struct uwb_rccb *cmd, size_t cmd_size) | |
92 | { | |
93 | int result = 0; | |
94 | struct whcrc *whcrc = uwb_rc->priv; | |
95 | struct device *dev = &whcrc->umc_dev->dev; | |
96 | u32 urccmd; | |
97 | ||
bce83697 DV |
98 | if (cmd_size >= 4096) |
99 | return -EINVAL; | |
b6e06983 IPG |
100 | |
101 | /* | |
102 | * If the URC is halted, then the hardware has reset itself. | |
103 | * Attempt to recover by restarting the device and then return | |
104 | * an error as it's likely that the current command isn't | |
105 | * valid for a newly started RC. | |
106 | */ | |
107 | if (le_readl(whcrc->rc_base + URCSTS) & URCSTS_HALTED) { | |
108 | dev_err(dev, "requesting reset of halted radio controller\n"); | |
109 | uwb_rc_reset_all(uwb_rc); | |
bce83697 | 110 | return -EIO; |
b6e06983 IPG |
111 | } |
112 | ||
113 | result = wait_event_timeout(whcrc->cmd_wq, | |
114 | !(le_readl(whcrc->rc_base + URCCMD) & URCCMD_ACTIVE), HZ/2); | |
115 | if (result == 0) { | |
116 | dev_err(dev, "device is not ready to execute commands\n"); | |
bce83697 | 117 | return -ETIMEDOUT; |
b6e06983 IPG |
118 | } |
119 | ||
120 | memmove(whcrc->cmd_buf, cmd, cmd_size); | |
121 | le_writeq(whcrc->cmd_dma_buf, whcrc->rc_base + URCCMDADDR); | |
122 | ||
123 | spin_lock(&whcrc->irq_lock); | |
124 | urccmd = le_readl(whcrc->rc_base + URCCMD); | |
125 | urccmd &= ~(URCCMD_EARV | URCCMD_SIZE_MASK); | |
126 | le_writel(urccmd | URCCMD_ACTIVE | URCCMD_IWR | cmd_size, | |
127 | whcrc->rc_base + URCCMD); | |
128 | spin_unlock(&whcrc->irq_lock); | |
129 | ||
bce83697 | 130 | return 0; |
b6e06983 IPG |
131 | } |
132 | ||
133 | static int whcrc_reset(struct uwb_rc *rc) | |
134 | { | |
135 | struct whcrc *whcrc = rc->priv; | |
136 | ||
137 | return umc_controller_reset(whcrc->umc_dev); | |
138 | } | |
139 | ||
140 | /** | |
141 | * Reset event reception mechanism and tell hw we are ready to get more | |
142 | * | |
143 | * We have read all the events in the event buffer, so we are ready to | |
144 | * reset it to the beginning. | |
145 | * | |
146 | * This is only called during initialization or after an event buffer | |
147 | * has been retired. This means we can be sure that event processing | |
148 | * is disabled and it's safe to update the URCEVTADDR register. | |
149 | * | |
150 | * There's no need to wait for the event processing to start as the | |
151 | * URC will not clear URCCMD_ACTIVE until (internal) event buffer | |
152 | * space is available. | |
153 | */ | |
154 | static | |
155 | void whcrc_enable_events(struct whcrc *whcrc) | |
156 | { | |
b6e06983 IPG |
157 | u32 urccmd; |
158 | ||
b6e06983 IPG |
159 | le_writeq(whcrc->evt_dma_buf, whcrc->rc_base + URCEVTADDR); |
160 | ||
161 | spin_lock(&whcrc->irq_lock); | |
162 | urccmd = le_readl(whcrc->rc_base + URCCMD) & ~URCCMD_ACTIVE; | |
163 | le_writel(urccmd | URCCMD_EARV, whcrc->rc_base + URCCMD); | |
164 | spin_unlock(&whcrc->irq_lock); | |
b6e06983 IPG |
165 | } |
166 | ||
167 | static void whcrc_event_work(struct work_struct *work) | |
168 | { | |
169 | struct whcrc *whcrc = container_of(work, struct whcrc, event_work); | |
b6e06983 IPG |
170 | size_t size; |
171 | u64 urcevtaddr; | |
172 | ||
173 | urcevtaddr = le_readq(whcrc->rc_base + URCEVTADDR); | |
174 | size = urcevtaddr & URCEVTADDR_OFFSET_MASK; | |
175 | ||
b6e06983 IPG |
176 | uwb_rc_neh_grok(whcrc->uwb_rc, whcrc->evt_buf, size); |
177 | whcrc_enable_events(whcrc); | |
178 | } | |
179 | ||
180 | /** | |
181 | * Catch interrupts? | |
182 | * | |
183 | * We ack inmediately (and expect the hw to do the right thing and | |
184 | * raise another IRQ if things have changed :) | |
185 | */ | |
186 | static | |
187 | irqreturn_t whcrc_irq_cb(int irq, void *_whcrc) | |
188 | { | |
189 | struct whcrc *whcrc = _whcrc; | |
190 | struct device *dev = &whcrc->umc_dev->dev; | |
191 | u32 urcsts; | |
192 | ||
b6e06983 IPG |
193 | urcsts = le_readl(whcrc->rc_base + URCSTS); |
194 | if (!(urcsts & URCSTS_INT_MASK)) | |
195 | return IRQ_NONE; | |
196 | le_writel(urcsts & URCSTS_INT_MASK, whcrc->rc_base + URCSTS); | |
197 | ||
b6e06983 IPG |
198 | if (urcsts & URCSTS_HSE) { |
199 | dev_err(dev, "host system error -- hardware halted\n"); | |
200 | /* FIXME: do something sensible here */ | |
201 | goto out; | |
202 | } | |
bce83697 | 203 | if (urcsts & URCSTS_ER) |
b6e06983 | 204 | schedule_work(&whcrc->event_work); |
bce83697 | 205 | if (urcsts & URCSTS_RCI) |
b6e06983 | 206 | wake_up_all(&whcrc->cmd_wq); |
b6e06983 IPG |
207 | out: |
208 | return IRQ_HANDLED; | |
209 | } | |
210 | ||
211 | ||
212 | /** | |
213 | * Initialize a UMC RC interface: map regions, get (shared) IRQ | |
214 | */ | |
215 | static | |
216 | int whcrc_setup_rc_umc(struct whcrc *whcrc) | |
217 | { | |
218 | int result = 0; | |
219 | struct device *dev = &whcrc->umc_dev->dev; | |
220 | struct umc_dev *umc_dev = whcrc->umc_dev; | |
221 | ||
222 | whcrc->area = umc_dev->resource.start; | |
223 | whcrc->rc_len = umc_dev->resource.end - umc_dev->resource.start + 1; | |
224 | result = -EBUSY; | |
bce83697 | 225 | if (request_mem_region(whcrc->area, whcrc->rc_len, KBUILD_MODNAME) == NULL) { |
b6e06983 IPG |
226 | dev_err(dev, "can't request URC region (%zu bytes @ 0x%lx): %d\n", |
227 | whcrc->rc_len, whcrc->area, result); | |
228 | goto error_request_region; | |
229 | } | |
230 | ||
231 | whcrc->rc_base = ioremap_nocache(whcrc->area, whcrc->rc_len); | |
232 | if (whcrc->rc_base == NULL) { | |
233 | dev_err(dev, "can't ioremap registers (%zu bytes @ 0x%lx): %d\n", | |
234 | whcrc->rc_len, whcrc->area, result); | |
235 | goto error_ioremap_nocache; | |
236 | } | |
237 | ||
238 | result = request_irq(umc_dev->irq, whcrc_irq_cb, IRQF_SHARED, | |
239 | KBUILD_MODNAME, whcrc); | |
240 | if (result < 0) { | |
241 | dev_err(dev, "can't allocate IRQ %d: %d\n", | |
242 | umc_dev->irq, result); | |
243 | goto error_request_irq; | |
244 | } | |
245 | ||
246 | result = -ENOMEM; | |
247 | whcrc->cmd_buf = dma_alloc_coherent(&umc_dev->dev, PAGE_SIZE, | |
248 | &whcrc->cmd_dma_buf, GFP_KERNEL); | |
249 | if (whcrc->cmd_buf == NULL) { | |
250 | dev_err(dev, "Can't allocate cmd transfer buffer\n"); | |
251 | goto error_cmd_buffer; | |
252 | } | |
253 | ||
254 | whcrc->evt_buf = dma_alloc_coherent(&umc_dev->dev, PAGE_SIZE, | |
255 | &whcrc->evt_dma_buf, GFP_KERNEL); | |
256 | if (whcrc->evt_buf == NULL) { | |
257 | dev_err(dev, "Can't allocate evt transfer buffer\n"); | |
258 | goto error_evt_buffer; | |
259 | } | |
b6e06983 IPG |
260 | return 0; |
261 | ||
262 | error_evt_buffer: | |
263 | dma_free_coherent(&umc_dev->dev, PAGE_SIZE, whcrc->cmd_buf, | |
264 | whcrc->cmd_dma_buf); | |
265 | error_cmd_buffer: | |
266 | free_irq(umc_dev->irq, whcrc); | |
267 | error_request_irq: | |
268 | iounmap(whcrc->rc_base); | |
269 | error_ioremap_nocache: | |
270 | release_mem_region(whcrc->area, whcrc->rc_len); | |
271 | error_request_region: | |
272 | return result; | |
273 | } | |
274 | ||
275 | ||
276 | /** | |
277 | * Release RC's UMC resources | |
278 | */ | |
279 | static | |
280 | void whcrc_release_rc_umc(struct whcrc *whcrc) | |
281 | { | |
282 | struct umc_dev *umc_dev = whcrc->umc_dev; | |
283 | ||
284 | dma_free_coherent(&umc_dev->dev, PAGE_SIZE, whcrc->evt_buf, | |
285 | whcrc->evt_dma_buf); | |
286 | dma_free_coherent(&umc_dev->dev, PAGE_SIZE, whcrc->cmd_buf, | |
287 | whcrc->cmd_dma_buf); | |
288 | free_irq(umc_dev->irq, whcrc); | |
289 | iounmap(whcrc->rc_base); | |
290 | release_mem_region(whcrc->area, whcrc->rc_len); | |
291 | } | |
292 | ||
293 | ||
294 | /** | |
295 | * whcrc_start_rc - start a WHCI radio controller | |
296 | * @whcrc: the radio controller to start | |
297 | * | |
298 | * Reset the UMC device, start the radio controller, enable events and | |
299 | * finally enable interrupts. | |
300 | */ | |
301 | static int whcrc_start_rc(struct uwb_rc *rc) | |
302 | { | |
303 | struct whcrc *whcrc = rc->priv; | |
b6e06983 | 304 | struct device *dev = &whcrc->umc_dev->dev; |
b6e06983 IPG |
305 | |
306 | /* Reset the thing */ | |
307 | le_writel(URCCMD_RESET, whcrc->rc_base + URCCMD); | |
b6e06983 | 308 | if (whci_wait_for(dev, whcrc->rc_base + URCCMD, URCCMD_RESET, 0, |
5a4e1a79 DV |
309 | 5000, "hardware reset") < 0) |
310 | return -EBUSY; | |
b6e06983 IPG |
311 | |
312 | /* Set the event buffer, start the controller (enable IRQs later) */ | |
313 | le_writel(0, whcrc->rc_base + URCINTR); | |
314 | le_writel(URCCMD_RS, whcrc->rc_base + URCCMD); | |
b6e06983 | 315 | if (whci_wait_for(dev, whcrc->rc_base + URCSTS, URCSTS_HALTED, 0, |
5a4e1a79 DV |
316 | 5000, "radio controller start") < 0) |
317 | return -ETIMEDOUT; | |
b6e06983 | 318 | whcrc_enable_events(whcrc); |
b6e06983 | 319 | le_writel(URCINTR_EN_ALL, whcrc->rc_base + URCINTR); |
5a4e1a79 | 320 | return 0; |
b6e06983 IPG |
321 | } |
322 | ||
323 | ||
324 | /** | |
325 | * whcrc_stop_rc - stop a WHCI radio controller | |
326 | * @whcrc: the radio controller to stop | |
327 | * | |
328 | * Disable interrupts and cancel any pending event processing work | |
329 | * before clearing the Run/Stop bit. | |
330 | */ | |
331 | static | |
332 | void whcrc_stop_rc(struct uwb_rc *rc) | |
333 | { | |
334 | struct whcrc *whcrc = rc->priv; | |
335 | struct umc_dev *umc_dev = whcrc->umc_dev; | |
336 | ||
337 | le_writel(0, whcrc->rc_base + URCINTR); | |
338 | cancel_work_sync(&whcrc->event_work); | |
339 | ||
340 | le_writel(0, whcrc->rc_base + URCCMD); | |
341 | whci_wait_for(&umc_dev->dev, whcrc->rc_base + URCSTS, | |
5a4e1a79 | 342 | URCSTS_HALTED, URCSTS_HALTED, 100, "radio controller stop"); |
b6e06983 IPG |
343 | } |
344 | ||
345 | static void whcrc_init(struct whcrc *whcrc) | |
346 | { | |
347 | spin_lock_init(&whcrc->irq_lock); | |
348 | init_waitqueue_head(&whcrc->cmd_wq); | |
349 | INIT_WORK(&whcrc->event_work, whcrc_event_work); | |
350 | } | |
351 | ||
352 | /** | |
353 | * Initialize the radio controller. | |
354 | * | |
355 | * NOTE: we setup whcrc->uwb_rc before calling uwb_rc_add(); in the | |
356 | * IRQ handler we use that to determine if the hw is ready to | |
357 | * handle events. Looks like a race condition, but it really is | |
358 | * not. | |
359 | */ | |
360 | static | |
361 | int whcrc_probe(struct umc_dev *umc_dev) | |
362 | { | |
363 | int result; | |
364 | struct uwb_rc *uwb_rc; | |
365 | struct whcrc *whcrc; | |
366 | struct device *dev = &umc_dev->dev; | |
367 | ||
b6e06983 IPG |
368 | result = -ENOMEM; |
369 | uwb_rc = uwb_rc_alloc(); | |
370 | if (uwb_rc == NULL) { | |
371 | dev_err(dev, "unable to allocate RC instance\n"); | |
372 | goto error_rc_alloc; | |
373 | } | |
374 | whcrc = kzalloc(sizeof(*whcrc), GFP_KERNEL); | |
375 | if (whcrc == NULL) { | |
376 | dev_err(dev, "unable to allocate WHC-RC instance\n"); | |
377 | goto error_alloc; | |
378 | } | |
379 | whcrc_init(whcrc); | |
380 | whcrc->umc_dev = umc_dev; | |
381 | ||
382 | result = whcrc_setup_rc_umc(whcrc); | |
383 | if (result < 0) { | |
384 | dev_err(dev, "Can't setup RC UMC interface: %d\n", result); | |
385 | goto error_setup_rc_umc; | |
386 | } | |
387 | whcrc->uwb_rc = uwb_rc; | |
388 | ||
389 | uwb_rc->owner = THIS_MODULE; | |
390 | uwb_rc->cmd = whcrc_cmd; | |
391 | uwb_rc->reset = whcrc_reset; | |
392 | uwb_rc->start = whcrc_start_rc; | |
393 | uwb_rc->stop = whcrc_stop_rc; | |
394 | ||
395 | result = uwb_rc_add(uwb_rc, dev, whcrc); | |
396 | if (result < 0) | |
397 | goto error_rc_add; | |
398 | umc_set_drvdata(umc_dev, whcrc); | |
b6e06983 IPG |
399 | return 0; |
400 | ||
401 | error_rc_add: | |
402 | whcrc_release_rc_umc(whcrc); | |
403 | error_setup_rc_umc: | |
404 | kfree(whcrc); | |
405 | error_alloc: | |
406 | uwb_rc_put(uwb_rc); | |
407 | error_rc_alloc: | |
b6e06983 IPG |
408 | return result; |
409 | } | |
410 | ||
411 | /** | |
412 | * Clean up the radio control resources | |
413 | * | |
414 | * When we up the command semaphore, everybody possibly held trying to | |
415 | * execute a command should be granted entry and then they'll see the | |
416 | * host is quiescing and up it (so it will chain to the next waiter). | |
417 | * This should not happen (in any case), as we can only remove when | |
418 | * there are no handles open... | |
419 | */ | |
420 | static void whcrc_remove(struct umc_dev *umc_dev) | |
421 | { | |
422 | struct whcrc *whcrc = umc_get_drvdata(umc_dev); | |
423 | struct uwb_rc *uwb_rc = whcrc->uwb_rc; | |
424 | ||
425 | umc_set_drvdata(umc_dev, NULL); | |
426 | uwb_rc_rm(uwb_rc); | |
427 | whcrc_release_rc_umc(whcrc); | |
428 | kfree(whcrc); | |
429 | uwb_rc_put(uwb_rc); | |
b6e06983 IPG |
430 | } |
431 | ||
307ba6dd DV |
432 | static int whcrc_pre_reset(struct umc_dev *umc) |
433 | { | |
434 | struct whcrc *whcrc = umc_get_drvdata(umc); | |
435 | struct uwb_rc *uwb_rc = whcrc->uwb_rc; | |
436 | ||
437 | uwb_rc_pre_reset(uwb_rc); | |
438 | return 0; | |
439 | } | |
440 | ||
441 | static int whcrc_post_reset(struct umc_dev *umc) | |
442 | { | |
443 | struct whcrc *whcrc = umc_get_drvdata(umc); | |
444 | struct uwb_rc *uwb_rc = whcrc->uwb_rc; | |
445 | ||
0396c215 | 446 | return uwb_rc_post_reset(uwb_rc); |
307ba6dd DV |
447 | } |
448 | ||
b6e06983 IPG |
449 | /* PCI device ID's that we handle [so it gets loaded] */ |
450 | static struct pci_device_id whcrc_id_table[] = { | |
451 | { PCI_DEVICE_CLASS(PCI_CLASS_WIRELESS_WHCI, ~0) }, | |
452 | { /* empty last entry */ } | |
453 | }; | |
454 | MODULE_DEVICE_TABLE(pci, whcrc_id_table); | |
455 | ||
456 | static struct umc_driver whcrc_driver = { | |
307ba6dd DV |
457 | .name = "whc-rc", |
458 | .cap_id = UMC_CAP_ID_WHCI_RC, | |
459 | .probe = whcrc_probe, | |
460 | .remove = whcrc_remove, | |
461 | .pre_reset = whcrc_pre_reset, | |
462 | .post_reset = whcrc_post_reset, | |
b6e06983 IPG |
463 | }; |
464 | ||
465 | static int __init whcrc_driver_init(void) | |
466 | { | |
467 | return umc_driver_register(&whcrc_driver); | |
468 | } | |
469 | module_init(whcrc_driver_init); | |
470 | ||
471 | static void __exit whcrc_driver_exit(void) | |
472 | { | |
473 | umc_driver_unregister(&whcrc_driver); | |
474 | } | |
475 | module_exit(whcrc_driver_exit); | |
476 | ||
477 | MODULE_AUTHOR("Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>"); | |
478 | MODULE_DESCRIPTION("Wireless Host Controller Radio Control Driver"); | |
479 | MODULE_LICENSE("GPL"); |