Commit | Line | Data |
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14340586 NF |
1 | /* |
2 | * Driver for AT91/AT32 LCD Controller | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Corporation | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive for | |
8 | * more details. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/fb.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/delay.h> | |
a9a84c37 | 19 | #include <linux/backlight.h> |
5a0e3ad6 | 20 | #include <linux/gfp.h> |
355b200b | 21 | #include <linux/module.h> |
bcd2360c | 22 | #include <linux/platform_data/atmel.h> |
14340586 | 23 | |
a09e64fb | 24 | #include <mach/cpu.h> |
60e8972d | 25 | #include <asm/gpio.h> |
14340586 NF |
26 | |
27 | #include <video/atmel_lcdc.h> | |
28 | ||
29 | #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) | |
30 | #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) | |
31 | ||
32 | /* configurable parameters */ | |
33 | #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 | |
53b7479b NF |
34 | #define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */ |
35 | #define ATMEL_LCDC_FIFO_SIZE 512 /* words */ | |
14340586 | 36 | |
bbd44f6b JH |
37 | struct atmel_lcdfb_config { |
38 | bool have_alt_pixclock; | |
39 | bool have_hozval; | |
40 | bool have_intensity_bit; | |
41 | }; | |
42 | ||
43 | static struct atmel_lcdfb_config at91sam9261_config = { | |
44 | .have_hozval = true, | |
45 | .have_intensity_bit = true, | |
46 | }; | |
47 | ||
48 | static struct atmel_lcdfb_config at91sam9263_config = { | |
49 | .have_intensity_bit = true, | |
50 | }; | |
51 | ||
52 | static struct atmel_lcdfb_config at91sam9g10_config = { | |
53 | .have_hozval = true, | |
54 | }; | |
55 | ||
56 | static struct atmel_lcdfb_config at91sam9g45_config = { | |
57 | .have_alt_pixclock = true, | |
58 | }; | |
59 | ||
60 | static struct atmel_lcdfb_config at91sam9g45es_config = { | |
61 | }; | |
62 | ||
63 | static struct atmel_lcdfb_config at91sam9rl_config = { | |
64 | .have_intensity_bit = true, | |
65 | }; | |
66 | ||
67 | static struct atmel_lcdfb_config at32ap_config = { | |
68 | .have_hozval = true, | |
69 | }; | |
70 | ||
71 | static const struct platform_device_id atmel_lcdfb_devtypes[] = { | |
72 | { | |
73 | .name = "at91sam9261-lcdfb", | |
74 | .driver_data = (unsigned long)&at91sam9261_config, | |
75 | }, { | |
76 | .name = "at91sam9263-lcdfb", | |
77 | .driver_data = (unsigned long)&at91sam9263_config, | |
78 | }, { | |
79 | .name = "at91sam9g10-lcdfb", | |
80 | .driver_data = (unsigned long)&at91sam9g10_config, | |
81 | }, { | |
82 | .name = "at91sam9g45-lcdfb", | |
83 | .driver_data = (unsigned long)&at91sam9g45_config, | |
84 | }, { | |
85 | .name = "at91sam9g45es-lcdfb", | |
86 | .driver_data = (unsigned long)&at91sam9g45es_config, | |
87 | }, { | |
88 | .name = "at91sam9rl-lcdfb", | |
89 | .driver_data = (unsigned long)&at91sam9rl_config, | |
90 | }, { | |
91 | .name = "at32ap-lcdfb", | |
92 | .driver_data = (unsigned long)&at32ap_config, | |
93 | }, { | |
94 | /* terminator */ | |
95 | } | |
96 | }; | |
97 | ||
98 | static struct atmel_lcdfb_config * | |
99 | atmel_lcdfb_get_config(struct platform_device *pdev) | |
100 | { | |
101 | unsigned long data; | |
102 | ||
103 | data = platform_get_device_id(pdev)->driver_data; | |
104 | ||
105 | return (struct atmel_lcdfb_config *)data; | |
106 | } | |
107 | ||
14340586 | 108 | #if defined(CONFIG_ARCH_AT91) |
e730d8b0 HS |
109 | #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \ |
110 | | FBINFO_PARTIAL_PAN_OK \ | |
111 | | FBINFO_HWACCEL_YPAN) | |
14340586 NF |
112 | |
113 | static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo, | |
b3e9c129 LP |
114 | struct fb_var_screeninfo *var, |
115 | struct fb_info *info) | |
14340586 NF |
116 | { |
117 | ||
118 | } | |
119 | #elif defined(CONFIG_AVR32) | |
120 | #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \ | |
121 | | FBINFO_PARTIAL_PAN_OK \ | |
122 | | FBINFO_HWACCEL_XPAN \ | |
123 | | FBINFO_HWACCEL_YPAN) | |
124 | ||
125 | static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo, | |
b3e9c129 LP |
126 | struct fb_var_screeninfo *var, |
127 | struct fb_info *info) | |
14340586 NF |
128 | { |
129 | u32 dma2dcfg; | |
130 | u32 pixeloff; | |
131 | ||
b3e9c129 | 132 | pixeloff = (var->xoffset * info->var.bits_per_pixel) & 0x1f; |
14340586 | 133 | |
b3e9c129 LP |
134 | dma2dcfg = (info->var.xres_virtual - info->var.xres) |
135 | * info->var.bits_per_pixel / 8; | |
14340586 NF |
136 | dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET; |
137 | lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg); | |
138 | ||
139 | /* Update configuration */ | |
140 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, | |
141 | lcdc_readl(sinfo, ATMEL_LCDC_DMACON) | |
142 | | ATMEL_LCDC_DMAUPDT); | |
143 | } | |
144 | #endif | |
145 | ||
7cdcdb69 | 146 | static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8 |
a9a84c37 DB |
147 | | ATMEL_LCDC_POL_POSITIVE |
148 | | ATMEL_LCDC_ENA_PWMENABLE; | |
149 | ||
150 | #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC | |
151 | ||
152 | /* some bl->props field just changed */ | |
153 | static int atmel_bl_update_status(struct backlight_device *bl) | |
154 | { | |
155 | struct atmel_lcdfb_info *sinfo = bl_get_data(bl); | |
156 | int power = sinfo->bl_power; | |
157 | int brightness = bl->props.brightness; | |
158 | ||
159 | /* REVISIT there may be a meaningful difference between | |
160 | * fb_blank and power ... there seem to be some cases | |
161 | * this doesn't handle correctly. | |
162 | */ | |
163 | if (bl->props.fb_blank != sinfo->bl_power) | |
164 | power = bl->props.fb_blank; | |
165 | else if (bl->props.power != sinfo->bl_power) | |
166 | power = bl->props.power; | |
167 | ||
168 | if (brightness < 0 && power == FB_BLANK_UNBLANK) | |
169 | brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL); | |
170 | else if (power != FB_BLANK_UNBLANK) | |
171 | brightness = 0; | |
172 | ||
173 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness); | |
acfdc2e1 AS |
174 | if (contrast_ctr & ATMEL_LCDC_POL_POSITIVE) |
175 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, | |
a9a84c37 | 176 | brightness ? contrast_ctr : 0); |
acfdc2e1 AS |
177 | else |
178 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); | |
a9a84c37 DB |
179 | |
180 | bl->props.fb_blank = bl->props.power = sinfo->bl_power = power; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static int atmel_bl_get_brightness(struct backlight_device *bl) | |
186 | { | |
187 | struct atmel_lcdfb_info *sinfo = bl_get_data(bl); | |
188 | ||
189 | return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL); | |
190 | } | |
191 | ||
acc2472e | 192 | static const struct backlight_ops atmel_lcdc_bl_ops = { |
a9a84c37 DB |
193 | .update_status = atmel_bl_update_status, |
194 | .get_brightness = atmel_bl_get_brightness, | |
195 | }; | |
196 | ||
197 | static void init_backlight(struct atmel_lcdfb_info *sinfo) | |
198 | { | |
a19a6ee6 | 199 | struct backlight_properties props; |
a9a84c37 DB |
200 | struct backlight_device *bl; |
201 | ||
202 | sinfo->bl_power = FB_BLANK_UNBLANK; | |
203 | ||
204 | if (sinfo->backlight) | |
205 | return; | |
206 | ||
a19a6ee6 | 207 | memset(&props, 0, sizeof(struct backlight_properties)); |
bb7ca747 | 208 | props.type = BACKLIGHT_RAW; |
a19a6ee6 MG |
209 | props.max_brightness = 0xff; |
210 | bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo, | |
211 | &atmel_lcdc_bl_ops, &props); | |
cf7b9a1e | 212 | if (IS_ERR(bl)) { |
a9a84c37 DB |
213 | dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n", |
214 | PTR_ERR(bl)); | |
215 | return; | |
216 | } | |
217 | sinfo->backlight = bl; | |
218 | ||
219 | bl->props.power = FB_BLANK_UNBLANK; | |
220 | bl->props.fb_blank = FB_BLANK_UNBLANK; | |
a9a84c37 DB |
221 | bl->props.brightness = atmel_bl_get_brightness(bl); |
222 | } | |
223 | ||
224 | static void exit_backlight(struct atmel_lcdfb_info *sinfo) | |
225 | { | |
56c21b53 RG |
226 | if (!sinfo->backlight) |
227 | return; | |
228 | ||
229 | if (sinfo->backlight->ops) { | |
230 | sinfo->backlight->props.power = FB_BLANK_POWERDOWN; | |
231 | sinfo->backlight->ops->update_status(sinfo->backlight); | |
232 | } | |
233 | backlight_device_unregister(sinfo->backlight); | |
a9a84c37 DB |
234 | } |
235 | ||
236 | #else | |
237 | ||
238 | static void init_backlight(struct atmel_lcdfb_info *sinfo) | |
239 | { | |
240 | dev_warn(&sinfo->pdev->dev, "backlight control is not available\n"); | |
241 | } | |
242 | ||
243 | static void exit_backlight(struct atmel_lcdfb_info *sinfo) | |
244 | { | |
245 | } | |
246 | ||
247 | #endif | |
248 | ||
249 | static void init_contrast(struct atmel_lcdfb_info *sinfo) | |
250 | { | |
7cdcdb69 AB |
251 | /* contrast pwm can be 'inverted' */ |
252 | if (sinfo->lcdcon_pol_negative) | |
253 | contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE); | |
254 | ||
a9a84c37 DB |
255 | /* have some default contrast/backlight settings */ |
256 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); | |
257 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); | |
258 | ||
259 | if (sinfo->lcdcon_is_backlight) | |
260 | init_backlight(sinfo); | |
261 | } | |
262 | ||
14340586 NF |
263 | |
264 | static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = { | |
265 | .type = FB_TYPE_PACKED_PIXELS, | |
266 | .visual = FB_VISUAL_TRUECOLOR, | |
267 | .xpanstep = 0, | |
e730d8b0 | 268 | .ypanstep = 1, |
14340586 NF |
269 | .ywrapstep = 0, |
270 | .accel = FB_ACCEL_NONE, | |
271 | }; | |
272 | ||
934a50bd JH |
273 | static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo, |
274 | unsigned long xres) | |
250a269d | 275 | { |
934a50bd | 276 | unsigned long lcdcon2; |
250a269d NF |
277 | unsigned long value; |
278 | ||
bbd44f6b | 279 | if (!sinfo->config->have_hozval) |
250a269d NF |
280 | return xres; |
281 | ||
934a50bd | 282 | lcdcon2 = lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2); |
250a269d NF |
283 | value = xres; |
284 | if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) { | |
285 | /* STN display */ | |
286 | if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) { | |
287 | value *= 3; | |
288 | } | |
289 | if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4 | |
290 | || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8 | |
291 | && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL )) | |
292 | value = DIV_ROUND_UP(value, 4); | |
293 | else | |
294 | value = DIV_ROUND_UP(value, 8); | |
295 | } | |
296 | ||
297 | return value; | |
298 | } | |
14340586 | 299 | |
3aa04f1b HS |
300 | static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo) |
301 | { | |
302 | /* Turn off the LCD controller and the DMA controller */ | |
303 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, | |
304 | sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET); | |
305 | ||
306 | /* Wait for the LCDC core to become idle */ | |
307 | while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) | |
308 | msleep(10); | |
309 | ||
310 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0); | |
311 | } | |
312 | ||
313 | static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo) | |
314 | { | |
315 | atmel_lcdfb_stop_nowait(sinfo); | |
316 | ||
317 | /* Wait for DMA engine to become idle... */ | |
318 | while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY) | |
319 | msleep(10); | |
320 | } | |
321 | ||
322 | static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo) | |
323 | { | |
324 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon); | |
325 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, | |
326 | (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | |
327 | | ATMEL_LCDC_PWR); | |
328 | } | |
329 | ||
14340586 NF |
330 | static void atmel_lcdfb_update_dma(struct fb_info *info, |
331 | struct fb_var_screeninfo *var) | |
332 | { | |
333 | struct atmel_lcdfb_info *sinfo = info->par; | |
334 | struct fb_fix_screeninfo *fix = &info->fix; | |
335 | unsigned long dma_addr; | |
336 | ||
337 | dma_addr = (fix->smem_start + var->yoffset * fix->line_length | |
b3e9c129 | 338 | + var->xoffset * info->var.bits_per_pixel / 8); |
14340586 NF |
339 | |
340 | dma_addr &= ~3UL; | |
341 | ||
342 | /* Set framebuffer DMA base address and pixel offset */ | |
343 | lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr); | |
344 | ||
b3e9c129 | 345 | atmel_lcdfb_update_dma2d(sinfo, var, info); |
14340586 NF |
346 | } |
347 | ||
348 | static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo) | |
349 | { | |
350 | struct fb_info *info = sinfo->info; | |
351 | ||
352 | dma_free_writecombine(info->device, info->fix.smem_len, | |
353 | info->screen_base, info->fix.smem_start); | |
354 | } | |
355 | ||
356 | /** | |
357 | * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory | |
358 | * @sinfo: the frame buffer to allocate memory for | |
1d01e835 KH |
359 | * |
360 | * This function is called only from the atmel_lcdfb_probe() | |
361 | * so no locking by fb_info->mm_lock around smem_len setting is needed. | |
14340586 NF |
362 | */ |
363 | static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo) | |
364 | { | |
365 | struct fb_info *info = sinfo->info; | |
366 | struct fb_var_screeninfo *var = &info->var; | |
ea757aca | 367 | unsigned int smem_len; |
14340586 | 368 | |
ea757aca HS |
369 | smem_len = (var->xres_virtual * var->yres_virtual |
370 | * ((var->bits_per_pixel + 7) / 8)); | |
371 | info->fix.smem_len = max(smem_len, sinfo->smem_len); | |
14340586 NF |
372 | |
373 | info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len, | |
374 | (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL); | |
375 | ||
376 | if (!info->screen_base) { | |
377 | return -ENOMEM; | |
378 | } | |
379 | ||
01d3a5e7 HS |
380 | memset(info->screen_base, 0, info->fix.smem_len); |
381 | ||
14340586 NF |
382 | return 0; |
383 | } | |
384 | ||
968910bd NF |
385 | static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var, |
386 | struct fb_info *info) | |
387 | { | |
388 | struct fb_videomode varfbmode; | |
389 | const struct fb_videomode *fbmode = NULL; | |
390 | ||
391 | fb_var_to_videomode(&varfbmode, var); | |
392 | fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist); | |
393 | if (fbmode) | |
394 | fb_videomode_to_var(var, fbmode); | |
395 | return fbmode; | |
396 | } | |
397 | ||
398 | ||
14340586 NF |
399 | /** |
400 | * atmel_lcdfb_check_var - Validates a var passed in. | |
401 | * @var: frame buffer variable screen structure | |
402 | * @info: frame buffer structure that represents a single frame buffer | |
403 | * | |
404 | * Checks to see if the hardware supports the state requested by | |
405 | * var passed in. This function does not alter the hardware | |
406 | * state!!! This means the data stored in struct fb_info and | |
407 | * struct atmel_lcdfb_info do not change. This includes the var | |
408 | * inside of struct fb_info. Do NOT change these. This function | |
409 | * can be called on its own if we intent to only test a mode and | |
410 | * not actually set it. The stuff in modedb.c is a example of | |
411 | * this. If the var passed in is slightly off by what the | |
412 | * hardware can support then we alter the var PASSED in to what | |
413 | * we can do. If the hardware doesn't support mode change a | |
414 | * -EINVAL will be returned by the upper layers. You don't need | |
415 | * to implement this function then. If you hardware doesn't | |
416 | * support changing the resolution then this function is not | |
417 | * needed. In this case the driver would just provide a var that | |
418 | * represents the static state the screen is in. | |
419 | * | |
420 | * Returns negative errno on error, or zero on success. | |
421 | */ | |
422 | static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, | |
423 | struct fb_info *info) | |
424 | { | |
425 | struct device *dev = info->device; | |
426 | struct atmel_lcdfb_info *sinfo = info->par; | |
427 | unsigned long clk_value_khz; | |
428 | ||
429 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; | |
430 | ||
431 | dev_dbg(dev, "%s:\n", __func__); | |
968910bd NF |
432 | |
433 | if (!(var->pixclock && var->bits_per_pixel)) { | |
434 | /* choose a suitable mode if possible */ | |
435 | if (!atmel_lcdfb_choose_mode(var, info)) { | |
436 | dev_err(dev, "needed value not specified\n"); | |
437 | return -EINVAL; | |
438 | } | |
439 | } | |
440 | ||
14340586 NF |
441 | dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres); |
442 | dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock)); | |
443 | dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel); | |
444 | dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz); | |
445 | ||
97b9a5a2 | 446 | if (PICOS2KHZ(var->pixclock) > clk_value_khz) { |
14340586 NF |
447 | dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock)); |
448 | return -EINVAL; | |
449 | } | |
450 | ||
968910bd NF |
451 | /* Do not allow to have real resoulution larger than virtual */ |
452 | if (var->xres > var->xres_virtual) | |
453 | var->xres_virtual = var->xres; | |
454 | ||
455 | if (var->yres > var->yres_virtual) | |
456 | var->yres_virtual = var->yres; | |
457 | ||
14340586 NF |
458 | /* Force same alignment for each line */ |
459 | var->xres = (var->xres + 3) & ~3UL; | |
460 | var->xres_virtual = (var->xres_virtual + 3) & ~3UL; | |
461 | ||
462 | var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0; | |
463 | var->transp.msb_right = 0; | |
464 | var->transp.offset = var->transp.length = 0; | |
465 | var->xoffset = var->yoffset = 0; | |
466 | ||
f928ac0a SG |
467 | if (info->fix.smem_len) { |
468 | unsigned int smem_len = (var->xres_virtual * var->yres_virtual | |
469 | * ((var->bits_per_pixel + 7) / 8)); | |
65ac057b RG |
470 | if (smem_len > info->fix.smem_len) { |
471 | dev_err(dev, "Frame buffer is too small (%u) for screen size (need at least %u)\n", | |
472 | info->fix.smem_len, smem_len); | |
f928ac0a | 473 | return -EINVAL; |
65ac057b | 474 | } |
f928ac0a SG |
475 | } |
476 | ||
162b3a08 HS |
477 | /* Saturate vertical and horizontal timings at maximum values */ |
478 | var->vsync_len = min_t(u32, var->vsync_len, | |
479 | (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1); | |
480 | var->upper_margin = min_t(u32, var->upper_margin, | |
481 | ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET); | |
482 | var->lower_margin = min_t(u32, var->lower_margin, | |
483 | ATMEL_LCDC_VFP); | |
484 | var->right_margin = min_t(u32, var->right_margin, | |
6b3cbe40 | 485 | (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1); |
162b3a08 HS |
486 | var->hsync_len = min_t(u32, var->hsync_len, |
487 | (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1); | |
488 | var->left_margin = min_t(u32, var->left_margin, | |
489 | ATMEL_LCDC_HBP + 1); | |
490 | ||
491 | /* Some parameters can't be zero */ | |
492 | var->vsync_len = max_t(u32, var->vsync_len, 1); | |
493 | var->right_margin = max_t(u32, var->right_margin, 1); | |
494 | var->hsync_len = max_t(u32, var->hsync_len, 1); | |
495 | var->left_margin = max_t(u32, var->left_margin, 1); | |
496 | ||
14340586 | 497 | switch (var->bits_per_pixel) { |
250a269d | 498 | case 1: |
14340586 NF |
499 | case 2: |
500 | case 4: | |
501 | case 8: | |
502 | var->red.offset = var->green.offset = var->blue.offset = 0; | |
503 | var->red.length = var->green.length = var->blue.length | |
504 | = var->bits_per_pixel; | |
505 | break; | |
14340586 | 506 | case 16: |
a79eac71 | 507 | /* Older SOCs use IBGR:555 rather than BGR:565. */ |
bbd44f6b | 508 | if (sinfo->config->have_intensity_bit) |
a79eac71 JH |
509 | var->green.length = 5; |
510 | else | |
511 | var->green.length = 6; | |
512 | ||
fd085801 | 513 | if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { |
a79eac71 JH |
514 | /* RGB:5X5 mode */ |
515 | var->red.offset = var->green.length + 5; | |
fd085801 | 516 | var->blue.offset = 0; |
fd085801 | 517 | } else { |
a79eac71 | 518 | /* BGR:5X5 mode */ |
fd085801 | 519 | var->red.offset = 0; |
a79eac71 | 520 | var->blue.offset = var->green.length + 5; |
fd085801 | 521 | } |
14340586 | 522 | var->green.offset = 5; |
fd085801 | 523 | var->red.length = var->blue.length = 5; |
14340586 | 524 | break; |
14340586 | 525 | case 32: |
4440e0e1 HS |
526 | var->transp.offset = 24; |
527 | var->transp.length = 8; | |
528 | /* fall through */ | |
529 | case 24: | |
fd085801 NF |
530 | if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { |
531 | /* RGB:888 mode */ | |
532 | var->red.offset = 16; | |
533 | var->blue.offset = 0; | |
534 | } else { | |
535 | /* BGR:888 mode */ | |
536 | var->red.offset = 0; | |
537 | var->blue.offset = 16; | |
538 | } | |
14340586 | 539 | var->green.offset = 8; |
14340586 NF |
540 | var->red.length = var->green.length = var->blue.length = 8; |
541 | break; | |
542 | default: | |
543 | dev_err(dev, "color depth %d not supported\n", | |
544 | var->bits_per_pixel); | |
545 | return -EINVAL; | |
546 | } | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
d22579b8 NF |
551 | /* |
552 | * LCD reset sequence | |
553 | */ | |
554 | static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo) | |
555 | { | |
556 | might_sleep(); | |
557 | ||
3aa04f1b HS |
558 | atmel_lcdfb_stop(sinfo); |
559 | atmel_lcdfb_start(sinfo); | |
d22579b8 NF |
560 | } |
561 | ||
14340586 NF |
562 | /** |
563 | * atmel_lcdfb_set_par - Alters the hardware state. | |
564 | * @info: frame buffer structure that represents a single frame buffer | |
565 | * | |
566 | * Using the fb_var_screeninfo in fb_info we set the resolution | |
567 | * of the this particular framebuffer. This function alters the | |
568 | * par AND the fb_fix_screeninfo stored in fb_info. It doesn't | |
569 | * not alter var in fb_info since we are using that data. This | |
570 | * means we depend on the data in var inside fb_info to be | |
571 | * supported by the hardware. atmel_lcdfb_check_var is always called | |
572 | * before atmel_lcdfb_set_par to ensure this. Again if you can't | |
573 | * change the resolution you don't need this function. | |
574 | * | |
575 | */ | |
576 | static int atmel_lcdfb_set_par(struct fb_info *info) | |
577 | { | |
578 | struct atmel_lcdfb_info *sinfo = info->par; | |
250a269d | 579 | unsigned long hozval_linesz; |
14340586 NF |
580 | unsigned long value; |
581 | unsigned long clk_value_khz; | |
250a269d | 582 | unsigned long bits_per_line; |
431861cf | 583 | unsigned long pix_factor = 2; |
14340586 | 584 | |
d22579b8 NF |
585 | might_sleep(); |
586 | ||
14340586 NF |
587 | dev_dbg(info->device, "%s:\n", __func__); |
588 | dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n", | |
589 | info->var.xres, info->var.yres, | |
590 | info->var.xres_virtual, info->var.yres_virtual); | |
591 | ||
3aa04f1b | 592 | atmel_lcdfb_stop_nowait(sinfo); |
14340586 | 593 | |
250a269d NF |
594 | if (info->var.bits_per_pixel == 1) |
595 | info->fix.visual = FB_VISUAL_MONO01; | |
596 | else if (info->var.bits_per_pixel <= 8) | |
14340586 NF |
597 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
598 | else | |
599 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
600 | ||
250a269d NF |
601 | bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel; |
602 | info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8); | |
14340586 NF |
603 | |
604 | /* Re-initialize the DMA engine... */ | |
605 | dev_dbg(info->device, " * update DMA engine\n"); | |
606 | atmel_lcdfb_update_dma(info, &info->var); | |
607 | ||
608 | /* ...set frame size and burst length = 8 words (?) */ | |
609 | value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32; | |
610 | value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); | |
611 | lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value); | |
612 | ||
613 | /* Now, the LCDC core... */ | |
614 | ||
615 | /* Set pixel clock */ | |
bbd44f6b | 616 | if (sinfo->config->have_alt_pixclock) |
431861cf NF |
617 | pix_factor = 1; |
618 | ||
14340586 NF |
619 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; |
620 | ||
250a269d | 621 | value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock)); |
14340586 | 622 | |
431861cf | 623 | if (value < pix_factor) { |
14340586 NF |
624 | dev_notice(info->device, "Bypassing pixel clock divider\n"); |
625 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); | |
250a269d | 626 | } else { |
431861cf | 627 | value = (value / pix_factor) - 1; |
baf6332a NF |
628 | dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", |
629 | value); | |
630 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, | |
631 | value << ATMEL_LCDC_CLKVAL_OFFSET); | |
431861cf NF |
632 | info->var.pixclock = |
633 | KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1))); | |
250a269d NF |
634 | dev_dbg(info->device, " updated pixclk: %lu KHz\n", |
635 | PICOS2KHZ(info->var.pixclock)); | |
636 | } | |
637 | ||
14340586 NF |
638 | |
639 | /* Initialize control register 2 */ | |
640 | value = sinfo->default_lcdcon2; | |
641 | ||
642 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) | |
643 | value |= ATMEL_LCDC_INVLINE_INVERTED; | |
644 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) | |
645 | value |= ATMEL_LCDC_INVFRAME_INVERTED; | |
646 | ||
647 | switch (info->var.bits_per_pixel) { | |
648 | case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break; | |
649 | case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break; | |
650 | case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break; | |
651 | case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break; | |
652 | case 15: /* fall through */ | |
653 | case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break; | |
654 | case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break; | |
655 | case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break; | |
656 | default: BUG(); break; | |
657 | } | |
658 | dev_dbg(info->device, " * LCDCON2 = %08lx\n", value); | |
659 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value); | |
660 | ||
661 | /* Vertical timing */ | |
662 | value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET; | |
663 | value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET; | |
664 | value |= info->var.lower_margin; | |
665 | dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value); | |
666 | lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value); | |
667 | ||
668 | /* Horizontal timing */ | |
6b3cbe40 | 669 | value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET; |
14340586 NF |
670 | value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET; |
671 | value |= (info->var.left_margin - 1); | |
672 | dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value); | |
673 | lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value); | |
674 | ||
250a269d | 675 | /* Horizontal value (aka line size) */ |
934a50bd | 676 | hozval_linesz = compute_hozval(sinfo, info->var.xres); |
250a269d | 677 | |
14340586 | 678 | /* Display size */ |
250a269d | 679 | value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET; |
14340586 | 680 | value |= info->var.yres - 1; |
250a269d | 681 | dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value); |
14340586 NF |
682 | lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value); |
683 | ||
684 | /* FIFO Threshold: Use formula from data sheet */ | |
685 | value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); | |
686 | lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value); | |
687 | ||
688 | /* Toggle LCD_MODE every frame */ | |
689 | lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0); | |
690 | ||
691 | /* Disable all interrupts */ | |
692 | lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL); | |
d22579b8 NF |
693 | /* Enable FIFO & DMA errors */ |
694 | lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI); | |
14340586 | 695 | |
14340586 NF |
696 | /* ...wait for DMA engine to become idle... */ |
697 | while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY) | |
698 | msleep(10); | |
699 | ||
3aa04f1b | 700 | atmel_lcdfb_start(sinfo); |
14340586 NF |
701 | |
702 | dev_dbg(info->device, " * DONE\n"); | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
707 | static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf) | |
708 | { | |
709 | chan &= 0xffff; | |
710 | chan >>= 16 - bf->length; | |
711 | return chan << bf->offset; | |
712 | } | |
713 | ||
714 | /** | |
715 | * atmel_lcdfb_setcolreg - Optional function. Sets a color register. | |
716 | * @regno: Which register in the CLUT we are programming | |
717 | * @red: The red value which can be up to 16 bits wide | |
718 | * @green: The green value which can be up to 16 bits wide | |
719 | * @blue: The blue value which can be up to 16 bits wide. | |
720 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
721 | * @info: frame buffer info structure | |
722 | * | |
723 | * Set a single color register. The values supplied have a 16 bit | |
724 | * magnitude which needs to be scaled in this function for the hardware. | |
725 | * Things to take into consideration are how many color registers, if | |
726 | * any, are supported with the current color visual. With truecolor mode | |
25985edc | 727 | * no color palettes are supported. Here a pseudo palette is created |
14340586 NF |
728 | * which we store the value in pseudo_palette in struct fb_info. For |
729 | * pseudocolor mode we have a limited color palette. To deal with this | |
730 | * we can program what color is displayed for a particular pixel value. | |
731 | * DirectColor is similar in that we can program each color field. If | |
732 | * we have a static colormap we don't need to implement this function. | |
733 | * | |
734 | * Returns negative errno on error, or zero on success. In an | |
735 | * ideal world, this would have been the case, but as it turns | |
736 | * out, the other drivers return 1 on failure, so that's what | |
737 | * we're going to do. | |
738 | */ | |
739 | static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red, | |
740 | unsigned int green, unsigned int blue, | |
741 | unsigned int transp, struct fb_info *info) | |
742 | { | |
743 | struct atmel_lcdfb_info *sinfo = info->par; | |
744 | unsigned int val; | |
745 | u32 *pal; | |
746 | int ret = 1; | |
747 | ||
748 | if (info->var.grayscale) | |
749 | red = green = blue = (19595 * red + 38470 * green | |
750 | + 7471 * blue) >> 16; | |
751 | ||
752 | switch (info->fix.visual) { | |
753 | case FB_VISUAL_TRUECOLOR: | |
754 | if (regno < 16) { | |
755 | pal = info->pseudo_palette; | |
756 | ||
757 | val = chan_to_field(red, &info->var.red); | |
758 | val |= chan_to_field(green, &info->var.green); | |
759 | val |= chan_to_field(blue, &info->var.blue); | |
760 | ||
761 | pal[regno] = val; | |
762 | ret = 0; | |
763 | } | |
764 | break; | |
765 | ||
766 | case FB_VISUAL_PSEUDOCOLOR: | |
767 | if (regno < 256) { | |
bbd44f6b | 768 | if (sinfo->config->have_intensity_bit) { |
5d67b89c PK |
769 | /* old style I+BGR:555 */ |
770 | val = ((red >> 11) & 0x001f); | |
771 | val |= ((green >> 6) & 0x03e0); | |
772 | val |= ((blue >> 1) & 0x7c00); | |
773 | ||
774 | /* | |
775 | * TODO: intensity bit. Maybe something like | |
776 | * ~(red[10] ^ green[10] ^ blue[10]) & 1 | |
777 | */ | |
778 | } else { | |
779 | /* new style BGR:565 / RGB:565 */ | |
780 | if (sinfo->lcd_wiring_mode == | |
781 | ATMEL_LCDC_WIRING_RGB) { | |
782 | val = ((blue >> 11) & 0x001f); | |
783 | val |= ((red >> 0) & 0xf800); | |
784 | } else { | |
785 | val = ((red >> 11) & 0x001f); | |
786 | val |= ((blue >> 0) & 0xf800); | |
787 | } | |
788 | ||
789 | val |= ((green >> 5) & 0x07e0); | |
790 | } | |
14340586 NF |
791 | |
792 | lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val); | |
793 | ret = 0; | |
794 | } | |
795 | break; | |
250a269d NF |
796 | |
797 | case FB_VISUAL_MONO01: | |
798 | if (regno < 2) { | |
799 | val = (regno == 0) ? 0x00 : 0x1F; | |
800 | lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val); | |
801 | ret = 0; | |
802 | } | |
803 | break; | |
804 | ||
14340586 NF |
805 | } |
806 | ||
807 | return ret; | |
808 | } | |
809 | ||
810 | static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var, | |
811 | struct fb_info *info) | |
812 | { | |
813 | dev_dbg(info->device, "%s\n", __func__); | |
814 | ||
815 | atmel_lcdfb_update_dma(info, var); | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
bed7bddb AB |
820 | static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info) |
821 | { | |
822 | struct atmel_lcdfb_info *sinfo = info->par; | |
823 | ||
824 | switch (blank_mode) { | |
825 | case FB_BLANK_UNBLANK: | |
826 | case FB_BLANK_NORMAL: | |
827 | atmel_lcdfb_start(sinfo); | |
828 | break; | |
829 | case FB_BLANK_VSYNC_SUSPEND: | |
830 | case FB_BLANK_HSYNC_SUSPEND: | |
831 | break; | |
832 | case FB_BLANK_POWERDOWN: | |
833 | atmel_lcdfb_stop(sinfo); | |
834 | break; | |
835 | default: | |
836 | return -EINVAL; | |
837 | } | |
838 | ||
839 | /* let fbcon do a soft blank for us */ | |
840 | return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0); | |
841 | } | |
842 | ||
14340586 NF |
843 | static struct fb_ops atmel_lcdfb_ops = { |
844 | .owner = THIS_MODULE, | |
845 | .fb_check_var = atmel_lcdfb_check_var, | |
846 | .fb_set_par = atmel_lcdfb_set_par, | |
847 | .fb_setcolreg = atmel_lcdfb_setcolreg, | |
bed7bddb | 848 | .fb_blank = atmel_lcdfb_blank, |
14340586 NF |
849 | .fb_pan_display = atmel_lcdfb_pan_display, |
850 | .fb_fillrect = cfb_fillrect, | |
851 | .fb_copyarea = cfb_copyarea, | |
852 | .fb_imageblit = cfb_imageblit, | |
853 | }; | |
854 | ||
855 | static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id) | |
856 | { | |
857 | struct fb_info *info = dev_id; | |
858 | struct atmel_lcdfb_info *sinfo = info->par; | |
859 | u32 status; | |
860 | ||
861 | status = lcdc_readl(sinfo, ATMEL_LCDC_ISR); | |
d22579b8 NF |
862 | if (status & ATMEL_LCDC_UFLWI) { |
863 | dev_warn(info->device, "FIFO underflow %#x\n", status); | |
864 | /* reset DMA and FIFO to avoid screen shifting */ | |
865 | schedule_work(&sinfo->task); | |
866 | } | |
867 | lcdc_writel(sinfo, ATMEL_LCDC_ICR, status); | |
14340586 NF |
868 | return IRQ_HANDLED; |
869 | } | |
870 | ||
d22579b8 NF |
871 | /* |
872 | * LCD controller task (to reset the LCD) | |
873 | */ | |
874 | static void atmel_lcdfb_task(struct work_struct *work) | |
875 | { | |
876 | struct atmel_lcdfb_info *sinfo = | |
877 | container_of(work, struct atmel_lcdfb_info, task); | |
878 | ||
879 | atmel_lcdfb_reset(sinfo); | |
880 | } | |
881 | ||
14340586 NF |
882 | static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo) |
883 | { | |
884 | struct fb_info *info = sinfo->info; | |
885 | int ret = 0; | |
886 | ||
14340586 NF |
887 | info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW; |
888 | ||
889 | dev_info(info->device, | |
890 | "%luKiB frame buffer at %08lx (mapped at %p)\n", | |
891 | (unsigned long)info->fix.smem_len / 1024, | |
892 | (unsigned long)info->fix.smem_start, | |
893 | info->screen_base); | |
894 | ||
895 | /* Allocate colormap */ | |
896 | ret = fb_alloc_cmap(&info->cmap, 256, 0); | |
897 | if (ret < 0) | |
898 | dev_err(info->device, "Alloc color map failed\n"); | |
899 | ||
900 | return ret; | |
901 | } | |
902 | ||
903 | static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo) | |
904 | { | |
6e665fb3 BB |
905 | clk_prepare_enable(sinfo->bus_clk); |
906 | clk_prepare_enable(sinfo->lcdc_clk); | |
14340586 NF |
907 | } |
908 | ||
909 | static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo) | |
910 | { | |
6e665fb3 BB |
911 | clk_disable_unprepare(sinfo->bus_clk); |
912 | clk_disable_unprepare(sinfo->lcdc_clk); | |
14340586 NF |
913 | } |
914 | ||
915 | ||
916 | static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |
917 | { | |
918 | struct device *dev = &pdev->dev; | |
919 | struct fb_info *info; | |
920 | struct atmel_lcdfb_info *sinfo; | |
921 | struct atmel_lcdfb_info *pdata_sinfo; | |
968910bd | 922 | struct fb_videomode fbmode; |
14340586 NF |
923 | struct resource *regs = NULL; |
924 | struct resource *map = NULL; | |
925 | int ret; | |
926 | ||
927 | dev_dbg(dev, "%s BEGIN\n", __func__); | |
928 | ||
929 | ret = -ENOMEM; | |
930 | info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev); | |
931 | if (!info) { | |
932 | dev_err(dev, "cannot allocate memory\n"); | |
933 | goto out; | |
934 | } | |
935 | ||
936 | sinfo = info->par; | |
937 | ||
938 | if (dev->platform_data) { | |
939 | pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data; | |
940 | sinfo->default_bpp = pdata_sinfo->default_bpp; | |
941 | sinfo->default_dmacon = pdata_sinfo->default_dmacon; | |
942 | sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2; | |
943 | sinfo->default_monspecs = pdata_sinfo->default_monspecs; | |
944 | sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control; | |
945 | sinfo->guard_time = pdata_sinfo->guard_time; | |
ea757aca | 946 | sinfo->smem_len = pdata_sinfo->smem_len; |
a9a84c37 | 947 | sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight; |
7cdcdb69 | 948 | sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative; |
fd085801 | 949 | sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode; |
14340586 NF |
950 | } else { |
951 | dev_err(dev, "cannot get default configuration\n"); | |
952 | goto free_info; | |
953 | } | |
954 | sinfo->info = info; | |
955 | sinfo->pdev = pdev; | |
bbd44f6b JH |
956 | sinfo->config = atmel_lcdfb_get_config(pdev); |
957 | if (!sinfo->config) | |
958 | goto free_info; | |
14340586 NF |
959 | |
960 | strcpy(info->fix.id, sinfo->pdev->name); | |
961 | info->flags = ATMEL_LCDFB_FBINFO_DEFAULT; | |
962 | info->pseudo_palette = sinfo->pseudo_palette; | |
963 | info->fbops = &atmel_lcdfb_ops; | |
964 | ||
965 | memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs)); | |
966 | info->fix = atmel_lcdfb_fix; | |
967 | ||
968 | /* Enable LCDC Clocks */ | |
557b7d5d JH |
969 | sinfo->bus_clk = clk_get(dev, "hclk"); |
970 | if (IS_ERR(sinfo->bus_clk)) { | |
971 | ret = PTR_ERR(sinfo->bus_clk); | |
972 | goto free_info; | |
14340586 NF |
973 | } |
974 | sinfo->lcdc_clk = clk_get(dev, "lcdc_clk"); | |
975 | if (IS_ERR(sinfo->lcdc_clk)) { | |
976 | ret = PTR_ERR(sinfo->lcdc_clk); | |
977 | goto put_bus_clk; | |
978 | } | |
979 | atmel_lcdfb_start_clock(sinfo); | |
980 | ||
981 | ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb, | |
982 | info->monspecs.modedb_len, info->monspecs.modedb, | |
983 | sinfo->default_bpp); | |
984 | if (!ret) { | |
985 | dev_err(dev, "no suitable video mode found\n"); | |
986 | goto stop_clk; | |
987 | } | |
988 | ||
989 | ||
990 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
991 | if (!regs) { | |
992 | dev_err(dev, "resources unusable\n"); | |
993 | ret = -ENXIO; | |
994 | goto stop_clk; | |
995 | } | |
996 | ||
997 | sinfo->irq_base = platform_get_irq(pdev, 0); | |
998 | if (sinfo->irq_base < 0) { | |
999 | dev_err(dev, "unable to get irq\n"); | |
1000 | ret = sinfo->irq_base; | |
1001 | goto stop_clk; | |
1002 | } | |
1003 | ||
1004 | /* Initialize video memory */ | |
1005 | map = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1006 | if (map) { | |
1007 | /* use a pre-allocated memory buffer */ | |
1008 | info->fix.smem_start = map->start; | |
28f65c11 | 1009 | info->fix.smem_len = resource_size(map); |
14340586 NF |
1010 | if (!request_mem_region(info->fix.smem_start, |
1011 | info->fix.smem_len, pdev->name)) { | |
1012 | ret = -EBUSY; | |
1013 | goto stop_clk; | |
1014 | } | |
1015 | ||
1016 | info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); | |
130320bf PST |
1017 | if (!info->screen_base) { |
1018 | ret = -ENOMEM; | |
14340586 | 1019 | goto release_intmem; |
130320bf | 1020 | } |
01d3a5e7 HS |
1021 | |
1022 | /* | |
1023 | * Don't clear the framebuffer -- someone may have set | |
1024 | * up a splash image. | |
1025 | */ | |
14340586 | 1026 | } else { |
ff0c2642 | 1027 | /* allocate memory buffer */ |
14340586 NF |
1028 | ret = atmel_lcdfb_alloc_video_memory(sinfo); |
1029 | if (ret < 0) { | |
1030 | dev_err(dev, "cannot allocate framebuffer: %d\n", ret); | |
1031 | goto stop_clk; | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | /* LCDC registers */ | |
1036 | info->fix.mmio_start = regs->start; | |
28f65c11 | 1037 | info->fix.mmio_len = resource_size(regs); |
14340586 NF |
1038 | |
1039 | if (!request_mem_region(info->fix.mmio_start, | |
1040 | info->fix.mmio_len, pdev->name)) { | |
1041 | ret = -EBUSY; | |
1042 | goto free_fb; | |
1043 | } | |
1044 | ||
1045 | sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len); | |
1046 | if (!sinfo->mmio) { | |
1047 | dev_err(dev, "cannot map LCDC registers\n"); | |
130320bf | 1048 | ret = -ENOMEM; |
14340586 NF |
1049 | goto release_mem; |
1050 | } | |
1051 | ||
a9a84c37 DB |
1052 | /* Initialize PWM for contrast or backlight ("off") */ |
1053 | init_contrast(sinfo); | |
1054 | ||
14340586 NF |
1055 | /* interrupt */ |
1056 | ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info); | |
1057 | if (ret) { | |
1058 | dev_err(dev, "request_irq failed: %d\n", ret); | |
1059 | goto unmap_mmio; | |
1060 | } | |
1061 | ||
d22579b8 NF |
1062 | /* Some operations on the LCDC might sleep and |
1063 | * require a preemptible task context */ | |
1064 | INIT_WORK(&sinfo->task, atmel_lcdfb_task); | |
1065 | ||
14340586 NF |
1066 | ret = atmel_lcdfb_init_fbinfo(sinfo); |
1067 | if (ret < 0) { | |
1068 | dev_err(dev, "init fbinfo failed: %d\n", ret); | |
1069 | goto unregister_irqs; | |
1070 | } | |
1071 | ||
1072 | /* | |
1073 | * This makes sure that our colour bitfield | |
1074 | * descriptors are correctly initialised. | |
1075 | */ | |
1076 | atmel_lcdfb_check_var(&info->var, info); | |
1077 | ||
1078 | ret = fb_set_var(info, &info->var); | |
1079 | if (ret) { | |
1080 | dev_warn(dev, "unable to set display parameters\n"); | |
1081 | goto free_cmap; | |
1082 | } | |
1083 | ||
1084 | dev_set_drvdata(dev, info); | |
1085 | ||
1086 | /* | |
1087 | * Tell the world that we're ready to go | |
1088 | */ | |
1089 | ret = register_framebuffer(info); | |
1090 | if (ret < 0) { | |
1091 | dev_err(dev, "failed to register framebuffer device: %d\n", ret); | |
34a35bdd | 1092 | goto reset_drvdata; |
14340586 NF |
1093 | } |
1094 | ||
968910bd NF |
1095 | /* add selected videomode to modelist */ |
1096 | fb_var_to_videomode(&fbmode, &info->var); | |
1097 | fb_add_videomode(&fbmode, &info->modelist); | |
1098 | ||
14340586 NF |
1099 | /* Power up the LCDC screen */ |
1100 | if (sinfo->atmel_lcdfb_power_control) | |
1101 | sinfo->atmel_lcdfb_power_control(1); | |
1102 | ||
93f6ced9 | 1103 | dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n", |
14340586 NF |
1104 | info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base); |
1105 | ||
1106 | return 0; | |
1107 | ||
34a35bdd SG |
1108 | reset_drvdata: |
1109 | dev_set_drvdata(dev, NULL); | |
14340586 NF |
1110 | free_cmap: |
1111 | fb_dealloc_cmap(&info->cmap); | |
1112 | unregister_irqs: | |
d22579b8 | 1113 | cancel_work_sync(&sinfo->task); |
14340586 NF |
1114 | free_irq(sinfo->irq_base, info); |
1115 | unmap_mmio: | |
a9a84c37 | 1116 | exit_backlight(sinfo); |
14340586 NF |
1117 | iounmap(sinfo->mmio); |
1118 | release_mem: | |
1119 | release_mem_region(info->fix.mmio_start, info->fix.mmio_len); | |
1120 | free_fb: | |
1121 | if (map) | |
1122 | iounmap(info->screen_base); | |
1123 | else | |
1124 | atmel_lcdfb_free_video_memory(sinfo); | |
1125 | ||
1126 | release_intmem: | |
1127 | if (map) | |
1128 | release_mem_region(info->fix.smem_start, info->fix.smem_len); | |
1129 | stop_clk: | |
1130 | atmel_lcdfb_stop_clock(sinfo); | |
1131 | clk_put(sinfo->lcdc_clk); | |
1132 | put_bus_clk: | |
557b7d5d | 1133 | clk_put(sinfo->bus_clk); |
14340586 NF |
1134 | free_info: |
1135 | framebuffer_release(info); | |
1136 | out: | |
1137 | dev_dbg(dev, "%s FAILED\n", __func__); | |
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | static int __exit atmel_lcdfb_remove(struct platform_device *pdev) | |
1142 | { | |
1143 | struct device *dev = &pdev->dev; | |
1144 | struct fb_info *info = dev_get_drvdata(dev); | |
34a35bdd | 1145 | struct atmel_lcdfb_info *sinfo; |
14340586 | 1146 | |
34a35bdd | 1147 | if (!info || !info->par) |
14340586 | 1148 | return 0; |
34a35bdd | 1149 | sinfo = info->par; |
14340586 | 1150 | |
d22579b8 | 1151 | cancel_work_sync(&sinfo->task); |
a9a84c37 | 1152 | exit_backlight(sinfo); |
14340586 NF |
1153 | if (sinfo->atmel_lcdfb_power_control) |
1154 | sinfo->atmel_lcdfb_power_control(0); | |
1155 | unregister_framebuffer(info); | |
1156 | atmel_lcdfb_stop_clock(sinfo); | |
1157 | clk_put(sinfo->lcdc_clk); | |
557b7d5d | 1158 | clk_put(sinfo->bus_clk); |
14340586 NF |
1159 | fb_dealloc_cmap(&info->cmap); |
1160 | free_irq(sinfo->irq_base, info); | |
1161 | iounmap(sinfo->mmio); | |
1162 | release_mem_region(info->fix.mmio_start, info->fix.mmio_len); | |
1163 | if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) { | |
1164 | iounmap(info->screen_base); | |
1165 | release_mem_region(info->fix.smem_start, info->fix.smem_len); | |
1166 | } else { | |
1167 | atmel_lcdfb_free_video_memory(sinfo); | |
1168 | } | |
1169 | ||
1170 | dev_set_drvdata(dev, NULL); | |
1171 | framebuffer_release(info); | |
1172 | ||
1173 | return 0; | |
1174 | } | |
1175 | ||
cf19a37e DB |
1176 | #ifdef CONFIG_PM |
1177 | ||
1178 | static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg) | |
1179 | { | |
1180 | struct fb_info *info = platform_get_drvdata(pdev); | |
1181 | struct atmel_lcdfb_info *sinfo = info->par; | |
1182 | ||
3aa04f1b HS |
1183 | /* |
1184 | * We don't want to handle interrupts while the clock is | |
1185 | * stopped. It may take forever. | |
1186 | */ | |
1187 | lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL); | |
1188 | ||
9f106503 | 1189 | sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR); |
cf19a37e DB |
1190 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0); |
1191 | if (sinfo->atmel_lcdfb_power_control) | |
1192 | sinfo->atmel_lcdfb_power_control(0); | |
3aa04f1b HS |
1193 | |
1194 | atmel_lcdfb_stop(sinfo); | |
cf19a37e | 1195 | atmel_lcdfb_stop_clock(sinfo); |
3aa04f1b | 1196 | |
cf19a37e DB |
1197 | return 0; |
1198 | } | |
1199 | ||
1200 | static int atmel_lcdfb_resume(struct platform_device *pdev) | |
1201 | { | |
1202 | struct fb_info *info = platform_get_drvdata(pdev); | |
1203 | struct atmel_lcdfb_info *sinfo = info->par; | |
1204 | ||
1205 | atmel_lcdfb_start_clock(sinfo); | |
3aa04f1b | 1206 | atmel_lcdfb_start(sinfo); |
cf19a37e DB |
1207 | if (sinfo->atmel_lcdfb_power_control) |
1208 | sinfo->atmel_lcdfb_power_control(1); | |
1209 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon); | |
3aa04f1b HS |
1210 | |
1211 | /* Enable FIFO & DMA errors */ | |
1212 | lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | |
1213 | | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI); | |
1214 | ||
cf19a37e DB |
1215 | return 0; |
1216 | } | |
1217 | ||
1218 | #else | |
1219 | #define atmel_lcdfb_suspend NULL | |
1220 | #define atmel_lcdfb_resume NULL | |
1221 | #endif | |
1222 | ||
14340586 NF |
1223 | static struct platform_driver atmel_lcdfb_driver = { |
1224 | .remove = __exit_p(atmel_lcdfb_remove), | |
cf19a37e DB |
1225 | .suspend = atmel_lcdfb_suspend, |
1226 | .resume = atmel_lcdfb_resume, | |
bbd44f6b | 1227 | .id_table = atmel_lcdfb_devtypes, |
14340586 NF |
1228 | .driver = { |
1229 | .name = "atmel_lcdfb", | |
1230 | .owner = THIS_MODULE, | |
1231 | }, | |
1232 | }; | |
1233 | ||
3ccbf89f | 1234 | module_platform_driver_probe(atmel_lcdfb_driver, atmel_lcdfb_probe); |
14340586 NF |
1235 | |
1236 | MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver"); | |
8f4c79ce | 1237 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); |
14340586 | 1238 | MODULE_LICENSE("GPL"); |