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1da177e4 LT |
1 | /* |
2 | * drivers/video/aty/radeon_pm.c | |
3 | * | |
4 | * Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org> | |
5 | * Copyright 2004 Paul Mackerras <paulus@samba.org> | |
6 | * | |
7 | * This is the power management code for ATI radeon chipsets. It contains | |
8 | * some dynamic clock PM enable/disable code similar to what X.org does, | |
9 | * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs, | |
10 | * and the necessary bits to re-initialize from scratch a few chips found | |
11 | * on PowerMacs as well. The later could be extended to more platforms | |
12 | * provided the memory controller configuration code be made more generic, | |
13 | * and you can get the proper mode register commands for your RAMs. | |
14 | * Those things may be found in the BIOS image... | |
15 | */ | |
16 | ||
17 | #include "radeonfb.h" | |
18 | ||
19 | #include <linux/console.h> | |
20 | #include <linux/agp_backend.h> | |
21 | ||
22 | #ifdef CONFIG_PPC_PMAC | |
e8222502 | 23 | #include <asm/machdep.h> |
1da177e4 LT |
24 | #include <asm/prom.h> |
25 | #include <asm/pmac_feature.h> | |
26 | #endif | |
27 | ||
28 | #include "ati_ids.h" | |
29 | ||
994aad25 VB |
30 | static void radeon_reinitialize_M10(struct radeonfb_info *rinfo); |
31 | ||
32 | /* | |
33 | * Workarounds for bugs in PC laptops: | |
34 | * - enable D2 sleep in some IBM Thinkpads | |
35 | * - special case for Samsung P35 | |
36 | * | |
37 | * Whitelist by subsystem vendor/device because | |
38 | * its the subsystem vendor's fault! | |
39 | */ | |
40 | ||
41 | #if defined(CONFIG_PM) && defined(CONFIG_X86) | |
42 | struct radeon_device_id { | |
43 | const char *ident; /* (arbitrary) Name */ | |
44 | const unsigned short subsystem_vendor; /* Subsystem Vendor ID */ | |
45 | const unsigned short subsystem_device; /* Subsystem Device ID */ | |
46 | const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */ | |
47 | const reinit_function_ptr new_reinit_func; /* changed reinit_func */ | |
48 | }; | |
49 | ||
50 | #define BUGFIX(model, sv, sd, pm, fn) { \ | |
51 | .ident = model, \ | |
52 | .subsystem_vendor = sv, \ | |
53 | .subsystem_device = sd, \ | |
54 | .pm_mode_modifier = pm, \ | |
55 | .new_reinit_func = fn \ | |
56 | } | |
57 | ||
58 | static struct radeon_device_id radeon_workaround_list[] = { | |
59 | BUGFIX("IBM Thinkpad R32", | |
60 | PCI_VENDOR_ID_IBM, 0x1905, | |
61 | radeon_pm_d2, NULL), | |
62 | BUGFIX("IBM Thinkpad R40", | |
63 | PCI_VENDOR_ID_IBM, 0x0526, | |
64 | radeon_pm_d2, NULL), | |
65 | BUGFIX("IBM Thinkpad R40", | |
66 | PCI_VENDOR_ID_IBM, 0x0527, | |
67 | radeon_pm_d2, NULL), | |
68 | BUGFIX("IBM Thinkpad R50/R51/T40/T41", | |
69 | PCI_VENDOR_ID_IBM, 0x0531, | |
70 | radeon_pm_d2, NULL), | |
71 | BUGFIX("IBM Thinkpad R51/T40/T41/T42", | |
72 | PCI_VENDOR_ID_IBM, 0x0530, | |
73 | radeon_pm_d2, NULL), | |
74 | BUGFIX("IBM Thinkpad T30", | |
75 | PCI_VENDOR_ID_IBM, 0x0517, | |
76 | radeon_pm_d2, NULL), | |
77 | BUGFIX("IBM Thinkpad T40p", | |
78 | PCI_VENDOR_ID_IBM, 0x054d, | |
79 | radeon_pm_d2, NULL), | |
80 | BUGFIX("IBM Thinkpad T42", | |
81 | PCI_VENDOR_ID_IBM, 0x0550, | |
82 | radeon_pm_d2, NULL), | |
83 | BUGFIX("IBM Thinkpad X31/X32", | |
84 | PCI_VENDOR_ID_IBM, 0x052f, | |
85 | radeon_pm_d2, NULL), | |
86 | BUGFIX("Samsung P35", | |
87 | PCI_VENDOR_ID_SAMSUNG, 0xc00c, | |
88 | radeon_pm_off, radeon_reinitialize_M10), | |
f5b747b4 CDH |
89 | BUGFIX("Acer Aspire 2010", |
90 | PCI_VENDOR_ID_AI, 0x0061, | |
91 | radeon_pm_off, radeon_reinitialize_M10), | |
994aad25 VB |
92 | { .ident = NULL } |
93 | }; | |
94 | ||
95 | static int radeon_apply_workarounds(struct radeonfb_info *rinfo) | |
96 | { | |
97 | struct radeon_device_id *id; | |
98 | ||
99 | for (id = radeon_workaround_list; id->ident != NULL; id++ ) | |
100 | if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) && | |
101 | (id->subsystem_device == rinfo->pdev->subsystem_device )) { | |
102 | ||
103 | /* we found a device that requires workaround */ | |
104 | printk(KERN_DEBUG "radeonfb: %s detected" | |
105 | ", enabling workaround\n", id->ident); | |
106 | ||
107 | rinfo->pm_mode |= id->pm_mode_modifier; | |
108 | ||
109 | if (id->new_reinit_func != NULL) | |
110 | rinfo->reinit_func = id->new_reinit_func; | |
111 | ||
112 | return 1; | |
113 | } | |
114 | return 0; /* not found */ | |
115 | } | |
116 | ||
117 | #else /* defined(CONFIG_PM) && defined(CONFIG_X86) */ | |
118 | static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo) | |
119 | { | |
120 | return 0; | |
121 | } | |
122 | #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */ | |
123 | ||
124 | ||
125 | ||
1da177e4 LT |
126 | static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo) |
127 | { | |
128 | u32 tmp; | |
129 | ||
130 | /* RV100 */ | |
131 | if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) { | |
132 | if (rinfo->has_CRTC2) { | |
133 | tmp = INPLL(pllSCLK_CNTL); | |
134 | tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK; | |
135 | tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK; | |
136 | OUTPLL(pllSCLK_CNTL, tmp); | |
137 | } | |
138 | tmp = INPLL(pllMCLK_CNTL); | |
139 | tmp |= (MCLK_CNTL__FORCE_MCLKA | | |
140 | MCLK_CNTL__FORCE_MCLKB | | |
141 | MCLK_CNTL__FORCE_YCLKA | | |
142 | MCLK_CNTL__FORCE_YCLKB | | |
143 | MCLK_CNTL__FORCE_AIC | | |
144 | MCLK_CNTL__FORCE_MC); | |
145 | OUTPLL(pllMCLK_CNTL, tmp); | |
146 | return; | |
147 | } | |
148 | /* R100 */ | |
149 | if (!rinfo->has_CRTC2) { | |
150 | tmp = INPLL(pllSCLK_CNTL); | |
151 | tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP | | |
152 | SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP | | |
153 | SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE | | |
154 | SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP | | |
155 | SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB | | |
156 | SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM | | |
157 | SCLK_CNTL__FORCE_RB); | |
158 | OUTPLL(pllSCLK_CNTL, tmp); | |
159 | return; | |
160 | } | |
14bfd1ff | 161 | /* RV350 (M10/M11) */ |
1da177e4 | 162 | if (rinfo->family == CHIP_FAMILY_RV350) { |
14bfd1ff | 163 | /* for RV350/M10/M11, no delays are required. */ |
1da177e4 LT |
164 | tmp = INPLL(pllSCLK_CNTL2); |
165 | tmp |= (SCLK_CNTL2__R300_FORCE_TCL | | |
166 | SCLK_CNTL2__R300_FORCE_GA | | |
167 | SCLK_CNTL2__R300_FORCE_CBA); | |
168 | OUTPLL(pllSCLK_CNTL2, tmp); | |
169 | ||
170 | tmp = INPLL(pllSCLK_CNTL); | |
171 | tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | | |
172 | SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | | |
173 | SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 | | |
174 | SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT | | |
175 | SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR | | |
176 | SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX | | |
177 | SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK | | |
178 | SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0); | |
179 | OUTPLL(pllSCLK_CNTL, tmp); | |
180 | ||
181 | tmp = INPLL(pllSCLK_MORE_CNTL); | |
182 | tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI | | |
183 | SCLK_MORE_CNTL__FORCE_MC_HOST); | |
184 | OUTPLL(pllSCLK_MORE_CNTL, tmp); | |
185 | ||
186 | tmp = INPLL(pllMCLK_CNTL); | |
187 | tmp |= (MCLK_CNTL__FORCE_MCLKA | | |
188 | MCLK_CNTL__FORCE_MCLKB | | |
189 | MCLK_CNTL__FORCE_YCLKA | | |
190 | MCLK_CNTL__FORCE_YCLKB | | |
191 | MCLK_CNTL__FORCE_MC); | |
192 | OUTPLL(pllMCLK_CNTL, tmp); | |
193 | ||
194 | tmp = INPLL(pllVCLK_ECP_CNTL); | |
195 | tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | | |
196 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb | | |
197 | VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); | |
198 | OUTPLL(pllVCLK_ECP_CNTL, tmp); | |
199 | ||
200 | tmp = INPLL(pllPIXCLKS_CNTL); | |
201 | tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | | |
202 | PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb | | |
203 | PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | | |
204 | PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb | | |
205 | PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb | | |
206 | PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | | |
207 | PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb | | |
208 | PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb | | |
209 | PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb | | |
210 | PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb | | |
211 | PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb | | |
212 | PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb | | |
213 | PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb | | |
214 | PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); | |
215 | OUTPLL(pllPIXCLKS_CNTL, tmp); | |
216 | ||
217 | return; | |
218 | } | |
219 | ||
220 | /* Default */ | |
221 | ||
222 | /* Force Core Clocks */ | |
223 | tmp = INPLL(pllSCLK_CNTL); | |
224 | tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2); | |
225 | ||
226 | /* XFree doesn't do that case, but we had this code from Apple and it | |
227 | * seem necessary for proper suspend/resume operations | |
228 | */ | |
229 | if (rinfo->is_mobility) { | |
230 | tmp |= SCLK_CNTL__FORCE_HDP| | |
231 | SCLK_CNTL__FORCE_DISP1| | |
232 | SCLK_CNTL__FORCE_DISP2| | |
233 | SCLK_CNTL__FORCE_TOP| | |
234 | SCLK_CNTL__FORCE_SE| | |
235 | SCLK_CNTL__FORCE_IDCT| | |
236 | SCLK_CNTL__FORCE_VIP| | |
237 | SCLK_CNTL__FORCE_PB| | |
238 | SCLK_CNTL__FORCE_RE| | |
239 | SCLK_CNTL__FORCE_TAM| | |
240 | SCLK_CNTL__FORCE_TDM| | |
241 | SCLK_CNTL__FORCE_RB| | |
242 | SCLK_CNTL__FORCE_TV_SCLK| | |
243 | SCLK_CNTL__FORCE_SUBPIC| | |
244 | SCLK_CNTL__FORCE_OV0; | |
245 | } | |
246 | else if (rinfo->family == CHIP_FAMILY_R300 || | |
247 | rinfo->family == CHIP_FAMILY_R350) { | |
248 | tmp |= SCLK_CNTL__FORCE_HDP | | |
249 | SCLK_CNTL__FORCE_DISP1 | | |
250 | SCLK_CNTL__FORCE_DISP2 | | |
251 | SCLK_CNTL__FORCE_TOP | | |
252 | SCLK_CNTL__FORCE_IDCT | | |
253 | SCLK_CNTL__FORCE_VIP; | |
254 | } | |
255 | OUTPLL(pllSCLK_CNTL, tmp); | |
256 | radeon_msleep(16); | |
257 | ||
258 | if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) { | |
259 | tmp = INPLL(pllSCLK_CNTL2); | |
260 | tmp |= SCLK_CNTL2__R300_FORCE_TCL | | |
261 | SCLK_CNTL2__R300_FORCE_GA | | |
262 | SCLK_CNTL2__R300_FORCE_CBA; | |
263 | OUTPLL(pllSCLK_CNTL2, tmp); | |
264 | radeon_msleep(16); | |
265 | } | |
266 | ||
267 | tmp = INPLL(pllCLK_PIN_CNTL); | |
268 | tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL; | |
269 | OUTPLL(pllCLK_PIN_CNTL, tmp); | |
270 | radeon_msleep(15); | |
271 | ||
272 | if (rinfo->is_IGP) { | |
273 | /* Weird ... X is _un_ forcing clocks here, I think it's | |
274 | * doing backward. Imitate it for now... | |
275 | */ | |
276 | tmp = INPLL(pllMCLK_CNTL); | |
277 | tmp &= ~(MCLK_CNTL__FORCE_MCLKA | | |
278 | MCLK_CNTL__FORCE_YCLKA); | |
279 | OUTPLL(pllMCLK_CNTL, tmp); | |
280 | radeon_msleep(16); | |
281 | } | |
282 | /* Hrm... same shit, X doesn't do that but I have to */ | |
283 | else if (rinfo->is_mobility) { | |
284 | tmp = INPLL(pllMCLK_CNTL); | |
285 | tmp |= (MCLK_CNTL__FORCE_MCLKA | | |
286 | MCLK_CNTL__FORCE_MCLKB | | |
287 | MCLK_CNTL__FORCE_YCLKA | | |
288 | MCLK_CNTL__FORCE_YCLKB); | |
289 | OUTPLL(pllMCLK_CNTL, tmp); | |
290 | radeon_msleep(16); | |
291 | ||
292 | tmp = INPLL(pllMCLK_MISC); | |
293 | tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| | |
294 | MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT| | |
295 | MCLK_MISC__MC_MCLK_DYN_ENABLE| | |
296 | MCLK_MISC__IO_MCLK_DYN_ENABLE); | |
297 | OUTPLL(pllMCLK_MISC, tmp); | |
298 | radeon_msleep(15); | |
299 | } | |
300 | ||
301 | if (rinfo->is_mobility) { | |
302 | tmp = INPLL(pllSCLK_MORE_CNTL); | |
303 | tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS| | |
304 | SCLK_MORE_CNTL__FORCE_MC_GUI| | |
305 | SCLK_MORE_CNTL__FORCE_MC_HOST; | |
306 | OUTPLL(pllSCLK_MORE_CNTL, tmp); | |
307 | radeon_msleep(16); | |
308 | } | |
309 | ||
310 | tmp = INPLL(pllPIXCLKS_CNTL); | |
311 | tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | | |
312 | PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb| | |
313 | PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb | | |
314 | PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb| | |
315 | PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb| | |
316 | PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb| | |
317 | PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb); | |
318 | OUTPLL(pllPIXCLKS_CNTL, tmp); | |
319 | radeon_msleep(16); | |
320 | ||
321 | tmp = INPLL( pllVCLK_ECP_CNTL); | |
322 | tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | | |
323 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb); | |
324 | OUTPLL( pllVCLK_ECP_CNTL, tmp); | |
325 | radeon_msleep(16); | |
326 | } | |
327 | ||
328 | static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo) | |
329 | { | |
330 | u32 tmp; | |
331 | ||
332 | /* R100 */ | |
333 | if (!rinfo->has_CRTC2) { | |
334 | tmp = INPLL(pllSCLK_CNTL); | |
335 | ||
336 | if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13) | |
337 | tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB); | |
338 | tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | | |
339 | SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE | | |
340 | SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE | | |
341 | SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM | | |
342 | SCLK_CNTL__FORCE_TDM); | |
343 | OUTPLL(pllSCLK_CNTL, tmp); | |
344 | return; | |
345 | } | |
346 | ||
14bfd1ff | 347 | /* M10/M11 */ |
1da177e4 LT |
348 | if (rinfo->family == CHIP_FAMILY_RV350) { |
349 | tmp = INPLL(pllSCLK_CNTL2); | |
350 | tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | | |
351 | SCLK_CNTL2__R300_FORCE_GA | | |
352 | SCLK_CNTL2__R300_FORCE_CBA); | |
353 | tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT | | |
354 | SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT | | |
355 | SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT); | |
356 | OUTPLL(pllSCLK_CNTL2, tmp); | |
357 | ||
358 | tmp = INPLL(pllSCLK_CNTL); | |
359 | tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | | |
360 | SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | | |
361 | SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 | | |
362 | SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT | | |
363 | SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR | | |
364 | SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX | | |
365 | SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK | | |
366 | SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0); | |
367 | tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK; | |
368 | OUTPLL(pllSCLK_CNTL, tmp); | |
369 | ||
370 | tmp = INPLL(pllSCLK_MORE_CNTL); | |
371 | tmp &= ~SCLK_MORE_CNTL__FORCEON; | |
372 | tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT | | |
373 | SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT | | |
374 | SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT; | |
375 | OUTPLL(pllSCLK_MORE_CNTL, tmp); | |
376 | ||
377 | tmp = INPLL(pllVCLK_ECP_CNTL); | |
378 | tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | | |
379 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb); | |
380 | OUTPLL(pllVCLK_ECP_CNTL, tmp); | |
381 | ||
382 | tmp = INPLL(pllPIXCLKS_CNTL); | |
383 | tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | | |
384 | PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb | | |
385 | PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | | |
386 | PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb | | |
387 | PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb | | |
388 | PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | | |
389 | PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb | | |
390 | PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb | | |
391 | PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb | | |
392 | PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb | | |
393 | PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb | | |
394 | PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb | | |
395 | PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb); | |
396 | OUTPLL(pllPIXCLKS_CNTL, tmp); | |
397 | ||
398 | tmp = INPLL(pllMCLK_MISC); | |
399 | tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE | | |
400 | MCLK_MISC__IO_MCLK_DYN_ENABLE); | |
401 | OUTPLL(pllMCLK_MISC, tmp); | |
402 | ||
403 | tmp = INPLL(pllMCLK_CNTL); | |
404 | tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB); | |
405 | tmp &= ~(MCLK_CNTL__FORCE_YCLKA | | |
406 | MCLK_CNTL__FORCE_YCLKB | | |
407 | MCLK_CNTL__FORCE_MC); | |
408 | ||
409 | /* Some releases of vbios have set DISABLE_MC_MCLKA | |
410 | * and DISABLE_MC_MCLKB bits in the vbios table. Setting these | |
411 | * bits will cause H/W hang when reading video memory with dynamic | |
412 | * clocking enabled. | |
413 | */ | |
414 | if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) && | |
415 | (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) { | |
416 | /* If both bits are set, then check the active channels */ | |
417 | tmp = INPLL(pllMCLK_CNTL); | |
418 | if (rinfo->vram_width == 64) { | |
419 | if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) | |
420 | tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB; | |
421 | else | |
422 | tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA; | |
423 | } else { | |
424 | tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA | | |
425 | MCLK_CNTL__R300_DISABLE_MC_MCLKB); | |
426 | } | |
427 | } | |
428 | OUTPLL(pllMCLK_CNTL, tmp); | |
429 | return; | |
430 | } | |
431 | ||
432 | /* R300 */ | |
433 | if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) { | |
434 | tmp = INPLL(pllSCLK_CNTL); | |
435 | tmp &= ~(SCLK_CNTL__R300_FORCE_VAP); | |
436 | tmp |= SCLK_CNTL__FORCE_CP; | |
437 | OUTPLL(pllSCLK_CNTL, tmp); | |
438 | radeon_msleep(15); | |
439 | ||
440 | tmp = INPLL(pllSCLK_CNTL2); | |
441 | tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | | |
442 | SCLK_CNTL2__R300_FORCE_GA | | |
443 | SCLK_CNTL2__R300_FORCE_CBA); | |
444 | OUTPLL(pllSCLK_CNTL2, tmp); | |
445 | } | |
446 | ||
447 | /* Others */ | |
448 | ||
449 | tmp = INPLL( pllCLK_PWRMGT_CNTL); | |
450 | tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK| | |
451 | CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK| | |
452 | CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK); | |
453 | tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK | | |
454 | (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT); | |
455 | OUTPLL( pllCLK_PWRMGT_CNTL, tmp); | |
456 | radeon_msleep(15); | |
457 | ||
458 | tmp = INPLL(pllCLK_PIN_CNTL); | |
459 | tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL; | |
460 | OUTPLL(pllCLK_PIN_CNTL, tmp); | |
461 | radeon_msleep(15); | |
462 | ||
463 | /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 | |
464 | * to lockup randomly, leave them as set by BIOS. | |
465 | */ | |
466 | tmp = INPLL(pllSCLK_CNTL); | |
467 | tmp &= ~SCLK_CNTL__FORCEON_MASK; | |
468 | ||
469 | /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/ | |
470 | if ((rinfo->family == CHIP_FAMILY_RV250 && | |
471 | ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) || | |
472 | ((rinfo->family == CHIP_FAMILY_RV100) && | |
473 | ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) { | |
474 | tmp |= SCLK_CNTL__FORCE_CP; | |
475 | tmp |= SCLK_CNTL__FORCE_VIP; | |
476 | } | |
477 | OUTPLL(pllSCLK_CNTL, tmp); | |
478 | radeon_msleep(15); | |
479 | ||
480 | if ((rinfo->family == CHIP_FAMILY_RV200) || | |
481 | (rinfo->family == CHIP_FAMILY_RV250) || | |
482 | (rinfo->family == CHIP_FAMILY_RV280)) { | |
483 | tmp = INPLL(pllSCLK_MORE_CNTL); | |
484 | tmp &= ~SCLK_MORE_CNTL__FORCEON; | |
485 | ||
486 | /* RV200::A11 A12 RV250::A11 A12 */ | |
487 | if (((rinfo->family == CHIP_FAMILY_RV200) || | |
488 | (rinfo->family == CHIP_FAMILY_RV250)) && | |
489 | ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) | |
490 | tmp |= SCLK_MORE_CNTL__FORCEON; | |
491 | ||
492 | OUTPLL(pllSCLK_MORE_CNTL, tmp); | |
493 | radeon_msleep(15); | |
494 | } | |
495 | ||
496 | ||
497 | /* RV200::A11 A12, RV250::A11 A12 */ | |
498 | if (((rinfo->family == CHIP_FAMILY_RV200) || | |
499 | (rinfo->family == CHIP_FAMILY_RV250)) && | |
500 | ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) { | |
501 | tmp = INPLL(pllPLL_PWRMGT_CNTL); | |
502 | tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE; | |
503 | OUTPLL(pllPLL_PWRMGT_CNTL, tmp); | |
504 | radeon_msleep(15); | |
505 | } | |
506 | ||
507 | tmp = INPLL(pllPIXCLKS_CNTL); | |
508 | tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | | |
509 | PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb| | |
510 | PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb| | |
511 | PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb| | |
512 | PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb| | |
513 | PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb| | |
514 | PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb; | |
515 | OUTPLL(pllPIXCLKS_CNTL, tmp); | |
516 | radeon_msleep(15); | |
517 | ||
518 | tmp = INPLL(pllVCLK_ECP_CNTL); | |
519 | tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | | |
520 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb; | |
521 | OUTPLL(pllVCLK_ECP_CNTL, tmp); | |
522 | ||
523 | /* X doesn't do that ... hrm, we do on mobility && Macs */ | |
524 | #ifdef CONFIG_PPC_OF | |
525 | if (rinfo->is_mobility) { | |
526 | tmp = INPLL(pllMCLK_CNTL); | |
527 | tmp &= ~(MCLK_CNTL__FORCE_MCLKA | | |
528 | MCLK_CNTL__FORCE_MCLKB | | |
529 | MCLK_CNTL__FORCE_YCLKA | | |
530 | MCLK_CNTL__FORCE_YCLKB); | |
531 | OUTPLL(pllMCLK_CNTL, tmp); | |
532 | radeon_msleep(15); | |
533 | ||
534 | tmp = INPLL(pllMCLK_MISC); | |
535 | tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| | |
536 | MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT| | |
537 | MCLK_MISC__MC_MCLK_DYN_ENABLE| | |
538 | MCLK_MISC__IO_MCLK_DYN_ENABLE; | |
539 | OUTPLL(pllMCLK_MISC, tmp); | |
540 | radeon_msleep(15); | |
541 | } | |
542 | #endif /* CONFIG_PPC_OF */ | |
543 | } | |
544 | ||
545 | #ifdef CONFIG_PM | |
546 | ||
547 | static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value) | |
548 | { | |
549 | OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN); | |
550 | OUTREG( MC_IND_DATA, value); | |
551 | } | |
552 | ||
553 | static u32 INMC(struct radeonfb_info *rinfo, u8 indx) | |
554 | { | |
555 | OUTREG( MC_IND_INDEX, indx); | |
556 | return INREG( MC_IND_DATA); | |
557 | } | |
558 | ||
559 | static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3) | |
560 | { | |
561 | rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL); | |
562 | rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL); | |
563 | rinfo->save_regs[2] = INPLL(MCLK_CNTL); | |
564 | rinfo->save_regs[3] = INPLL(SCLK_CNTL); | |
565 | rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL); | |
566 | rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL); | |
567 | rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL); | |
568 | rinfo->save_regs[7] = INPLL(MCLK_MISC); | |
569 | rinfo->save_regs[8] = INPLL(P2PLL_CNTL); | |
570 | ||
571 | rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); | |
572 | rinfo->save_regs[10] = INREG(DISP_PWR_MAN); | |
573 | rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); | |
574 | rinfo->save_regs[13] = INREG(TV_DAC_CNTL); | |
575 | rinfo->save_regs[14] = INREG(BUS_CNTL1); | |
576 | rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL); | |
577 | rinfo->save_regs[16] = INREG(AGP_CNTL); | |
578 | rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000; | |
579 | rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000; | |
580 | rinfo->save_regs[19] = INREG(GPIOPAD_A); | |
581 | rinfo->save_regs[20] = INREG(GPIOPAD_EN); | |
582 | rinfo->save_regs[21] = INREG(GPIOPAD_MASK); | |
583 | rinfo->save_regs[22] = INREG(ZV_LCDPAD_A); | |
584 | rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN); | |
585 | rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK); | |
586 | rinfo->save_regs[25] = INREG(GPIO_VGA_DDC); | |
587 | rinfo->save_regs[26] = INREG(GPIO_DVI_DDC); | |
588 | rinfo->save_regs[27] = INREG(GPIO_MONID); | |
589 | rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC); | |
590 | ||
591 | rinfo->save_regs[29] = INREG(SURFACE_CNTL); | |
592 | rinfo->save_regs[30] = INREG(MC_FB_LOCATION); | |
593 | rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR); | |
594 | rinfo->save_regs[32] = INREG(MC_AGP_LOCATION); | |
595 | rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR); | |
596 | ||
597 | rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL); | |
598 | rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG); | |
599 | rinfo->save_regs[36] = INREG(BUS_CNTL); | |
600 | rinfo->save_regs[39] = INREG(RBBM_CNTL); | |
601 | rinfo->save_regs[40] = INREG(DAC_CNTL); | |
602 | rinfo->save_regs[41] = INREG(HOST_PATH_CNTL); | |
603 | rinfo->save_regs[37] = INREG(MPP_TB_CONFIG); | |
604 | rinfo->save_regs[38] = INREG(FCP_CNTL); | |
605 | ||
606 | if (rinfo->is_mobility) { | |
607 | rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL); | |
608 | rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL); | |
609 | rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV); | |
610 | rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0); | |
611 | rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL); | |
612 | rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL); | |
613 | rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL); | |
614 | } | |
615 | ||
616 | if (rinfo->family >= CHIP_FAMILY_RV200) { | |
617 | rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL); | |
618 | rinfo->save_regs[46] = INREG(MC_CNTL); | |
619 | rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER); | |
620 | rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER); | |
621 | rinfo->save_regs[49] = INREG(MC_TIMING_CNTL); | |
622 | rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB); | |
623 | rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL); | |
624 | rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB); | |
625 | rinfo->save_regs[53] = INREG(MC_DEBUG); | |
626 | } | |
627 | rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL); | |
628 | rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL); | |
629 | rinfo->save_regs[56] = INREG(PAD_CTLR_MISC); | |
630 | rinfo->save_regs[57] = INREG(FW_CNTL); | |
631 | ||
632 | if (rinfo->family >= CHIP_FAMILY_R300) { | |
633 | rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER); | |
634 | rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL); | |
635 | rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0); | |
636 | rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1); | |
637 | rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0); | |
638 | rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1); | |
639 | rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3); | |
640 | rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0); | |
641 | rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1); | |
642 | rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0); | |
643 | rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1); | |
644 | rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL); | |
645 | rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL); | |
646 | rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0); | |
647 | rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL); | |
648 | rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD); | |
649 | } else { | |
650 | rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL); | |
651 | rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0); | |
652 | rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1); | |
653 | rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0); | |
654 | rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1); | |
655 | rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0); | |
656 | } | |
657 | ||
658 | rinfo->save_regs[73] = INPLL(pllMPLL_CNTL); | |
659 | rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); | |
660 | rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL); | |
661 | rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL); | |
662 | rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV); | |
663 | rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL); | |
664 | rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL); | |
665 | ||
666 | rinfo->save_regs[80] = INREG(OV0_BASE_ADDR); | |
667 | rinfo->save_regs[82] = INREG(FP_GEN_CNTL); | |
668 | rinfo->save_regs[83] = INREG(FP2_GEN_CNTL); | |
669 | rinfo->save_regs[84] = INREG(TMDS_CNTL); | |
670 | rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL); | |
671 | rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL); | |
672 | rinfo->save_regs[87] = INREG(DISP_HW_DEBUG); | |
673 | rinfo->save_regs[88] = INREG(TV_MASTER_CNTL); | |
674 | rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV); | |
675 | rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0); | |
676 | rinfo->save_regs[93] = INPLL(pllPPLL_CNTL); | |
677 | rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL); | |
678 | rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL); | |
679 | rinfo->save_regs[96] = INREG(HDP_DEBUG); | |
680 | rinfo->save_regs[97] = INPLL(pllMDLL_CKO); | |
681 | rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA); | |
682 | rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB); | |
683 | } | |
684 | ||
685 | static void radeon_pm_restore_regs(struct radeonfb_info *rinfo) | |
686 | { | |
687 | OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */ | |
688 | ||
689 | OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]); | |
690 | OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]); | |
691 | OUTPLL(MCLK_CNTL, rinfo->save_regs[2]); | |
692 | OUTPLL(SCLK_CNTL, rinfo->save_regs[3]); | |
693 | OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]); | |
694 | OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]); | |
695 | OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]); | |
696 | OUTPLL(MCLK_MISC, rinfo->save_regs[7]); | |
697 | if (rinfo->family == CHIP_FAMILY_RV350) | |
698 | OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]); | |
699 | ||
700 | OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); | |
701 | OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); | |
702 | OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); | |
703 | OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); | |
704 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); | |
705 | OUTREG(CONFIG_MEMSIZE, rinfo->video_ram); | |
706 | ||
707 | OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); | |
708 | OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]); | |
709 | OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]); | |
710 | OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]); | |
711 | OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]); | |
712 | OUTREG(BUS_CNTL1, rinfo->save_regs[14]); | |
713 | OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]); | |
714 | OUTREG(AGP_CNTL, rinfo->save_regs[16]); | |
715 | OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]); | |
716 | OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]); | |
717 | OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]); | |
718 | ||
719 | OUTREG(GPIOPAD_A, rinfo->save_regs[19]); | |
720 | OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); | |
721 | OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); | |
722 | OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]); | |
723 | OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]); | |
724 | OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]); | |
725 | OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]); | |
726 | OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]); | |
727 | OUTREG(GPIO_MONID, rinfo->save_regs[27]); | |
728 | OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]); | |
729 | } | |
730 | ||
731 | static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo) | |
732 | { | |
733 | OUTREG(GPIOPAD_MASK, 0x0001ffff); | |
734 | OUTREG(GPIOPAD_EN, 0x00000400); | |
735 | OUTREG(GPIOPAD_A, 0x00000000); | |
736 | OUTREG(ZV_LCDPAD_MASK, 0x00000000); | |
737 | OUTREG(ZV_LCDPAD_EN, 0x00000000); | |
738 | OUTREG(ZV_LCDPAD_A, 0x00000000); | |
739 | OUTREG(GPIO_VGA_DDC, 0x00030000); | |
740 | OUTREG(GPIO_DVI_DDC, 0x00000000); | |
741 | OUTREG(GPIO_MONID, 0x00030000); | |
742 | OUTREG(GPIO_CRT2_DDC, 0x00000000); | |
743 | } | |
744 | ||
745 | static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo) | |
746 | { | |
747 | /* Set v2clk to 65MHz */ | |
748 | if (rinfo->family <= CHIP_FAMILY_RV280) { | |
749 | OUTPLL(pllPIXCLKS_CNTL, | |
750 | __INPLL(rinfo, pllPIXCLKS_CNTL) | |
751 | & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK); | |
752 | ||
753 | OUTPLL(pllP2PLL_REF_DIV, 0x0000000c); | |
754 | OUTPLL(pllP2PLL_CNTL, 0x0000bf00); | |
755 | } else { | |
756 | OUTPLL(pllP2PLL_REF_DIV, 0x0000000c); | |
757 | INPLL(pllP2PLL_REF_DIV); | |
758 | OUTPLL(pllP2PLL_CNTL, 0x0000a700); | |
759 | } | |
760 | ||
761 | OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W); | |
762 | ||
763 | OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP); | |
764 | mdelay(1); | |
765 | ||
766 | OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET); | |
767 | mdelay( 1); | |
768 | ||
769 | OUTPLL(pllPIXCLKS_CNTL, | |
770 | (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK) | |
771 | | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT)); | |
772 | mdelay( 1); | |
773 | } | |
774 | ||
775 | static void radeon_pm_low_current(struct radeonfb_info *rinfo) | |
776 | { | |
777 | u32 reg; | |
778 | ||
779 | reg = INREG(BUS_CNTL1); | |
780 | if (rinfo->family <= CHIP_FAMILY_RV280) { | |
781 | reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK; | |
782 | reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT); | |
783 | } else { | |
784 | reg |= 0x4080; | |
785 | } | |
786 | OUTREG(BUS_CNTL1, reg); | |
787 | ||
788 | reg = INPLL(PLL_PWRMGT_CNTL); | |
789 | reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF | | |
790 | PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF; | |
791 | reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; | |
792 | reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU; | |
793 | OUTPLL(PLL_PWRMGT_CNTL, reg); | |
794 | ||
795 | reg = INREG(TV_DAC_CNTL); | |
796 | reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK); | |
797 | reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD | | |
798 | TV_DAC_CNTL_BDACPD | | |
799 | (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT); | |
800 | OUTREG(TV_DAC_CNTL, reg); | |
801 | ||
802 | reg = INREG(TMDS_TRANSMITTER_CNTL); | |
803 | reg &= ~(TMDS_PLL_EN | TMDS_PLLRST); | |
804 | OUTREG(TMDS_TRANSMITTER_CNTL, reg); | |
805 | ||
806 | reg = INREG(DAC_CNTL); | |
807 | reg &= ~DAC_CMP_EN; | |
808 | OUTREG(DAC_CNTL, reg); | |
809 | ||
810 | reg = INREG(DAC_CNTL2); | |
811 | reg &= ~DAC2_CMP_EN; | |
812 | OUTREG(DAC_CNTL2, reg); | |
813 | ||
814 | reg = INREG(TV_DAC_CNTL); | |
815 | reg &= ~TV_DAC_CNTL_DETECT; | |
816 | OUTREG(TV_DAC_CNTL, reg); | |
817 | } | |
818 | ||
819 | static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo) | |
820 | { | |
821 | ||
822 | u32 sclk_cntl, mclk_cntl, sclk_more_cntl; | |
823 | ||
824 | u32 pll_pwrmgt_cntl; | |
825 | u32 clk_pwrmgt_cntl; | |
826 | u32 clk_pin_cntl; | |
827 | u32 vclk_ecp_cntl; | |
828 | u32 pixclks_cntl; | |
829 | u32 disp_mis_cntl; | |
830 | u32 disp_pwr_man; | |
831 | u32 tmp; | |
832 | ||
833 | /* Force Core Clocks */ | |
834 | sclk_cntl = INPLL( pllSCLK_CNTL); | |
835 | sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT| | |
836 | SCLK_CNTL__VIP_MAX_DYN_STOP_LAT| | |
837 | SCLK_CNTL__RE_MAX_DYN_STOP_LAT| | |
838 | SCLK_CNTL__PB_MAX_DYN_STOP_LAT| | |
839 | SCLK_CNTL__TAM_MAX_DYN_STOP_LAT| | |
840 | SCLK_CNTL__TDM_MAX_DYN_STOP_LAT| | |
841 | SCLK_CNTL__RB_MAX_DYN_STOP_LAT| | |
842 | ||
843 | SCLK_CNTL__FORCE_DISP2| | |
844 | SCLK_CNTL__FORCE_CP| | |
845 | SCLK_CNTL__FORCE_HDP| | |
846 | SCLK_CNTL__FORCE_DISP1| | |
847 | SCLK_CNTL__FORCE_TOP| | |
848 | SCLK_CNTL__FORCE_E2| | |
849 | SCLK_CNTL__FORCE_SE| | |
850 | SCLK_CNTL__FORCE_IDCT| | |
851 | SCLK_CNTL__FORCE_VIP| | |
852 | ||
853 | SCLK_CNTL__FORCE_PB| | |
854 | SCLK_CNTL__FORCE_TAM| | |
855 | SCLK_CNTL__FORCE_TDM| | |
856 | SCLK_CNTL__FORCE_RB| | |
857 | SCLK_CNTL__FORCE_TV_SCLK| | |
858 | SCLK_CNTL__FORCE_SUBPIC| | |
859 | SCLK_CNTL__FORCE_OV0; | |
860 | if (rinfo->family <= CHIP_FAMILY_RV280) | |
861 | sclk_cntl |= SCLK_CNTL__FORCE_RE; | |
862 | else | |
863 | sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT | | |
864 | SCLK_CNTL__E2_MAX_DYN_STOP_LAT | | |
865 | SCLK_CNTL__TV_MAX_DYN_STOP_LAT | | |
866 | SCLK_CNTL__HDP_MAX_DYN_STOP_LAT | | |
867 | SCLK_CNTL__CP_MAX_DYN_STOP_LAT; | |
868 | ||
869 | OUTPLL( pllSCLK_CNTL, sclk_cntl); | |
870 | ||
871 | sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL); | |
872 | sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS | | |
873 | SCLK_MORE_CNTL__FORCE_MC_GUI | | |
874 | SCLK_MORE_CNTL__FORCE_MC_HOST; | |
875 | ||
876 | OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl); | |
877 | ||
878 | ||
879 | mclk_cntl = INPLL( pllMCLK_CNTL); | |
880 | mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA | | |
881 | MCLK_CNTL__FORCE_MCLKB | | |
882 | MCLK_CNTL__FORCE_YCLKA | | |
883 | MCLK_CNTL__FORCE_YCLKB | | |
884 | MCLK_CNTL__FORCE_MC | |
885 | ); | |
886 | OUTPLL( pllMCLK_CNTL, mclk_cntl); | |
887 | ||
888 | /* Force Display clocks */ | |
889 | vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL); | |
890 | vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | |
891 | | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb); | |
892 | vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON; | |
893 | OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl); | |
894 | ||
895 | ||
896 | pixclks_cntl = INPLL( pllPIXCLKS_CNTL); | |
897 | pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | | |
898 | PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb| | |
899 | PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb | | |
900 | PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb| | |
901 | PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb| | |
902 | PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb| | |
903 | PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb); | |
904 | ||
905 | OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl); | |
906 | ||
907 | /* Switch off LVDS interface */ | |
908 | OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & | |
909 | ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON)); | |
910 | ||
911 | /* Enable System power management */ | |
912 | pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL); | |
913 | ||
914 | pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF | | |
915 | PLL_PWRMGT_CNTL__MPLL_TURNOFF| | |
916 | PLL_PWRMGT_CNTL__PPLL_TURNOFF| | |
917 | PLL_PWRMGT_CNTL__P2PLL_TURNOFF| | |
918 | PLL_PWRMGT_CNTL__TVPLL_TURNOFF; | |
919 | ||
920 | OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl); | |
921 | ||
922 | clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); | |
923 | ||
924 | clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF| | |
925 | CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF| | |
926 | CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF| | |
927 | CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF| | |
928 | CLK_PWRMGT_CNTL__MCLK_TURNOFF| | |
929 | CLK_PWRMGT_CNTL__SCLK_TURNOFF| | |
930 | CLK_PWRMGT_CNTL__PCLK_TURNOFF| | |
931 | CLK_PWRMGT_CNTL__P2CLK_TURNOFF| | |
932 | CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF| | |
933 | CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN| | |
934 | CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE| | |
935 | CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK| | |
936 | CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK | |
937 | ); | |
938 | ||
939 | clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN | |
940 | | CLK_PWRMGT_CNTL__DISP_PM; | |
941 | ||
942 | OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl); | |
943 | ||
944 | clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); | |
945 | ||
946 | clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND; | |
947 | ||
948 | /* because both INPLL and OUTPLL take the same lock, that's why. */ | |
949 | tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND; | |
950 | OUTPLL( pllMCLK_MISC, tmp); | |
1da177e4 | 951 | |
994aad25 VB |
952 | /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset |
953 | * and radeon chip dependent. Thus we only enable it on Mac for | |
954 | * now (until we get more info on how to compute the correct | |
955 | * value for various X86 bridges). | |
956 | */ | |
957 | #ifdef CONFIG_PPC_PMAC | |
958 | if (machine_is(powermac)) { | |
959 | /* AGP PLL control */ | |
960 | if (rinfo->family <= CHIP_FAMILY_RV280) { | |
961 | OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); | |
962 | OUTREG(BUS_CNTL1, | |
963 | (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK) | |
964 | | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX | |
965 | } else { | |
966 | OUTREG(BUS_CNTL1, INREG(BUS_CNTL1)); | |
967 | OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000); | |
968 | } | |
1da177e4 | 969 | } |
994aad25 | 970 | #endif |
1da177e4 LT |
971 | |
972 | OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) | |
973 | & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN)); | |
974 | ||
975 | clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN; | |
976 | clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb; | |
977 | OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); | |
978 | ||
979 | /* Solano2M */ | |
980 | OUTREG(AGP_CNTL, | |
981 | (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK)) | |
982 | | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT)); | |
983 | ||
984 | /* ACPI mode */ | |
985 | /* because both INPLL and OUTPLL take the same lock, that's why. */ | |
986 | tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL; | |
987 | OUTPLL( pllPLL_PWRMGT_CNTL, tmp); | |
988 | ||
989 | ||
990 | disp_mis_cntl = INREG(DISP_MISC_CNTL); | |
991 | ||
992 | disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP | | |
993 | DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP | | |
994 | DISP_MISC_CNTL__SOFT_RESET_OV0_PP | | |
995 | DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK| | |
996 | DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK| | |
997 | DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK| | |
998 | DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP| | |
999 | DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK| | |
1000 | DISP_MISC_CNTL__SOFT_RESET_LVDS| | |
1001 | DISP_MISC_CNTL__SOFT_RESET_TMDS| | |
1002 | DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS| | |
1003 | DISP_MISC_CNTL__SOFT_RESET_TV); | |
1004 | ||
1005 | OUTREG(DISP_MISC_CNTL, disp_mis_cntl); | |
1006 | ||
1007 | disp_pwr_man = INREG(DISP_PWR_MAN); | |
1008 | ||
1009 | disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN | | |
1010 | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN | | |
1011 | DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK| | |
1012 | DISP_PWR_MAN__DISP_D3_RST| | |
1013 | DISP_PWR_MAN__DISP_D3_REG_RST | |
1014 | ); | |
1015 | ||
1016 | disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST| | |
1017 | DISP_PWR_MAN__DISP_D3_SUBPIC_RST| | |
1018 | DISP_PWR_MAN__DISP_D3_OV0_RST| | |
1019 | DISP_PWR_MAN__DISP_D1D2_GRPH_RST| | |
1020 | DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST| | |
1021 | DISP_PWR_MAN__DISP_D1D2_OV0_RST| | |
1022 | DISP_PWR_MAN__DIG_TMDS_ENABLE_RST| | |
1023 | DISP_PWR_MAN__TV_ENABLE_RST| | |
1024 | // DISP_PWR_MAN__AUTO_PWRUP_EN| | |
1025 | 0; | |
1026 | ||
1027 | OUTREG(DISP_PWR_MAN, disp_pwr_man); | |
1028 | ||
1029 | clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); | |
1030 | pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ; | |
1031 | clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); | |
1032 | disp_pwr_man = INREG(DISP_PWR_MAN); | |
1033 | ||
1034 | ||
1035 | /* D2 */ | |
1036 | clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM; | |
1037 | pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK; | |
1038 | clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb; | |
1039 | disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK | |
1040 | | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK); | |
1041 | ||
1042 | OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl); | |
1043 | OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl); | |
1044 | OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); | |
1045 | OUTREG(DISP_PWR_MAN, disp_pwr_man); | |
1046 | ||
1047 | /* disable display request & disable display */ | |
1048 | OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) | |
1049 | | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B); | |
1050 | OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) | |
1051 | | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B); | |
1052 | ||
1053 | mdelay(17); | |
1054 | ||
1055 | } | |
1056 | ||
1057 | static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo) | |
1058 | { | |
1059 | u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1; | |
1060 | ||
1061 | mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1) | |
1062 | & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK; | |
1063 | mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1) | |
1064 | & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK; | |
1065 | ||
1066 | OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1 | |
1067 | | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT)); | |
1068 | OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1 | |
1069 | | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT)); | |
1070 | ||
1071 | OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1); | |
1072 | OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1); | |
1073 | ||
1074 | mdelay( 1); | |
1075 | } | |
1076 | ||
1077 | static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo) | |
1078 | { | |
1079 | u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1; | |
1080 | ||
1081 | mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1) | |
1082 | & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK; | |
1083 | mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1) | |
1084 | & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK; | |
1085 | ||
1086 | OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, | |
1087 | mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT)); | |
1088 | OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, | |
1089 | mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT)); | |
1090 | ||
1091 | OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1); | |
1092 | OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1); | |
1093 | ||
1094 | mdelay( 1); | |
1095 | } | |
1096 | ||
1097 | static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value, | |
1098 | u8 delay_required) | |
1099 | { | |
1100 | u32 mem_sdram_mode; | |
1101 | ||
1102 | mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG); | |
1103 | ||
1104 | mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK; | |
1105 | mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT) | |
1106 | | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE; | |
1107 | OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); | |
1108 | if (delay_required >= 2) | |
1109 | mdelay(1); | |
1110 | ||
1111 | mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET; | |
1112 | OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); | |
1113 | if (delay_required >= 2) | |
1114 | mdelay(1); | |
1115 | ||
1116 | mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET; | |
1117 | OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); | |
1118 | if (delay_required >= 2) | |
1119 | mdelay(1); | |
1120 | ||
1121 | if (delay_required) { | |
1122 | do { | |
1123 | if (delay_required >= 2) | |
1124 | mdelay(1); | |
1125 | } while ((INREG(MC_STATUS) | |
1126 | & (MC_STATUS__MEM_PWRUP_COMPL_A | | |
1127 | MC_STATUS__MEM_PWRUP_COMPL_B)) == 0); | |
1128 | } | |
1129 | } | |
1130 | ||
1131 | static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo) | |
1132 | { | |
1133 | int cnt; | |
1134 | ||
1135 | for (cnt = 0; cnt < 100; ++cnt) { | |
1136 | mdelay(1); | |
1137 | if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A | |
1138 | | MC_STATUS__MEM_PWRUP_COMPL_B)) | |
1139 | break; | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | ||
1144 | static void radeon_pm_enable_dll(struct radeonfb_info *rinfo) | |
1145 | { | |
1146 | #define DLL_RESET_DELAY 5 | |
1147 | #define DLL_SLEEP_DELAY 1 | |
1148 | ||
1149 | u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP | |
1150 | | MDLL_CKO__MCKOA_RESET; | |
1151 | u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP | |
1152 | | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET | |
1153 | | MDLL_RDCKA__MRDCKA1_RESET; | |
1154 | u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP | |
1155 | | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET | |
1156 | | MDLL_RDCKB__MRDCKB1_RESET; | |
1157 | ||
1158 | /* Setting up the DLL range for write */ | |
1159 | OUTPLL(pllMDLL_CKO, cko); | |
1160 | OUTPLL(pllMDLL_RDCKA, cka); | |
1161 | OUTPLL(pllMDLL_RDCKB, ckb); | |
1162 | ||
1163 | mdelay(DLL_RESET_DELAY*2); | |
1164 | ||
1165 | cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP); | |
1166 | OUTPLL(pllMDLL_CKO, cko); | |
1167 | mdelay(DLL_SLEEP_DELAY); | |
1168 | cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET); | |
1169 | OUTPLL(pllMDLL_CKO, cko); | |
1170 | mdelay(DLL_RESET_DELAY); | |
1171 | ||
1172 | cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP); | |
1173 | OUTPLL(pllMDLL_RDCKA, cka); | |
1174 | mdelay(DLL_SLEEP_DELAY); | |
1175 | cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET); | |
1176 | OUTPLL(pllMDLL_RDCKA, cka); | |
1177 | mdelay(DLL_RESET_DELAY); | |
1178 | ||
1179 | ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP); | |
1180 | OUTPLL(pllMDLL_RDCKB, ckb); | |
1181 | mdelay(DLL_SLEEP_DELAY); | |
1182 | ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET); | |
1183 | OUTPLL(pllMDLL_RDCKB, ckb); | |
1184 | mdelay(DLL_RESET_DELAY); | |
1185 | ||
1186 | ||
1187 | #undef DLL_RESET_DELAY | |
1188 | #undef DLL_SLEEP_DELAY | |
1189 | } | |
1190 | ||
1191 | static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo) | |
1192 | { | |
1193 | u32 dll_value; | |
1194 | u32 dll_sleep_mask = 0; | |
1195 | u32 dll_reset_mask = 0; | |
1196 | u32 mc; | |
1197 | ||
1198 | #define DLL_RESET_DELAY 5 | |
1199 | #define DLL_SLEEP_DELAY 1 | |
1200 | ||
1201 | OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); | |
1202 | mc = INREG(MC_CNTL); | |
1203 | /* Check which channels are enabled */ | |
1204 | switch (mc & 0x3) { | |
1205 | case 1: | |
1206 | if (mc & 0x4) | |
1207 | break; | |
1208 | case 2: | |
1209 | dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP; | |
1210 | dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET; | |
1211 | case 0: | |
1212 | dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP; | |
1213 | dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET; | |
1214 | } | |
1215 | switch (mc & 0x3) { | |
1216 | case 1: | |
1217 | if (!(mc & 0x4)) | |
1218 | break; | |
1219 | case 2: | |
1220 | dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP; | |
1221 | dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET; | |
1222 | dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP; | |
1223 | dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET; | |
1224 | } | |
1225 | ||
1226 | dll_value = INPLL(pllMDLL_RDCKA); | |
1227 | ||
1228 | /* Power Up */ | |
1229 | dll_value &= ~(dll_sleep_mask); | |
1230 | OUTPLL(pllMDLL_RDCKA, dll_value); | |
1231 | mdelay( DLL_SLEEP_DELAY); | |
1232 | ||
1233 | dll_value &= ~(dll_reset_mask); | |
1234 | OUTPLL(pllMDLL_RDCKA, dll_value); | |
1235 | mdelay( DLL_RESET_DELAY); | |
1236 | ||
1237 | #undef DLL_RESET_DELAY | |
1238 | #undef DLL_SLEEP_DELAY | |
1239 | } | |
1240 | ||
1241 | ||
1242 | static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo) | |
1243 | { | |
1244 | u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl, | |
1245 | fp_gen_cntl, fp2_gen_cntl; | |
1246 | ||
1247 | crtcGenCntl = INREG( CRTC_GEN_CNTL); | |
1248 | crtcGenCntl2 = INREG( CRTC2_GEN_CNTL); | |
1249 | ||
1250 | crtc_more_cntl = INREG( CRTC_MORE_CNTL); | |
1251 | fp_gen_cntl = INREG( FP_GEN_CNTL); | |
1252 | fp2_gen_cntl = INREG( FP2_GEN_CNTL); | |
1253 | ||
1254 | ||
1255 | OUTREG( CRTC_MORE_CNTL, 0); | |
1256 | OUTREG( FP_GEN_CNTL, 0); | |
1257 | OUTREG( FP2_GEN_CNTL,0); | |
1258 | ||
1259 | OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) ); | |
1260 | OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) ); | |
1261 | ||
14bfd1ff | 1262 | /* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */ |
1da177e4 LT |
1263 | if (rinfo->family == CHIP_FAMILY_RV350) { |
1264 | u32 sdram_mode_reg = rinfo->save_regs[35]; | |
a7edd0e6 | 1265 | static const u32 default_mrtable[] = |
1da177e4 LT |
1266 | { 0x21320032, |
1267 | 0x21321000, 0xa1321000, 0x21321000, 0xffffffff, | |
1268 | 0x21320032, 0xa1320032, 0x21320032, 0xffffffff, | |
1269 | 0x21321002, 0xa1321002, 0x21321002, 0xffffffff, | |
1270 | 0x21320132, 0xa1320132, 0x21320132, 0xffffffff, | |
1271 | 0x21320032, 0xa1320032, 0x21320032, 0xffffffff, | |
1272 | 0x31320032 }; | |
1273 | ||
b04e3dd4 | 1274 | const u32 *mrtable = default_mrtable; |
1da177e4 LT |
1275 | int i, mrtable_size = ARRAY_SIZE(default_mrtable); |
1276 | ||
1277 | mdelay(30); | |
1278 | ||
1279 | /* Disable refresh */ | |
1280 | memRefreshCntl = INREG( MEM_REFRESH_CNTL) | |
1281 | & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS; | |
1282 | OUTREG( MEM_REFRESH_CNTL, memRefreshCntl | |
1283 | | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); | |
1284 | ||
1285 | /* Configure and enable M & SPLLs */ | |
1286 | radeon_pm_enable_dll_m10(rinfo); | |
1287 | radeon_pm_yclk_mclk_sync_m10(rinfo); | |
1288 | ||
1289 | #ifdef CONFIG_PPC_OF | |
1290 | if (rinfo->of_node != NULL) { | |
1291 | int size; | |
1292 | ||
40cd3a45 | 1293 | mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size); |
1da177e4 LT |
1294 | if (mrtable) |
1295 | mrtable_size = size >> 2; | |
1296 | else | |
1297 | mrtable = default_mrtable; | |
1298 | } | |
1299 | #endif /* CONFIG_PPC_OF */ | |
1300 | ||
1301 | /* Program the SDRAM */ | |
1302 | sdram_mode_reg = mrtable[0]; | |
1303 | OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); | |
1304 | for (i = 0; i < mrtable_size; i++) { | |
1305 | if (mrtable[i] == 0xffffffffu) | |
1306 | radeon_pm_m10_program_mode_wait(rinfo); | |
1307 | else { | |
1308 | sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK | |
1309 | | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE | |
1310 | | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET); | |
1311 | sdram_mode_reg |= mrtable[i]; | |
1312 | ||
1313 | OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); | |
1314 | mdelay(1); | |
1315 | } | |
1316 | } | |
1317 | ||
1318 | /* Restore memory refresh */ | |
1319 | OUTREG(MEM_REFRESH_CNTL, memRefreshCntl); | |
1320 | mdelay(30); | |
1321 | ||
1322 | } | |
1323 | /* Here come the desktop RV200 "QW" card */ | |
1324 | else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) { | |
1325 | /* Disable refresh */ | |
1326 | memRefreshCntl = INREG( MEM_REFRESH_CNTL) | |
1327 | & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS; | |
1328 | OUTREG(MEM_REFRESH_CNTL, memRefreshCntl | |
1329 | | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); | |
1330 | mdelay(30); | |
1331 | ||
1332 | /* Reset memory */ | |
1333 | OUTREG(MEM_SDRAM_MODE_REG, | |
1334 | INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1335 | ||
1336 | radeon_pm_program_mode_reg(rinfo, 0x2002, 2); | |
1337 | radeon_pm_program_mode_reg(rinfo, 0x0132, 2); | |
1338 | radeon_pm_program_mode_reg(rinfo, 0x0032, 2); | |
1339 | ||
1340 | OUTREG(MEM_SDRAM_MODE_REG, | |
1341 | INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1342 | ||
1343 | OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); | |
1344 | ||
1345 | } | |
1346 | /* The M6 */ | |
1347 | else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) { | |
1348 | /* Disable refresh */ | |
1349 | memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20); | |
1350 | OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20)); | |
1351 | ||
1352 | /* Reset memory */ | |
1353 | OUTREG( MEM_SDRAM_MODE_REG, | |
1354 | INREG( MEM_SDRAM_MODE_REG) | |
1355 | & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1356 | ||
1357 | /* DLL */ | |
1358 | radeon_pm_enable_dll(rinfo); | |
1359 | ||
1360 | /* MLCK / YCLK sync */ | |
1361 | radeon_pm_yclk_mclk_sync(rinfo); | |
1362 | ||
1363 | /* Program Mode Register */ | |
1364 | radeon_pm_program_mode_reg(rinfo, 0x2000, 1); | |
1365 | radeon_pm_program_mode_reg(rinfo, 0x2001, 1); | |
1366 | radeon_pm_program_mode_reg(rinfo, 0x2002, 1); | |
1367 | radeon_pm_program_mode_reg(rinfo, 0x0132, 1); | |
1368 | radeon_pm_program_mode_reg(rinfo, 0x0032, 1); | |
1369 | ||
1370 | /* Complete & re-enable refresh */ | |
1371 | OUTREG( MEM_SDRAM_MODE_REG, | |
1372 | INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1373 | ||
1374 | OUTREG(EXT_MEM_CNTL, memRefreshCntl); | |
1375 | } | |
1376 | /* And finally, the M7..M9 models, including M9+ (RV280) */ | |
1377 | else if (rinfo->is_mobility) { | |
1378 | ||
1379 | /* Disable refresh */ | |
1380 | memRefreshCntl = INREG( MEM_REFRESH_CNTL) | |
1381 | & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS; | |
1382 | OUTREG( MEM_REFRESH_CNTL, memRefreshCntl | |
1383 | | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); | |
1384 | ||
1385 | /* Reset memory */ | |
1386 | OUTREG( MEM_SDRAM_MODE_REG, | |
1387 | INREG( MEM_SDRAM_MODE_REG) | |
1388 | & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1389 | ||
1390 | /* DLL */ | |
1391 | radeon_pm_enable_dll(rinfo); | |
1392 | ||
1393 | /* MLCK / YCLK sync */ | |
1394 | radeon_pm_yclk_mclk_sync(rinfo); | |
1395 | ||
1396 | /* M6, M7 and M9 so far ... */ | |
1397 | if (rinfo->family <= CHIP_FAMILY_RV250) { | |
1398 | radeon_pm_program_mode_reg(rinfo, 0x2000, 1); | |
1399 | radeon_pm_program_mode_reg(rinfo, 0x2001, 1); | |
1400 | radeon_pm_program_mode_reg(rinfo, 0x2002, 1); | |
1401 | radeon_pm_program_mode_reg(rinfo, 0x0132, 1); | |
1402 | radeon_pm_program_mode_reg(rinfo, 0x0032, 1); | |
1403 | } | |
1404 | /* M9+ (iBook G4) */ | |
1405 | else if (rinfo->family == CHIP_FAMILY_RV280) { | |
1406 | radeon_pm_program_mode_reg(rinfo, 0x2000, 1); | |
1407 | radeon_pm_program_mode_reg(rinfo, 0x0132, 1); | |
1408 | radeon_pm_program_mode_reg(rinfo, 0x0032, 1); | |
1409 | } | |
1410 | ||
1411 | /* Complete & re-enable refresh */ | |
1412 | OUTREG( MEM_SDRAM_MODE_REG, | |
1413 | INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1414 | ||
1415 | OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); | |
1416 | } | |
1417 | ||
1418 | OUTREG( CRTC_GEN_CNTL, crtcGenCntl); | |
1419 | OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2); | |
1420 | OUTREG( FP_GEN_CNTL, fp_gen_cntl); | |
1421 | OUTREG( FP2_GEN_CNTL, fp2_gen_cntl); | |
1422 | ||
1423 | OUTREG( CRTC_MORE_CNTL, crtc_more_cntl); | |
1424 | ||
1425 | mdelay( 15); | |
1426 | } | |
1427 | ||
1da177e4 LT |
1428 | static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo) |
1429 | { | |
1430 | u32 tmp, tmp2; | |
1431 | int i,j; | |
1432 | ||
1433 | /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */ | |
1434 | INREG(PAD_CTLR_STRENGTH); | |
1435 | OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE); | |
1436 | tmp = INREG(PAD_CTLR_STRENGTH); | |
1437 | for (i = j = 0; i < 65; ++i) { | |
1438 | mdelay(1); | |
1439 | tmp2 = INREG(PAD_CTLR_STRENGTH); | |
1440 | if (tmp != tmp2) { | |
1441 | tmp = tmp2; | |
1442 | i = 0; | |
1443 | j++; | |
1444 | if (j > 10) { | |
1445 | printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't " | |
1446 | "stabilize !\n"); | |
1447 | break; | |
1448 | } | |
1449 | } | |
1450 | } | |
1451 | } | |
1452 | ||
1453 | static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo) | |
1454 | { | |
1455 | u32 tmp; | |
1456 | ||
1457 | tmp = INPLL(pllPPLL_CNTL); | |
1458 | OUTPLL(pllPPLL_CNTL, tmp | 0x3); | |
1459 | tmp = INPLL(pllP2PLL_CNTL); | |
1460 | OUTPLL(pllP2PLL_CNTL, tmp | 0x3); | |
1461 | tmp = INPLL(pllSPLL_CNTL); | |
1462 | OUTPLL(pllSPLL_CNTL, tmp | 0x3); | |
1463 | tmp = INPLL(pllMPLL_CNTL); | |
1464 | OUTPLL(pllMPLL_CNTL, tmp | 0x3); | |
1465 | } | |
1466 | ||
1467 | static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo) | |
1468 | { | |
1469 | u32 tmp; | |
1470 | ||
1471 | /* Switch SPLL to PCI source */ | |
1472 | tmp = INPLL(pllSCLK_CNTL); | |
1473 | OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK); | |
1474 | ||
1475 | /* Reconfigure SPLL charge pump, VCO gain, duty cycle */ | |
1476 | tmp = INPLL(pllSPLL_CNTL); | |
1477 | OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); | |
1478 | radeon_pll_errata_after_index(rinfo); | |
1479 | OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); | |
1480 | radeon_pll_errata_after_data(rinfo); | |
1481 | ||
1482 | /* Set SPLL feedback divider */ | |
1483 | tmp = INPLL(pllM_SPLL_REF_FB_DIV); | |
1484 | tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul); | |
1485 | OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); | |
1486 | ||
1487 | /* Power up SPLL */ | |
1488 | tmp = INPLL(pllSPLL_CNTL); | |
1489 | OUTPLL(pllSPLL_CNTL, tmp & ~1); | |
1490 | (void)INPLL(pllSPLL_CNTL); | |
1491 | ||
1492 | mdelay(10); | |
1493 | ||
1494 | /* Release SPLL reset */ | |
1495 | tmp = INPLL(pllSPLL_CNTL); | |
1496 | OUTPLL(pllSPLL_CNTL, tmp & ~0x2); | |
1497 | (void)INPLL(pllSPLL_CNTL); | |
1498 | ||
1499 | mdelay(10); | |
1500 | ||
1501 | /* Select SCLK source */ | |
1502 | tmp = INPLL(pllSCLK_CNTL); | |
1503 | tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK; | |
1504 | tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK; | |
1505 | OUTPLL(pllSCLK_CNTL, tmp); | |
1506 | (void)INPLL(pllSCLK_CNTL); | |
1507 | ||
1508 | mdelay(10); | |
1509 | ||
1510 | /* Reconfigure MPLL charge pump, VCO gain, duty cycle */ | |
1511 | tmp = INPLL(pllMPLL_CNTL); | |
1512 | OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN); | |
1513 | radeon_pll_errata_after_index(rinfo); | |
1514 | OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); | |
1515 | radeon_pll_errata_after_data(rinfo); | |
1516 | ||
1517 | /* Set MPLL feedback divider */ | |
1518 | tmp = INPLL(pllM_SPLL_REF_FB_DIV); | |
1519 | tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul); | |
1520 | ||
1521 | OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); | |
1522 | /* Power up MPLL */ | |
1523 | tmp = INPLL(pllMPLL_CNTL); | |
1524 | OUTPLL(pllMPLL_CNTL, tmp & ~0x2); | |
1525 | (void)INPLL(pllMPLL_CNTL); | |
1526 | ||
1527 | mdelay(10); | |
1528 | ||
1529 | /* Un-reset MPLL */ | |
1530 | tmp = INPLL(pllMPLL_CNTL); | |
1531 | OUTPLL(pllMPLL_CNTL, tmp & ~0x1); | |
1532 | (void)INPLL(pllMPLL_CNTL); | |
1533 | ||
1534 | mdelay(10); | |
1535 | ||
1536 | /* Select source for MCLK */ | |
1537 | tmp = INPLL(pllMCLK_CNTL); | |
1538 | tmp |= rinfo->save_regs[2] & 0xffff; | |
1539 | OUTPLL(pllMCLK_CNTL, tmp); | |
1540 | (void)INPLL(pllMCLK_CNTL); | |
1541 | ||
1542 | mdelay(10); | |
1543 | } | |
1544 | ||
1545 | static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo) | |
1546 | { | |
1547 | u32 r2ec; | |
1548 | ||
1549 | /* GACK ! I though we didn't have a DDA on Radeon's anymore | |
1550 | * here we rewrite with the same value, ... I suppose we clear | |
1551 | * some bits that are already clear ? Or maybe this 0x2ec | |
1552 | * register is something new ? | |
1553 | */ | |
1554 | mdelay(20); | |
1555 | r2ec = INREG(VGA_DDA_ON_OFF); | |
1556 | OUTREG(VGA_DDA_ON_OFF, r2ec); | |
1557 | mdelay(1); | |
1558 | ||
1559 | /* Spread spectrum PLLL off */ | |
1560 | OUTPLL(pllSSPLL_CNTL, 0xbf03); | |
1561 | ||
1562 | /* Spread spectrum disabled */ | |
1563 | OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3); | |
1564 | ||
1565 | /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same | |
1566 | * value, not sure what for... | |
1567 | */ | |
1568 | ||
1569 | r2ec |= 0x3f0; | |
1570 | OUTREG(VGA_DDA_ON_OFF, r2ec); | |
1571 | mdelay(1); | |
1572 | } | |
1573 | ||
1574 | static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo) | |
1575 | { | |
1576 | u32 r2ec, tmp; | |
1577 | ||
1578 | /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore | |
1579 | * here we rewrite with the same value, ... I suppose we clear/set | |
1580 | * some bits that are already clear/set ? | |
1581 | */ | |
1582 | r2ec = INREG(VGA_DDA_ON_OFF); | |
1583 | OUTREG(VGA_DDA_ON_OFF, r2ec); | |
1584 | mdelay(1); | |
1585 | ||
1586 | /* Enable spread spectrum */ | |
1587 | OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3); | |
1588 | mdelay(3); | |
1589 | ||
1590 | OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]); | |
1591 | OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]); | |
1592 | tmp = INPLL(pllSSPLL_CNTL); | |
1593 | OUTPLL(pllSSPLL_CNTL, tmp & ~0x2); | |
1594 | mdelay(6); | |
1595 | tmp = INPLL(pllSSPLL_CNTL); | |
1596 | OUTPLL(pllSSPLL_CNTL, tmp & ~0x1); | |
1597 | mdelay(5); | |
1598 | ||
1599 | OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]); | |
1600 | ||
1601 | r2ec |= 8; | |
1602 | OUTREG(VGA_DDA_ON_OFF, r2ec); | |
1603 | mdelay(20); | |
1604 | ||
1605 | /* Enable LVDS interface */ | |
1606 | tmp = INREG(LVDS_GEN_CNTL); | |
1607 | OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN); | |
1608 | ||
1609 | /* Enable LVDS_PLL */ | |
1610 | tmp = INREG(LVDS_PLL_CNTL); | |
1611 | tmp &= ~0x30000; | |
1612 | tmp |= 0x10000; | |
1613 | OUTREG(LVDS_PLL_CNTL, tmp); | |
1614 | ||
1615 | OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]); | |
1616 | OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]); | |
1617 | ||
1618 | /* The trace reads that one here, waiting for something to settle down ? */ | |
1619 | INREG(RBBM_STATUS); | |
1620 | ||
1621 | /* Ugh ? SS_TST_DEC is supposed to be a read register in the | |
1622 | * R300 register spec at least... | |
1623 | */ | |
1624 | tmp = INPLL(pllSS_TST_CNTL); | |
1625 | tmp |= 0x00400000; | |
1626 | OUTPLL(pllSS_TST_CNTL, tmp); | |
1627 | } | |
1628 | ||
1629 | static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo) | |
1630 | { | |
1631 | u32 tmp; | |
1632 | ||
1633 | OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN); | |
1634 | radeon_pll_errata_after_index(rinfo); | |
1635 | OUTREG8(CLOCK_CNTL_DATA, 0); | |
1636 | radeon_pll_errata_after_data(rinfo); | |
1637 | ||
1638 | tmp = INPLL(pllVCLK_ECP_CNTL); | |
1639 | OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80); | |
1640 | mdelay(5); | |
1641 | ||
1642 | tmp = INPLL(pllPPLL_REF_DIV); | |
1643 | tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; | |
1644 | OUTPLL(pllPPLL_REF_DIV, tmp); | |
1645 | INPLL(pllPPLL_REF_DIV); | |
1646 | ||
1647 | /* Reconfigure SPLL charge pump, VCO gain, duty cycle, | |
1648 | * probably useless since we already did it ... | |
1649 | */ | |
1650 | tmp = INPLL(pllPPLL_CNTL); | |
1651 | OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); | |
1652 | radeon_pll_errata_after_index(rinfo); | |
1653 | OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); | |
1654 | radeon_pll_errata_after_data(rinfo); | |
1655 | ||
1656 | /* Restore our "reference" PPLL divider set by firmware | |
1657 | * according to proper spread spectrum calculations | |
1658 | */ | |
1659 | OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); | |
1660 | ||
1661 | tmp = INPLL(pllPPLL_CNTL); | |
1662 | OUTPLL(pllPPLL_CNTL, tmp & ~0x2); | |
1663 | mdelay(5); | |
1664 | ||
1665 | tmp = INPLL(pllPPLL_CNTL); | |
1666 | OUTPLL(pllPPLL_CNTL, tmp & ~0x1); | |
1667 | mdelay(5); | |
1668 | ||
1669 | tmp = INPLL(pllVCLK_ECP_CNTL); | |
1670 | OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); | |
1671 | mdelay(5); | |
1672 | ||
1673 | tmp = INPLL(pllVCLK_ECP_CNTL); | |
1674 | OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); | |
1675 | mdelay(5); | |
1676 | ||
1677 | /* Switch pixel clock to firmware default div 0 */ | |
1678 | OUTREG8(CLOCK_CNTL_INDEX+1, 0); | |
1679 | radeon_pll_errata_after_index(rinfo); | |
1680 | radeon_pll_errata_after_data(rinfo); | |
1681 | } | |
1682 | ||
1683 | static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo) | |
1684 | { | |
1685 | OUTREG(MC_CNTL, rinfo->save_regs[46]); | |
1686 | OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); | |
1687 | OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); | |
1688 | OUTREG(MEM_SDRAM_MODE_REG, | |
1689 | rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1690 | OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); | |
1691 | OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); | |
1692 | OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); | |
1693 | OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); | |
1694 | OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); | |
1695 | OUTREG(MC_DEBUG, rinfo->save_regs[53]); | |
1696 | ||
1697 | OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]); | |
1698 | OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]); | |
1699 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]); | |
1700 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]); | |
1701 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]); | |
1702 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]); | |
1703 | OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]); | |
1704 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]); | |
1705 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]); | |
1706 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]); | |
1707 | OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]); | |
1708 | OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]); | |
1709 | OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); | |
1710 | OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]); | |
1711 | OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]); | |
1712 | OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]); | |
1713 | OUTREG(MC_IND_INDEX, 0); | |
1714 | } | |
1715 | ||
1716 | static void radeon_reinitialize_M10(struct radeonfb_info *rinfo) | |
1717 | { | |
1718 | u32 tmp, i; | |
1719 | ||
1720 | /* Restore a bunch of registers first */ | |
1721 | OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); | |
1722 | OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); | |
1723 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); | |
1724 | OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); | |
1725 | OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); | |
1726 | OUTREG(CONFIG_MEMSIZE, rinfo->video_ram); | |
1727 | OUTREG(BUS_CNTL, rinfo->save_regs[36]); | |
1728 | OUTREG(BUS_CNTL1, rinfo->save_regs[14]); | |
1729 | OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); | |
1730 | OUTREG(FCP_CNTL, rinfo->save_regs[38]); | |
1731 | OUTREG(RBBM_CNTL, rinfo->save_regs[39]); | |
1732 | OUTREG(DAC_CNTL, rinfo->save_regs[40]); | |
1733 | OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); | |
1734 | OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); | |
1735 | ||
1736 | /* Hrm... */ | |
1737 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); | |
1738 | ||
1739 | /* Reset the PAD CTLR */ | |
1740 | radeon_pm_reset_pad_ctlr_strength(rinfo); | |
1741 | ||
1742 | /* Some PLLs are Read & written identically in the trace here... | |
1743 | * I suppose it's actually to switch them all off & reset, | |
1744 | * let's assume off is what we want. I'm just doing that for all major PLLs now. | |
1745 | */ | |
1746 | radeon_pm_all_ppls_off(rinfo); | |
1747 | ||
1748 | /* Clear tiling, reset swappers */ | |
1749 | INREG(SURFACE_CNTL); | |
1750 | OUTREG(SURFACE_CNTL, 0); | |
1751 | ||
1752 | /* Some black magic with TV_DAC_CNTL, we should restore those from backups | |
1753 | * rather than hard coding... | |
1754 | */ | |
1755 | tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; | |
1756 | tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT; | |
1757 | OUTREG(TV_DAC_CNTL, tmp); | |
1758 | ||
1759 | tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; | |
1760 | tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT; | |
1761 | OUTREG(TV_DAC_CNTL, tmp); | |
1762 | ||
1763 | /* More registers restored */ | |
1764 | OUTREG(AGP_CNTL, rinfo->save_regs[16]); | |
1765 | OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); | |
1766 | OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); | |
1767 | ||
1768 | /* Hrmmm ... What is that ? */ | |
1769 | tmp = rinfo->save_regs[1] | |
1770 | & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK | | |
1771 | CLK_PWRMGT_CNTL__MC_BUSY); | |
1772 | OUTPLL(pllCLK_PWRMGT_CNTL, tmp); | |
1773 | ||
1774 | OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]); | |
1775 | OUTREG(FW_CNTL, rinfo->save_regs[57]); | |
1776 | OUTREG(HDP_DEBUG, rinfo->save_regs[96]); | |
1777 | OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); | |
1778 | OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); | |
1779 | OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); | |
1780 | ||
1781 | /* Restore Memory Controller configuration */ | |
1782 | radeon_pm_m10_reconfigure_mc(rinfo); | |
1783 | ||
1784 | /* Make sure CRTC's dont touch memory */ | |
1785 | OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL) | |
1786 | | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B); | |
1787 | OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL) | |
1788 | | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B); | |
1789 | mdelay(30); | |
1790 | ||
1791 | /* Disable SDRAM refresh */ | |
1792 | OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) | |
1793 | | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); | |
1794 | ||
1795 | /* Restore XTALIN routing (CLK_PIN_CNTL) */ | |
1796 | OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); | |
1797 | ||
1798 | /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */ | |
1799 | tmp = rinfo->save_regs[2] & 0xff000000; | |
1800 | tmp |= MCLK_CNTL__FORCE_MCLKA | | |
1801 | MCLK_CNTL__FORCE_MCLKB | | |
1802 | MCLK_CNTL__FORCE_YCLKA | | |
1803 | MCLK_CNTL__FORCE_YCLKB | | |
1804 | MCLK_CNTL__FORCE_MC; | |
1805 | OUTPLL(pllMCLK_CNTL, tmp); | |
1806 | ||
1807 | /* Force all clocks on in SCLK */ | |
1808 | tmp = INPLL(pllSCLK_CNTL); | |
1809 | tmp |= SCLK_CNTL__FORCE_DISP2| | |
1810 | SCLK_CNTL__FORCE_CP| | |
1811 | SCLK_CNTL__FORCE_HDP| | |
1812 | SCLK_CNTL__FORCE_DISP1| | |
1813 | SCLK_CNTL__FORCE_TOP| | |
1814 | SCLK_CNTL__FORCE_E2| | |
1815 | SCLK_CNTL__FORCE_SE| | |
1816 | SCLK_CNTL__FORCE_IDCT| | |
1817 | SCLK_CNTL__FORCE_VIP| | |
1818 | SCLK_CNTL__FORCE_PB| | |
1819 | SCLK_CNTL__FORCE_TAM| | |
1820 | SCLK_CNTL__FORCE_TDM| | |
1821 | SCLK_CNTL__FORCE_RB| | |
1822 | SCLK_CNTL__FORCE_TV_SCLK| | |
1823 | SCLK_CNTL__FORCE_SUBPIC| | |
1824 | SCLK_CNTL__FORCE_OV0; | |
1825 | tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | | |
1826 | SCLK_CNTL__HDP_MAX_DYN_STOP_LAT | | |
1827 | SCLK_CNTL__TV_MAX_DYN_STOP_LAT | | |
1828 | SCLK_CNTL__E2_MAX_DYN_STOP_LAT | | |
1829 | SCLK_CNTL__SE_MAX_DYN_STOP_LAT | | |
1830 | SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT| | |
1831 | SCLK_CNTL__VIP_MAX_DYN_STOP_LAT | | |
1832 | SCLK_CNTL__RE_MAX_DYN_STOP_LAT | | |
1833 | SCLK_CNTL__PB_MAX_DYN_STOP_LAT | | |
1834 | SCLK_CNTL__TAM_MAX_DYN_STOP_LAT | | |
1835 | SCLK_CNTL__TDM_MAX_DYN_STOP_LAT | | |
1836 | SCLK_CNTL__RB_MAX_DYN_STOP_LAT; | |
1837 | OUTPLL(pllSCLK_CNTL, tmp); | |
1838 | ||
1839 | OUTPLL(pllVCLK_ECP_CNTL, 0); | |
1840 | OUTPLL(pllPIXCLKS_CNTL, 0); | |
1841 | OUTPLL(pllMCLK_MISC, | |
1842 | MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT | | |
1843 | MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT); | |
1844 | ||
1845 | mdelay(5); | |
1846 | ||
1847 | /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */ | |
1848 | OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); | |
1849 | OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); | |
1850 | OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); | |
1851 | ||
1852 | /* Now restore the major PLLs settings, keeping them off & reset though */ | |
1853 | OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); | |
1854 | OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); | |
1855 | OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); | |
1856 | OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); | |
1857 | ||
1858 | /* Restore MC DLL state and switch it off/reset too */ | |
1859 | OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); | |
1860 | ||
1861 | /* Switch MDLL off & reset */ | |
1862 | OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff); | |
1863 | mdelay(5); | |
1864 | ||
1865 | /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved | |
1866 | * 0xa1100007... and MacOS writes 0xa1000007 .. | |
1867 | */ | |
1868 | OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]); | |
1869 | ||
1870 | /* Restore more stuffs */ | |
1871 | OUTPLL(pllHTOTAL_CNTL, 0); | |
1872 | OUTPLL(pllHTOTAL2_CNTL, 0); | |
1873 | ||
1874 | /* More PLL initial configuration */ | |
1875 | tmp = INPLL(pllSCLK_CNTL2); /* What for ? */ | |
1876 | OUTPLL(pllSCLK_CNTL2, tmp); | |
1877 | ||
1878 | tmp = INPLL(pllSCLK_MORE_CNTL); | |
1879 | tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */ | |
1880 | SCLK_MORE_CNTL__FORCE_MC_GUI | | |
1881 | SCLK_MORE_CNTL__FORCE_MC_HOST; | |
1882 | OUTPLL(pllSCLK_MORE_CNTL, tmp); | |
1883 | ||
1884 | /* Now we actually start MCLK and SCLK */ | |
1885 | radeon_pm_start_mclk_sclk(rinfo); | |
1886 | ||
1887 | /* Full reset sdrams, this also re-inits the MDLL */ | |
1888 | radeon_pm_full_reset_sdram(rinfo); | |
1889 | ||
1890 | /* Fill palettes */ | |
1891 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); | |
1892 | for (i=0; i<256; i++) | |
1893 | OUTREG(PALETTE_30_DATA, 0x15555555); | |
1894 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); | |
1895 | udelay(20); | |
1896 | for (i=0; i<256; i++) | |
1897 | OUTREG(PALETTE_30_DATA, 0x15555555); | |
1898 | ||
1899 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); | |
1900 | mdelay(3); | |
1901 | ||
1902 | /* Restore TMDS */ | |
1903 | OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]); | |
1904 | OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]); | |
1905 | ||
1906 | /* Set LVDS registers but keep interface & pll down */ | |
1907 | OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & | |
1908 | ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN)); | |
1909 | OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); | |
1910 | ||
1911 | OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]); | |
1912 | ||
1913 | /* Restore GPIOPAD state */ | |
1914 | OUTREG(GPIOPAD_A, rinfo->save_regs[19]); | |
1915 | OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); | |
1916 | OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); | |
1917 | ||
1918 | /* write some stuff to the framebuffer... */ | |
1919 | for (i = 0; i < 0x8000; ++i) | |
1920 | writeb(0, rinfo->fb_base + i); | |
1921 | ||
1922 | mdelay(40); | |
1923 | OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); | |
1924 | mdelay(40); | |
1925 | ||
1926 | /* Restore a few more things */ | |
1927 | OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); | |
1928 | OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); | |
1929 | ||
1930 | /* Take care of spread spectrum & PPLLs now */ | |
1931 | radeon_pm_m10_disable_spread_spectrum(rinfo); | |
1932 | radeon_pm_restore_pixel_pll(rinfo); | |
1933 | ||
1934 | /* GRRRR... I can't figure out the proper LVDS power sequence, and the | |
1935 | * code I have for blank/unblank doesn't quite work on some laptop models | |
1936 | * it seems ... Hrm. What I have here works most of the time ... | |
1937 | */ | |
1938 | radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); | |
1939 | } | |
1940 | ||
a1909e63 CDH |
1941 | #ifdef CONFIG_PPC_OF |
1942 | ||
1da177e4 LT |
1943 | static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo) |
1944 | { | |
1945 | OUTREG(MC_CNTL, rinfo->save_regs[46]); | |
1946 | OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); | |
1947 | OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); | |
1948 | OUTREG(MEM_SDRAM_MODE_REG, | |
1949 | rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); | |
1950 | OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); | |
1951 | OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); | |
1952 | OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); | |
1953 | OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); | |
1954 | OUTREG(MC_DEBUG, rinfo->save_regs[53]); | |
1955 | OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); | |
1956 | ||
1957 | OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/); | |
1958 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/); | |
1959 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/); | |
1960 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/); | |
1961 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/); | |
1962 | OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/); | |
1963 | OUTREG(MC_IND_INDEX, 0); | |
1964 | OUTREG(CONFIG_MEMSIZE, rinfo->video_ram); | |
1965 | ||
1966 | mdelay(20); | |
1967 | } | |
1968 | ||
1969 | static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo) | |
1970 | { | |
1971 | u32 tmp, i; | |
1972 | ||
1973 | /* Restore a bunch of registers first */ | |
1974 | OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); | |
1975 | OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); | |
1976 | OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); | |
1977 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); | |
1978 | OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); | |
1979 | OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); | |
1980 | OUTREG(BUS_CNTL, rinfo->save_regs[36]); | |
1981 | OUTREG(BUS_CNTL1, rinfo->save_regs[14]); | |
1982 | OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); | |
1983 | OUTREG(FCP_CNTL, rinfo->save_regs[38]); | |
1984 | OUTREG(RBBM_CNTL, rinfo->save_regs[39]); | |
1985 | ||
1986 | OUTREG(DAC_CNTL, rinfo->save_regs[40]); | |
1987 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); | |
1988 | ||
1989 | /* Reset the PAD CTLR */ | |
1990 | radeon_pm_reset_pad_ctlr_strength(rinfo); | |
1991 | ||
1992 | /* Some PLLs are Read & written identically in the trace here... | |
1993 | * I suppose it's actually to switch them all off & reset, | |
1994 | * let's assume off is what we want. I'm just doing that for all major PLLs now. | |
1995 | */ | |
1996 | radeon_pm_all_ppls_off(rinfo); | |
1997 | ||
1998 | /* Clear tiling, reset swappers */ | |
1999 | INREG(SURFACE_CNTL); | |
2000 | OUTREG(SURFACE_CNTL, 0); | |
2001 | ||
2002 | /* Some black magic with TV_DAC_CNTL, we should restore those from backups | |
2003 | * rather than hard coding... | |
2004 | */ | |
2005 | tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; | |
2006 | tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT; | |
2007 | OUTREG(TV_DAC_CNTL, tmp); | |
2008 | ||
2009 | tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; | |
2010 | tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT; | |
2011 | OUTREG(TV_DAC_CNTL, tmp); | |
2012 | ||
2013 | OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]); | |
2014 | ||
2015 | OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); | |
2016 | OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); | |
2017 | OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); | |
2018 | ||
2019 | OUTREG(AGP_CNTL, rinfo->save_regs[16]); | |
2020 | OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */ | |
2021 | OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); | |
2022 | ||
2023 | tmp = rinfo->save_regs[1] | |
2024 | & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK | | |
2025 | CLK_PWRMGT_CNTL__MC_BUSY); | |
2026 | OUTPLL(pllCLK_PWRMGT_CNTL, tmp); | |
2027 | ||
2028 | OUTREG(FW_CNTL, rinfo->save_regs[57]); | |
2029 | ||
2030 | /* Disable SDRAM refresh */ | |
2031 | OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) | |
2032 | | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); | |
2033 | ||
2034 | /* Restore XTALIN routing (CLK_PIN_CNTL) */ | |
2035 | OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); | |
2036 | ||
2037 | /* Force MCLK to be PCI sourced and forced ON */ | |
2038 | tmp = rinfo->save_regs[2] & 0xff000000; | |
2039 | tmp |= MCLK_CNTL__FORCE_MCLKA | | |
2040 | MCLK_CNTL__FORCE_MCLKB | | |
2041 | MCLK_CNTL__FORCE_YCLKA | | |
2042 | MCLK_CNTL__FORCE_YCLKB | | |
2043 | MCLK_CNTL__FORCE_MC | | |
2044 | MCLK_CNTL__FORCE_AIC; | |
2045 | OUTPLL(pllMCLK_CNTL, tmp); | |
2046 | ||
2047 | /* Force SCLK to be PCI sourced with a bunch forced */ | |
2048 | tmp = 0 | | |
2049 | SCLK_CNTL__FORCE_DISP2| | |
2050 | SCLK_CNTL__FORCE_CP| | |
2051 | SCLK_CNTL__FORCE_HDP| | |
2052 | SCLK_CNTL__FORCE_DISP1| | |
2053 | SCLK_CNTL__FORCE_TOP| | |
2054 | SCLK_CNTL__FORCE_E2| | |
2055 | SCLK_CNTL__FORCE_SE| | |
2056 | SCLK_CNTL__FORCE_IDCT| | |
2057 | SCLK_CNTL__FORCE_VIP| | |
2058 | SCLK_CNTL__FORCE_RE| | |
2059 | SCLK_CNTL__FORCE_PB| | |
2060 | SCLK_CNTL__FORCE_TAM| | |
2061 | SCLK_CNTL__FORCE_TDM| | |
2062 | SCLK_CNTL__FORCE_RB; | |
2063 | OUTPLL(pllSCLK_CNTL, tmp); | |
2064 | ||
2065 | /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */ | |
2066 | OUTPLL(pllVCLK_ECP_CNTL, 0); | |
2067 | OUTPLL(pllPIXCLKS_CNTL, 0); | |
2068 | ||
2069 | /* Setup MCLK_MISC, non dynamic mode */ | |
2070 | OUTPLL(pllMCLK_MISC, | |
2071 | MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT | | |
2072 | MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT); | |
2073 | ||
2074 | mdelay(5); | |
2075 | ||
2076 | /* Set back the default clock dividers */ | |
2077 | OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); | |
2078 | OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); | |
2079 | OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); | |
2080 | ||
2081 | /* PPLL and P2PLL default values & off */ | |
2082 | OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); | |
2083 | OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); | |
2084 | ||
2085 | /* S and M PLLs are reset & off, configure them */ | |
2086 | OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); | |
2087 | OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); | |
2088 | ||
2089 | /* Default values for MDLL ... fixme */ | |
2090 | OUTPLL(pllMDLL_CKO, 0x9c009c); | |
2091 | OUTPLL(pllMDLL_RDCKA, 0x08830883); | |
2092 | OUTPLL(pllMDLL_RDCKB, 0x08830883); | |
2093 | mdelay(5); | |
2094 | ||
2095 | /* Restore PLL_PWRMGT_CNTL */ // XXXX | |
2096 | tmp = rinfo->save_regs[0]; | |
2097 | tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK; | |
2098 | tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; | |
2099 | OUTPLL(PLL_PWRMGT_CNTL, tmp); | |
2100 | ||
2101 | /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */ | |
2102 | OUTPLL(pllHTOTAL_CNTL, 0); | |
2103 | OUTPLL(pllHTOTAL2_CNTL, 0); | |
2104 | ||
2105 | /* All outputs off */ | |
2106 | OUTREG(CRTC_GEN_CNTL, 0x04000000); | |
2107 | OUTREG(CRTC2_GEN_CNTL, 0x04000000); | |
2108 | OUTREG(FP_GEN_CNTL, 0x00004008); | |
2109 | OUTREG(FP2_GEN_CNTL, 0x00000008); | |
2110 | OUTREG(LVDS_GEN_CNTL, 0x08000008); | |
2111 | ||
2112 | /* Restore Memory Controller configuration */ | |
2113 | radeon_pm_m9p_reconfigure_mc(rinfo); | |
2114 | ||
2115 | /* Now we actually start MCLK and SCLK */ | |
2116 | radeon_pm_start_mclk_sclk(rinfo); | |
2117 | ||
2118 | /* Full reset sdrams, this also re-inits the MDLL */ | |
2119 | radeon_pm_full_reset_sdram(rinfo); | |
2120 | ||
2121 | /* Fill palettes */ | |
2122 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); | |
2123 | for (i=0; i<256; i++) | |
2124 | OUTREG(PALETTE_30_DATA, 0x15555555); | |
2125 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); | |
2126 | udelay(20); | |
2127 | for (i=0; i<256; i++) | |
2128 | OUTREG(PALETTE_30_DATA, 0x15555555); | |
2129 | ||
2130 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); | |
2131 | mdelay(3); | |
2132 | ||
2133 | /* Restore TV stuff, make sure TV DAC is down */ | |
2134 | OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]); | |
2135 | OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000); | |
2136 | ||
2137 | /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits, | |
2138 | * possibly related to the weird PLL related workarounds and to the | |
2139 | * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand, | |
2140 | * but we keep things the simple way here | |
2141 | */ | |
2142 | OUTREG(GPIOPAD_A, rinfo->save_regs[19]); | |
2143 | OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); | |
2144 | OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); | |
2145 | ||
2146 | /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy | |
2147 | * high bits from backup | |
2148 | */ | |
2149 | tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; | |
2150 | tmp |= rinfo->save_regs[34] & 0xffff0000; | |
2151 | tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; | |
2152 | OUTPLL(pllSCLK_MORE_CNTL, tmp); | |
2153 | ||
2154 | tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; | |
2155 | tmp |= rinfo->save_regs[34] & 0xffff0000; | |
2156 | tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; | |
2157 | OUTPLL(pllSCLK_MORE_CNTL, tmp); | |
2158 | ||
2159 | OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & | |
2160 | ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN)); | |
2161 | OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON); | |
2162 | OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); | |
2163 | mdelay(20); | |
2164 | ||
2165 | /* write some stuff to the framebuffer... */ | |
2166 | for (i = 0; i < 0x8000; ++i) | |
2167 | writeb(0, rinfo->fb_base + i); | |
2168 | ||
2169 | OUTREG(0x2ec, 0x6332a020); | |
2170 | OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */); | |
2171 | OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */); | |
2172 | tmp = INPLL(pllSSPLL_CNTL); | |
2173 | tmp &= ~2; | |
2174 | OUTPLL(pllSSPLL_CNTL, tmp); | |
2175 | mdelay(6); | |
2176 | tmp &= ~1; | |
2177 | OUTPLL(pllSSPLL_CNTL, tmp); | |
2178 | mdelay(5); | |
2179 | tmp |= 3; | |
2180 | OUTPLL(pllSSPLL_CNTL, tmp); | |
2181 | mdelay(5); | |
2182 | ||
2183 | OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/ | |
2184 | OUTREG(0x2ec, 0x6332a3f0); | |
2185 | mdelay(17); | |
2186 | ||
53b3531b | 2187 | OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div); |
1da177e4 LT |
2188 | OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); |
2189 | ||
2190 | mdelay(40); | |
2191 | OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); | |
2192 | mdelay(40); | |
2193 | ||
2194 | /* Restore a few more things */ | |
2195 | OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); | |
2196 | OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); | |
2197 | ||
2198 | /* Restore PPLL, spread spectrum & LVDS */ | |
2199 | radeon_pm_m10_disable_spread_spectrum(rinfo); | |
2200 | radeon_pm_restore_pixel_pll(rinfo); | |
2201 | radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); | |
2202 | } | |
2203 | ||
2204 | #if 0 /* Not ready yet */ | |
2205 | static void radeon_reinitialize_QW(struct radeonfb_info *rinfo) | |
2206 | { | |
2207 | int i; | |
2208 | u32 tmp, tmp2; | |
2209 | u32 cko, cka, ckb; | |
2210 | u32 cgc, cec, c2gc; | |
2211 | ||
2212 | OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); | |
2213 | OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); | |
2214 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); | |
2215 | OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); | |
2216 | OUTREG(BUS_CNTL, rinfo->save_regs[36]); | |
2217 | OUTREG(RBBM_CNTL, rinfo->save_regs[39]); | |
2218 | ||
2219 | INREG(PAD_CTLR_STRENGTH); | |
2220 | OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000); | |
2221 | for (i = 0; i < 65; ++i) { | |
2222 | mdelay(1); | |
2223 | INREG(PAD_CTLR_STRENGTH); | |
2224 | } | |
2225 | ||
2226 | OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000); | |
2227 | OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100); | |
2228 | OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)); | |
2229 | OUTREG(DAC_CNTL, 0xff00410a); | |
2230 | OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)); | |
2231 | OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000); | |
2232 | ||
2233 | OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); | |
2234 | OUTREG(AGP_CNTL, rinfo->save_regs[16]); | |
2235 | OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); | |
2236 | OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); | |
2237 | ||
2238 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433); | |
2239 | OUTREG(MC_IND_INDEX, 0); | |
2240 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433); | |
2241 | OUTREG(MC_IND_INDEX, 0); | |
2242 | ||
2243 | OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL)); | |
2244 | ||
2245 | tmp = INPLL(pllVCLK_ECP_CNTL); | |
2246 | OUTPLL(pllVCLK_ECP_CNTL, tmp); | |
2247 | tmp = INPLL(pllPIXCLKS_CNTL); | |
2248 | OUTPLL(pllPIXCLKS_CNTL, tmp); | |
2249 | ||
2250 | OUTPLL(MCLK_CNTL, 0xaa3f0000); | |
2251 | OUTPLL(SCLK_CNTL, 0xffff0000); | |
2252 | OUTPLL(pllMPLL_AUX_CNTL, 6); | |
2253 | OUTPLL(pllSPLL_AUX_CNTL, 1); | |
2254 | OUTPLL(MDLL_CKO, 0x9f009f); | |
2255 | OUTPLL(MDLL_RDCKA, 0x830083); | |
2256 | OUTPLL(pllMDLL_RDCKB, 0x830083); | |
2257 | OUTPLL(PPLL_CNTL, 0xa433); | |
2258 | OUTPLL(P2PLL_CNTL, 0xa433); | |
2259 | OUTPLL(MPLL_CNTL, 0x0400a403); | |
2260 | OUTPLL(SPLL_CNTL, 0x0400a433); | |
2261 | ||
2262 | tmp = INPLL(M_SPLL_REF_FB_DIV); | |
2263 | OUTPLL(M_SPLL_REF_FB_DIV, tmp); | |
2264 | tmp = INPLL(M_SPLL_REF_FB_DIV); | |
2265 | OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc); | |
2266 | INPLL(M_SPLL_REF_FB_DIV); | |
2267 | ||
2268 | tmp = INPLL(MPLL_CNTL); | |
2269 | OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN); | |
2270 | radeon_pll_errata_after_index(rinfo); | |
2271 | OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); | |
2272 | radeon_pll_errata_after_data(rinfo); | |
2273 | ||
2274 | tmp = INPLL(M_SPLL_REF_FB_DIV); | |
2275 | OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900); | |
2276 | ||
2277 | tmp = INPLL(MPLL_CNTL); | |
2278 | OUTPLL(MPLL_CNTL, tmp & ~0x2); | |
2279 | mdelay(1); | |
2280 | tmp = INPLL(MPLL_CNTL); | |
2281 | OUTPLL(MPLL_CNTL, tmp & ~0x1); | |
2282 | mdelay(10); | |
2283 | ||
2284 | OUTPLL(MCLK_CNTL, 0xaa3f1212); | |
2285 | mdelay(1); | |
2286 | ||
2287 | INPLL(M_SPLL_REF_FB_DIV); | |
2288 | INPLL(MCLK_CNTL); | |
2289 | INPLL(M_SPLL_REF_FB_DIV); | |
2290 | ||
2291 | tmp = INPLL(SPLL_CNTL); | |
2292 | OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN); | |
2293 | radeon_pll_errata_after_index(rinfo); | |
2294 | OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); | |
2295 | radeon_pll_errata_after_data(rinfo); | |
2296 | ||
2297 | tmp = INPLL(M_SPLL_REF_FB_DIV); | |
2298 | OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000); | |
2299 | ||
2300 | tmp = INPLL(SPLL_CNTL); | |
2301 | OUTPLL(SPLL_CNTL, tmp & ~0x1); | |
2302 | mdelay(1); | |
2303 | tmp = INPLL(SPLL_CNTL); | |
2304 | OUTPLL(SPLL_CNTL, tmp & ~0x2); | |
2305 | mdelay(10); | |
2306 | ||
2307 | tmp = INPLL(SCLK_CNTL); | |
2308 | OUTPLL(SCLK_CNTL, tmp | 2); | |
2309 | mdelay(1); | |
2310 | ||
2311 | cko = INPLL(pllMDLL_CKO); | |
2312 | cka = INPLL(pllMDLL_RDCKA); | |
2313 | ckb = INPLL(pllMDLL_RDCKB); | |
2314 | ||
2315 | cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP); | |
2316 | OUTPLL(pllMDLL_CKO, cko); | |
2317 | mdelay(1); | |
2318 | cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET); | |
2319 | OUTPLL(pllMDLL_CKO, cko); | |
2320 | mdelay(5); | |
2321 | ||
2322 | cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP); | |
2323 | OUTPLL(pllMDLL_RDCKA, cka); | |
2324 | mdelay(1); | |
2325 | cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET); | |
2326 | OUTPLL(pllMDLL_RDCKA, cka); | |
2327 | mdelay(5); | |
2328 | ||
2329 | ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP); | |
2330 | OUTPLL(pllMDLL_RDCKB, ckb); | |
2331 | mdelay(1); | |
2332 | ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET); | |
2333 | OUTPLL(pllMDLL_RDCKB, ckb); | |
2334 | mdelay(5); | |
2335 | ||
2336 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff); | |
2337 | OUTREG(MC_IND_INDEX, 0); | |
2338 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff); | |
2339 | OUTREG(MC_IND_INDEX, 0); | |
2340 | mdelay(1); | |
2341 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff); | |
2342 | OUTREG(MC_IND_INDEX, 0); | |
2343 | OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff); | |
2344 | OUTREG(MC_IND_INDEX, 0); | |
2345 | mdelay(1); | |
2346 | ||
2347 | OUTPLL(pllHTOTAL_CNTL, 0); | |
2348 | OUTPLL(pllHTOTAL2_CNTL, 0); | |
2349 | ||
2350 | OUTREG(MEM_CNTL, 0x29002901); | |
2351 | OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */ | |
2352 | OUTREG(EXT_MEM_CNTL, 0x1a394333); | |
2353 | OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac); | |
2354 | OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444); | |
2355 | OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */ | |
2356 | OUTREG(MC_DEBUG, 0); | |
2357 | OUTREG(MEM_IO_OE_CNTL, 0x04300430); | |
2358 | ||
2359 | OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6); | |
2360 | OUTREG(MC_IND_INDEX, 0); | |
2361 | OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249); | |
2362 | OUTREG(MC_IND_INDEX, 0); | |
2363 | ||
2364 | OUTREG(CONFIG_MEMSIZE, rinfo->video_ram); | |
2365 | ||
2366 | radeon_pm_full_reset_sdram(rinfo); | |
2367 | ||
2368 | INREG(FP_GEN_CNTL); | |
2369 | OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */ | |
2370 | tmp = INREG(FP_GEN_CNTL); | |
2371 | tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200; | |
2372 | OUTREG(FP_GEN_CNTL, tmp); | |
2373 | ||
2374 | tmp = INREG(DISP_OUTPUT_CNTL); | |
2375 | tmp &= ~0x400; | |
2376 | OUTREG(DISP_OUTPUT_CNTL, tmp); | |
2377 | ||
2378 | OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]); | |
2379 | OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]); | |
2380 | OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]); | |
2381 | ||
2382 | tmp = INPLL(MCLK_MISC); | |
2383 | tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE; | |
2384 | OUTPLL(MCLK_MISC, tmp); | |
2385 | ||
2386 | tmp = INPLL(SCLK_CNTL); | |
2387 | OUTPLL(SCLK_CNTL, tmp); | |
2388 | ||
2389 | OUTREG(CRTC_MORE_CNTL, 0); | |
2390 | OUTREG8(CRTC_GEN_CNTL+1, 6); | |
2391 | OUTREG8(CRTC_GEN_CNTL+3, 1); | |
2392 | OUTREG(CRTC_PITCH, 32); | |
2393 | ||
2394 | tmp = INPLL(VCLK_ECP_CNTL); | |
2395 | OUTPLL(VCLK_ECP_CNTL, tmp); | |
2396 | ||
2397 | tmp = INPLL(PPLL_CNTL); | |
2398 | OUTPLL(PPLL_CNTL, tmp); | |
2399 | ||
2400 | /* palette stuff and BIOS_1_SCRATCH... */ | |
2401 | ||
2402 | tmp = INREG(FP_GEN_CNTL); | |
2403 | tmp2 = INREG(TMDS_TRANSMITTER_CNTL); | |
2404 | tmp |= 2; | |
2405 | OUTREG(FP_GEN_CNTL, tmp); | |
2406 | mdelay(5); | |
2407 | OUTREG(FP_GEN_CNTL, tmp); | |
2408 | mdelay(5); | |
2409 | OUTREG(TMDS_TRANSMITTER_CNTL, tmp2); | |
2410 | OUTREG(CRTC_MORE_CNTL, 0); | |
2411 | mdelay(20); | |
2412 | ||
2413 | tmp = INREG(CRTC_MORE_CNTL); | |
2414 | OUTREG(CRTC_MORE_CNTL, tmp); | |
2415 | ||
2416 | cgc = INREG(CRTC_GEN_CNTL); | |
2417 | cec = INREG(CRTC_EXT_CNTL); | |
2418 | c2gc = INREG(CRTC2_GEN_CNTL); | |
2419 | ||
2420 | OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580); | |
2421 | OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2); | |
2422 | OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN); | |
2423 | radeon_pll_errata_after_index(rinfo); | |
2424 | OUTREG8(CLOCK_CNTL_DATA, 0); | |
2425 | radeon_pll_errata_after_data(rinfo); | |
2426 | OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403); | |
2427 | OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429); | |
2428 | OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033); | |
2429 | OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080); | |
2430 | OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080); | |
2431 | OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a); | |
2432 | OUTREG(FP_V_SYNC_STRT_WID, 0x00830004); | |
2433 | OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004); | |
2434 | OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff); | |
2435 | OUTREG(FP_HORZ_STRETCH, 0); | |
2436 | OUTREG(FP_VERT_STRETCH, 0); | |
2437 | OUTREG(OVR_CLR, 0); | |
2438 | OUTREG(OVR_WID_LEFT_RIGHT, 0); | |
2439 | OUTREG(OVR_WID_TOP_BOTTOM, 0); | |
2440 | ||
2441 | tmp = INPLL(PPLL_REF_DIV); | |
2442 | tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; | |
2443 | OUTPLL(PPLL_REF_DIV, tmp); | |
2444 | INPLL(PPLL_REF_DIV); | |
2445 | ||
2446 | OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN); | |
2447 | radeon_pll_errata_after_index(rinfo); | |
2448 | OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc); | |
2449 | radeon_pll_errata_after_data(rinfo); | |
2450 | ||
2451 | tmp = INREG(CLOCK_CNTL_INDEX); | |
2452 | radeon_pll_errata_after_index(rinfo); | |
2453 | OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff); | |
2454 | radeon_pll_errata_after_index(rinfo); | |
2455 | radeon_pll_errata_after_data(rinfo); | |
2456 | ||
2457 | OUTPLL(PPLL_DIV_0, 0x48090); | |
2458 | ||
2459 | tmp = INPLL(PPLL_CNTL); | |
2460 | OUTPLL(PPLL_CNTL, tmp & ~0x2); | |
2461 | mdelay(1); | |
2462 | tmp = INPLL(PPLL_CNTL); | |
2463 | OUTPLL(PPLL_CNTL, tmp & ~0x1); | |
2464 | mdelay(10); | |
2465 | ||
2466 | tmp = INPLL(VCLK_ECP_CNTL); | |
2467 | OUTPLL(VCLK_ECP_CNTL, tmp | 3); | |
2468 | mdelay(1); | |
2469 | ||
2470 | tmp = INPLL(VCLK_ECP_CNTL); | |
2471 | OUTPLL(VCLK_ECP_CNTL, tmp); | |
2472 | ||
2473 | c2gc |= CRTC2_DISP_REQ_EN_B; | |
2474 | OUTREG(CRTC2_GEN_CNTL, c2gc); | |
2475 | cgc |= CRTC_EN; | |
2476 | OUTREG(CRTC_GEN_CNTL, cgc); | |
2477 | OUTREG(CRTC_EXT_CNTL, cec); | |
2478 | OUTREG(CRTC_PITCH, 0xa0); | |
2479 | OUTREG(CRTC_OFFSET, 0); | |
2480 | OUTREG(CRTC_OFFSET_CNTL, 0); | |
2481 | ||
2482 | OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c); | |
2483 | OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c); | |
2484 | ||
2485 | tmp2 = INREG(FP_GEN_CNTL); | |
2486 | tmp = INREG(TMDS_TRANSMITTER_CNTL); | |
2487 | OUTREG(0x2a8, 0x0000061b); | |
2488 | tmp |= TMDS_PLL_EN; | |
2489 | OUTREG(TMDS_TRANSMITTER_CNTL, tmp); | |
2490 | mdelay(1); | |
2491 | tmp &= ~TMDS_PLLRST; | |
2492 | OUTREG(TMDS_TRANSMITTER_CNTL, tmp); | |
2493 | tmp2 &= ~2; | |
2494 | tmp2 |= FP_TMDS_EN; | |
2495 | OUTREG(FP_GEN_CNTL, tmp2); | |
2496 | mdelay(5); | |
2497 | tmp2 |= FP_FPON; | |
2498 | OUTREG(FP_GEN_CNTL, tmp2); | |
2499 | ||
2500 | OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1); | |
2501 | cgc = INREG(CRTC_GEN_CNTL); | |
2502 | OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff); | |
2503 | cgc |= 0x10000; | |
2504 | OUTREG(CUR_OFFSET, 0); | |
2505 | } | |
2506 | #endif /* 0 */ | |
2507 | ||
2508 | #endif /* CONFIG_PPC_OF */ | |
2509 | ||
2510 | static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend) | |
2511 | { | |
2512 | u16 pwr_cmd; | |
2513 | u32 tmp; | |
2514 | int i; | |
2515 | ||
2516 | if (!rinfo->pm_reg) | |
2517 | return; | |
2518 | ||
2519 | /* Set the chip into appropriate suspend mode (we use D2, | |
2520 | * D3 would require a compete re-initialization of the chip, | |
2521 | * including PCI config registers, clocks, AGP conf, ...) | |
2522 | */ | |
2523 | if (suspend) { | |
2524 | printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n", | |
2525 | pci_name(rinfo->pdev)); | |
2526 | ||
2527 | /* Disable dynamic power management of clocks for the | |
2528 | * duration of the suspend/resume process | |
2529 | */ | |
2530 | radeon_pm_disable_dynamic_mode(rinfo); | |
2531 | ||
2532 | /* Save some registers */ | |
2533 | radeon_pm_save_regs(rinfo, 0); | |
2534 | ||
2535 | /* Prepare mobility chips for suspend. | |
2536 | */ | |
2537 | if (rinfo->is_mobility) { | |
2538 | /* Program V2CLK */ | |
2539 | radeon_pm_program_v2clk(rinfo); | |
2540 | ||
2541 | /* Disable IO PADs */ | |
2542 | radeon_pm_disable_iopad(rinfo); | |
2543 | ||
2544 | /* Set low current */ | |
2545 | radeon_pm_low_current(rinfo); | |
2546 | ||
2547 | /* Prepare chip for power management */ | |
2548 | radeon_pm_setup_for_suspend(rinfo); | |
2549 | ||
2550 | if (rinfo->family <= CHIP_FAMILY_RV280) { | |
2551 | /* Reset the MDLL */ | |
2552 | /* because both INPLL and OUTPLL take the same | |
2553 | * lock, that's why. */ | |
2554 | tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET | |
2555 | | MDLL_CKO__MCKOB_RESET; | |
2556 | OUTPLL( pllMDLL_CKO, tmp ); | |
2557 | } | |
2558 | } | |
2559 | ||
2560 | for (i = 0; i < 64; ++i) | |
2561 | pci_read_config_dword(rinfo->pdev, i * 4, | |
2562 | &rinfo->cfg_save[i]); | |
2563 | ||
2564 | /* Switch PCI power managment to D2. */ | |
2565 | pci_disable_device(rinfo->pdev); | |
2566 | for (;;) { | |
2567 | pci_read_config_word( | |
2568 | rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, | |
2569 | &pwr_cmd); | |
2570 | if (pwr_cmd & 2) | |
2571 | break; | |
2572 | pci_write_config_word( | |
2573 | rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, | |
2574 | (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2); | |
2575 | mdelay(500); | |
2576 | } | |
2577 | } else { | |
2578 | printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n", | |
2579 | pci_name(rinfo->pdev)); | |
2580 | ||
2581 | /* Switch back PCI powermanagment to D0 */ | |
2582 | mdelay(200); | |
2583 | pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0); | |
2584 | mdelay(500); | |
2585 | ||
2586 | if (rinfo->family <= CHIP_FAMILY_RV250) { | |
2587 | /* Reset the SDRAM controller */ | |
2588 | radeon_pm_full_reset_sdram(rinfo); | |
2589 | ||
2590 | /* Restore some registers */ | |
2591 | radeon_pm_restore_regs(rinfo); | |
2592 | } else { | |
2593 | /* Restore registers first */ | |
2594 | radeon_pm_restore_regs(rinfo); | |
2595 | /* init sdram controller */ | |
2596 | radeon_pm_full_reset_sdram(rinfo); | |
2597 | } | |
2598 | } | |
2599 | } | |
2600 | ||
2601 | static int radeon_restore_pci_cfg(struct radeonfb_info *rinfo) | |
2602 | { | |
2603 | int i; | |
2604 | static u32 radeon_cfg_after_resume[64]; | |
2605 | ||
2606 | for (i = 0; i < 64; ++i) | |
2607 | pci_read_config_dword(rinfo->pdev, i * 4, | |
2608 | &radeon_cfg_after_resume[i]); | |
2609 | ||
2610 | if (radeon_cfg_after_resume[PCI_BASE_ADDRESS_0/4] | |
2611 | == rinfo->cfg_save[PCI_BASE_ADDRESS_0/4]) | |
2612 | return 0; /* assume everything is ok */ | |
2613 | ||
2614 | for (i = PCI_BASE_ADDRESS_0/4; i < 64; ++i) { | |
2615 | if (radeon_cfg_after_resume[i] != rinfo->cfg_save[i]) | |
2616 | pci_write_config_dword(rinfo->pdev, i * 4, | |
2617 | rinfo->cfg_save[i]); | |
2618 | } | |
2619 | pci_write_config_word(rinfo->pdev, PCI_CACHE_LINE_SIZE, | |
2620 | rinfo->cfg_save[PCI_CACHE_LINE_SIZE/4]); | |
2621 | pci_write_config_word(rinfo->pdev, PCI_COMMAND, | |
2622 | rinfo->cfg_save[PCI_COMMAND/4]); | |
2623 | return 1; | |
2624 | } | |
2625 | ||
2626 | ||
c78a7c2d | 2627 | int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) |
1da177e4 LT |
2628 | { |
2629 | struct fb_info *info = pci_get_drvdata(pdev); | |
2630 | struct radeonfb_info *rinfo = info->par; | |
1da177e4 LT |
2631 | int i; |
2632 | ||
c78a7c2d | 2633 | if (mesg.event == pdev->dev.power.power_state.event) |
1da177e4 LT |
2634 | return 0; |
2635 | ||
c78a7c2d DB |
2636 | printk(KERN_DEBUG "radeonfb (%s): suspending for event: %d...\n", |
2637 | pci_name(pdev), mesg.event); | |
1da177e4 LT |
2638 | |
2639 | /* For suspend-to-disk, we cheat here. We don't suspend anything and | |
2640 | * let fbcon continue drawing until we are all set. That shouldn't | |
2641 | * really cause any problem at this point, provided that the wakeup | |
2642 | * code knows that any state in memory may not match the HW | |
2643 | */ | |
c78a7c2d DB |
2644 | switch (mesg.event) { |
2645 | case PM_EVENT_FREEZE: /* about to take snapshot */ | |
2646 | case PM_EVENT_PRETHAW: /* before restoring snapshot */ | |
1da177e4 | 2647 | goto done; |
c78a7c2d | 2648 | } |
1da177e4 LT |
2649 | |
2650 | acquire_console_sem(); | |
2651 | ||
2652 | fb_set_suspend(info, 1); | |
2653 | ||
2654 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { | |
2655 | /* Make sure engine is reset */ | |
2656 | radeon_engine_idle(); | |
2657 | radeonfb_engine_reset(rinfo); | |
2658 | radeon_engine_idle(); | |
2659 | } | |
2660 | ||
2661 | /* Blank display and LCD */ | |
2662 | radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1); | |
2663 | ||
2664 | /* Sleep */ | |
2665 | rinfo->asleep = 1; | |
2666 | rinfo->lock_blank = 1; | |
2667 | del_timer_sync(&rinfo->lvds_timer); | |
2668 | ||
0c541b44 BH |
2669 | #ifdef CONFIG_PPC_PMAC |
2670 | /* On powermac, we have hooks to properly suspend/resume AGP now, | |
2671 | * use them here. We'll ultimately need some generic support here, | |
2672 | * but the generic code isn't quite ready for that yet | |
1da177e4 | 2673 | */ |
0c541b44 BH |
2674 | pmac_suspend_agp_for_card(pdev); |
2675 | #endif /* CONFIG_PPC_PMAC */ | |
1da177e4 LT |
2676 | |
2677 | /* If we support wakeup from poweroff, we save all regs we can including cfg | |
2678 | * space | |
2679 | */ | |
2680 | if (rinfo->pm_mode & radeon_pm_off) { | |
2681 | /* Always disable dynamic clocks or weird things are happening when | |
2682 | * the chip goes off (basically the panel doesn't shut down properly | |
2683 | * and we crash on wakeup), | |
2684 | * also, we want the saved regs context to have no dynamic clocks in | |
2685 | * it, we'll restore the dynamic clocks state on wakeup | |
2686 | */ | |
2687 | radeon_pm_disable_dynamic_mode(rinfo); | |
2688 | mdelay(50); | |
2689 | radeon_pm_save_regs(rinfo, 1); | |
2690 | ||
2691 | if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) { | |
2692 | /* Switch off LVDS interface */ | |
2693 | mdelay(1); | |
2694 | OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN)); | |
2695 | mdelay(1); | |
2696 | OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON)); | |
2697 | OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000); | |
2698 | mdelay(20); | |
2699 | OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON)); | |
2700 | } | |
2701 | // FIXME: Use PCI layer | |
2702 | for (i = 0; i < 64; ++i) | |
2703 | pci_read_config_dword(pdev, i * 4, &rinfo->cfg_save[i]); | |
2704 | pci_disable_device(pdev); | |
2705 | } | |
2706 | /* If we support D2, we go to it (should be fixed later with a flag forcing | |
2707 | * D3 only for some laptops) | |
2708 | */ | |
2709 | if (rinfo->pm_mode & radeon_pm_d2) | |
2710 | radeon_set_suspend(rinfo, 1); | |
2711 | ||
2712 | release_console_sem(); | |
2713 | ||
2714 | done: | |
c78a7c2d | 2715 | pdev->dev.power.power_state = mesg; |
1da177e4 LT |
2716 | |
2717 | return 0; | |
2718 | } | |
2719 | ||
2720 | int radeonfb_pci_resume(struct pci_dev *pdev) | |
2721 | { | |
2722 | struct fb_info *info = pci_get_drvdata(pdev); | |
2723 | struct radeonfb_info *rinfo = info->par; | |
2724 | int rc = 0; | |
2725 | ||
ca078bae | 2726 | if (pdev->dev.power.power_state.event == PM_EVENT_ON) |
1da177e4 LT |
2727 | return 0; |
2728 | ||
2729 | if (rinfo->no_schedule) { | |
2730 | if (try_acquire_console_sem()) | |
2731 | return 0; | |
2732 | } else | |
2733 | acquire_console_sem(); | |
2734 | ||
2735 | printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n", | |
ca078bae | 2736 | pci_name(pdev), pdev->dev.power.power_state.event); |
1da177e4 LT |
2737 | |
2738 | ||
2739 | if (pci_enable_device(pdev)) { | |
2740 | rc = -ENODEV; | |
2741 | printk(KERN_ERR "radeonfb (%s): can't enable PCI device !\n", | |
2742 | pci_name(pdev)); | |
2743 | goto bail; | |
2744 | } | |
2745 | pci_set_master(pdev); | |
2746 | ||
ca078bae | 2747 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
1da177e4 LT |
2748 | /* Wakeup chip. Check from config space if we were powered off |
2749 | * (todo: additionally, check CLK_PIN_CNTL too) | |
2750 | */ | |
2751 | if ((rinfo->pm_mode & radeon_pm_off) && radeon_restore_pci_cfg(rinfo)) { | |
2752 | if (rinfo->reinit_func != NULL) | |
2753 | rinfo->reinit_func(rinfo); | |
2754 | else { | |
2755 | printk(KERN_ERR "radeonfb (%s): can't resume radeon from" | |
2756 | " D3 cold, need softboot !", pci_name(pdev)); | |
2757 | rc = -EIO; | |
2758 | goto bail; | |
2759 | } | |
2760 | } | |
2761 | /* If we support D2, try to resume... we should check what was our | |
2762 | * state though... (were we really in D2 state ?). Right now, this code | |
2763 | * is only enable on Macs so it's fine. | |
2764 | */ | |
2765 | else if (rinfo->pm_mode & radeon_pm_d2) | |
2766 | radeon_set_suspend(rinfo, 0); | |
2767 | ||
2768 | rinfo->asleep = 0; | |
2769 | } else | |
2770 | radeon_engine_idle(); | |
2771 | ||
2772 | /* Restore display & engine */ | |
2773 | radeon_write_mode (rinfo, &rinfo->state, 1); | |
2774 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
2775 | radeonfb_engine_init (rinfo); | |
2776 | ||
2777 | fb_pan_display(info, &info->var); | |
2778 | fb_set_cmap(&info->cmap, info); | |
2779 | ||
2780 | /* Refresh */ | |
2781 | fb_set_suspend(info, 0); | |
2782 | ||
2783 | /* Unblank */ | |
2784 | rinfo->lock_blank = 0; | |
2785 | radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1); | |
2786 | ||
0c541b44 BH |
2787 | #ifdef CONFIG_PPC_PMAC |
2788 | /* On powermac, we have hooks to properly suspend/resume AGP now, | |
2789 | * use them here. We'll ultimately need some generic support here, | |
2790 | * but the generic code isn't quite ready for that yet | |
2791 | */ | |
2792 | pmac_resume_agp_for_card(pdev); | |
2793 | #endif /* CONFIG_PPC_PMAC */ | |
2794 | ||
2795 | ||
1da177e4 LT |
2796 | /* Check status of dynclk */ |
2797 | if (rinfo->dynclk == 1) | |
2798 | radeon_pm_enable_dynamic_mode(rinfo); | |
2799 | else if (rinfo->dynclk == 0) | |
2800 | radeon_pm_disable_dynamic_mode(rinfo); | |
2801 | ||
2802 | pdev->dev.power.power_state = PMSG_ON; | |
2803 | ||
2804 | bail: | |
2805 | release_console_sem(); | |
2806 | ||
2807 | return rc; | |
2808 | } | |
2809 | ||
2810 | #ifdef CONFIG_PPC_OF | |
2811 | static void radeonfb_early_resume(void *data) | |
2812 | { | |
2813 | struct radeonfb_info *rinfo = data; | |
2814 | ||
2815 | rinfo->no_schedule = 1; | |
2816 | radeonfb_pci_resume(rinfo->pdev); | |
2817 | rinfo->no_schedule = 0; | |
2818 | } | |
2819 | #endif /* CONFIG_PPC_OF */ | |
2820 | ||
2821 | #endif /* CONFIG_PM */ | |
2822 | ||
994aad25 | 2823 | void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep) |
1da177e4 LT |
2824 | { |
2825 | /* Find PM registers in config space if any*/ | |
2826 | rinfo->pm_reg = pci_find_capability(rinfo->pdev, PCI_CAP_ID_PM); | |
2827 | ||
2828 | /* Enable/Disable dynamic clocks: TODO add sysfs access */ | |
2829 | rinfo->dynclk = dynclk; | |
2830 | if (dynclk == 1) { | |
2831 | radeon_pm_enable_dynamic_mode(rinfo); | |
2832 | printk("radeonfb: Dynamic Clock Power Management enabled\n"); | |
2833 | } else if (dynclk == 0) { | |
2834 | radeon_pm_disable_dynamic_mode(rinfo); | |
2835 | printk("radeonfb: Dynamic Clock Power Management disabled\n"); | |
2836 | } | |
2837 | ||
a1909e63 | 2838 | #if defined(CONFIG_PM) |
994aad25 | 2839 | #if defined(CONFIG_PPC_PMAC) |
1da177e4 LT |
2840 | /* Check if we can power manage on suspend/resume. We can do |
2841 | * D2 on M6, M7 and M9, and we can resume from D3 cold a few other | |
2842 | * "Mac" cards, but that's all. We need more infos about what the | |
2843 | * BIOS does tho. Right now, all this PM stuff is pmac-only for that | |
2844 | * reason. --BenH | |
2845 | */ | |
e8222502 | 2846 | if (machine_is(powermac) && rinfo->of_node) { |
1da177e4 LT |
2847 | if (rinfo->is_mobility && rinfo->pm_reg && |
2848 | rinfo->family <= CHIP_FAMILY_RV250) | |
2849 | rinfo->pm_mode |= radeon_pm_d2; | |
2850 | ||
2851 | /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip | |
14bfd1ff SH |
2852 | * in some desktop G4s), Via (M9+ chip on iBook G4) and |
2853 | * Snowy (M11 chip on iBook G4 manufactured after July 2005) | |
1da177e4 | 2854 | */ |
14bfd1ff SH |
2855 | if (!strcmp(rinfo->of_node->name, "ATY,JasperParent") || |
2856 | !strcmp(rinfo->of_node->name, "ATY,SnowyParent")) { | |
1da177e4 LT |
2857 | rinfo->reinit_func = radeon_reinitialize_M10; |
2858 | rinfo->pm_mode |= radeon_pm_off; | |
2859 | } | |
2860 | #if 0 /* Not ready yet */ | |
2861 | if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) { | |
2862 | rinfo->reinit_func = radeon_reinitialize_QW; | |
2863 | rinfo->pm_mode |= radeon_pm_off; | |
2864 | } | |
2865 | #endif | |
2866 | if (!strcmp(rinfo->of_node->name, "ATY,ViaParent")) { | |
2867 | rinfo->reinit_func = radeon_reinitialize_M9P; | |
2868 | rinfo->pm_mode |= radeon_pm_off; | |
2869 | } | |
2870 | ||
2871 | /* If any of the above is set, we assume the machine can sleep/resume. | |
2872 | * It's a bit of a "shortcut" but will work fine. Ideally, we need infos | |
2873 | * from the platform about what happens to the chip... | |
2874 | * Now we tell the platform about our capability | |
2875 | */ | |
2876 | if (rinfo->pm_mode != radeon_pm_none) { | |
2877 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1); | |
2878 | pmac_set_early_video_resume(radeonfb_early_resume, rinfo); | |
2879 | } | |
2880 | ||
2881 | #if 0 | |
2882 | /* Power down TV DAC, taht saves a significant amount of power, | |
2883 | * we'll have something better once we actually have some TVOut | |
2884 | * support | |
2885 | */ | |
2886 | OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000); | |
2887 | #endif | |
2888 | } | |
a1909e63 CDH |
2889 | #endif /* defined(CONFIG_PPC_PMAC) */ |
2890 | #endif /* defined(CONFIG_PM) */ | |
994aad25 VB |
2891 | |
2892 | if (ignore_devlist) | |
2893 | printk(KERN_DEBUG | |
2894 | "radeonfb: skipping test for device workarounds\n"); | |
2895 | else | |
2896 | radeon_apply_workarounds(rinfo); | |
2897 | ||
2898 | if (force_sleep) { | |
2899 | printk(KERN_DEBUG | |
2900 | "radeonfb: forcefully enabling D2 sleep mode\n"); | |
2901 | rinfo->pm_mode |= radeon_pm_d2; | |
2902 | } | |
1da177e4 LT |
2903 | } |
2904 | ||
2905 | void radeonfb_pm_exit(struct radeonfb_info *rinfo) | |
2906 | { | |
a7fdd90b | 2907 | #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC) |
1da177e4 LT |
2908 | if (rinfo->pm_mode != radeon_pm_none) |
2909 | pmac_set_early_video_resume(NULL, NULL); | |
2910 | #endif | |
2911 | } |