[deliverable/linux.git] / drivers / video / aty / radeonfb.h

#ifndef __RADEONFB_H__
#define __RADEONFB_H__

#ifdef CONFIG_FB_RADEON_DEBUG
#define DEBUG		1
#endif

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/fb.h>


#ifdef CONFIG_FB_RADEON_I2C
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#endif

#include <asm/io.h>

#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
#include <asm/prom.h>
#endif

#include <video/radeon.h>

/***************************************************************
 * Most of the definitions here are adapted right from XFree86 *
 ***************************************************************/


/*
 * Chip families. Must fit in the low 16 bits of a long word
 */
enum radeon_family {
	CHIP_FAMILY_UNKNOW,
	CHIP_FAMILY_LEGACY,
	CHIP_FAMILY_RADEON,
	CHIP_FAMILY_RV100,
	CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
	CHIP_FAMILY_RV200,
	CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
				 RS250 (IGP 7000) */
	CHIP_FAMILY_R200,
	CHIP_FAMILY_RV250,
	CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
	CHIP_FAMILY_RV280,
	CHIP_FAMILY_R300,
	CHIP_FAMILY_R350,
	CHIP_FAMILY_RV350,
	CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
	CHIP_FAMILY_R420,     /* R420/R423/M18 */
	CHIP_FAMILY_RC410,
	CHIP_FAMILY_RS400,
	CHIP_FAMILY_RS480,
	CHIP_FAMILY_LAST,
};

#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
				 ((rinfo)->family == CHIP_FAMILY_RV200)  || \
				 ((rinfo)->family == CHIP_FAMILY_RS100)  || \
				 ((rinfo)->family == CHIP_FAMILY_RS200)  || \
				 ((rinfo)->family == CHIP_FAMILY_RV250)  || \
				 ((rinfo)->family == CHIP_FAMILY_RV280)  || \
				 ((rinfo)->family == CHIP_FAMILY_RS300))


#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
				((rinfo)->family == CHIP_FAMILY_RV350) || \
				((rinfo)->family == CHIP_FAMILY_R350)  || \
				((rinfo)->family == CHIP_FAMILY_RV380) || \
				((rinfo)->family == CHIP_FAMILY_R420)  || \
                               ((rinfo)->family == CHIP_FAMILY_RC410) || \
                               ((rinfo)->family == CHIP_FAMILY_RS480))

/*
 * Chip flags
 */
enum radeon_chip_flags {
	CHIP_FAMILY_MASK	= 0x0000ffffUL,
	CHIP_FLAGS_MASK		= 0xffff0000UL,
	CHIP_IS_MOBILITY	= 0x00010000UL,
	CHIP_IS_IGP		= 0x00020000UL,
	CHIP_HAS_CRTC2		= 0x00040000UL,	
};

/*
 * Errata workarounds
 */
enum radeon_errata {
	CHIP_ERRATA_R300_CG		= 0x00000001,
	CHIP_ERRATA_PLL_DUMMYREADS	= 0x00000002,
	CHIP_ERRATA_PLL_DELAY		= 0x00000004,
};


/*
 * Monitor types
 */
enum radeon_montype {
	MT_NONE = 0,
	MT_CRT,		/* CRT */
	MT_LCD,		/* LCD */
	MT_DFP,		/* DVI */
	MT_CTV,		/* composite TV */
	MT_STV		/* S-Video out */
};

/*
 * DDC i2c ports
 */
enum ddc_type {
	ddc_none,
	ddc_monid,
	ddc_dvi,
	ddc_vga,
	ddc_crt2,
};

/*
 * Connector types
 */
enum conn_type {
	conn_none,
	conn_proprietary,
	conn_crt,
	conn_DVI_I,
	conn_DVI_D,
};


/*
 * PLL infos
 */
struct pll_info {
	int ppll_max;
	int ppll_min;
	int sclk, mclk;
	int ref_div;
	int ref_clk;
};


/*
 * This structure contains the various registers manipulated by this
 * driver for setting or restoring a mode. It's mostly copied from
 * XFree's RADEONSaveRec structure. A few chip settings might still be
 * tweaked without beeing reflected or saved in these registers though
 */
struct radeon_regs {
	/* Common registers */
	u32		ovr_clr;
	u32		ovr_wid_left_right;
	u32		ovr_wid_top_bottom;
	u32		ov0_scale_cntl;
	u32		mpp_tb_config;
	u32		mpp_gp_config;
	u32		subpic_cntl;
	u32		viph_control;
	u32		i2c_cntl_1;
	u32		gen_int_cntl;
	u32		cap0_trig_cntl;
	u32		cap1_trig_cntl;
	u32		bus_cntl;
	u32		surface_cntl;
	u32		bios_5_scratch;

	/* Other registers to save for VT switches or driver load/unload */
	u32		dp_datatype;
	u32		rbbm_soft_reset;
	u32		clock_cntl_index;
	u32		amcgpio_en_reg;
	u32		amcgpio_mask;

	/* Surface/tiling registers */
	u32		surf_lower_bound[8];
	u32		surf_upper_bound[8];
	u32		surf_info[8];

	/* CRTC registers */
	u32		crtc_gen_cntl;
	u32		crtc_ext_cntl;
	u32		dac_cntl;
	u32		crtc_h_total_disp;
	u32		crtc_h_sync_strt_wid;
	u32		crtc_v_total_disp;
	u32		crtc_v_sync_strt_wid;
	u32		crtc_offset;
	u32		crtc_offset_cntl;
	u32		crtc_pitch;
	u32		disp_merge_cntl;
	u32		grph_buffer_cntl;
	u32		crtc_more_cntl;

	/* CRTC2 registers */
	u32		crtc2_gen_cntl;
	u32		dac2_cntl;
	u32		disp_output_cntl;
	u32		disp_hw_debug;
	u32		disp2_merge_cntl;
	u32		grph2_buffer_cntl;
	u32		crtc2_h_total_disp;
	u32		crtc2_h_sync_strt_wid;
	u32		crtc2_v_total_disp;
	u32		crtc2_v_sync_strt_wid;
	u32		crtc2_offset;
	u32		crtc2_offset_cntl;
	u32		crtc2_pitch;

	/* Flat panel regs */
	u32 		fp_crtc_h_total_disp;
	u32		fp_crtc_v_total_disp;
	u32		fp_gen_cntl;
	u32		fp2_gen_cntl;
	u32		fp_h_sync_strt_wid;
	u32		fp2_h_sync_strt_wid;
	u32		fp_horz_stretch;
	u32		fp_panel_cntl;
	u32		fp_v_sync_strt_wid;
	u32		fp2_v_sync_strt_wid;
	u32		fp_vert_stretch;
	u32		lvds_gen_cntl;
	u32		lvds_pll_cntl;
	u32		tmds_crc;
	u32		tmds_transmitter_cntl;

	/* Computed values for PLL */
	u32		dot_clock_freq;
	int		feedback_div;
	int		post_div;	

	/* PLL registers */
	u32		ppll_div_3;
	u32		ppll_ref_div;
	u32		vclk_ecp_cntl;
	u32		clk_cntl_index;

	/* Computed values for PLL2 */
	u32		dot_clock_freq_2;
	int		feedback_div_2;
	int		post_div_2;

	/* PLL2 registers */
	u32		p2pll_ref_div;
	u32		p2pll_div_0;
	u32		htotal_cntl2;

       	/* Palette */
	int		palette_valid;
};

struct panel_info {
	int xres, yres;
	int valid;
	int clock;
	int hOver_plus, hSync_width, hblank;
	int vOver_plus, vSync_width, vblank;
	int hAct_high, vAct_high, interlaced;
	int pwr_delay;
	int use_bios_dividers;
	int ref_divider;
	int post_divider;
	int fbk_divider;
};

struct radeonfb_info;

#ifdef CONFIG_FB_RADEON_I2C
struct radeon_i2c_chan {
	struct radeonfb_info		*rinfo;
	u32		 		ddc_reg;
	struct i2c_adapter		adapter;
	struct i2c_algo_bit_data	algo;
};
#endif

enum radeon_pm_mode {
	radeon_pm_none	= 0,		/* Nothing supported */
	radeon_pm_d2	= 0x00000001,	/* Can do D2 state */
	radeon_pm_off	= 0x00000002,	/* Can resume from D3 cold */
};

typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);

struct radeonfb_info {
	struct fb_info		*info;

	struct radeon_regs 	state;
	struct radeon_regs	init_state;

	char			name[50];

	unsigned long		mmio_base_phys;
	unsigned long		fb_base_phys;

	void __iomem		*mmio_base;
	void __iomem		*fb_base;

	unsigned long		fb_local_base;

	struct pci_dev		*pdev;
#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
	struct device_node	*of_node;
#endif

	void __iomem		*bios_seg;
	int			fp_bios_start;

	u32			pseudo_palette[16];
	struct { u8 red, green, blue, pad; }
				palette[256];

	int			chipset;
	u8			family;
	u8			rev;
	unsigned int		errata;
	unsigned long		video_ram;
	unsigned long		mapped_vram;
	int			vram_width;
	int			vram_ddr;

	int			pitch, bpp, depth;

	int			has_CRTC2;
	int			is_mobility;
	int			is_IGP;
	int			reversed_DAC;
	int			reversed_TMDS;
	struct panel_info	panel_info;
	int			mon1_type;
	u8			*mon1_EDID;
	struct fb_videomode	*mon1_modedb;
	int			mon1_dbsize;
	int			mon2_type;
	u8		        *mon2_EDID;

	u32			dp_gui_master_cntl;

	struct pll_info		pll;

	int			mtrr_hdl;

	int			pm_reg;
	u32			save_regs[100];
	int			asleep;
	int			lock_blank;
	int			dynclk;
	int			no_schedule;
	enum radeon_pm_mode	pm_mode;
	reinit_function_ptr     reinit_func;

	/* Lock on register access */
	spinlock_t		reg_lock;

	/* Timer used for delayed LVDS operations */
	struct timer_list	lvds_timer;
	u32			pending_lvds_gen_cntl;

#ifdef CONFIG_FB_RADEON_I2C
	struct radeon_i2c_chan 	i2c[4];
#endif

	u32			cfg_save[64];
};


#define PRIMARY_MONITOR(rinfo)	(rinfo->mon1_type)


/*
 * IO macros
 */

/* Note about this function: we have some rare cases where we must not schedule,
 * this typically happen with our special "wake up early" hook which allows us to
 * wake up the graphic chip (and thus get the console back) before everything else
 * on some machines that support that mechanism. At this point, interrupts are off
 * and scheduling is not permitted
 */
static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
{
	if (rinfo->no_schedule || oops_in_progress)
		mdelay(ms);
	else
		msleep(ms);
}


#define INREG8(addr)		readb((rinfo->mmio_base)+addr)
#define OUTREG8(addr,val)	writeb(val, (rinfo->mmio_base)+addr)
#define INREG16(addr)		readw((rinfo->mmio_base)+addr)
#define OUTREG16(addr,val)	writew(val, (rinfo->mmio_base)+addr)
#define INREG(addr)		readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val)	writel(val, (rinfo->mmio_base)+addr)

static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
		       u32 val, u32 mask)
{
	unsigned long flags;
	unsigned int tmp;

	spin_lock_irqsave(&rinfo->reg_lock, flags);
	tmp = INREG(addr);
	tmp &= (mask);
	tmp |= (val);
	OUTREG(addr, tmp);
	spin_unlock_irqrestore(&rinfo->reg_lock, flags);
}

#define OUTREGP(addr,val,mask)	_OUTREGP(rinfo, addr, val,mask)

/*
 * Note about PLL register accesses:
 *
 * I have removed the spinlock on them on purpose. The driver now
 * expects that it will only manipulate the PLL registers in normal
 * task environment, where radeon_msleep() will be called, protected
 * by a semaphore (currently the console semaphore) so that no conflict
 * will happen on the PLL register index.
 *
 * With the latest changes to the VT layer, this is guaranteed for all
 * calls except the actual drawing/blits which aren't supposed to use
 * the PLL registers anyway
 *
 * This is very important for the workarounds to work properly. The only
 * possible exception to this rule is the call to unblank(), which may
 * be done at irq time if an oops is in progress.
 */
static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
{
	if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
		return;

	(void)INREG(CLOCK_CNTL_DATA);
	(void)INREG(CRTC_GEN_CNTL);
}

static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
{
	if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
		/* we can't deal with posted writes here ... */
		_radeon_msleep(rinfo, 5);
	}
	if (rinfo->errata & CHIP_ERRATA_R300_CG) {
		u32 save, tmp;
		save = INREG(CLOCK_CNTL_INDEX);
		tmp = save & ~(0x3f | PLL_WR_EN);
		OUTREG(CLOCK_CNTL_INDEX, tmp);
		tmp = INREG(CLOCK_CNTL_DATA);
		OUTREG(CLOCK_CNTL_INDEX, save);
	}
}

static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
{
	u32 data;

	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
	radeon_pll_errata_after_index(rinfo);
	data = INREG(CLOCK_CNTL_DATA);
	radeon_pll_errata_after_data(rinfo);
	return data;
}

static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
			    u32 val)
{

	OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
	radeon_pll_errata_after_index(rinfo);
	OUTREG(CLOCK_CNTL_DATA, val);
	radeon_pll_errata_after_data(rinfo);
}


static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
			     u32 val, u32 mask)
{
	unsigned int tmp;

	tmp  = __INPLL(rinfo, index);
	tmp &= (mask);
	tmp |= (val);
	__OUTPLL(rinfo, index, tmp);
}


#define INPLL(addr)			__INPLL(rinfo, addr)
#define OUTPLL(index, val)		__OUTPLL(rinfo, index, val)
#define OUTPLLP(index, val, mask)	__OUTPLLP(rinfo, index, val, mask)


#define BIOS_IN8(v)  	(readb(rinfo->bios_seg + (v)))
#define BIOS_IN16(v) 	(readb(rinfo->bios_seg + (v)) | \
			  (readb(rinfo->bios_seg + (v) + 1) << 8))
#define BIOS_IN32(v) 	(readb(rinfo->bios_seg + (v)) | \
			  (readb(rinfo->bios_seg + (v) + 1) << 8) | \
			  (readb(rinfo->bios_seg + (v) + 2) << 16) | \
			  (readb(rinfo->bios_seg + (v) + 3) << 24))

/*
 * Inline utilities
 */
static inline int round_div(int num, int den)
{
        return (num + (den / 2)) / den;
}

static inline int var_to_depth(const struct fb_var_screeninfo *var)
{
	if (var->bits_per_pixel != 16)
		return var->bits_per_pixel;
	return (var->green.length == 5) ? 15 : 16;
}

static inline u32 radeon_get_dstbpp(u16 depth)
{
	switch (depth) {
       	case 8:
       		return DST_8BPP;
       	case 15:
       		return DST_15BPP;
       	case 16:
       		return DST_16BPP;
       	case 32:
       		return DST_32BPP;
       	default:
       		return 0;
	}
}

/*
 * 2D Engine helper routines
 */

static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
	int i;

	for (i=0; i<2000000; i++) {
		if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
			return;
		udelay(1);
	}
	printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
}

static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
{
	int i;

	/* Initiate flush */
	OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
	        ~RB2D_DC_FLUSH_ALL);

	/* Ensure FIFO is empty, ie, make sure the flush commands
	 * has reached the cache
	 */
	_radeon_fifo_wait (rinfo, 64);

	/* Wait for the flush to complete */
	for (i=0; i < 2000000; i++) {
		if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
			return;
		udelay(1);
	}
	printk(KERN_ERR "radeonfb: Flush Timeout !\n");
}


static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
{
	int i;

	/* ensure FIFO is empty before waiting for idle */
	_radeon_fifo_wait (rinfo, 64);

	for (i=0; i<2000000; i++) {
		if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
			radeon_engine_flush (rinfo);
			return;
		}
		udelay(1);
	}
	printk(KERN_ERR "radeonfb: Idle Timeout !\n");
}


#define radeon_engine_idle()		_radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries)	_radeon_fifo_wait(rinfo,entries)
#define radeon_msleep(ms)		_radeon_msleep(rinfo,ms)


/* I2C Functions */
extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);

/* PM Functions */
extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
extern int radeonfb_pci_resume(struct pci_dev *pdev);
extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);

/* Monitor probe functions */
extern void radeon_probe_screens(struct radeonfb_info *rinfo,
				 const char *monitor_layout, int ignore_edid);
extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
extern int radeon_match_mode(struct radeonfb_info *rinfo,
			     struct fb_var_screeninfo *dest,
			     const struct fb_var_screeninfo *src);

/* Accel functions */
extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
extern int radeonfb_sync(struct fb_info *info);
extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);

/* Other functions */
extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
			       int reg_only);

/* Backlight functions */
#ifdef CONFIG_FB_RADEON_BACKLIGHT
extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
#else
static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
#endif

#endif /* __RADEONFB_H__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __RADEONFB_H__
	2	#define __RADEONFB_H__
	3
b0313f89 JD	4	#ifdef CONFIG_FB_RADEON_DEBUG
	5	#define DEBUG 1
	6	#endif
	7
1da177e4 LT	8	#include <linux/module.h>
	9	#include <linux/kernel.h>
	10	#include <linux/sched.h>
	11	#include <linux/delay.h>
	12	#include <linux/pci.h>
	13	#include <linux/fb.h>
	14
	15
e764a201	16	#ifdef CONFIG_FB_RADEON_I2C
1da177e4	17	#include <linux/i2c.h>
1da177e4	18	#include <linux/i2c-algo-bit.h>
e764a201	19	#endif
1da177e4 LT	20
	21	#include <asm/io.h>
	22
9f47df26	23	#if defined(CONFIG_PPC_OF) \|\| defined(CONFIG_SPARC)
1da177e4 LT	24	#include <asm/prom.h>
	25	#endif
	26
	27	#include <video/radeon.h>
	28
	29	/***************************************************************
	30	* Most of the definitions here are adapted right from XFree86 *
	31	***************************************************************/
	32
	33
	34	/*
	35	* Chip families. Must fit in the low 16 bits of a long word
	36	*/
	37	enum radeon_family {
	38	CHIP_FAMILY_UNKNOW,
	39	CHIP_FAMILY_LEGACY,
	40	CHIP_FAMILY_RADEON,
	41	CHIP_FAMILY_RV100,
	42	CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
	43	CHIP_FAMILY_RV200,
	44	CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
	45	RS250 (IGP 7000) */
	46	CHIP_FAMILY_R200,
	47	CHIP_FAMILY_RV250,
	48	CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
	49	CHIP_FAMILY_RV280,
	50	CHIP_FAMILY_R300,
	51	CHIP_FAMILY_R350,
	52	CHIP_FAMILY_RV350,
	53	CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
	54	CHIP_FAMILY_R420, /* R420/R423/M18 */
0b693eaf	55	CHIP_FAMILY_RC410,
a6c0c37d	56	CHIP_FAMILY_RS400,
dd144713	57	CHIP_FAMILY_RS480,
1da177e4 LT	58	CHIP_FAMILY_LAST,
	59	};
	60
	61	#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) \|\| \
	62	((rinfo)->family == CHIP_FAMILY_RV200) \|\| \
	63	((rinfo)->family == CHIP_FAMILY_RS100) \|\| \
	64	((rinfo)->family == CHIP_FAMILY_RS200) \|\| \
	65	((rinfo)->family == CHIP_FAMILY_RV250) \|\| \
	66	((rinfo)->family == CHIP_FAMILY_RV280) \|\| \
	67	((rinfo)->family == CHIP_FAMILY_RS300))
	68
	69
	70	#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) \|\| \
	71	((rinfo)->family == CHIP_FAMILY_RV350) \|\| \
	72	((rinfo)->family == CHIP_FAMILY_R350) \|\| \
	73	((rinfo)->family == CHIP_FAMILY_RV380) \|\| \
dd144713	74	((rinfo)->family == CHIP_FAMILY_R420) \|\| \
0b693eaf SB	75	((rinfo)->family == CHIP_FAMILY_RC410) \|\| \
0b693eaf SB	76	((rinfo)->family == CHIP_FAMILY_RS480))
1da177e4 LT	77
	78	/*
	79	* Chip flags
	80	*/
	81	enum radeon_chip_flags {
	82	CHIP_FAMILY_MASK = 0x0000ffffUL,
	83	CHIP_FLAGS_MASK = 0xffff0000UL,
	84	CHIP_IS_MOBILITY = 0x00010000UL,
	85	CHIP_IS_IGP = 0x00020000UL,
	86	CHIP_HAS_CRTC2 = 0x00040000UL,
	87	};
	88
	89	/*
	90	* Errata workarounds
	91	*/
	92	enum radeon_errata {
	93	CHIP_ERRATA_R300_CG = 0x00000001,
	94	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
	95	CHIP_ERRATA_PLL_DELAY = 0x00000004,
	96	};
	97
	98
	99	/*
	100	* Monitor types
	101	*/
	102	enum radeon_montype {
	103	MT_NONE = 0,
	104	MT_CRT, /* CRT */
	105	MT_LCD, /* LCD */
	106	MT_DFP, /* DVI */
	107	MT_CTV, /* composite TV */
	108	MT_STV /* S-Video out */
	109	};
	110
	111	/*
	112	* DDC i2c ports
	113	*/
	114	enum ddc_type {
	115	ddc_none,
	116	ddc_monid,
	117	ddc_dvi,
	118	ddc_vga,
	119	ddc_crt2,
	120	};
	121
	122	/*
	123	* Connector types
	124	*/
	125	enum conn_type {
	126	conn_none,
	127	conn_proprietary,
	128	conn_crt,
	129	conn_DVI_I,
	130	conn_DVI_D,
	131	};
	132
	133
	134	/*
	135	* PLL infos
	136	*/
	137	struct pll_info {
	138	int ppll_max;
	139	int ppll_min;
	140	int sclk, mclk;
141	int ref_div;
142	int ref_clk;
143	};
144
145
146	/*
147	* This structure contains the various registers manipulated by this
148	* driver for setting or restoring a mode. It's mostly copied from
149	* XFree's RADEONSaveRec structure. A few chip settings might still be
150	* tweaked without beeing reflected or saved in these registers though
151	*/
152	struct radeon_regs {
153	/* Common registers */
154	u32 ovr_clr;
155	u32 ovr_wid_left_right;
156	u32 ovr_wid_top_bottom;
157	u32 ov0_scale_cntl;
158	u32 mpp_tb_config;
159	u32 mpp_gp_config;
160	u32 subpic_cntl;
161	u32 viph_control;
162	u32 i2c_cntl_1;
163	u32 gen_int_cntl;
164	u32 cap0_trig_cntl;
165	u32 cap1_trig_cntl;
166	u32 bus_cntl;
167	u32 surface_cntl;
168	u32 bios_5_scratch;
169
170	/* Other registers to save for VT switches or driver load/unload */
171	u32 dp_datatype;
172	u32 rbbm_soft_reset;
173	u32 clock_cntl_index;
174	u32 amcgpio_en_reg;
175	u32 amcgpio_mask;
176
177	/* Surface/tiling registers */
178	u32 surf_lower_bound[8];
179	u32 surf_upper_bound[8];
180	u32 surf_info[8];
181
182	/* CRTC registers */
183	u32 crtc_gen_cntl;
184	u32 crtc_ext_cntl;
185	u32 dac_cntl;
186	u32 crtc_h_total_disp;
187	u32 crtc_h_sync_strt_wid;
188	u32 crtc_v_total_disp;
189	u32 crtc_v_sync_strt_wid;
190	u32 crtc_offset;
191	u32 crtc_offset_cntl;
192	u32 crtc_pitch;
193	u32 disp_merge_cntl;
194	u32 grph_buffer_cntl;
195	u32 crtc_more_cntl;
196
197	/* CRTC2 registers */
198	u32 crtc2_gen_cntl;
199	u32 dac2_cntl;
200	u32 disp_output_cntl;
201	u32 disp_hw_debug;
202	u32 disp2_merge_cntl;
203	u32 grph2_buffer_cntl;
204	u32 crtc2_h_total_disp;
205	u32 crtc2_h_sync_strt_wid;
206	u32 crtc2_v_total_disp;
207	u32 crtc2_v_sync_strt_wid;
208	u32 crtc2_offset;
209	u32 crtc2_offset_cntl;
210	u32 crtc2_pitch;
211
212	/* Flat panel regs */
213	u32 fp_crtc_h_total_disp;
214	u32 fp_crtc_v_total_disp;
215	u32 fp_gen_cntl;
216	u32 fp2_gen_cntl;
217	u32 fp_h_sync_strt_wid;
218	u32 fp2_h_sync_strt_wid;
219	u32 fp_horz_stretch;
220	u32 fp_panel_cntl;
221	u32 fp_v_sync_strt_wid;
222	u32 fp2_v_sync_strt_wid;
223	u32 fp_vert_stretch;
224	u32 lvds_gen_cntl;
225	u32 lvds_pll_cntl;
226	u32 tmds_crc;
227	u32 tmds_transmitter_cntl;
228
229	/* Computed values for PLL */
230	u32 dot_clock_freq;
231	int feedback_div;
232	int post_div;
233
234	/* PLL registers */
235	u32 ppll_div_3;
236	u32 ppll_ref_div;
237	u32 vclk_ecp_cntl;
238	u32 clk_cntl_index;
239
240	/* Computed values for PLL2 */
241	u32 dot_clock_freq_2;
242	int feedback_div_2;
243	int post_div_2;
244
245	/* PLL2 registers */
246	u32 p2pll_ref_div;
247	u32 p2pll_div_0;
248	u32 htotal_cntl2;
249
250	/* Palette */
251	int palette_valid;
252	};
253
254	struct panel_info {
255	int xres, yres;
256	int valid;
257	int clock;
258	int hOver_plus, hSync_width, hblank;
259	int vOver_plus, vSync_width, vblank;
260	int hAct_high, vAct_high, interlaced;
261	int pwr_delay;
262	int use_bios_dividers;
263	int ref_divider;
264	int post_divider;
265	int fbk_divider;
266	};
267
268	struct radeonfb_info;
269
270	#ifdef CONFIG_FB_RADEON_I2C
271	struct radeon_i2c_chan {
272	struct radeonfb_info *rinfo;
273	u32 ddc_reg;
274	struct i2c_adapter adapter;
275	struct i2c_algo_bit_data algo;
276	};
277	#endif
278
279	enum radeon_pm_mode {
280	radeon_pm_none = 0, /* Nothing supported */
281	radeon_pm_d2 = 0x00000001, /* Can do D2 state */
282	radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
283	};
284
994aad25 VB	285	typedef void (reinit_function_ptr)(struct radeonfb_info rinfo);
994aad25 VB	286
1da177e4 LT	287	struct radeonfb_info {
	288	struct fb_info *info;
	289
	290	struct radeon_regs state;
	291	struct radeon_regs init_state;
	292
ca52a498	293	char name[50];
1da177e4 LT	294
	295	unsigned long mmio_base_phys;
	296	unsigned long fb_base_phys;
	297
	298	void __iomem *mmio_base;
	299	void __iomem *fb_base;
	300
	301	unsigned long fb_local_base;
	302
	303	struct pci_dev *pdev;
9f47df26	304	#if defined(CONFIG_PPC_OF) \|\| defined(CONFIG_SPARC)
1da177e4 LT	305	struct device_node *of_node;
	306	#endif
	307
	308	void __iomem *bios_seg;
	309	int fp_bios_start;
	310
f0e3ad44	311	u32 pseudo_palette[16];
1da177e4 LT	312	struct { u8 red, green, blue, pad; }
	313	palette[256];
	314
	315	int chipset;
	316	u8 family;
	317	u8 rev;
	318	unsigned int errata;
	319	unsigned long video_ram;
	320	unsigned long mapped_vram;
	321	int vram_width;
	322	int vram_ddr;
	323
	324	int pitch, bpp, depth;
	325
	326	int has_CRTC2;
	327	int is_mobility;
	328	int is_IGP;
	329	int reversed_DAC;
	330	int reversed_TMDS;
	331	struct panel_info panel_info;
	332	int mon1_type;
	333	u8 *mon1_EDID;
	334	struct fb_videomode *mon1_modedb;
	335	int mon1_dbsize;
	336	int mon2_type;
	337	u8 *mon2_EDID;
	338
6c34bc29	339	u32 dp_gui_master_cntl;
1da177e4 LT	340
	341	struct pll_info pll;
	342
	343	int mtrr_hdl;
	344
	345	int pm_reg;
	346	u32 save_regs[100];
	347	int asleep;
	348	int lock_blank;
	349	int dynclk;
	350	int no_schedule;
	351	enum radeon_pm_mode pm_mode;
994aad25	352	reinit_function_ptr reinit_func;
1da177e4 LT	353
	354	/* Lock on register access */
	355	spinlock_t reg_lock;
	356
	357	/* Timer used for delayed LVDS operations */
	358	struct timer_list lvds_timer;
	359	u32 pending_lvds_gen_cntl;
	360
	361	#ifdef CONFIG_FB_RADEON_I2C
	362	struct radeon_i2c_chan i2c[4];
	363	#endif
	364
	365	u32 cfg_save[64];
	366	};
	367
	368
	369	#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
	370
	371
1da177e4 LT	372	/*
	373	* IO macros
	374	*/
	375
	376	/* Note about this function: we have some rare cases where we must not schedule,
	377	* this typically happen with our special "wake up early" hook which allows us to
	378	* wake up the graphic chip (and thus get the console back) before everything else
b3c2ffd5	379	* on some machines that support that mechanism. At this point, interrupts are off
1da177e4 LT	380	* and scheduling is not permitted
	381	*/
	382	static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
	383	{
	384	if (rinfo->no_schedule \|\| oops_in_progress)
	385	mdelay(ms);
	386	else
	387	msleep(ms);
	388	}
	389
	390
	391	#define INREG8(addr) readb((rinfo->mmio_base)+addr)
	392	#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
017fb98e DM	393	#define INREG16(addr) readw((rinfo->mmio_base)+addr)
017fb98e DM	394	#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
1da177e4 LT	395	#define INREG(addr) readl((rinfo->mmio_base)+addr)
	396	#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
	397
	398	static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
	399	u32 val, u32 mask)
	400	{
	401	unsigned long flags;
	402	unsigned int tmp;
	403
	404	spin_lock_irqsave(&rinfo->reg_lock, flags);
	405	tmp = INREG(addr);
	406	tmp &= (mask);
	407	tmp \|= (val);
	408	OUTREG(addr, tmp);
	409	spin_unlock_irqrestore(&rinfo->reg_lock, flags);
	410	}
	411
	412	#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
	413
	414	/*
	415	* Note about PLL register accesses:
	416	*
	417	* I have removed the spinlock on them on purpose. The driver now
	418	* expects that it will only manipulate the PLL registers in normal
	419	* task environment, where radeon_msleep() will be called, protected
	420	* by a semaphore (currently the console semaphore) so that no conflict
	421	* will happen on the PLL register index.
	422	*
	423	* With the latest changes to the VT layer, this is guaranteed for all
	424	* calls except the actual drawing/blits which aren't supposed to use
	425	* the PLL registers anyway
	426	*
	427	* This is very important for the workarounds to work properly. The only
	428	* possible exception to this rule is the call to unblank(), which may
	429	* be done at irq time if an oops is in progress.
	430	*/
	431	static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
	432	{
	433	if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
	434	return;
	435
	436	(void)INREG(CLOCK_CNTL_DATA);
	437	(void)INREG(CRTC_GEN_CNTL);
	438	}
	439
	440	static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
	441	{
	442	if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
	443	/* we can't deal with posted writes here ... */
	444	_radeon_msleep(rinfo, 5);
	445	}
	446	if (rinfo->errata & CHIP_ERRATA_R300_CG) {
	447	u32 save, tmp;
	448	save = INREG(CLOCK_CNTL_INDEX);
	449	tmp = save & ~(0x3f \| PLL_WR_EN);
	450	OUTREG(CLOCK_CNTL_INDEX, tmp);
	451	tmp = INREG(CLOCK_CNTL_DATA);
	452	OUTREG(CLOCK_CNTL_INDEX, save);
	453	}
	454	}
	455
	456	static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
	457	{
	458	u32 data;
459
460	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
461	radeon_pll_errata_after_index(rinfo);
462	data = INREG(CLOCK_CNTL_DATA);
463	radeon_pll_errata_after_data(rinfo);
464	return data;
465	}
466
467	static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
468	u32 val)
469	{
470
471	OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) \| 0x00000080);
472	radeon_pll_errata_after_index(rinfo);
473	OUTREG(CLOCK_CNTL_DATA, val);
474	radeon_pll_errata_after_data(rinfo);
475	}
476
477
478	static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
479	u32 val, u32 mask)
480	{
481	unsigned int tmp;
482
483	tmp = __INPLL(rinfo, index);
484	tmp &= (mask);
485	tmp \|= (val);
486	__OUTPLL(rinfo, index, tmp);
487	}
488
489
490	#define INPLL(addr) __INPLL(rinfo, addr)
491	#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
492	#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
493
494
495	#define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
496	#define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) \| \
497	(readb(rinfo->bios_seg + (v) + 1) << 8))
498	#define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) \| \
499	(readb(rinfo->bios_seg + (v) + 1) << 8) \| \
500	(readb(rinfo->bios_seg + (v) + 2) << 16) \| \
501	(readb(rinfo->bios_seg + (v) + 3) << 24))
502
503	/*
504	* Inline utilities
505	*/
506	static inline int round_div(int num, int den)
507	{
508	return (num + (den / 2)) / den;
509	}
510
511	static inline int var_to_depth(const struct fb_var_screeninfo *var)
512	{
513	if (var->bits_per_pixel != 16)
514	return var->bits_per_pixel;
515	return (var->green.length == 5) ? 15 : 16;
516	}
517
518	static inline u32 radeon_get_dstbpp(u16 depth)
519	{
520	switch (depth) {
521	case 8:
522	return DST_8BPP;
523	case 15:
524	return DST_15BPP;
525	case 16:
526	return DST_16BPP;
527	case 32:
528	return DST_32BPP;
529	default:
530	return 0;
531	}
532	}
533
534	/*
535	* 2D Engine helper routines
536	*/
a6c0c37d	537
6c34bc29 LT	538	static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
	539	{
	540	int i;
	541
	542	for (i=0; i<2000000; i++) {
	543	if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
	544	return;
	545	udelay(1);
	546	}
	547	printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
	548	}
1da177e4	549
a6c0c37d	550	static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
1da177e4 LT	551	{
	552	int i;
	553
a6c0c37d BH	554	/* Initiate flush */
	555	OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
	556	~RB2D_DC_FLUSH_ALL);
	557
	558	/* Ensure FIFO is empty, ie, make sure the flush commands
	559	* has reached the cache
	560	*/
6c34bc29	561	_radeon_fifo_wait (rinfo, 64);
a6c0c37d BH	562
	563	/* Wait for the flush to complete */
	564	for (i=0; i < 2000000; i++) {
	565	if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
1da177e4 LT	566	return;
	567	udelay(1);
	568	}
a6c0c37d	569	printk(KERN_ERR "radeonfb: Flush Timeout !\n");
1da177e4 LT	570	}
	571
	572
6c34bc29	573	static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
1da177e4 LT	574	{
	575	int i;
	576
	577	/* ensure FIFO is empty before waiting for idle */
6c34bc29	578	_radeon_fifo_wait (rinfo, 64);
1da177e4 LT	579
	580	for (i=0; i<2000000; i++) {
	581	if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
	582	radeon_engine_flush (rinfo);
	583	return;
	584	}
	585	udelay(1);
	586	}
	587	printk(KERN_ERR "radeonfb: Idle Timeout !\n");
	588	}
	589
	590
6c34bc29 LT	591	#define radeon_engine_idle() _radeon_engine_idle(rinfo)
6c34bc29 LT	592	#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
1da177e4 LT	593	#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
	594
	595
	596	/* I2C Functions */
	597	extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
	598	extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
	599	extern int radeon_probe_i2c_connector(struct radeonfb_info rinfo, int conn, u8 *out_edid);
	600
	601	/* PM Functions */
	602	extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
	603	extern int radeonfb_pci_resume(struct pci_dev *pdev);
994aad25	604	extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
1da177e4 LT	605	extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
	606
	607	/* Monitor probe functions */
	608	extern void radeon_probe_screens(struct radeonfb_info *rinfo,
	609	const char *monitor_layout, int ignore_edid);
	610	extern void radeon_check_modes(struct radeonfb_info rinfo, const char mode_option);
	611	extern int radeon_match_mode(struct radeonfb_info *rinfo,
	612	struct fb_var_screeninfo *dest,
	613	const struct fb_var_screeninfo *src);
	614
	615	/* Accel functions */
	616	extern void radeonfb_fillrect(struct fb_info info, const struct fb_fillrect region);
	617	extern void radeonfb_copyarea(struct fb_info info, const struct fb_copyarea area);
	618	extern void radeonfb_imageblit(struct fb_info p, const struct fb_image image);
	619	extern int radeonfb_sync(struct fb_info *info);
	620	extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
	621	extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
	622
	623	/* Other functions */
	624	extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
	625	extern void radeon_write_mode (struct radeonfb_info rinfo, struct radeon_regs mode,
	626	int reg_only);
	627
5474c120 MH	628	/* Backlight functions */
	629	#ifdef CONFIG_FB_RADEON_BACKLIGHT
	630	extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
	631	extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
	632	#else
	633	static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
	634	static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
	635	#endif
	636
1da177e4	637	#endif /* __RADEONFB_H__ */