Commit | Line | Data |
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1da177e4 LT |
1 | /* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver |
2 | * | |
50312ce9 | 3 | * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) |
5 | * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) | |
6 | * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) | |
7 | * | |
8 | * Driver layout based loosely on tgafb.c, see that file for credits. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/fb.h> | |
19 | #include <linux/mm.h> | |
6cd5a86b | 20 | #include <linux/of_device.h> |
1da177e4 LT |
21 | |
22 | #include <asm/io.h> | |
1da177e4 LT |
23 | #include <asm/fbio.h> |
24 | ||
25 | #include "sbuslib.h" | |
26 | ||
27 | /* | |
28 | * Local functions. | |
29 | */ | |
30 | ||
31 | static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned, | |
32 | unsigned, struct fb_info *); | |
33 | static int cg6_blank(int, struct fb_info *); | |
34 | ||
35 | static void cg6_imageblit(struct fb_info *, const struct fb_image *); | |
36 | static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *); | |
291d5f30 | 37 | static void cg6_copyarea(struct fb_info *info, const struct fb_copyarea *area); |
1da177e4 | 38 | static int cg6_sync(struct fb_info *); |
216d526c | 39 | static int cg6_mmap(struct fb_info *, struct vm_area_struct *); |
67a6680d | 40 | static int cg6_ioctl(struct fb_info *, unsigned int, unsigned long); |
291d5f30 | 41 | static int cg6_pan_display(struct fb_var_screeninfo *, struct fb_info *); |
1da177e4 LT |
42 | |
43 | /* | |
44 | * Frame buffer operations | |
45 | */ | |
46 | ||
47 | static struct fb_ops cg6_ops = { | |
48 | .owner = THIS_MODULE, | |
49 | .fb_setcolreg = cg6_setcolreg, | |
50 | .fb_blank = cg6_blank, | |
291d5f30 | 51 | .fb_pan_display = cg6_pan_display, |
1da177e4 | 52 | .fb_fillrect = cg6_fillrect, |
a140e94d | 53 | .fb_copyarea = cg6_copyarea, |
1da177e4 LT |
54 | .fb_imageblit = cg6_imageblit, |
55 | .fb_sync = cg6_sync, | |
56 | .fb_mmap = cg6_mmap, | |
57 | .fb_ioctl = cg6_ioctl, | |
9ffb83bc CH |
58 | #ifdef CONFIG_COMPAT |
59 | .fb_compat_ioctl = sbusfb_compat_ioctl, | |
60 | #endif | |
1da177e4 LT |
61 | }; |
62 | ||
63 | /* Offset of interesting structures in the OBIO space */ | |
64 | /* | |
65 | * Brooktree is the video dac and is funny to program on the cg6. | |
66 | * (it's even funnier on the cg3) | |
67 | * The FBC could be the frame buffer control | |
68 | * The FHC could is the frame buffer hardware control. | |
69 | */ | |
6993bea1 KH |
70 | #define CG6_ROM_OFFSET 0x0UL |
71 | #define CG6_BROOKTREE_OFFSET 0x200000UL | |
72 | #define CG6_DHC_OFFSET 0x240000UL | |
73 | #define CG6_ALT_OFFSET 0x280000UL | |
74 | #define CG6_FHC_OFFSET 0x300000UL | |
75 | #define CG6_THC_OFFSET 0x301000UL | |
76 | #define CG6_FBC_OFFSET 0x700000UL | |
77 | #define CG6_TEC_OFFSET 0x701000UL | |
78 | #define CG6_RAM_OFFSET 0x800000UL | |
1da177e4 LT |
79 | |
80 | /* FHC definitions */ | |
6993bea1 KH |
81 | #define CG6_FHC_FBID_SHIFT 24 |
82 | #define CG6_FHC_FBID_MASK 255 | |
83 | #define CG6_FHC_REV_SHIFT 20 | |
84 | #define CG6_FHC_REV_MASK 15 | |
85 | #define CG6_FHC_FROP_DISABLE (1 << 19) | |
86 | #define CG6_FHC_ROW_DISABLE (1 << 18) | |
87 | #define CG6_FHC_SRC_DISABLE (1 << 17) | |
88 | #define CG6_FHC_DST_DISABLE (1 << 16) | |
89 | #define CG6_FHC_RESET (1 << 15) | |
90 | #define CG6_FHC_LITTLE_ENDIAN (1 << 13) | |
91 | #define CG6_FHC_RES_MASK (3 << 11) | |
92 | #define CG6_FHC_1024 (0 << 11) | |
93 | #define CG6_FHC_1152 (1 << 11) | |
94 | #define CG6_FHC_1280 (2 << 11) | |
95 | #define CG6_FHC_1600 (3 << 11) | |
96 | #define CG6_FHC_CPU_MASK (3 << 9) | |
97 | #define CG6_FHC_CPU_SPARC (0 << 9) | |
98 | #define CG6_FHC_CPU_68020 (1 << 9) | |
99 | #define CG6_FHC_CPU_386 (2 << 9) | |
100 | #define CG6_FHC_TEST (1 << 8) | |
101 | #define CG6_FHC_TEST_X_SHIFT 4 | |
102 | #define CG6_FHC_TEST_X_MASK 15 | |
103 | #define CG6_FHC_TEST_Y_SHIFT 0 | |
104 | #define CG6_FHC_TEST_Y_MASK 15 | |
1da177e4 LT |
105 | |
106 | /* FBC mode definitions */ | |
107 | #define CG6_FBC_BLIT_IGNORE 0x00000000 | |
108 | #define CG6_FBC_BLIT_NOSRC 0x00100000 | |
109 | #define CG6_FBC_BLIT_SRC 0x00200000 | |
110 | #define CG6_FBC_BLIT_ILLEGAL 0x00300000 | |
111 | #define CG6_FBC_BLIT_MASK 0x00300000 | |
112 | ||
113 | #define CG6_FBC_VBLANK 0x00080000 | |
114 | ||
115 | #define CG6_FBC_MODE_IGNORE 0x00000000 | |
116 | #define CG6_FBC_MODE_COLOR8 0x00020000 | |
117 | #define CG6_FBC_MODE_COLOR1 0x00040000 | |
118 | #define CG6_FBC_MODE_HRMONO 0x00060000 | |
119 | #define CG6_FBC_MODE_MASK 0x00060000 | |
120 | ||
121 | #define CG6_FBC_DRAW_IGNORE 0x00000000 | |
122 | #define CG6_FBC_DRAW_RENDER 0x00008000 | |
123 | #define CG6_FBC_DRAW_PICK 0x00010000 | |
124 | #define CG6_FBC_DRAW_ILLEGAL 0x00018000 | |
125 | #define CG6_FBC_DRAW_MASK 0x00018000 | |
126 | ||
127 | #define CG6_FBC_BWRITE0_IGNORE 0x00000000 | |
128 | #define CG6_FBC_BWRITE0_ENABLE 0x00002000 | |
129 | #define CG6_FBC_BWRITE0_DISABLE 0x00004000 | |
130 | #define CG6_FBC_BWRITE0_ILLEGAL 0x00006000 | |
131 | #define CG6_FBC_BWRITE0_MASK 0x00006000 | |
132 | ||
133 | #define CG6_FBC_BWRITE1_IGNORE 0x00000000 | |
134 | #define CG6_FBC_BWRITE1_ENABLE 0x00000800 | |
135 | #define CG6_FBC_BWRITE1_DISABLE 0x00001000 | |
136 | #define CG6_FBC_BWRITE1_ILLEGAL 0x00001800 | |
137 | #define CG6_FBC_BWRITE1_MASK 0x00001800 | |
138 | ||
139 | #define CG6_FBC_BREAD_IGNORE 0x00000000 | |
140 | #define CG6_FBC_BREAD_0 0x00000200 | |
141 | #define CG6_FBC_BREAD_1 0x00000400 | |
142 | #define CG6_FBC_BREAD_ILLEGAL 0x00000600 | |
143 | #define CG6_FBC_BREAD_MASK 0x00000600 | |
144 | ||
145 | #define CG6_FBC_BDISP_IGNORE 0x00000000 | |
146 | #define CG6_FBC_BDISP_0 0x00000080 | |
147 | #define CG6_FBC_BDISP_1 0x00000100 | |
148 | #define CG6_FBC_BDISP_ILLEGAL 0x00000180 | |
149 | #define CG6_FBC_BDISP_MASK 0x00000180 | |
150 | ||
151 | #define CG6_FBC_INDEX_MOD 0x00000040 | |
152 | #define CG6_FBC_INDEX_MASK 0x00000030 | |
153 | ||
154 | /* THC definitions */ | |
6993bea1 KH |
155 | #define CG6_THC_MISC_REV_SHIFT 16 |
156 | #define CG6_THC_MISC_REV_MASK 15 | |
157 | #define CG6_THC_MISC_RESET (1 << 12) | |
158 | #define CG6_THC_MISC_VIDEO (1 << 10) | |
159 | #define CG6_THC_MISC_SYNC (1 << 9) | |
160 | #define CG6_THC_MISC_VSYNC (1 << 8) | |
161 | #define CG6_THC_MISC_SYNC_ENAB (1 << 7) | |
162 | #define CG6_THC_MISC_CURS_RES (1 << 6) | |
163 | #define CG6_THC_MISC_INT_ENAB (1 << 5) | |
164 | #define CG6_THC_MISC_INT (1 << 4) | |
165 | #define CG6_THC_MISC_INIT 0x9f | |
291d5f30 | 166 | #define CG6_THC_CURSOFF ((65536-32) | ((65536-32) << 16)) |
1da177e4 LT |
167 | |
168 | /* The contents are unknown */ | |
169 | struct cg6_tec { | |
50312ce9 DM |
170 | int tec_matrix; |
171 | int tec_clip; | |
172 | int tec_vdc; | |
1da177e4 LT |
173 | }; |
174 | ||
175 | struct cg6_thc { | |
6993bea1 KH |
176 | u32 thc_pad0[512]; |
177 | u32 thc_hs; /* hsync timing */ | |
178 | u32 thc_hsdvs; | |
179 | u32 thc_hd; | |
180 | u32 thc_vs; /* vsync timing */ | |
181 | u32 thc_vd; | |
182 | u32 thc_refresh; | |
183 | u32 thc_misc; | |
184 | u32 thc_pad1[56]; | |
185 | u32 thc_cursxy; /* cursor x,y position (16 bits each) */ | |
186 | u32 thc_cursmask[32]; /* cursor mask bits */ | |
187 | u32 thc_cursbits[32]; /* what to show where mask enabled */ | |
1da177e4 LT |
188 | }; |
189 | ||
190 | struct cg6_fbc { | |
50312ce9 DM |
191 | u32 xxx0[1]; |
192 | u32 mode; | |
193 | u32 clip; | |
6993bea1 | 194 | u32 xxx1[1]; |
50312ce9 DM |
195 | u32 s; |
196 | u32 draw; | |
197 | u32 blit; | |
198 | u32 font; | |
199 | u32 xxx2[24]; | |
200 | u32 x0, y0, z0, color0; | |
201 | u32 x1, y1, z1, color1; | |
202 | u32 x2, y2, z2, color2; | |
203 | u32 x3, y3, z3, color3; | |
204 | u32 offx, offy; | |
205 | u32 xxx3[2]; | |
206 | u32 incx, incy; | |
207 | u32 xxx4[2]; | |
208 | u32 clipminx, clipminy; | |
209 | u32 xxx5[2]; | |
210 | u32 clipmaxx, clipmaxy; | |
211 | u32 xxx6[2]; | |
212 | u32 fg; | |
213 | u32 bg; | |
214 | u32 alu; | |
215 | u32 pm; | |
216 | u32 pixelm; | |
217 | u32 xxx7[2]; | |
218 | u32 patalign; | |
219 | u32 pattern[8]; | |
220 | u32 xxx8[432]; | |
221 | u32 apointx, apointy, apointz; | |
222 | u32 xxx9[1]; | |
223 | u32 rpointx, rpointy, rpointz; | |
224 | u32 xxx10[5]; | |
225 | u32 pointr, pointg, pointb, pointa; | |
226 | u32 alinex, aliney, alinez; | |
227 | u32 xxx11[1]; | |
228 | u32 rlinex, rliney, rlinez; | |
229 | u32 xxx12[5]; | |
230 | u32 liner, lineg, lineb, linea; | |
231 | u32 atrix, atriy, atriz; | |
232 | u32 xxx13[1]; | |
233 | u32 rtrix, rtriy, rtriz; | |
234 | u32 xxx14[5]; | |
235 | u32 trir, trig, trib, tria; | |
236 | u32 aquadx, aquady, aquadz; | |
237 | u32 xxx15[1]; | |
238 | u32 rquadx, rquady, rquadz; | |
239 | u32 xxx16[5]; | |
240 | u32 quadr, quadg, quadb, quada; | |
241 | u32 arectx, arecty, arectz; | |
242 | u32 xxx17[1]; | |
243 | u32 rrectx, rrecty, rrectz; | |
244 | u32 xxx18[5]; | |
245 | u32 rectr, rectg, rectb, recta; | |
1da177e4 LT |
246 | }; |
247 | ||
248 | struct bt_regs { | |
6993bea1 KH |
249 | u32 addr; |
250 | u32 color_map; | |
251 | u32 control; | |
252 | u32 cursor; | |
1da177e4 LT |
253 | }; |
254 | ||
255 | struct cg6_par { | |
256 | spinlock_t lock; | |
257 | struct bt_regs __iomem *bt; | |
258 | struct cg6_fbc __iomem *fbc; | |
259 | struct cg6_thc __iomem *thc; | |
260 | struct cg6_tec __iomem *tec; | |
50312ce9 | 261 | u32 __iomem *fhc; |
1da177e4 LT |
262 | |
263 | u32 flags; | |
264 | #define CG6_FLAG_BLANKED 0x00000001 | |
265 | ||
266 | unsigned long physbase; | |
50312ce9 | 267 | unsigned long which_io; |
1da177e4 | 268 | unsigned long fbsize; |
1da177e4 LT |
269 | }; |
270 | ||
271 | static int cg6_sync(struct fb_info *info) | |
272 | { | |
6993bea1 | 273 | struct cg6_par *par = (struct cg6_par *)info->par; |
1da177e4 LT |
274 | struct cg6_fbc __iomem *fbc = par->fbc; |
275 | int limit = 10000; | |
276 | ||
277 | do { | |
278 | if (!(sbus_readl(&fbc->s) & 0x10000000)) | |
279 | break; | |
280 | udelay(10); | |
281 | } while (--limit > 0); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
291d5f30 RR |
286 | static void cg6_switch_from_graph(struct cg6_par *par) |
287 | { | |
288 | struct cg6_thc __iomem *thc = par->thc; | |
289 | unsigned long flags; | |
290 | ||
291 | spin_lock_irqsave(&par->lock, flags); | |
292 | ||
293 | /* Hide the cursor. */ | |
294 | sbus_writel(CG6_THC_CURSOFF, &thc->thc_cursxy); | |
295 | ||
296 | spin_unlock_irqrestore(&par->lock, flags); | |
297 | } | |
298 | ||
299 | static int cg6_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |
300 | { | |
301 | struct cg6_par *par = (struct cg6_par *)info->par; | |
302 | ||
303 | /* We just use this to catch switches out of | |
304 | * graphics mode. | |
305 | */ | |
306 | cg6_switch_from_graph(par); | |
307 | ||
308 | if (var->xoffset || var->yoffset || var->vmode) | |
309 | return -EINVAL; | |
310 | return 0; | |
311 | } | |
312 | ||
1da177e4 | 313 | /** |
6993bea1 | 314 | * cg6_fillrect - Draws a rectangle on the screen. |
1da177e4 | 315 | * |
6993bea1 KH |
316 | * @info: frame buffer structure that represents a single frame buffer |
317 | * @rect: structure defining the rectagle and operation. | |
1da177e4 LT |
318 | */ |
319 | static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
320 | { | |
6993bea1 | 321 | struct cg6_par *par = (struct cg6_par *)info->par; |
1da177e4 LT |
322 | struct cg6_fbc __iomem *fbc = par->fbc; |
323 | unsigned long flags; | |
324 | s32 val; | |
325 | ||
a140e94d | 326 | /* CG6 doesn't handle ROP_XOR */ |
1da177e4 LT |
327 | |
328 | spin_lock_irqsave(&par->lock, flags); | |
a140e94d | 329 | |
1da177e4 | 330 | cg6_sync(info); |
a140e94d | 331 | |
1da177e4 LT |
332 | sbus_writel(rect->color, &fbc->fg); |
333 | sbus_writel(~(u32)0, &fbc->pixelm); | |
334 | sbus_writel(0xea80ff00, &fbc->alu); | |
335 | sbus_writel(0, &fbc->s); | |
336 | sbus_writel(0, &fbc->clip); | |
337 | sbus_writel(~(u32)0, &fbc->pm); | |
338 | sbus_writel(rect->dy, &fbc->arecty); | |
339 | sbus_writel(rect->dx, &fbc->arectx); | |
340 | sbus_writel(rect->dy + rect->height, &fbc->arecty); | |
341 | sbus_writel(rect->dx + rect->width, &fbc->arectx); | |
342 | do { | |
343 | val = sbus_readl(&fbc->draw); | |
344 | } while (val < 0 && (val & 0x20000000)); | |
345 | spin_unlock_irqrestore(&par->lock, flags); | |
346 | } | |
347 | ||
a140e94d KH |
348 | /** |
349 | * cg6_copyarea - Copies one area of the screen to another area. | |
350 | * | |
351 | * @info: frame buffer structure that represents a single frame buffer | |
352 | * @area: Structure providing the data to copy the framebuffer contents | |
353 | * from one region to another. | |
354 | * | |
355 | * This drawing operation copies a rectangular area from one area of the | |
356 | * screen to another area. | |
357 | */ | |
358 | static void cg6_copyarea(struct fb_info *info, const struct fb_copyarea *area) | |
359 | { | |
360 | struct cg6_par *par = (struct cg6_par *)info->par; | |
361 | struct cg6_fbc __iomem *fbc = par->fbc; | |
362 | unsigned long flags; | |
363 | int i; | |
364 | ||
365 | spin_lock_irqsave(&par->lock, flags); | |
366 | ||
367 | cg6_sync(info); | |
368 | ||
369 | sbus_writel(0xff, &fbc->fg); | |
370 | sbus_writel(0x00, &fbc->bg); | |
371 | sbus_writel(~0, &fbc->pixelm); | |
372 | sbus_writel(0xe880cccc, &fbc->alu); | |
373 | sbus_writel(0, &fbc->s); | |
374 | sbus_writel(0, &fbc->clip); | |
375 | ||
376 | sbus_writel(area->sy, &fbc->y0); | |
377 | sbus_writel(area->sx, &fbc->x0); | |
378 | sbus_writel(area->sy + area->height - 1, &fbc->y1); | |
379 | sbus_writel(area->sx + area->width - 1, &fbc->x1); | |
380 | sbus_writel(area->dy, &fbc->y2); | |
381 | sbus_writel(area->dx, &fbc->x2); | |
382 | sbus_writel(area->dy + area->height - 1, &fbc->y3); | |
383 | sbus_writel(area->dx + area->width - 1, &fbc->x3); | |
384 | do { | |
385 | i = sbus_readl(&fbc->blit); | |
386 | } while (i < 0 && (i & 0x20000000)); | |
387 | spin_unlock_irqrestore(&par->lock, flags); | |
388 | } | |
389 | ||
1da177e4 | 390 | /** |
6993bea1 | 391 | * cg6_imageblit - Copies a image from system memory to the screen. |
1da177e4 | 392 | * |
6993bea1 KH |
393 | * @info: frame buffer structure that represents a single frame buffer |
394 | * @image: structure defining the image. | |
1da177e4 LT |
395 | */ |
396 | static void cg6_imageblit(struct fb_info *info, const struct fb_image *image) | |
397 | { | |
6993bea1 | 398 | struct cg6_par *par = (struct cg6_par *)info->par; |
1da177e4 LT |
399 | struct cg6_fbc __iomem *fbc = par->fbc; |
400 | const u8 *data = image->data; | |
401 | unsigned long flags; | |
402 | u32 x, y; | |
403 | int i, width; | |
404 | ||
405 | if (image->depth > 1) { | |
406 | cfb_imageblit(info, image); | |
407 | return; | |
408 | } | |
409 | ||
410 | spin_lock_irqsave(&par->lock, flags); | |
411 | ||
412 | cg6_sync(info); | |
413 | ||
414 | sbus_writel(image->fg_color, &fbc->fg); | |
415 | sbus_writel(image->bg_color, &fbc->bg); | |
416 | sbus_writel(0x140000, &fbc->mode); | |
417 | sbus_writel(0xe880fc30, &fbc->alu); | |
418 | sbus_writel(~(u32)0, &fbc->pixelm); | |
419 | sbus_writel(0, &fbc->s); | |
420 | sbus_writel(0, &fbc->clip); | |
421 | sbus_writel(0xff, &fbc->pm); | |
422 | sbus_writel(32, &fbc->incx); | |
423 | sbus_writel(0, &fbc->incy); | |
424 | ||
425 | x = image->dx; | |
426 | y = image->dy; | |
427 | for (i = 0; i < image->height; i++) { | |
428 | width = image->width; | |
429 | ||
430 | while (width >= 32) { | |
431 | u32 val; | |
432 | ||
433 | sbus_writel(y, &fbc->y0); | |
434 | sbus_writel(x, &fbc->x0); | |
435 | sbus_writel(x + 32 - 1, &fbc->x1); | |
6993bea1 | 436 | |
1da177e4 LT |
437 | val = ((u32)data[0] << 24) | |
438 | ((u32)data[1] << 16) | | |
439 | ((u32)data[2] << 8) | | |
440 | ((u32)data[3] << 0); | |
441 | sbus_writel(val, &fbc->font); | |
442 | ||
443 | data += 4; | |
444 | x += 32; | |
445 | width -= 32; | |
446 | } | |
447 | if (width) { | |
448 | u32 val; | |
449 | ||
450 | sbus_writel(y, &fbc->y0); | |
451 | sbus_writel(x, &fbc->x0); | |
452 | sbus_writel(x + width - 1, &fbc->x1); | |
453 | if (width <= 8) { | |
454 | val = (u32) data[0] << 24; | |
455 | data += 1; | |
456 | } else if (width <= 16) { | |
457 | val = ((u32) data[0] << 24) | | |
458 | ((u32) data[1] << 16); | |
459 | data += 2; | |
460 | } else { | |
461 | val = ((u32) data[0] << 24) | | |
462 | ((u32) data[1] << 16) | | |
463 | ((u32) data[2] << 8); | |
464 | data += 3; | |
465 | } | |
466 | sbus_writel(val, &fbc->font); | |
467 | } | |
468 | ||
469 | y += 1; | |
470 | x = image->dx; | |
471 | } | |
472 | ||
473 | spin_unlock_irqrestore(&par->lock, flags); | |
474 | } | |
475 | ||
476 | /** | |
6993bea1 KH |
477 | * cg6_setcolreg - Sets a color register. |
478 | * | |
479 | * @regno: boolean, 0 copy local, 1 get_user() function | |
480 | * @red: frame buffer colormap structure | |
481 | * @green: The green value which can be up to 16 bits wide | |
482 | * @blue: The blue value which can be up to 16 bits wide. | |
483 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
484 | * @info: frame buffer info structure | |
1da177e4 LT |
485 | */ |
486 | static int cg6_setcolreg(unsigned regno, | |
487 | unsigned red, unsigned green, unsigned blue, | |
488 | unsigned transp, struct fb_info *info) | |
489 | { | |
6993bea1 | 490 | struct cg6_par *par = (struct cg6_par *)info->par; |
1da177e4 LT |
491 | struct bt_regs __iomem *bt = par->bt; |
492 | unsigned long flags; | |
493 | ||
494 | if (regno >= 256) | |
495 | return 1; | |
496 | ||
497 | red >>= 8; | |
498 | green >>= 8; | |
499 | blue >>= 8; | |
500 | ||
501 | spin_lock_irqsave(&par->lock, flags); | |
502 | ||
503 | sbus_writel((u32)regno << 24, &bt->addr); | |
504 | sbus_writel((u32)red << 24, &bt->color_map); | |
505 | sbus_writel((u32)green << 24, &bt->color_map); | |
506 | sbus_writel((u32)blue << 24, &bt->color_map); | |
507 | ||
508 | spin_unlock_irqrestore(&par->lock, flags); | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | /** | |
6993bea1 KH |
514 | * cg6_blank - Blanks the display. |
515 | * | |
516 | * @blank_mode: the blank mode we want. | |
517 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 | 518 | */ |
6993bea1 | 519 | static int cg6_blank(int blank, struct fb_info *info) |
1da177e4 | 520 | { |
6993bea1 | 521 | struct cg6_par *par = (struct cg6_par *)info->par; |
1da177e4 LT |
522 | struct cg6_thc __iomem *thc = par->thc; |
523 | unsigned long flags; | |
524 | u32 val; | |
525 | ||
526 | spin_lock_irqsave(&par->lock, flags); | |
6993bea1 | 527 | val = sbus_readl(&thc->thc_misc); |
1da177e4 LT |
528 | |
529 | switch (blank) { | |
530 | case FB_BLANK_UNBLANK: /* Unblanking */ | |
1da177e4 | 531 | val |= CG6_THC_MISC_VIDEO; |
1da177e4 LT |
532 | par->flags &= ~CG6_FLAG_BLANKED; |
533 | break; | |
534 | ||
535 | case FB_BLANK_NORMAL: /* Normal blanking */ | |
536 | case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ | |
537 | case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ | |
538 | case FB_BLANK_POWERDOWN: /* Poweroff */ | |
1da177e4 | 539 | val &= ~CG6_THC_MISC_VIDEO; |
1da177e4 LT |
540 | par->flags |= CG6_FLAG_BLANKED; |
541 | break; | |
542 | } | |
543 | ||
6993bea1 | 544 | sbus_writel(val, &thc->thc_misc); |
1da177e4 LT |
545 | spin_unlock_irqrestore(&par->lock, flags); |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
550 | static struct sbus_mmap_map cg6_mmap_map[] = { | |
551 | { | |
552 | .voff = CG6_FBC, | |
553 | .poff = CG6_FBC_OFFSET, | |
554 | .size = PAGE_SIZE | |
555 | }, | |
556 | { | |
557 | .voff = CG6_TEC, | |
558 | .poff = CG6_TEC_OFFSET, | |
559 | .size = PAGE_SIZE | |
560 | }, | |
561 | { | |
562 | .voff = CG6_BTREGS, | |
563 | .poff = CG6_BROOKTREE_OFFSET, | |
564 | .size = PAGE_SIZE | |
565 | }, | |
566 | { | |
567 | .voff = CG6_FHC, | |
568 | .poff = CG6_FHC_OFFSET, | |
569 | .size = PAGE_SIZE | |
570 | }, | |
571 | { | |
572 | .voff = CG6_THC, | |
573 | .poff = CG6_THC_OFFSET, | |
574 | .size = PAGE_SIZE | |
575 | }, | |
576 | { | |
577 | .voff = CG6_ROM, | |
578 | .poff = CG6_ROM_OFFSET, | |
579 | .size = 0x10000 | |
580 | }, | |
581 | { | |
582 | .voff = CG6_RAM, | |
583 | .poff = CG6_RAM_OFFSET, | |
584 | .size = SBUS_MMAP_FBSIZE(1) | |
585 | }, | |
586 | { | |
587 | .voff = CG6_DHC, | |
588 | .poff = CG6_DHC_OFFSET, | |
589 | .size = 0x40000 | |
590 | }, | |
591 | { .size = 0 } | |
592 | }; | |
593 | ||
216d526c | 594 | static int cg6_mmap(struct fb_info *info, struct vm_area_struct *vma) |
1da177e4 LT |
595 | { |
596 | struct cg6_par *par = (struct cg6_par *)info->par; | |
597 | ||
598 | return sbusfb_mmap_helper(cg6_mmap_map, | |
599 | par->physbase, par->fbsize, | |
50312ce9 | 600 | par->which_io, vma); |
1da177e4 LT |
601 | } |
602 | ||
67a6680d | 603 | static int cg6_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) |
1da177e4 | 604 | { |
6993bea1 | 605 | struct cg6_par *par = (struct cg6_par *)info->par; |
1da177e4 LT |
606 | |
607 | return sbusfb_ioctl_helper(cmd, arg, info, | |
608 | FBTYPE_SUNFAST_COLOR, 8, par->fbsize); | |
609 | } | |
610 | ||
611 | /* | |
612 | * Initialisation | |
613 | */ | |
614 | ||
6993bea1 | 615 | static void __devinit cg6_init_fix(struct fb_info *info, int linebytes) |
1da177e4 LT |
616 | { |
617 | struct cg6_par *par = (struct cg6_par *)info->par; | |
618 | const char *cg6_cpu_name, *cg6_card_name; | |
619 | u32 conf; | |
620 | ||
621 | conf = sbus_readl(par->fhc); | |
6993bea1 | 622 | switch (conf & CG6_FHC_CPU_MASK) { |
1da177e4 LT |
623 | case CG6_FHC_CPU_SPARC: |
624 | cg6_cpu_name = "sparc"; | |
625 | break; | |
626 | case CG6_FHC_CPU_68020: | |
627 | cg6_cpu_name = "68020"; | |
628 | break; | |
629 | default: | |
630 | cg6_cpu_name = "i386"; | |
631 | break; | |
632 | }; | |
633 | if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) { | |
6993bea1 | 634 | if (par->fbsize <= 0x100000) |
1da177e4 | 635 | cg6_card_name = "TGX"; |
6993bea1 | 636 | else |
1da177e4 | 637 | cg6_card_name = "TGX+"; |
1da177e4 | 638 | } else { |
6993bea1 | 639 | if (par->fbsize <= 0x100000) |
1da177e4 | 640 | cg6_card_name = "GX"; |
6993bea1 | 641 | else |
1da177e4 | 642 | cg6_card_name = "GX+"; |
1da177e4 LT |
643 | } |
644 | ||
645 | sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name); | |
6993bea1 | 646 | info->fix.id[sizeof(info->fix.id) - 1] = 0; |
1da177e4 LT |
647 | |
648 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
649 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
650 | ||
651 | info->fix.line_length = linebytes; | |
652 | ||
653 | info->fix.accel = FB_ACCEL_SUN_CGSIX; | |
654 | } | |
655 | ||
656 | /* Initialize Brooktree DAC */ | |
6993bea1 | 657 | static void __devinit cg6_bt_init(struct cg6_par *par) |
1da177e4 LT |
658 | { |
659 | struct bt_regs __iomem *bt = par->bt; | |
660 | ||
6993bea1 | 661 | sbus_writel(0x04 << 24, &bt->addr); /* color planes */ |
1da177e4 LT |
662 | sbus_writel(0xff << 24, &bt->control); |
663 | sbus_writel(0x05 << 24, &bt->addr); | |
664 | sbus_writel(0x00 << 24, &bt->control); | |
6993bea1 | 665 | sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */ |
1da177e4 LT |
666 | sbus_writel(0x73 << 24, &bt->control); |
667 | sbus_writel(0x07 << 24, &bt->addr); | |
668 | sbus_writel(0x00 << 24, &bt->control); | |
669 | } | |
670 | ||
6993bea1 | 671 | static void __devinit cg6_chip_init(struct fb_info *info) |
1da177e4 | 672 | { |
6993bea1 | 673 | struct cg6_par *par = (struct cg6_par *)info->par; |
1da177e4 LT |
674 | struct cg6_tec __iomem *tec = par->tec; |
675 | struct cg6_fbc __iomem *fbc = par->fbc; | |
291d5f30 | 676 | struct cg6_thc __iomem *thc = par->thc; |
806f7bf6 | 677 | u32 rev, conf, mode; |
1da177e4 | 678 | int i; |
6993bea1 | 679 | |
291d5f30 RR |
680 | /* Hide the cursor. */ |
681 | sbus_writel(CG6_THC_CURSOFF, &thc->thc_cursxy); | |
682 | ||
1da177e4 LT |
683 | /* Turn off stuff in the Transform Engine. */ |
684 | sbus_writel(0, &tec->tec_matrix); | |
685 | sbus_writel(0, &tec->tec_clip); | |
686 | sbus_writel(0, &tec->tec_vdc); | |
687 | ||
688 | /* Take care of bugs in old revisions. */ | |
689 | rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK; | |
690 | if (rev < 5) { | |
691 | conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) | | |
692 | CG6_FHC_CPU_68020 | CG6_FHC_TEST | | |
693 | (11 << CG6_FHC_TEST_X_SHIFT) | | |
694 | (11 << CG6_FHC_TEST_Y_SHIFT); | |
695 | if (rev < 2) | |
696 | conf |= CG6_FHC_DST_DISABLE; | |
697 | sbus_writel(conf, par->fhc); | |
698 | } | |
699 | ||
700 | /* Set things in the FBC. Bad things appear to happen if we do | |
701 | * back to back store/loads on the mode register, so copy it | |
702 | * out instead. */ | |
703 | mode = sbus_readl(&fbc->mode); | |
704 | do { | |
705 | i = sbus_readl(&fbc->s); | |
706 | } while (i & 0x10000000); | |
707 | mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK | | |
6993bea1 KH |
708 | CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK | |
709 | CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK | | |
710 | CG6_FBC_BDISP_MASK); | |
1da177e4 | 711 | mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 | |
6993bea1 KH |
712 | CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE | |
713 | CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 | | |
714 | CG6_FBC_BDISP_0); | |
1da177e4 LT |
715 | sbus_writel(mode, &fbc->mode); |
716 | ||
717 | sbus_writel(0, &fbc->clip); | |
718 | sbus_writel(0, &fbc->offx); | |
719 | sbus_writel(0, &fbc->offy); | |
720 | sbus_writel(0, &fbc->clipminx); | |
721 | sbus_writel(0, &fbc->clipminy); | |
722 | sbus_writel(info->var.xres - 1, &fbc->clipmaxx); | |
723 | sbus_writel(info->var.yres - 1, &fbc->clipmaxy); | |
1da177e4 LT |
724 | } |
725 | ||
c7f439b9 DM |
726 | static void cg6_unmap_regs(struct of_device *op, struct fb_info *info, |
727 | struct cg6_par *par) | |
1da177e4 | 728 | { |
c7f439b9 DM |
729 | if (par->fbc) |
730 | of_iounmap(&op->resource[0], par->fbc, 4096); | |
731 | if (par->tec) | |
732 | of_iounmap(&op->resource[0], par->tec, sizeof(struct cg6_tec)); | |
733 | if (par->thc) | |
734 | of_iounmap(&op->resource[0], par->thc, sizeof(struct cg6_thc)); | |
735 | if (par->bt) | |
736 | of_iounmap(&op->resource[0], par->bt, sizeof(struct bt_regs)); | |
737 | if (par->fhc) | |
738 | of_iounmap(&op->resource[0], par->fhc, sizeof(u32)); | |
739 | ||
740 | if (info->screen_base) | |
741 | of_iounmap(&op->resource[0], info->screen_base, par->fbsize); | |
50312ce9 | 742 | } |
1da177e4 | 743 | |
6993bea1 KH |
744 | static int __devinit cg6_probe(struct of_device *op, |
745 | const struct of_device_id *match) | |
50312ce9 DM |
746 | { |
747 | struct device_node *dp = op->node; | |
c7f439b9 DM |
748 | struct fb_info *info; |
749 | struct cg6_par *par; | |
50312ce9 | 750 | int linebytes, err; |
3fc701d5 | 751 | int dblbuf; |
1da177e4 | 752 | |
c7f439b9 DM |
753 | info = framebuffer_alloc(sizeof(struct cg6_par), &op->dev); |
754 | ||
755 | err = -ENOMEM; | |
756 | if (!info) | |
757 | goto out_err; | |
758 | par = info->par; | |
1da177e4 | 759 | |
c7f439b9 | 760 | spin_lock_init(&par->lock); |
1da177e4 | 761 | |
c7f439b9 DM |
762 | par->physbase = op->resource[0].start; |
763 | par->which_io = op->resource[0].flags & IORESOURCE_BITS; | |
1da177e4 | 764 | |
6cd5a86b | 765 | sbusfb_fill_var(&info->var, dp, 8); |
c7f439b9 DM |
766 | info->var.red.length = 8; |
767 | info->var.green.length = 8; | |
768 | info->var.blue.length = 8; | |
1da177e4 | 769 | |
50312ce9 | 770 | linebytes = of_getintprop_default(dp, "linebytes", |
c7f439b9 DM |
771 | info->var.xres); |
772 | par->fbsize = PAGE_ALIGN(linebytes * info->var.yres); | |
3fc701d5 KH |
773 | |
774 | dblbuf = of_getintprop_default(dp, "dblbuf", 0); | |
775 | if (dblbuf) | |
c7f439b9 | 776 | par->fbsize *= 4; |
1da177e4 | 777 | |
c7f439b9 | 778 | par->fbc = of_ioremap(&op->resource[0], CG6_FBC_OFFSET, |
6993bea1 | 779 | 4096, "cgsix fbc"); |
c7f439b9 | 780 | par->tec = of_ioremap(&op->resource[0], CG6_TEC_OFFSET, |
6993bea1 | 781 | sizeof(struct cg6_tec), "cgsix tec"); |
c7f439b9 | 782 | par->thc = of_ioremap(&op->resource[0], CG6_THC_OFFSET, |
6993bea1 | 783 | sizeof(struct cg6_thc), "cgsix thc"); |
c7f439b9 | 784 | par->bt = of_ioremap(&op->resource[0], CG6_BROOKTREE_OFFSET, |
6993bea1 | 785 | sizeof(struct bt_regs), "cgsix dac"); |
c7f439b9 | 786 | par->fhc = of_ioremap(&op->resource[0], CG6_FHC_OFFSET, |
6993bea1 | 787 | sizeof(u32), "cgsix fhc"); |
1da177e4 | 788 | |
c7f439b9 | 789 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT | |
a140e94d KH |
790 | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | |
791 | FBINFO_READS_FAST; | |
c7f439b9 | 792 | info->fbops = &cg6_ops; |
50312ce9 | 793 | |
6993bea1 KH |
794 | info->screen_base = of_ioremap(&op->resource[0], CG6_RAM_OFFSET, |
795 | par->fbsize, "cgsix ram"); | |
c7f439b9 DM |
796 | if (!par->fbc || !par->tec || !par->thc || |
797 | !par->bt || !par->fhc || !info->screen_base) | |
798 | goto out_unmap_regs; | |
1da177e4 | 799 | |
c7f439b9 | 800 | info->var.accel_flags = FB_ACCELF_TEXT; |
1da177e4 | 801 | |
c7f439b9 DM |
802 | cg6_bt_init(par); |
803 | cg6_chip_init(info); | |
59f7137a | 804 | cg6_blank(FB_BLANK_UNBLANK, info); |
1da177e4 | 805 | |
c7f439b9 DM |
806 | if (fb_alloc_cmap(&info->cmap, 256, 0)) |
807 | goto out_unmap_regs; | |
1da177e4 | 808 | |
c7f439b9 DM |
809 | fb_set_cmap(&info->cmap, info); |
810 | cg6_init_fix(info, linebytes); | |
1da177e4 | 811 | |
c7f439b9 DM |
812 | err = register_framebuffer(info); |
813 | if (err < 0) | |
814 | goto out_dealloc_cmap; | |
1da177e4 | 815 | |
c7f439b9 | 816 | dev_set_drvdata(&op->dev, info); |
1da177e4 | 817 | |
194f1a68 | 818 | printk(KERN_INFO "%s: CGsix [%s] at %lx:%lx\n", |
c7f439b9 DM |
819 | dp->full_name, info->fix.id, |
820 | par->which_io, par->physbase); | |
50312ce9 DM |
821 | |
822 | return 0; | |
1da177e4 | 823 | |
c7f439b9 DM |
824 | out_dealloc_cmap: |
825 | fb_dealloc_cmap(&info->cmap); | |
826 | ||
827 | out_unmap_regs: | |
828 | cg6_unmap_regs(op, info, par); | |
1da177e4 | 829 | |
c7f439b9 DM |
830 | out_err: |
831 | return err; | |
50312ce9 | 832 | } |
1da177e4 | 833 | |
e3a411a3 | 834 | static int __devexit cg6_remove(struct of_device *op) |
50312ce9 | 835 | { |
c7f439b9 DM |
836 | struct fb_info *info = dev_get_drvdata(&op->dev); |
837 | struct cg6_par *par = info->par; | |
50312ce9 | 838 | |
c7f439b9 DM |
839 | unregister_framebuffer(info); |
840 | fb_dealloc_cmap(&info->cmap); | |
50312ce9 | 841 | |
c7f439b9 | 842 | cg6_unmap_regs(op, info, par); |
50312ce9 | 843 | |
c7f439b9 | 844 | framebuffer_release(info); |
50312ce9 | 845 | |
e3a411a3 | 846 | dev_set_drvdata(&op->dev, NULL); |
1da177e4 LT |
847 | |
848 | return 0; | |
849 | } | |
850 | ||
fd098316 | 851 | static const struct of_device_id cg6_match[] = { |
50312ce9 DM |
852 | { |
853 | .name = "cgsix", | |
854 | }, | |
855 | { | |
856 | .name = "cgthree+", | |
857 | }, | |
858 | {}, | |
859 | }; | |
860 | MODULE_DEVICE_TABLE(of, cg6_match); | |
1da177e4 | 861 | |
50312ce9 DM |
862 | static struct of_platform_driver cg6_driver = { |
863 | .name = "cg6", | |
864 | .match_table = cg6_match, | |
865 | .probe = cg6_probe, | |
866 | .remove = __devexit_p(cg6_remove), | |
867 | }; | |
1da177e4 | 868 | |
50312ce9 DM |
869 | static int __init cg6_init(void) |
870 | { | |
871 | if (fb_get_options("cg6fb", NULL)) | |
872 | return -ENODEV; | |
873 | ||
874 | return of_register_driver(&cg6_driver, &of_bus_type); | |
1da177e4 LT |
875 | } |
876 | ||
50312ce9 | 877 | static void __exit cg6_exit(void) |
1da177e4 | 878 | { |
50312ce9 | 879 | of_unregister_driver(&cg6_driver); |
1da177e4 LT |
880 | } |
881 | ||
882 | module_init(cg6_init); | |
1da177e4 | 883 | module_exit(cg6_exit); |
1da177e4 LT |
884 | |
885 | MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets"); | |
50312ce9 DM |
886 | MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); |
887 | MODULE_VERSION("2.0"); | |
1da177e4 | 888 | MODULE_LICENSE("GPL"); |