Commit | Line | Data |
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4ed824d9 SR |
1 | /* |
2 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
3 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
4 | * | |
5 | * Based on the LCD driver for TI Avalanche processors written by | |
6 | * Ajay Singh and Shalom Hai. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option)any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/fb.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
9dd44d5d | 29 | #include <linux/pm_runtime.h> |
4ed824d9 | 30 | #include <linux/interrupt.h> |
a481b37a | 31 | #include <linux/wait.h> |
4ed824d9 | 32 | #include <linux/clk.h> |
e04e5483 | 33 | #include <linux/cpufreq.h> |
1d3c6c7b | 34 | #include <linux/console.h> |
deb95c6c | 35 | #include <linux/spinlock.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
a0239073 | 37 | #include <linux/delay.h> |
3b9cc4ea | 38 | #include <linux/lcm.h> |
4ed824d9 | 39 | #include <video/da8xx-fb.h> |
12fa8350 | 40 | #include <asm/div64.h> |
4ed824d9 SR |
41 | |
42 | #define DRIVER_NAME "da8xx_lcdc" | |
43 | ||
c6daf05b MP |
44 | #define LCD_VERSION_1 1 |
45 | #define LCD_VERSION_2 2 | |
46 | ||
4ed824d9 | 47 | /* LCD Status Register */ |
1f9c3e1f | 48 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 49 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 50 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
51 | #define LCD_FIFO_UNDERFLOW BIT(5) |
52 | #define LCD_SYNC_LOST BIT(2) | |
a481b37a | 53 | #define LCD_FRAME_DONE BIT(0) |
4ed824d9 SR |
54 | |
55 | /* LCD DMA Control Register */ | |
56 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
57 | #define LCD_DMA_BURST_1 0x0 | |
58 | #define LCD_DMA_BURST_2 0x1 | |
59 | #define LCD_DMA_BURST_4 0x2 | |
60 | #define LCD_DMA_BURST_8 0x3 | |
61 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
62 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
63 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
64 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
65 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
66 | ||
67 | /* LCD Control Register */ | |
68 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
69 | #define LCD_RASTER_MODE 0x01 | |
70 | ||
71 | /* LCD Raster Control Register */ | |
72 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
73 | #define PALETTE_AND_DATA 0x00 | |
74 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 75 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
76 | |
77 | #define LCD_MONO_8BIT_MODE BIT(9) | |
78 | #define LCD_RASTER_ORDER BIT(8) | |
79 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
80 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
81 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
82 | #define LCD_V1_PL_INT_ENA BIT(4) | |
83 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
84 | #define LCD_MONOCHROME_MODE BIT(1) |
85 | #define LCD_RASTER_ENABLE BIT(0) | |
86 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
87 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
88 | #define LCD_V2_DMA_CLK_EN BIT(2) |
89 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
90 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
91 | #define LCD_V2_LPP_B10 26 | |
1a2b750c MP |
92 | #define LCD_V2_TFT_24BPP_MODE BIT(25) |
93 | #define LCD_V2_TFT_24BPP_UNPACK BIT(26) | |
4ed824d9 SR |
94 | |
95 | /* LCD Raster Timing 2 Register */ | |
96 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
97 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
98 | #define LCD_SYNC_CTRL BIT(25) | |
99 | #define LCD_SYNC_EDGE BIT(24) | |
100 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
101 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
102 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
103 | ||
104 | /* LCD Block */ | |
c6daf05b | 105 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
106 | #define LCD_CTRL_REG 0x4 |
107 | #define LCD_STAT_REG 0x8 | |
108 | #define LCD_RASTER_CTRL_REG 0x28 | |
109 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
110 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
111 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
112 | #define LCD_DMA_CTRL_REG 0x40 | |
113 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
114 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
115 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
116 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
117 | ||
c6daf05b MP |
118 | /* Interrupt Registers available only in Version 2 */ |
119 | #define LCD_RAW_STAT_REG 0x58 | |
120 | #define LCD_MASKED_STAT_REG 0x5c | |
121 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
122 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
123 | #define LCD_END_OF_INT_IND_REG 0x68 | |
124 | ||
125 | /* Clock registers available only on Version 2 */ | |
126 | #define LCD_CLK_ENABLE_REG 0x6c | |
127 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 128 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 129 | |
1f9c3e1f | 130 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 SR |
131 | |
132 | #define WSI_TIMEOUT 50 | |
133 | #define PALETTE_SIZE 256 | |
4ed824d9 | 134 | |
2dfa77a2 DE |
135 | #define CLK_MIN_DIV 2 |
136 | #define CLK_MAX_DIV 255 | |
137 | ||
34aef6eb | 138 | static void __iomem *da8xx_fb_reg_base; |
c6daf05b MP |
139 | static unsigned int lcd_revision; |
140 | static irq_handler_t lcdc_irq_handler; | |
a481b37a MP |
141 | static wait_queue_head_t frame_done_wq; |
142 | static int frame_done_flag; | |
4ed824d9 | 143 | |
a9cd67c8 | 144 | static unsigned int lcdc_read(unsigned int addr) |
4ed824d9 SR |
145 | { |
146 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
147 | } | |
148 | ||
a9cd67c8 | 149 | static void lcdc_write(unsigned int val, unsigned int addr) |
4ed824d9 SR |
150 | { |
151 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
152 | } | |
153 | ||
154 | struct da8xx_fb_par { | |
dbe8e48a | 155 | struct device *dev; |
4ed824d9 SR |
156 | resource_size_t p_palette_base; |
157 | unsigned char *v_palette_base; | |
1f9c3e1f MA |
158 | dma_addr_t vram_phys; |
159 | unsigned long vram_size; | |
160 | void *vram_virt; | |
161 | unsigned int dma_start; | |
162 | unsigned int dma_end; | |
4ed824d9 SR |
163 | struct clk *lcdc_clk; |
164 | int irq; | |
4ed824d9 | 165 | unsigned int palette_sz; |
36113804 | 166 | int blank; |
1f9c3e1f MA |
167 | wait_queue_head_t vsync_wait; |
168 | int vsync_flag; | |
169 | int vsync_timeout; | |
deb95c6c MP |
170 | spinlock_t lock_for_chan_update; |
171 | ||
172 | /* | |
173 | * LCDC has 2 ping pong DMA channels, channel 0 | |
174 | * and channel 1. | |
175 | */ | |
176 | unsigned int which_dma_channel_done; | |
e04e5483 C |
177 | #ifdef CONFIG_CPU_FREQ |
178 | struct notifier_block freq_transition; | |
179 | #endif | |
0715c72d | 180 | unsigned int lcdc_clk_rate; |
36113804 | 181 | void (*panel_power_ctrl)(int); |
1a2b750c | 182 | u32 pseudo_palette[16]; |
b6dbe8e4 AM |
183 | struct fb_videomode mode; |
184 | struct lcd_ctrl_config cfg; | |
4ed824d9 SR |
185 | }; |
186 | ||
be0f6dbc | 187 | static struct fb_var_screeninfo da8xx_fb_var; |
4ed824d9 | 188 | |
48c68c4f | 189 | static struct fb_fix_screeninfo da8xx_fb_fix = { |
4ed824d9 SR |
190 | .id = "DA8xx FB Drv", |
191 | .type = FB_TYPE_PACKED_PIXELS, | |
192 | .type_aux = 0, | |
193 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 194 | .xpanstep = 0, |
4ed824d9 | 195 | .ypanstep = 1, |
1f9c3e1f | 196 | .ywrapstep = 0, |
4ed824d9 SR |
197 | .accel = FB_ACCEL_NONE |
198 | }; | |
199 | ||
f772fabd | 200 | static struct fb_videomode known_lcd_panels[] = { |
4ed824d9 SR |
201 | /* Sharp LCD035Q3DG01 */ |
202 | [0] = { | |
f772fabd MP |
203 | .name = "Sharp_LCD035Q3DG01", |
204 | .xres = 320, | |
205 | .yres = 240, | |
a6a799f8 | 206 | .pixclock = KHZ2PICOS(4607), |
f772fabd MP |
207 | .left_margin = 6, |
208 | .right_margin = 8, | |
209 | .upper_margin = 2, | |
210 | .lower_margin = 2, | |
211 | .hsync_len = 0, | |
212 | .vsync_len = 0, | |
3b43ad20 MP |
213 | .sync = FB_SYNC_CLK_INVERT | |
214 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
4ed824d9 SR |
215 | }, |
216 | /* Sharp LK043T1DG01 */ | |
217 | [1] = { | |
f772fabd MP |
218 | .name = "Sharp_LK043T1DG01", |
219 | .xres = 480, | |
220 | .yres = 272, | |
a6a799f8 | 221 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
222 | .left_margin = 2, |
223 | .right_margin = 2, | |
224 | .upper_margin = 2, | |
225 | .lower_margin = 2, | |
226 | .hsync_len = 41, | |
227 | .vsync_len = 10, | |
3b43ad20 | 228 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
f772fabd | 229 | .flag = 0, |
4ed824d9 | 230 | }, |
f413070e AG |
231 | [2] = { |
232 | /* Hitachi SP10Q010 */ | |
f772fabd MP |
233 | .name = "SP10Q010", |
234 | .xres = 320, | |
235 | .yres = 240, | |
a6a799f8 | 236 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
237 | .left_margin = 10, |
238 | .right_margin = 10, | |
239 | .upper_margin = 10, | |
240 | .lower_margin = 10, | |
241 | .hsync_len = 10, | |
242 | .vsync_len = 10, | |
3b43ad20 | 243 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
f772fabd | 244 | .flag = 0, |
f413070e | 245 | }, |
4ed824d9 SR |
246 | }; |
247 | ||
a9cd67c8 | 248 | static bool da8xx_fb_is_raster_enabled(void) |
fe8c98f0 DE |
249 | { |
250 | return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE); | |
251 | } | |
252 | ||
36113804 | 253 | /* Enable the Raster Engine of the LCD Controller */ |
a9cd67c8 | 254 | static void lcd_enable_raster(void) |
36113804 C |
255 | { |
256 | u32 reg; | |
257 | ||
92b4e450 MP |
258 | /* Put LCDC in reset for several cycles */ |
259 | if (lcd_revision == LCD_VERSION_2) | |
260 | /* Write 1 to reset LCDC */ | |
261 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
262 | mdelay(1); | |
263 | ||
74a0efde MP |
264 | /* Bring LCDC out of reset */ |
265 | if (lcd_revision == LCD_VERSION_2) | |
266 | lcdc_write(0, LCD_CLK_RESET_REG); | |
92b4e450 | 267 | mdelay(1); |
74a0efde | 268 | |
92b4e450 | 269 | /* Above reset sequence doesnot reset register context */ |
36113804 C |
270 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
271 | if (!(reg & LCD_RASTER_ENABLE)) | |
272 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
273 | } | |
274 | ||
4ed824d9 | 275 | /* Disable the Raster Engine of the LCD Controller */ |
a9cd67c8 | 276 | static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done) |
4ed824d9 | 277 | { |
4ed824d9 | 278 | u32 reg; |
a481b37a | 279 | int ret; |
4ed824d9 SR |
280 | |
281 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 282 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 283 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
a481b37a MP |
284 | else |
285 | /* return if already disabled */ | |
286 | return; | |
287 | ||
26e71645 DE |
288 | if ((wait_for_frame_done == DA8XX_FRAME_WAIT) && |
289 | (lcd_revision == LCD_VERSION_2)) { | |
a481b37a MP |
290 | frame_done_flag = 0; |
291 | ret = wait_event_interruptible_timeout(frame_done_wq, | |
292 | frame_done_flag != 0, | |
293 | msecs_to_jiffies(50)); | |
294 | if (ret == 0) | |
295 | pr_err("LCD Controller timed out\n"); | |
296 | } | |
4ed824d9 SR |
297 | } |
298 | ||
299 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
300 | { | |
1f9c3e1f MA |
301 | u32 start; |
302 | u32 end; | |
303 | u32 reg_ras; | |
304 | u32 reg_dma; | |
c6daf05b | 305 | u32 reg_int; |
1f9c3e1f MA |
306 | |
307 | /* init reg to clear PLM (loading mode) fields */ | |
308 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
309 | reg_ras &= ~(3 << 20); | |
310 | ||
311 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
312 | ||
313 | if (load_mode == LOAD_DATA) { | |
314 | start = par->dma_start; | |
315 | end = par->dma_end; | |
316 | ||
317 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
318 | if (lcd_revision == LCD_VERSION_1) { |
319 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
320 | } else { | |
321 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
322 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
a481b37a | 323 | LCD_V2_END_OF_FRAME1_INT_ENA | |
e4008e22 | 324 | LCD_FRAME_DONE | LCD_SYNC_LOST; |
c6daf05b MP |
325 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
326 | } | |
1f9c3e1f MA |
327 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
328 | ||
329 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
330 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
331 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
332 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
333 | } else if (load_mode == LOAD_PALETTE) { | |
334 | start = par->p_palette_base; | |
335 | end = start + par->palette_sz - 1; | |
336 | ||
337 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
338 | |
339 | if (lcd_revision == LCD_VERSION_1) { | |
340 | reg_ras |= LCD_V1_PL_INT_ENA; | |
341 | } else { | |
342 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
343 | LCD_V2_PL_INT_ENA; | |
344 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
345 | } | |
1f9c3e1f MA |
346 | |
347 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
348 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
349 | } | |
4ed824d9 | 350 | |
1f9c3e1f MA |
351 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
352 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 353 | |
1f9c3e1f MA |
354 | /* |
355 | * The Raster enable bit must be set after all other control fields are | |
356 | * set. | |
357 | */ | |
358 | lcd_enable_raster(); | |
4ed824d9 SR |
359 | } |
360 | ||
fb8fa943 MP |
361 | /* Configure the Burst Size and fifo threhold of DMA */ |
362 | static int lcd_cfg_dma(int burst_size, int fifo_th) | |
4ed824d9 SR |
363 | { |
364 | u32 reg; | |
365 | ||
366 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
367 | switch (burst_size) { | |
368 | case 1: | |
369 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
370 | break; | |
371 | case 2: | |
372 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
373 | break; | |
374 | case 4: | |
375 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
376 | break; | |
377 | case 8: | |
378 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
379 | break; | |
380 | case 16: | |
3b43ad20 | 381 | default: |
4ed824d9 SR |
382 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); |
383 | break; | |
4ed824d9 | 384 | } |
fb8fa943 MP |
385 | |
386 | reg |= (fifo_th << 8); | |
387 | ||
2f93e8f4 | 388 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
393 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
394 | { | |
395 | u32 reg; | |
396 | ||
397 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
398 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
399 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
400 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
401 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
402 | } | |
403 | ||
404 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
405 | int front_porch) | |
406 | { | |
407 | u32 reg; | |
408 | ||
409 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; | |
83edd73a DE |
410 | reg |= (((back_porch-1) & 0xff) << 24) |
411 | | (((front_porch-1) & 0xff) << 16) | |
412 | | (((pulse_width-1) & 0x3f) << 10); | |
4ed824d9 | 413 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
2645ad16 DE |
414 | |
415 | /* | |
416 | * LCDC Version 2 adds some extra bits that increase the allowable | |
417 | * size of the horizontal timing registers. | |
418 | * remember that the registers use 0 to represent 1 so all values | |
419 | * that get set into register need to be decremented by 1 | |
420 | */ | |
421 | if (lcd_revision == LCD_VERSION_2) { | |
422 | /* Mask off the bits we want to change */ | |
423 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff; | |
424 | reg |= ((front_porch-1) & 0x300) >> 8; | |
425 | reg |= ((back_porch-1) & 0x300) >> 4; | |
426 | reg |= ((pulse_width-1) & 0x3c0) << 21; | |
427 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
428 | } | |
4ed824d9 SR |
429 | } |
430 | ||
431 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
432 | int front_porch) | |
433 | { | |
434 | u32 reg; | |
435 | ||
436 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
437 | reg |= ((back_porch & 0xff) << 24) | |
438 | | ((front_porch & 0xff) << 16) | |
83edd73a | 439 | | (((pulse_width-1) & 0x3f) << 10); |
4ed824d9 SR |
440 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); |
441 | } | |
442 | ||
3b43ad20 MP |
443 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, |
444 | struct fb_videomode *panel) | |
4ed824d9 SR |
445 | { |
446 | u32 reg; | |
c6daf05b | 447 | u32 reg_int; |
4ed824d9 SR |
448 | |
449 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
450 | LCD_MONO_8BIT_MODE | | |
451 | LCD_MONOCHROME_MODE); | |
452 | ||
3b43ad20 | 453 | switch (cfg->panel_shade) { |
4ed824d9 SR |
454 | case MONOCHROME: |
455 | reg |= LCD_MONOCHROME_MODE; | |
456 | if (cfg->mono_8bit_mode) | |
457 | reg |= LCD_MONO_8BIT_MODE; | |
458 | break; | |
459 | case COLOR_ACTIVE: | |
460 | reg |= LCD_TFT_MODE; | |
461 | if (cfg->tft_alt_mode) | |
462 | reg |= LCD_TFT_ALT_ENABLE; | |
463 | break; | |
464 | ||
465 | case COLOR_PASSIVE: | |
3b43ad20 MP |
466 | /* AC bias applicable only for Pasive panels */ |
467 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
468 | if (cfg->bpp == 12 && cfg->stn_565_mode) | |
4ed824d9 SR |
469 | reg |= LCD_STN_565_ENABLE; |
470 | break; | |
471 | ||
472 | default: | |
473 | return -EINVAL; | |
474 | } | |
475 | ||
476 | /* enable additional interrupts here */ | |
c6daf05b MP |
477 | if (lcd_revision == LCD_VERSION_1) { |
478 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
479 | } else { | |
480 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
481 | LCD_V2_UNDERFLOW_INT_ENA; | |
482 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
483 | } | |
4ed824d9 SR |
484 | |
485 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
486 | ||
487 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
488 | ||
3b43ad20 | 489 | reg |= LCD_SYNC_CTRL; |
4ed824d9 SR |
490 | |
491 | if (cfg->sync_edge) | |
492 | reg |= LCD_SYNC_EDGE; | |
493 | else | |
494 | reg &= ~LCD_SYNC_EDGE; | |
495 | ||
028cd86b | 496 | if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0) |
4ed824d9 SR |
497 | reg |= LCD_INVERT_LINE_CLOCK; |
498 | else | |
499 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
500 | ||
028cd86b | 501 | if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0) |
4ed824d9 SR |
502 | reg |= LCD_INVERT_FRAME_CLOCK; |
503 | else | |
504 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
505 | ||
506 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
512 | u32 bpp, u32 raster_order) | |
513 | { | |
1f9c3e1f | 514 | u32 reg; |
4ed824d9 | 515 | |
1a2b750c MP |
516 | if (bpp > 16 && lcd_revision == LCD_VERSION_1) |
517 | return -EINVAL; | |
518 | ||
4ed824d9 SR |
519 | /* Set the Panel Width */ |
520 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
521 | if (lcd_revision == LCD_VERSION_1) { |
522 | /* | |
523 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
524 | * pixels. | |
525 | */ | |
526 | width &= 0x3f0; | |
527 | } else { | |
528 | /* | |
529 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
530 | * pixels. | |
531 | */ | |
532 | width &= 0x7f0; | |
533 | } | |
534 | ||
4ed824d9 SR |
535 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
536 | reg &= 0xfffffc00; | |
4d740801 MP |
537 | if (lcd_revision == LCD_VERSION_1) { |
538 | reg |= ((width >> 4) - 1) << 4; | |
539 | } else { | |
540 | width = (width >> 4) - 1; | |
541 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
542 | } | |
4ed824d9 SR |
543 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
544 | ||
545 | /* Set the Panel Height */ | |
4d740801 | 546 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
547 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
548 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
549 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
550 | ||
4d740801 MP |
551 | /* Set bit 10 of Lines Per Pixel */ |
552 | if (lcd_revision == LCD_VERSION_2) { | |
553 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
554 | reg |= ((height - 1) & 0x400) << 16; | |
555 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
556 | } | |
557 | ||
4ed824d9 SR |
558 | /* Set the Raster Order of the Frame Buffer */ |
559 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
560 | if (raster_order) | |
561 | reg |= LCD_RASTER_ORDER; | |
1a2b750c MP |
562 | |
563 | par->palette_sz = 16 * 2; | |
4ed824d9 SR |
564 | |
565 | switch (bpp) { | |
566 | case 1: | |
567 | case 2: | |
568 | case 4: | |
569 | case 16: | |
1a2b750c MP |
570 | break; |
571 | case 24: | |
572 | reg |= LCD_V2_TFT_24BPP_MODE; | |
fa8a00cc | 573 | break; |
1a2b750c | 574 | case 32: |
fa8a00cc | 575 | reg |= LCD_V2_TFT_24BPP_MODE; |
1a2b750c | 576 | reg |= LCD_V2_TFT_24BPP_UNPACK; |
4ed824d9 | 577 | break; |
4ed824d9 SR |
578 | case 8: |
579 | par->palette_sz = 256 * 2; | |
580 | break; | |
581 | ||
582 | default: | |
583 | return -EINVAL; | |
584 | } | |
585 | ||
1a2b750c MP |
586 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
587 | ||
4ed824d9 SR |
588 | return 0; |
589 | } | |
590 | ||
1a2b750c | 591 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
4ed824d9 SR |
592 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
593 | unsigned blue, unsigned transp, | |
594 | struct fb_info *info) | |
595 | { | |
596 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 597 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 598 | u_short pal; |
1f9c3e1f | 599 | int update_hw = 0; |
4ed824d9 SR |
600 | |
601 | if (regno > 255) | |
602 | return 1; | |
603 | ||
604 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
605 | return 1; | |
606 | ||
1a2b750c MP |
607 | if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
608 | return -EINVAL; | |
f413070e | 609 | |
1a2b750c MP |
610 | switch (info->fix.visual) { |
611 | case FB_VISUAL_TRUECOLOR: | |
612 | red = CNVT_TOHW(red, info->var.red.length); | |
613 | green = CNVT_TOHW(green, info->var.green.length); | |
614 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
615 | break; | |
616 | case FB_VISUAL_PSEUDOCOLOR: | |
617 | switch (info->var.bits_per_pixel) { | |
618 | case 4: | |
619 | if (regno > 15) | |
620 | return -EINVAL; | |
621 | ||
622 | if (info->var.grayscale) { | |
623 | pal = regno; | |
624 | } else { | |
625 | red >>= 4; | |
626 | green >>= 8; | |
627 | blue >>= 12; | |
628 | ||
629 | pal = red & 0x0f00; | |
630 | pal |= green & 0x00f0; | |
631 | pal |= blue & 0x000f; | |
632 | } | |
633 | if (regno == 0) | |
634 | pal |= 0x2000; | |
635 | palette[regno] = pal; | |
636 | break; | |
637 | ||
638 | case 8: | |
f413070e AG |
639 | red >>= 4; |
640 | green >>= 8; | |
641 | blue >>= 12; | |
642 | ||
643 | pal = (red & 0x0f00); | |
644 | pal |= (green & 0x00f0); | |
645 | pal |= (blue & 0x000f); | |
4ed824d9 | 646 | |
1a2b750c MP |
647 | if (palette[regno] != pal) { |
648 | update_hw = 1; | |
649 | palette[regno] = pal; | |
650 | } | |
651 | break; | |
1f9c3e1f | 652 | } |
1a2b750c MP |
653 | break; |
654 | } | |
4ed824d9 | 655 | |
1a2b750c MP |
656 | /* Truecolor has hardware independent palette */ |
657 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
658 | u32 v; | |
4ed824d9 | 659 | |
1a2b750c MP |
660 | if (regno > 15) |
661 | return -EINVAL; | |
4ed824d9 | 662 | |
1a2b750c MP |
663 | v = (red << info->var.red.offset) | |
664 | (green << info->var.green.offset) | | |
665 | (blue << info->var.blue.offset); | |
4ed824d9 | 666 | |
1a2b750c MP |
667 | switch (info->var.bits_per_pixel) { |
668 | case 16: | |
669 | ((u16 *) (info->pseudo_palette))[regno] = v; | |
670 | break; | |
671 | case 24: | |
672 | case 32: | |
673 | ((u32 *) (info->pseudo_palette))[regno] = v; | |
674 | break; | |
675 | } | |
1f9c3e1f MA |
676 | if (palette[0] != 0x4000) { |
677 | update_hw = 1; | |
678 | palette[0] = 0x4000; | |
679 | } | |
4ed824d9 SR |
680 | } |
681 | ||
1f9c3e1f MA |
682 | /* Update the palette in the h/w as needed. */ |
683 | if (update_hw) | |
684 | lcd_blit(LOAD_PALETTE, par); | |
685 | ||
4ed824d9 SR |
686 | return 0; |
687 | } | |
1a2b750c | 688 | #undef CNVT_TOHW |
4ed824d9 | 689 | |
39c87d45 | 690 | static void da8xx_fb_lcd_reset(void) |
4ed824d9 | 691 | { |
4ed824d9 SR |
692 | /* DMA has to be disabled */ |
693 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
694 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 695 | |
74a0efde | 696 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 697 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
698 | /* Write 1 to reset */ |
699 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
700 | lcdc_write(0, LCD_CLK_RESET_REG); | |
701 | } | |
4ed824d9 SR |
702 | } |
703 | ||
2dfa77a2 DE |
704 | static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par, |
705 | unsigned lcdc_clk_div, | |
706 | unsigned lcdc_clk_rate) | |
404fdfe7 | 707 | { |
2dfa77a2 | 708 | int ret; |
404fdfe7 | 709 | |
0715c72d | 710 | if (par->lcdc_clk_rate != lcdc_clk_rate) { |
2dfa77a2 DE |
711 | ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate); |
712 | if (IS_ERR_VALUE(ret)) { | |
713 | dev_err(par->dev, | |
714 | "unable to set clock rate at %u\n", | |
715 | lcdc_clk_rate); | |
716 | return ret; | |
717 | } | |
0715c72d | 718 | par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); |
2dfa77a2 | 719 | } |
404fdfe7 | 720 | |
8097b174 | 721 | /* Configure the LCD clock divisor. */ |
2dfa77a2 | 722 | lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) | |
8097b174 | 723 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); |
c6daf05b MP |
724 | |
725 | if (lcd_revision == LCD_VERSION_2) | |
726 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
727 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
2dfa77a2 DE |
728 | |
729 | return 0; | |
a6a799f8 DE |
730 | } |
731 | ||
2dfa77a2 DE |
732 | static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par, |
733 | unsigned pixclock, | |
734 | unsigned *lcdc_clk_rate) | |
a6a799f8 | 735 | { |
2dfa77a2 DE |
736 | unsigned lcdc_clk_div; |
737 | ||
738 | pixclock = PICOS2KHZ(pixclock) * 1000; | |
739 | ||
0715c72d | 740 | *lcdc_clk_rate = par->lcdc_clk_rate; |
c6daf05b | 741 | |
2dfa77a2 DE |
742 | if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) { |
743 | *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, | |
744 | pixclock * CLK_MAX_DIV); | |
745 | lcdc_clk_div = CLK_MAX_DIV; | |
746 | } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) { | |
747 | *lcdc_clk_rate = clk_round_rate(par->lcdc_clk, | |
748 | pixclock * CLK_MIN_DIV); | |
749 | lcdc_clk_div = CLK_MIN_DIV; | |
750 | } else { | |
751 | lcdc_clk_div = *lcdc_clk_rate / pixclock; | |
752 | } | |
753 | ||
754 | return lcdc_clk_div; | |
755 | } | |
756 | ||
757 | static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par, | |
758 | struct fb_videomode *mode) | |
759 | { | |
760 | unsigned lcdc_clk_rate; | |
761 | unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock, | |
762 | &lcdc_clk_rate); | |
763 | ||
764 | return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate); | |
765 | } | |
766 | ||
a9cd67c8 | 767 | static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par, |
2dfa77a2 DE |
768 | unsigned pixclock) |
769 | { | |
770 | unsigned lcdc_clk_div, lcdc_clk_rate; | |
771 | ||
772 | lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate); | |
773 | return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div)); | |
8097b174 C |
774 | } |
775 | ||
4ed824d9 | 776 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
f772fabd | 777 | struct fb_videomode *panel) |
4ed824d9 SR |
778 | { |
779 | u32 bpp; | |
780 | int ret = 0; | |
781 | ||
2dfa77a2 DE |
782 | ret = da8xx_fb_calc_config_clk_divider(par, panel); |
783 | if (IS_ERR_VALUE(ret)) { | |
784 | dev_err(par->dev, "unable to configure clock\n"); | |
785 | return ret; | |
786 | } | |
4ed824d9 | 787 | |
f772fabd | 788 | if (panel->sync & FB_SYNC_CLK_INVERT) |
2f93e8f4 SR |
789 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | |
790 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
791 | else | |
792 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
793 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
794 | ||
fb8fa943 MP |
795 | /* Configure the DMA burst size and fifo threshold. */ |
796 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); | |
4ed824d9 SR |
797 | if (ret < 0) |
798 | return ret; | |
799 | ||
4ed824d9 | 800 | /* Configure the vertical and horizontal sync properties. */ |
a592d9fd DE |
801 | lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len, |
802 | panel->lower_margin); | |
803 | lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len, | |
804 | panel->right_margin); | |
4ed824d9 SR |
805 | |
806 | /* Configure for disply */ | |
3b43ad20 | 807 | ret = lcd_cfg_display(cfg, panel); |
4ed824d9 SR |
808 | if (ret < 0) |
809 | return ret; | |
810 | ||
3b43ad20 | 811 | bpp = cfg->bpp; |
4ed824d9 | 812 | |
4ed824d9 SR |
813 | if (bpp == 12) |
814 | bpp = 16; | |
f772fabd MP |
815 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, |
816 | (unsigned int)panel->yres, bpp, | |
4ed824d9 SR |
817 | cfg->raster_order); |
818 | if (ret < 0) | |
819 | return ret; | |
820 | ||
821 | /* Configure FDD */ | |
822 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
823 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
c6daf05b MP |
828 | /* IRQ handler for version 2 of LCDC */ |
829 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
830 | { | |
831 | struct da8xx_fb_par *par = arg; | |
832 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
c6daf05b MP |
833 | |
834 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
26e71645 | 835 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
c6daf05b MP |
836 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
837 | lcd_enable_raster(); | |
838 | } else if (stat & LCD_PL_LOAD_DONE) { | |
839 | /* | |
840 | * Must disable raster before changing state of any control bit. | |
841 | * And also must be disabled before clearing the PL loading | |
842 | * interrupt via the following write to the status register. If | |
843 | * this is done after then one gets multiple PL done interrupts. | |
844 | */ | |
26e71645 | 845 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
c6daf05b MP |
846 | |
847 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
848 | ||
8a81dccd MP |
849 | /* Disable PL completion interrupt */ |
850 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); | |
c6daf05b MP |
851 | |
852 | /* Setup and start data loading mode */ | |
853 | lcd_blit(LOAD_DATA, par); | |
854 | } else { | |
855 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
856 | ||
857 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 858 | par->which_dma_channel_done = 0; |
c6daf05b MP |
859 | lcdc_write(par->dma_start, |
860 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
861 | lcdc_write(par->dma_end, | |
862 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
863 | par->vsync_flag = 1; | |
864 | wake_up_interruptible(&par->vsync_wait); | |
865 | } | |
866 | ||
867 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 868 | par->which_dma_channel_done = 1; |
c6daf05b MP |
869 | lcdc_write(par->dma_start, |
870 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
871 | lcdc_write(par->dma_end, | |
872 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
873 | par->vsync_flag = 1; | |
874 | wake_up_interruptible(&par->vsync_wait); | |
875 | } | |
a481b37a MP |
876 | |
877 | /* Set only when controller is disabled and at the end of | |
878 | * active frame | |
879 | */ | |
880 | if (stat & BIT(0)) { | |
881 | frame_done_flag = 1; | |
882 | wake_up_interruptible(&frame_done_wq); | |
883 | } | |
c6daf05b MP |
884 | } |
885 | ||
886 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
887 | return IRQ_HANDLED; | |
888 | } | |
889 | ||
890 | /* IRQ handler for version 1 LCDC */ | |
891 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 892 | { |
1f9c3e1f | 893 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 894 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 895 | u32 reg_ras; |
4ed824d9 SR |
896 | |
897 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
26e71645 | 898 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
4ed824d9 | 899 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 900 | lcd_enable_raster(); |
1f9c3e1f MA |
901 | } else if (stat & LCD_PL_LOAD_DONE) { |
902 | /* | |
903 | * Must disable raster before changing state of any control bit. | |
904 | * And also must be disabled before clearing the PL loading | |
905 | * interrupt via the following write to the status register. If | |
906 | * this is done after then one gets multiple PL done interrupts. | |
907 | */ | |
26e71645 | 908 | lcd_disable_raster(DA8XX_FRAME_NOWAIT); |
1f9c3e1f | 909 | |
4ed824d9 SR |
910 | lcdc_write(stat, LCD_STAT_REG); |
911 | ||
1f9c3e1f MA |
912 | /* Disable PL completion inerrupt */ |
913 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 914 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
915 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
916 | ||
917 | /* Setup and start data loading mode */ | |
918 | lcd_blit(LOAD_DATA, par); | |
919 | } else { | |
920 | lcdc_write(stat, LCD_STAT_REG); | |
921 | ||
922 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 923 | par->which_dma_channel_done = 0; |
1f9c3e1f MA |
924 | lcdc_write(par->dma_start, |
925 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
926 | lcdc_write(par->dma_end, | |
927 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
928 | par->vsync_flag = 1; | |
929 | wake_up_interruptible(&par->vsync_wait); | |
930 | } | |
931 | ||
932 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 933 | par->which_dma_channel_done = 1; |
1f9c3e1f MA |
934 | lcdc_write(par->dma_start, |
935 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
936 | lcdc_write(par->dma_end, | |
937 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
938 | par->vsync_flag = 1; | |
939 | wake_up_interruptible(&par->vsync_wait); | |
940 | } | |
941 | } | |
942 | ||
4ed824d9 SR |
943 | return IRQ_HANDLED; |
944 | } | |
945 | ||
946 | static int fb_check_var(struct fb_var_screeninfo *var, | |
947 | struct fb_info *info) | |
948 | { | |
949 | int err = 0; | |
87dac71d AM |
950 | struct da8xx_fb_par *par = info->par; |
951 | int bpp = var->bits_per_pixel >> 3; | |
952 | unsigned long line_size = var->xres_virtual * bpp; | |
4ed824d9 | 953 | |
1a2b750c MP |
954 | if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
955 | return -EINVAL; | |
956 | ||
4ed824d9 SR |
957 | switch (var->bits_per_pixel) { |
958 | case 1: | |
959 | case 8: | |
960 | var->red.offset = 0; | |
961 | var->red.length = 8; | |
962 | var->green.offset = 0; | |
963 | var->green.length = 8; | |
964 | var->blue.offset = 0; | |
965 | var->blue.length = 8; | |
966 | var->transp.offset = 0; | |
967 | var->transp.length = 0; | |
f413070e | 968 | var->nonstd = 0; |
4ed824d9 SR |
969 | break; |
970 | case 4: | |
971 | var->red.offset = 0; | |
972 | var->red.length = 4; | |
973 | var->green.offset = 0; | |
974 | var->green.length = 4; | |
975 | var->blue.offset = 0; | |
976 | var->blue.length = 4; | |
977 | var->transp.offset = 0; | |
978 | var->transp.length = 0; | |
f413070e | 979 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
980 | break; |
981 | case 16: /* RGB 565 */ | |
3510b8f7 | 982 | var->red.offset = 11; |
4ed824d9 SR |
983 | var->red.length = 5; |
984 | var->green.offset = 5; | |
985 | var->green.length = 6; | |
3510b8f7 | 986 | var->blue.offset = 0; |
4ed824d9 SR |
987 | var->blue.length = 5; |
988 | var->transp.offset = 0; | |
989 | var->transp.length = 0; | |
f413070e | 990 | var->nonstd = 0; |
4ed824d9 | 991 | break; |
1a2b750c MP |
992 | case 24: |
993 | var->red.offset = 16; | |
994 | var->red.length = 8; | |
995 | var->green.offset = 8; | |
996 | var->green.length = 8; | |
997 | var->blue.offset = 0; | |
998 | var->blue.length = 8; | |
999 | var->nonstd = 0; | |
1000 | break; | |
1001 | case 32: | |
1002 | var->transp.offset = 24; | |
1003 | var->transp.length = 8; | |
1004 | var->red.offset = 16; | |
1005 | var->red.length = 8; | |
1006 | var->green.offset = 8; | |
1007 | var->green.length = 8; | |
1008 | var->blue.offset = 0; | |
1009 | var->blue.length = 8; | |
1010 | var->nonstd = 0; | |
1011 | break; | |
4ed824d9 SR |
1012 | default: |
1013 | err = -EINVAL; | |
1014 | } | |
1015 | ||
1016 | var->red.msb_right = 0; | |
1017 | var->green.msb_right = 0; | |
1018 | var->blue.msb_right = 0; | |
1019 | var->transp.msb_right = 0; | |
87dac71d AM |
1020 | |
1021 | if (line_size * var->yres_virtual > par->vram_size) | |
1022 | var->yres_virtual = par->vram_size / line_size; | |
1023 | ||
1024 | if (var->yres > var->yres_virtual) | |
1025 | var->yres = var->yres_virtual; | |
1026 | ||
1027 | if (var->xres > var->xres_virtual) | |
1028 | var->xres = var->xres_virtual; | |
1029 | ||
1030 | if (var->xres + var->xoffset > var->xres_virtual) | |
1031 | var->xoffset = var->xres_virtual - var->xres; | |
1032 | if (var->yres + var->yoffset > var->yres_virtual) | |
1033 | var->yoffset = var->yres_virtual - var->yres; | |
1034 | ||
404fdfe7 AM |
1035 | var->pixclock = da8xx_fb_round_clk(par, var->pixclock); |
1036 | ||
4ed824d9 SR |
1037 | return err; |
1038 | } | |
1039 | ||
e04e5483 C |
1040 | #ifdef CONFIG_CPU_FREQ |
1041 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
1042 | unsigned long val, void *data) | |
1043 | { | |
1044 | struct da8xx_fb_par *par; | |
e04e5483 C |
1045 | |
1046 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a | 1047 | if (val == CPUFREQ_POSTCHANGE) { |
0715c72d DE |
1048 | if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) { |
1049 | par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); | |
26e71645 | 1050 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
a6a799f8 | 1051 | da8xx_fb_calc_config_clk_divider(par, &par->mode); |
67900814 MP |
1052 | if (par->blank == FB_BLANK_UNBLANK) |
1053 | lcd_enable_raster(); | |
f820917a | 1054 | } |
e04e5483 C |
1055 | } |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
a9cd67c8 | 1060 | static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) |
e04e5483 C |
1061 | { |
1062 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
1063 | ||
1064 | return cpufreq_register_notifier(&par->freq_transition, | |
1065 | CPUFREQ_TRANSITION_NOTIFIER); | |
1066 | } | |
1067 | ||
a9cd67c8 | 1068 | static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) |
e04e5483 C |
1069 | { |
1070 | cpufreq_unregister_notifier(&par->freq_transition, | |
1071 | CPUFREQ_TRANSITION_NOTIFIER); | |
1072 | } | |
1073 | #endif | |
1074 | ||
48c68c4f | 1075 | static int fb_remove(struct platform_device *dev) |
4ed824d9 SR |
1076 | { |
1077 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
1078 | |
1079 | if (info) { | |
1080 | struct da8xx_fb_par *par = info->par; | |
1081 | ||
e04e5483 C |
1082 | #ifdef CONFIG_CPU_FREQ |
1083 | lcd_da8xx_cpufreq_deregister(par); | |
1084 | #endif | |
36113804 C |
1085 | if (par->panel_power_ctrl) |
1086 | par->panel_power_ctrl(0); | |
1087 | ||
26e71645 | 1088 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
4ed824d9 SR |
1089 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
1090 | ||
1091 | /* disable DMA */ | |
1092 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
1093 | ||
1094 | unregister_framebuffer(info); | |
1095 | fb_dealloc_cmap(&info->cmap); | |
1f9c3e1f MA |
1096 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
1097 | par->p_palette_base); | |
1098 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, | |
1099 | par->vram_phys); | |
9dd44d5d MP |
1100 | pm_runtime_put_sync(&dev->dev); |
1101 | pm_runtime_disable(&dev->dev); | |
4ed824d9 | 1102 | framebuffer_release(info); |
4ed824d9 SR |
1103 | |
1104 | } | |
2f93e8f4 | 1105 | return 0; |
4ed824d9 SR |
1106 | } |
1107 | ||
1f9c3e1f MA |
1108 | /* |
1109 | * Function to wait for vertical sync which for this LCD peripheral | |
1110 | * translates into waiting for the current raster frame to complete. | |
1111 | */ | |
1112 | static int fb_wait_for_vsync(struct fb_info *info) | |
1113 | { | |
1114 | struct da8xx_fb_par *par = info->par; | |
1115 | int ret; | |
1116 | ||
1117 | /* | |
1118 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 1119 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
1120 | * just after this set. But since we are just coarsely waiting for |
1121 | * a frame to complete then that's OK. i.e. if the frame completed | |
1122 | * just before this code executed then we have to wait another full | |
1123 | * frame time but there is no way to avoid such a situation. On the | |
1124 | * other hand if the frame completed just after then we don't need | |
1125 | * to wait long at all. Either way we are guaranteed to return to the | |
1126 | * user immediately after a frame completion which is all that is | |
1127 | * required. | |
1128 | */ | |
1129 | par->vsync_flag = 0; | |
1130 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
1131 | par->vsync_flag != 0, | |
1132 | par->vsync_timeout); | |
1133 | if (ret < 0) | |
1134 | return ret; | |
1135 | if (ret == 0) | |
1136 | return -ETIMEDOUT; | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
4ed824d9 SR |
1141 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
1142 | unsigned long arg) | |
1143 | { | |
1144 | struct lcd_sync_arg sync_arg; | |
1145 | ||
1146 | switch (cmd) { | |
1147 | case FBIOGET_CONTRAST: | |
1148 | case FBIOPUT_CONTRAST: | |
1149 | case FBIGET_BRIGHTNESS: | |
1150 | case FBIPUT_BRIGHTNESS: | |
1151 | case FBIGET_COLOR: | |
1152 | case FBIPUT_COLOR: | |
2f93e8f4 | 1153 | return -ENOTTY; |
4ed824d9 SR |
1154 | case FBIPUT_HSYNC: |
1155 | if (copy_from_user(&sync_arg, (char *)arg, | |
1156 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1157 | return -EFAULT; |
4ed824d9 SR |
1158 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
1159 | sync_arg.pulse_width, | |
1160 | sync_arg.front_porch); | |
1161 | break; | |
1162 | case FBIPUT_VSYNC: | |
1163 | if (copy_from_user(&sync_arg, (char *)arg, | |
1164 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1165 | return -EFAULT; |
4ed824d9 SR |
1166 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1167 | sync_arg.pulse_width, | |
1168 | sync_arg.front_porch); | |
1169 | break; | |
1f9c3e1f MA |
1170 | case FBIO_WAITFORVSYNC: |
1171 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1172 | default: |
1173 | return -EINVAL; | |
1174 | } | |
1175 | return 0; | |
1176 | } | |
1177 | ||
312d9715 C |
1178 | static int cfb_blank(int blank, struct fb_info *info) |
1179 | { | |
1180 | struct da8xx_fb_par *par = info->par; | |
1181 | int ret = 0; | |
1182 | ||
1183 | if (par->blank == blank) | |
1184 | return 0; | |
1185 | ||
1186 | par->blank = blank; | |
1187 | switch (blank) { | |
1188 | case FB_BLANK_UNBLANK: | |
f7c848b6 MP |
1189 | lcd_enable_raster(); |
1190 | ||
312d9715 C |
1191 | if (par->panel_power_ctrl) |
1192 | par->panel_power_ctrl(1); | |
312d9715 | 1193 | break; |
99a647d1 YY |
1194 | case FB_BLANK_NORMAL: |
1195 | case FB_BLANK_VSYNC_SUSPEND: | |
1196 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1197 | case FB_BLANK_POWERDOWN: |
1198 | if (par->panel_power_ctrl) | |
1199 | par->panel_power_ctrl(0); | |
1200 | ||
26e71645 | 1201 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
312d9715 C |
1202 | break; |
1203 | default: | |
1204 | ret = -EINVAL; | |
1205 | } | |
1206 | ||
1207 | return ret; | |
1208 | } | |
1209 | ||
1f9c3e1f MA |
1210 | /* |
1211 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1212 | * to the new mode. | |
1213 | */ | |
1214 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1215 | struct fb_info *fbi) | |
1216 | { | |
1217 | int ret = 0; | |
1218 | struct fb_var_screeninfo new_var; | |
1219 | struct da8xx_fb_par *par = fbi->par; | |
1220 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1221 | unsigned int end; | |
1222 | unsigned int start; | |
deb95c6c | 1223 | unsigned long irq_flags; |
1f9c3e1f MA |
1224 | |
1225 | if (var->xoffset != fbi->var.xoffset || | |
1226 | var->yoffset != fbi->var.yoffset) { | |
1227 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1228 | new_var.xoffset = var->xoffset; | |
1229 | new_var.yoffset = var->yoffset; | |
1230 | if (fb_check_var(&new_var, fbi)) | |
1231 | ret = -EINVAL; | |
1232 | else { | |
1233 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1234 | ||
1235 | start = fix->smem_start + | |
1236 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1237 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1238 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1239 | par->dma_start = start; |
1240 | par->dma_end = end; | |
deb95c6c MP |
1241 | spin_lock_irqsave(&par->lock_for_chan_update, |
1242 | irq_flags); | |
1243 | if (par->which_dma_channel_done == 0) { | |
1244 | lcdc_write(par->dma_start, | |
1245 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1246 | lcdc_write(par->dma_end, | |
1247 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1248 | } else if (par->which_dma_channel_done == 1) { | |
1249 | lcdc_write(par->dma_start, | |
1250 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1251 | lcdc_write(par->dma_end, | |
1252 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1253 | } | |
1254 | spin_unlock_irqrestore(&par->lock_for_chan_update, | |
1255 | irq_flags); | |
1f9c3e1f MA |
1256 | } |
1257 | } | |
1258 | ||
1259 | return ret; | |
1260 | } | |
1261 | ||
fe8c98f0 DE |
1262 | static int da8xxfb_set_par(struct fb_info *info) |
1263 | { | |
1264 | struct da8xx_fb_par *par = info->par; | |
1265 | int ret; | |
1266 | bool raster = da8xx_fb_is_raster_enabled(); | |
1267 | ||
1268 | if (raster) | |
26e71645 | 1269 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
fe8c98f0 DE |
1270 | |
1271 | fb_var_to_videomode(&par->mode, &info->var); | |
1272 | ||
1273 | par->cfg.bpp = info->var.bits_per_pixel; | |
1274 | ||
1275 | info->fix.visual = (par->cfg.bpp <= 8) ? | |
1276 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
1277 | info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8; | |
1278 | ||
1279 | ret = lcd_init(par, &par->cfg, &par->mode); | |
1280 | if (ret < 0) { | |
1281 | dev_err(par->dev, "lcd init failed\n"); | |
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | par->dma_start = info->fix.smem_start + | |
1286 | info->var.yoffset * info->fix.line_length + | |
1287 | info->var.xoffset * info->var.bits_per_pixel / 8; | |
1288 | par->dma_end = par->dma_start + | |
1289 | info->var.yres * info->fix.line_length - 1; | |
1290 | ||
1291 | lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1292 | lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1293 | lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1294 | lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1295 | ||
1296 | if (raster) | |
1297 | lcd_enable_raster(); | |
1298 | ||
1299 | return 0; | |
1300 | } | |
1301 | ||
4ed824d9 SR |
1302 | static struct fb_ops da8xx_fb_ops = { |
1303 | .owner = THIS_MODULE, | |
1304 | .fb_check_var = fb_check_var, | |
fe8c98f0 | 1305 | .fb_set_par = da8xxfb_set_par, |
4ed824d9 | 1306 | .fb_setcolreg = fb_setcolreg, |
1f9c3e1f | 1307 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1308 | .fb_ioctl = fb_ioctl, |
1309 | .fb_fillrect = cfb_fillrect, | |
1310 | .fb_copyarea = cfb_copyarea, | |
1311 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1312 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1313 | }; |
1314 | ||
2bdff068 AM |
1315 | static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev) |
1316 | { | |
1317 | struct da8xx_lcdc_platform_data *fb_pdata = dev->dev.platform_data; | |
1318 | struct fb_videomode *lcdc_info; | |
1319 | int i; | |
1320 | ||
1321 | for (i = 0, lcdc_info = known_lcd_panels; | |
1322 | i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) { | |
1323 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1324 | break; | |
1325 | } | |
1326 | ||
1327 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1328 | dev_err(&dev->dev, "no panel found\n"); | |
1329 | return NULL; | |
1330 | } | |
1331 | dev_info(&dev->dev, "found %s panel\n", lcdc_info->name); | |
1332 | ||
1333 | return lcdc_info; | |
1334 | } | |
1335 | ||
48c68c4f | 1336 | static int fb_probe(struct platform_device *device) |
4ed824d9 SR |
1337 | { |
1338 | struct da8xx_lcdc_platform_data *fb_pdata = | |
1339 | device->dev.platform_data; | |
c45757f0 | 1340 | static struct resource *lcdc_regs; |
4ed824d9 | 1341 | struct lcd_ctrl_config *lcd_cfg; |
f772fabd | 1342 | struct fb_videomode *lcdc_info; |
4ed824d9 | 1343 | struct fb_info *da8xx_fb_info; |
4ed824d9 | 1344 | struct da8xx_fb_par *par; |
0715c72d | 1345 | struct clk *tmp_lcdc_clk; |
2bdff068 | 1346 | int ret; |
3b9cc4ea | 1347 | unsigned long ulcm; |
4ed824d9 SR |
1348 | |
1349 | if (fb_pdata == NULL) { | |
1350 | dev_err(&device->dev, "Can not get platform data\n"); | |
1351 | return -ENOENT; | |
1352 | } | |
1353 | ||
2bdff068 AM |
1354 | lcdc_info = da8xx_fb_get_videomode(device); |
1355 | if (lcdc_info == NULL) | |
1356 | return -ENODEV; | |
1357 | ||
4ed824d9 | 1358 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); |
c45757f0 DE |
1359 | da8xx_fb_reg_base = devm_ioremap_resource(&device->dev, lcdc_regs); |
1360 | if (IS_ERR(da8xx_fb_reg_base)) | |
1361 | return PTR_ERR(da8xx_fb_reg_base); | |
4ed824d9 | 1362 | |
0715c72d DE |
1363 | tmp_lcdc_clk = devm_clk_get(&device->dev, "fck"); |
1364 | if (IS_ERR(tmp_lcdc_clk)) { | |
4ed824d9 | 1365 | dev_err(&device->dev, "Can not get device clock\n"); |
0715c72d | 1366 | return PTR_ERR(tmp_lcdc_clk); |
4ed824d9 | 1367 | } |
9dd44d5d MP |
1368 | |
1369 | pm_runtime_enable(&device->dev); | |
1370 | pm_runtime_get_sync(&device->dev); | |
4ed824d9 | 1371 | |
c6daf05b MP |
1372 | /* Determine LCD IP Version */ |
1373 | switch (lcdc_read(LCD_PID_REG)) { | |
1374 | case 0x4C100102: | |
1375 | lcd_revision = LCD_VERSION_1; | |
1376 | break; | |
1377 | case 0x4F200800: | |
8f22e8ea | 1378 | case 0x4F201000: |
c6daf05b MP |
1379 | lcd_revision = LCD_VERSION_2; |
1380 | break; | |
1381 | default: | |
1382 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1383 | "defaulting to LCD revision 1\n", | |
1384 | lcdc_read(LCD_PID_REG)); | |
1385 | lcd_revision = LCD_VERSION_1; | |
1386 | break; | |
1387 | } | |
1388 | ||
4ed824d9 SR |
1389 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; |
1390 | ||
3a58101d AM |
1391 | if (!lcd_cfg) { |
1392 | ret = -EINVAL; | |
1393 | goto err_pm_runtime_disable; | |
1394 | } | |
1395 | ||
4ed824d9 SR |
1396 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), |
1397 | &device->dev); | |
1398 | if (!da8xx_fb_info) { | |
1399 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); | |
1400 | ret = -ENOMEM; | |
9dd44d5d | 1401 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1402 | } |
1403 | ||
1404 | par = da8xx_fb_info->par; | |
dbe8e48a | 1405 | par->dev = &device->dev; |
0715c72d DE |
1406 | par->lcdc_clk = tmp_lcdc_clk; |
1407 | par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk); | |
36113804 C |
1408 | if (fb_pdata->panel_power_ctrl) { |
1409 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1410 | par->panel_power_ctrl(1); | |
1411 | } | |
4ed824d9 | 1412 | |
b866458b | 1413 | fb_videomode_to_var(&da8xx_fb_var, lcdc_info); |
b6dbe8e4 | 1414 | par->cfg = *lcd_cfg; |
b866458b | 1415 | |
fe8c98f0 | 1416 | da8xx_fb_lcd_reset(); |
4ed824d9 SR |
1417 | |
1418 | /* allocate frame buffer */ | |
f772fabd MP |
1419 | par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; |
1420 | ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); | |
3b9cc4ea | 1421 | par->vram_size = roundup(par->vram_size/8, ulcm); |
1f9c3e1f MA |
1422 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1423 | ||
1424 | par->vram_virt = dma_alloc_coherent(NULL, | |
1425 | par->vram_size, | |
1426 | (resource_size_t *) &par->vram_phys, | |
1427 | GFP_KERNEL | GFP_DMA); | |
1428 | if (!par->vram_virt) { | |
4ed824d9 SR |
1429 | dev_err(&device->dev, |
1430 | "GLCD: kmalloc for frame buffer failed\n"); | |
1431 | ret = -EINVAL; | |
1432 | goto err_release_fb; | |
1433 | } | |
1434 | ||
1f9c3e1f MA |
1435 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1436 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1437 | da8xx_fb_fix.smem_len = par->vram_size; | |
f772fabd | 1438 | da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; |
1f9c3e1f MA |
1439 | |
1440 | par->dma_start = par->vram_phys; | |
f772fabd | 1441 | par->dma_end = par->dma_start + lcdc_info->yres * |
1f9c3e1f MA |
1442 | da8xx_fb_fix.line_length - 1; |
1443 | ||
1444 | /* allocate palette buffer */ | |
1445 | par->v_palette_base = dma_alloc_coherent(NULL, | |
1446 | PALETTE_SIZE, | |
1447 | (resource_size_t *) | |
1448 | &par->p_palette_base, | |
1449 | GFP_KERNEL | GFP_DMA); | |
1450 | if (!par->v_palette_base) { | |
1451 | dev_err(&device->dev, | |
1452 | "GLCD: kmalloc for palette buffer failed\n"); | |
1453 | ret = -EINVAL; | |
1454 | goto err_release_fb_mem; | |
1455 | } | |
1456 | memset(par->v_palette_base, 0, PALETTE_SIZE); | |
4ed824d9 | 1457 | |
4ed824d9 SR |
1458 | par->irq = platform_get_irq(device, 0); |
1459 | if (par->irq < 0) { | |
1460 | ret = -ENOENT; | |
1f9c3e1f | 1461 | goto err_release_pl_mem; |
4ed824d9 SR |
1462 | } |
1463 | ||
4ed824d9 | 1464 | da8xx_fb_var.grayscale = |
3b43ad20 | 1465 | lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; |
4ed824d9 | 1466 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; |
4ed824d9 SR |
1467 | |
1468 | /* Initialize fbinfo */ | |
1469 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1470 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1471 | da8xx_fb_info->var = da8xx_fb_var; | |
1472 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1473 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1474 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1475 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1476 | |
1477 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1478 | if (ret) | |
93c176f3 | 1479 | goto err_release_pl_mem; |
4ed824d9 SR |
1480 | da8xx_fb_info->cmap.len = par->palette_sz; |
1481 | ||
4ed824d9 SR |
1482 | /* initialize var_screeninfo */ |
1483 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1484 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1485 | ||
1486 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1487 | |
1488 | /* initialize the vsync wait queue */ | |
1489 | init_waitqueue_head(&par->vsync_wait); | |
1490 | par->vsync_timeout = HZ / 5; | |
deb95c6c MP |
1491 | par->which_dma_channel_done = -1; |
1492 | spin_lock_init(&par->lock_for_chan_update); | |
1f9c3e1f | 1493 | |
4ed824d9 SR |
1494 | /* Register the Frame Buffer */ |
1495 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1496 | dev_err(&device->dev, | |
1497 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1498 | ret = -EINVAL; | |
1499 | goto err_dealloc_cmap; | |
1500 | } | |
1501 | ||
e04e5483 C |
1502 | #ifdef CONFIG_CPU_FREQ |
1503 | ret = lcd_da8xx_cpufreq_register(par); | |
1504 | if (ret) { | |
1505 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1506 | goto err_cpu_freq; | |
1507 | } | |
1508 | #endif | |
93c176f3 | 1509 | |
c6daf05b MP |
1510 | if (lcd_revision == LCD_VERSION_1) |
1511 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
a481b37a MP |
1512 | else { |
1513 | init_waitqueue_head(&frame_done_wq); | |
c6daf05b | 1514 | lcdc_irq_handler = lcdc_irq_handler_rev02; |
a481b37a | 1515 | } |
c6daf05b | 1516 | |
c45757f0 DE |
1517 | ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0, |
1518 | DRIVER_NAME, par); | |
93c176f3 CA |
1519 | if (ret) |
1520 | goto irq_freq; | |
4ed824d9 SR |
1521 | return 0; |
1522 | ||
93c176f3 | 1523 | irq_freq: |
e04e5483 | 1524 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1525 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1526 | err_cpu_freq: |
3a84409c | 1527 | #endif |
e04e5483 | 1528 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1529 | |
4ed824d9 SR |
1530 | err_dealloc_cmap: |
1531 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1532 | ||
1f9c3e1f MA |
1533 | err_release_pl_mem: |
1534 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, | |
1535 | par->p_palette_base); | |
1536 | ||
4ed824d9 | 1537 | err_release_fb_mem: |
1f9c3e1f | 1538 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
4ed824d9 SR |
1539 | |
1540 | err_release_fb: | |
1541 | framebuffer_release(da8xx_fb_info); | |
1542 | ||
9dd44d5d MP |
1543 | err_pm_runtime_disable: |
1544 | pm_runtime_put_sync(&device->dev); | |
1545 | pm_runtime_disable(&device->dev); | |
4ed824d9 | 1546 | |
4ed824d9 SR |
1547 | return ret; |
1548 | } | |
1549 | ||
1550 | #ifdef CONFIG_PM | |
7a93cbbb MP |
1551 | struct lcdc_context { |
1552 | u32 clk_enable; | |
1553 | u32 ctrl; | |
1554 | u32 dma_ctrl; | |
1555 | u32 raster_timing_0; | |
1556 | u32 raster_timing_1; | |
1557 | u32 raster_timing_2; | |
1558 | u32 int_enable_set; | |
1559 | u32 dma_frm_buf_base_addr_0; | |
1560 | u32 dma_frm_buf_ceiling_addr_0; | |
1561 | u32 dma_frm_buf_base_addr_1; | |
1562 | u32 dma_frm_buf_ceiling_addr_1; | |
1563 | u32 raster_ctrl; | |
1564 | } reg_context; | |
1565 | ||
1566 | static void lcd_context_save(void) | |
1567 | { | |
1568 | if (lcd_revision == LCD_VERSION_2) { | |
1569 | reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG); | |
1570 | reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG); | |
1571 | } | |
1572 | ||
1573 | reg_context.ctrl = lcdc_read(LCD_CTRL_REG); | |
1574 | reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG); | |
1575 | reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG); | |
1576 | reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG); | |
1577 | reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
1578 | reg_context.dma_frm_buf_base_addr_0 = | |
1579 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1580 | reg_context.dma_frm_buf_ceiling_addr_0 = | |
1581 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1582 | reg_context.dma_frm_buf_base_addr_1 = | |
1583 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1584 | reg_context.dma_frm_buf_ceiling_addr_1 = | |
1585 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1586 | reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG); | |
1587 | return; | |
1588 | } | |
1589 | ||
1590 | static void lcd_context_restore(void) | |
1591 | { | |
1592 | if (lcd_revision == LCD_VERSION_2) { | |
1593 | lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG); | |
1594 | lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG); | |
1595 | } | |
1596 | ||
1597 | lcdc_write(reg_context.ctrl, LCD_CTRL_REG); | |
1598 | lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG); | |
1599 | lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG); | |
1600 | lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG); | |
1601 | lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG); | |
1602 | lcdc_write(reg_context.dma_frm_buf_base_addr_0, | |
1603 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1604 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0, | |
1605 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1606 | lcdc_write(reg_context.dma_frm_buf_base_addr_1, | |
1607 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1608 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1, | |
1609 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1610 | lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG); | |
1611 | return; | |
1612 | } | |
1613 | ||
4ed824d9 SR |
1614 | static int fb_suspend(struct platform_device *dev, pm_message_t state) |
1615 | { | |
1d3c6c7b C |
1616 | struct fb_info *info = platform_get_drvdata(dev); |
1617 | struct da8xx_fb_par *par = info->par; | |
1618 | ||
ac751efa | 1619 | console_lock(); |
1d3c6c7b C |
1620 | if (par->panel_power_ctrl) |
1621 | par->panel_power_ctrl(0); | |
1622 | ||
1623 | fb_set_suspend(info, 1); | |
26e71645 | 1624 | lcd_disable_raster(DA8XX_FRAME_WAIT); |
7a93cbbb | 1625 | lcd_context_save(); |
9dd44d5d | 1626 | pm_runtime_put_sync(&dev->dev); |
ac751efa | 1627 | console_unlock(); |
1d3c6c7b C |
1628 | |
1629 | return 0; | |
4ed824d9 SR |
1630 | } |
1631 | static int fb_resume(struct platform_device *dev) | |
1632 | { | |
1d3c6c7b C |
1633 | struct fb_info *info = platform_get_drvdata(dev); |
1634 | struct da8xx_fb_par *par = info->par; | |
1635 | ||
ac751efa | 1636 | console_lock(); |
9dd44d5d | 1637 | pm_runtime_get_sync(&dev->dev); |
7a93cbbb | 1638 | lcd_context_restore(); |
67900814 MP |
1639 | if (par->blank == FB_BLANK_UNBLANK) { |
1640 | lcd_enable_raster(); | |
f7c848b6 | 1641 | |
67900814 MP |
1642 | if (par->panel_power_ctrl) |
1643 | par->panel_power_ctrl(1); | |
1644 | } | |
1d3c6c7b | 1645 | |
1d3c6c7b | 1646 | fb_set_suspend(info, 0); |
ac751efa | 1647 | console_unlock(); |
1d3c6c7b C |
1648 | |
1649 | return 0; | |
4ed824d9 SR |
1650 | } |
1651 | #else | |
1652 | #define fb_suspend NULL | |
1653 | #define fb_resume NULL | |
1654 | #endif | |
1655 | ||
1656 | static struct platform_driver da8xx_fb_driver = { | |
1657 | .probe = fb_probe, | |
48c68c4f | 1658 | .remove = fb_remove, |
4ed824d9 SR |
1659 | .suspend = fb_suspend, |
1660 | .resume = fb_resume, | |
1661 | .driver = { | |
1662 | .name = DRIVER_NAME, | |
1663 | .owner = THIS_MODULE, | |
1664 | }, | |
1665 | }; | |
1666 | ||
1667 | static int __init da8xx_fb_init(void) | |
1668 | { | |
1669 | return platform_driver_register(&da8xx_fb_driver); | |
1670 | } | |
1671 | ||
1672 | static void __exit da8xx_fb_cleanup(void) | |
1673 | { | |
1674 | platform_driver_unregister(&da8xx_fb_driver); | |
1675 | } | |
1676 | ||
1677 | module_init(da8xx_fb_init); | |
1678 | module_exit(da8xx_fb_cleanup); | |
1679 | ||
1680 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1681 | MODULE_AUTHOR("Texas Instruments"); | |
1682 | MODULE_LICENSE("GPL"); |