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video: exynos_dp: Move hotplug into a workqueue
[deliverable/linux.git] / drivers / video / exynos / exynos_dp_core.h
CommitLineData
e9474be4
JH		 1/*
2 * Header file for Samsung DP (Display Port) interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef _EXYNOS_DP_CORE_H
14#define _EXYNOS_DP_CORE_H
15
16struct link_train {
17 int eq_loop;
18 int cr_loop[4];
19
20 u8 link_rate;
21 u8 lane_count;
22 u8 training_lane[4];
23
24 enum link_training_state lt_state;
25};
26
27struct exynos_dp_device {
28 struct device *dev;
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JH		 29 struct clk *clock;
30 unsigned int irq;
31 void __iomem *reg_base;
c4e235c2
AK		 32 void __iomem *phy_addr;
33 unsigned int enable_mask;
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JH		 34
35 struct video_info *video_info;
36 struct link_train link_train;
784fa9a1 37 struct work_struct hotplug_work;
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JH		 38};
39
40/* exynos_dp_reg.c */
41void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
42void exynos_dp_stop_video(struct exynos_dp_device *dp);
43void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
8affaf5c 44void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
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JH		 45void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
46void exynos_dp_reset(struct exynos_dp_device *dp);
24db03a8 47void exynos_dp_swreset(struct exynos_dp_device *dp);
e9474be4 48void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
09d00d17 49enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
e9474be4
JH		 50void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
51void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
52 enum analog_power_block block,
53 bool enable);
54void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
55void exynos_dp_init_hpd(struct exynos_dp_device *dp);
56void exynos_dp_reset_aux(struct exynos_dp_device *dp);
57void exynos_dp_init_aux(struct exynos_dp_device *dp);
58int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
59void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
60int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
61int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
62 unsigned int reg_addr,
63 unsigned char data);
64int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
65 unsigned int reg_addr,
66 unsigned char *data);
67int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
68 unsigned int reg_addr,
69 unsigned int count,
70 unsigned char data[]);
71int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
72 unsigned int reg_addr,
73 unsigned int count,
74 unsigned char data[]);
75int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
76 unsigned int device_addr,
77 unsigned int reg_addr);
78int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
79 unsigned int device_addr,
80 unsigned int reg_addr,
81 unsigned int *data);
82int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
83 unsigned int device_addr,
84 unsigned int reg_addr,
85 unsigned int count,
86 unsigned char edid[]);
87void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
88void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
89void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
90void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
e9474be4
JH		 91void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
92void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
93 enum pattern_set pattern);
94void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
95void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
96void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
97void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
98void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
99 u32 training_lane);
100void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
101 u32 training_lane);
102void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
103 u32 training_lane);
104void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
105 u32 training_lane);
106u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
107u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
108u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
109u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
110void exynos_dp_reset_macro(struct exynos_dp_device *dp);
1ec7be9c 111void exynos_dp_init_video(struct exynos_dp_device *dp);
e9474be4
JH		 112
113void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
114 u32 color_depth,
115 u32 color_space,
116 u32 dynamic_range,
117 u32 ycbcr_coeff);
118int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
119void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
120 enum clock_recovery_m_value_type type,
121 u32 m_value,
122 u32 n_value);
123void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
124void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
125void exynos_dp_start_video(struct exynos_dp_device *dp);
126int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
127void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
128 struct video_info *video_info);
129void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
130void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
131
132/* I2C EDID Chip ID, Slave Address */
133#define I2C_EDID_DEVICE_ADDR 0x50
134#define I2C_E_EDID_DEVICE_ADDR 0x30
135
136#define EDID_BLOCK_LENGTH 0x80
137#define EDID_HEADER_PATTERN 0x00
138#define EDID_EXTENSION_FLAG 0x7e
139#define EDID_CHECKSUM 0x7f
140
141/* Definition for DPCD Register */
142#define DPCD_ADDR_DPCD_REV 0x0000
143#define DPCD_ADDR_MAX_LINK_RATE 0x0001
144#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
145#define DPCD_ADDR_LINK_BW_SET 0x0100
146#define DPCD_ADDR_LANE_COUNT_SET 0x0101
147#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
148#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
149#define DPCD_ADDR_LANE0_1_STATUS 0x0202
d5c0eed0 150#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
e9474be4
JH		 151#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
152#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
153#define DPCD_ADDR_TEST_REQUEST 0x0218
154#define DPCD_ADDR_TEST_RESPONSE 0x0260
155#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
156#define DPCD_ADDR_SINK_POWER_STATE 0x0600
157
158/* DPCD_ADDR_MAX_LANE_COUNT */
159#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
160#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
161
162/* DPCD_ADDR_LANE_COUNT_SET */
163#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
164#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
165
166/* DPCD_ADDR_TRAINING_PATTERN_SET */
167#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
168#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
169#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
170#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
171#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
172
173/* DPCD_ADDR_TRAINING_LANE0_SET */
174#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
175#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
176#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
177#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
178#define DPCD_MAX_SWING_REACHED (0x1 << 2)
179#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
180#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
181#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
182
183/* DPCD_ADDR_LANE0_1_STATUS */
184#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
185#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
186#define DPCD_LANE_CR_DONE (0x1 << 0)
187#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
188 DPCD_LANE_CHANNEL_EQ_DONE|\
189 DPCD_LANE_SYMBOL_LOCKED)
190
191/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
192#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
193#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
194#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
195
196/* DPCD_ADDR_TEST_REQUEST */
197#define DPCD_TEST_EDID_READ (0x1 << 2)
198
199/* DPCD_ADDR_TEST_RESPONSE */
200#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
201
202/* DPCD_ADDR_SINK_POWER_STATE */
203#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
204#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
205
206#endif /* _EXYNOS_DP_CORE_H */
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