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OMAPDSS: DISPC: work-around for errata i631
[deliverable/linux.git] / drivers / video / fbdev / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
80c39712 42
a0b38cc4 43#include <video/omapdss.h>
80c39712
TV		 44
45#include "dss.h"
a0acb557 46#include "dss_features.h"
9b372c2d 47#include "dispc.h"
80c39712
TV		 48
49/* DISPC */
8613b000 50#define DISPC_SZ_REGS SZ_4K
80c39712 51
5ed8cf5b
TV		 52enum omap_burst_size {
53 BURST_SIZE_X2 = 0,
54 BURST_SIZE_X4 = 1,
55 BURST_SIZE_X8 = 2,
56};
57
80c39712
TV		 58#define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
60
61#define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
63
dcbe765b
CM		 64struct dispc_features {
65 u8 sw_start;
66 u8 fp_start;
67 u8 bp_start;
68 u16 sw_max;
69 u16 vp_max;
70 u16 hp_max;
33b89928
AT		 71 u8 mgr_width_start;
72 u8 mgr_height_start;
73 u16 mgr_width_max;
74 u16 mgr_height_max;
ca5ca69c
AT		 75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk;
0c6921de 77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 78 const struct omap_video_timings *mgr_timings,
79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 82 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 83 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 84 u16 width, u16 height, u16 out_width, u16 out_height,
85 bool mem_to_mem);
42a6961c 86 u8 num_fifos;
66a0f9e4
TV		 87
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround:1;
cffa947d
TV		 90
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv:1;
d0df9a2c
AT		 93
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround:1;
8bc65552
AT		 96
97 bool set_max_preload:1;
dcbe765b
CM		 98};
99
42a6961c
TV		 100#define DISPC_MAX_NR_FIFOS 5
101
80c39712 102static struct {
060b6d9c 103 struct platform_device *pdev;
80c39712 104 void __iomem *base;
4fbafaf3 105
affe360d 106 int irq;
0925afc9
TV		 107 irq_handler_t user_handler;
108 void *user_data;
80c39712 109
7b3926b3 110 unsigned long core_clk_rate;
5391e87d 111 unsigned long tv_pclk_rate;
7b3926b3 112
42a6961c
TV		 113 u32 fifo_size[DISPC_MAX_NR_FIFOS];
114 /* maps which plane is using a fifo. fifo-id -> plane-id */
115 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 116
49ea86f3 117 bool ctx_valid;
80c39712 118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 119
dcbe765b 120 const struct dispc_features *feat;
0925afc9
TV		 121
122 bool is_enabled;
0006fd63
TV		 123
124 struct regmap *syscon_pol;
125 u32 syscon_pol_offset;
d49cd155
TV		 126
127 /* DISPC_CONTROL & DISPC_CONFIG lock*/
128 spinlock_t control_lock;
80c39712
TV		 129} dispc;
130
0d66cbb5
AJ		 131enum omap_color_component {
132 /* used for all color formats for OMAP3 and earlier
133 * and for RGB and Y color component on OMAP4
134 */
135 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
136 /* used for UV component for
137 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
138 * color formats on OMAP4
139 */
140 DISPC_COLOR_COMPONENT_UV = 1 << 1,
141};
142
efa70b3b
CM		 143enum mgr_reg_fields {
144 DISPC_MGR_FLD_ENABLE,
145 DISPC_MGR_FLD_STNTFT,
146 DISPC_MGR_FLD_GO,
147 DISPC_MGR_FLD_TFTDATALINES,
148 DISPC_MGR_FLD_STALLMODE,
149 DISPC_MGR_FLD_TCKENABLE,
150 DISPC_MGR_FLD_TCKSELECTION,
151 DISPC_MGR_FLD_CPR,
152 DISPC_MGR_FLD_FIFOHANDCHECK,
153 /* used to maintain a count of the above fields */
154 DISPC_MGR_FLD_NUM,
155};
156
5c348ba9
JS		 157struct dispc_reg_field {
158 u16 reg;
159 u8 high;
160 u8 low;
161};
162
efa70b3b
CM		 163static const struct {
164 const char *name;
165 u32 vsync_irq;
166 u32 framedone_irq;
167 u32 sync_lost_irq;
5c348ba9 168 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 169} mgr_desc[] = {
170 [OMAP_DSS_CHANNEL_LCD] = {
171 .name = "LCD",
172 .vsync_irq = DISPC_IRQ_VSYNC,
173 .framedone_irq = DISPC_IRQ_FRAMEDONE,
174 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
175 .reg_desc = {
176 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
177 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
178 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
179 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
180 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
181 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
182 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
183 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
184 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
185 },
186 },
187 [OMAP_DSS_CHANNEL_DIGIT] = {
188 .name = "DIGIT",
189 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 190 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 191 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
192 .reg_desc = {
193 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
194 [DISPC_MGR_FLD_STNTFT] = { },
195 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
196 [DISPC_MGR_FLD_TFTDATALINES] = { },
197 [DISPC_MGR_FLD_STALLMODE] = { },
198 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
199 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
200 [DISPC_MGR_FLD_CPR] = { },
201 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
202 },
203 },
204 [OMAP_DSS_CHANNEL_LCD2] = {
205 .name = "LCD2",
206 .vsync_irq = DISPC_IRQ_VSYNC2,
207 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
208 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
209 .reg_desc = {
210 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
211 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
212 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
213 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
214 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
215 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
216 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
217 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
218 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
219 },
220 },
e86d456a
CM		 221 [OMAP_DSS_CHANNEL_LCD3] = {
222 .name = "LCD3",
223 .vsync_irq = DISPC_IRQ_VSYNC3,
224 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
225 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
226 .reg_desc = {
227 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
228 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
229 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
230 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
231 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
232 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
233 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
234 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
235 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
236 },
237 },
efa70b3b
CM		 238};
239
6e5264b0
AT		 240struct color_conv_coef {
241 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
242 int full_range;
243};
244
3e8a6ff2
AT		 245static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
246static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 247
55978cc2 248static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 249{
55978cc2 250 __raw_writel(val, dispc.base + idx);
80c39712
TV		 251}
252
55978cc2 253static inline u32 dispc_read_reg(const u16 idx)
80c39712 254{
55978cc2 255 return __raw_readl(dispc.base + idx);
80c39712
TV		 256}
257
efa70b3b
CM		 258static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
259{
5c348ba9 260 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 261 return REG_GET(rfld.reg, rfld.high, rfld.low);
262}
263
264static void mgr_fld_write(enum omap_channel channel,
265 enum mgr_reg_fields regfld, int val) {
5c348ba9 266 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
d49cd155
TV		 267 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
268 unsigned long flags;
269
270 if (need_lock)
271 spin_lock_irqsave(&dispc.control_lock, flags);
272
efa70b3b 273 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
d49cd155
TV		 274
275 if (need_lock)
276 spin_unlock_irqrestore(&dispc.control_lock, flags);
efa70b3b
CM		 277}
278
80c39712 279#define SR(reg) \
55978cc2 280 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 281#define RR(reg) \
55978cc2 282 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 283
4fbafaf3 284static void dispc_save_context(void)
80c39712 285{
c6104b8e 286 int i, j;
80c39712 287
4fbafaf3
TV		 288 DSSDBG("dispc_save_context\n");
289
80c39712
TV		 290 SR(IRQENABLE);
291 SR(CONTROL);
292 SR(CONFIG);
80c39712 293 SR(LINE_NUMBER);
11354dd5
AT		 294 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
295 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 296 SR(GLOBAL_ALPHA);
2a205f34
SS		 297 if (dss_has_feature(FEAT_MGR_LCD2)) {
298 SR(CONTROL2);
2a205f34
SS		 299 SR(CONFIG2);
300 }
e86d456a
CM		 301 if (dss_has_feature(FEAT_MGR_LCD3)) {
302 SR(CONTROL3);
303 SR(CONFIG3);
304 }
80c39712 305
c6104b8e
AT		 306 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
307 SR(DEFAULT_COLOR(i));
308 SR(TRANS_COLOR(i));
309 SR(SIZE_MGR(i));
310 if (i == OMAP_DSS_CHANNEL_DIGIT)
311 continue;
312 SR(TIMING_H(i));
313 SR(TIMING_V(i));
314 SR(POL_FREQ(i));
315 SR(DIVISORo(i));
316
317 SR(DATA_CYCLE1(i));
318 SR(DATA_CYCLE2(i));
319 SR(DATA_CYCLE3(i));
320
332e9d70 321 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 322 SR(CPR_COEF_R(i));
323 SR(CPR_COEF_G(i));
324 SR(CPR_COEF_B(i));
332e9d70 325 }
2a205f34 326 }
80c39712 327
c6104b8e
AT		 328 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
329 SR(OVL_BA0(i));
330 SR(OVL_BA1(i));
331 SR(OVL_POSITION(i));
332 SR(OVL_SIZE(i));
333 SR(OVL_ATTRIBUTES(i));
334 SR(OVL_FIFO_THRESHOLD(i));
335 SR(OVL_ROW_INC(i));
336 SR(OVL_PIXEL_INC(i));
337 if (dss_has_feature(FEAT_PRELOAD))
338 SR(OVL_PRELOAD(i));
339 if (i == OMAP_DSS_GFX) {
340 SR(OVL_WINDOW_SKIP(i));
341 SR(OVL_TABLE_BA(i));
342 continue;
343 }
344 SR(OVL_FIR(i));
345 SR(OVL_PICTURE_SIZE(i));
346 SR(OVL_ACCU0(i));
347 SR(OVL_ACCU1(i));
9b372c2d 348
c6104b8e
AT		 349 for (j = 0; j < 8; j++)
350 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 351
c6104b8e
AT		 352 for (j = 0; j < 8; j++)
353 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 354
c6104b8e
AT		 355 for (j = 0; j < 5; j++)
356 SR(OVL_CONV_COEF(i, j));
ab5ca071 357
c6104b8e
AT		 358 if (dss_has_feature(FEAT_FIR_COEF_V)) {
359 for (j = 0; j < 8; j++)
360 SR(OVL_FIR_COEF_V(i, j));
361 }
9b372c2d 362
c6104b8e
AT		 363 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
364 SR(OVL_BA0_UV(i));
365 SR(OVL_BA1_UV(i));
366 SR(OVL_FIR2(i));
367 SR(OVL_ACCU2_0(i));
368 SR(OVL_ACCU2_1(i));
ab5ca071 369
c6104b8e
AT		 370 for (j = 0; j < 8; j++)
371 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 372
c6104b8e
AT		 373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 375
c6104b8e
AT		 376 for (j = 0; j < 8; j++)
377 SR(OVL_FIR_COEF_V2(i, j));
378 }
379 if (dss_has_feature(FEAT_ATTR2))
380 SR(OVL_ATTRIBUTES2(i));
ab5ca071 381 }
0cf35df3
MR		 382
383 if (dss_has_feature(FEAT_CORE_CLK_DIV))
384 SR(DIVISOR);
49ea86f3 385
49ea86f3
TV		 386 dispc.ctx_valid = true;
387
9229b516 388 DSSDBG("context saved\n");
80c39712
TV		 389}
390
4fbafaf3 391static void dispc_restore_context(void)
80c39712 392{
9229b516 393 int i, j;
4fbafaf3
TV		 394
395 DSSDBG("dispc_restore_context\n");
396
49ea86f3
TV		 397 if (!dispc.ctx_valid)
398 return;
399
75c7d59d 400 /*RR(IRQENABLE);*/
80c39712
TV		 401 /*RR(CONTROL);*/
402 RR(CONFIG);
80c39712 403 RR(LINE_NUMBER);
11354dd5
AT		 404 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
405 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 406 RR(GLOBAL_ALPHA);
c6104b8e 407 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 408 RR(CONFIG2);
e86d456a
CM		 409 if (dss_has_feature(FEAT_MGR_LCD3))
410 RR(CONFIG3);
80c39712 411
c6104b8e
AT		 412 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
413 RR(DEFAULT_COLOR(i));
414 RR(TRANS_COLOR(i));
415 RR(SIZE_MGR(i));
416 if (i == OMAP_DSS_CHANNEL_DIGIT)
417 continue;
418 RR(TIMING_H(i));
419 RR(TIMING_V(i));
420 RR(POL_FREQ(i));
421 RR(DIVISORo(i));
422
423 RR(DATA_CYCLE1(i));
424 RR(DATA_CYCLE2(i));
425 RR(DATA_CYCLE3(i));
2a205f34 426
332e9d70 427 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 428 RR(CPR_COEF_R(i));
429 RR(CPR_COEF_G(i));
430 RR(CPR_COEF_B(i));
332e9d70 431 }
2a205f34 432 }
80c39712 433
c6104b8e
AT		 434 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
435 RR(OVL_BA0(i));
436 RR(OVL_BA1(i));
437 RR(OVL_POSITION(i));
438 RR(OVL_SIZE(i));
439 RR(OVL_ATTRIBUTES(i));
440 RR(OVL_FIFO_THRESHOLD(i));
441 RR(OVL_ROW_INC(i));
442 RR(OVL_PIXEL_INC(i));
443 if (dss_has_feature(FEAT_PRELOAD))
444 RR(OVL_PRELOAD(i));
445 if (i == OMAP_DSS_GFX) {
446 RR(OVL_WINDOW_SKIP(i));
447 RR(OVL_TABLE_BA(i));
448 continue;
449 }
450 RR(OVL_FIR(i));
451 RR(OVL_PICTURE_SIZE(i));
452 RR(OVL_ACCU0(i));
453 RR(OVL_ACCU1(i));
9b372c2d 454
c6104b8e
AT		 455 for (j = 0; j < 8; j++)
456 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 457
c6104b8e
AT		 458 for (j = 0; j < 8; j++)
459 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 460
c6104b8e
AT		 461 for (j = 0; j < 5; j++)
462 RR(OVL_CONV_COEF(i, j));
ab5ca071 463
c6104b8e
AT		 464 if (dss_has_feature(FEAT_FIR_COEF_V)) {
465 for (j = 0; j < 8; j++)
466 RR(OVL_FIR_COEF_V(i, j));
467 }
9b372c2d 468
c6104b8e
AT		 469 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
470 RR(OVL_BA0_UV(i));
471 RR(OVL_BA1_UV(i));
472 RR(OVL_FIR2(i));
473 RR(OVL_ACCU2_0(i));
474 RR(OVL_ACCU2_1(i));
ab5ca071 475
c6104b8e
AT		 476 for (j = 0; j < 8; j++)
477 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 478
c6104b8e
AT		 479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 481
c6104b8e
AT		 482 for (j = 0; j < 8; j++)
483 RR(OVL_FIR_COEF_V2(i, j));
484 }
485 if (dss_has_feature(FEAT_ATTR2))
486 RR(OVL_ATTRIBUTES2(i));
ab5ca071 487 }
80c39712 488
0cf35df3
MR		 489 if (dss_has_feature(FEAT_CORE_CLK_DIV))
490 RR(DIVISOR);
491
80c39712
TV		 492 /* enable last, because LCD & DIGIT enable are here */
493 RR(CONTROL);
2a205f34
SS		 494 if (dss_has_feature(FEAT_MGR_LCD2))
495 RR(CONTROL2);
e86d456a
CM		 496 if (dss_has_feature(FEAT_MGR_LCD3))
497 RR(CONTROL3);
75c7d59d 498 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 499 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 500
501 /*
502 * enable last so IRQs won't trigger before
503 * the context is fully restored
504 */
505 RR(IRQENABLE);
49ea86f3
TV		 506
507 DSSDBG("context restored\n");
80c39712
TV		 508}
509
510#undef SR
511#undef RR
512
4fbafaf3
TV		 513int dispc_runtime_get(void)
514{
515 int r;
516
517 DSSDBG("dispc_runtime_get\n");
518
519 r = pm_runtime_get_sync(&dispc.pdev->dev);
520 WARN_ON(r < 0);
521 return r < 0 ? r : 0;
522}
348be69d 523EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 524
525void dispc_runtime_put(void)
526{
527 int r;
528
529 DSSDBG("dispc_runtime_put\n");
530
0eaf9f52 531 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 532 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 533}
348be69d 534EXPORT_SYMBOL(dispc_runtime_put);
80c39712 535
3dcec4d6
TV		 536u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
537{
efa70b3b 538 return mgr_desc[channel].vsync_irq;
3dcec4d6 539}
348be69d 540EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 541
7d1365c9
TV		 542u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
543{
cffa947d
TV		 544 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
545 return 0;
546
efa70b3b 547 return mgr_desc[channel].framedone_irq;
7d1365c9 548}
348be69d 549EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 550
cb699200
TV		 551u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
552{
553 return mgr_desc[channel].sync_lost_irq;
554}
348be69d 555EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 556
0b23e5b8
AT		 557u32 dispc_wb_get_framedone_irq(void)
558{
559 return DISPC_IRQ_FRAMEDONEWB;
560}
561
26d9dd0d 562bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 563{
efa70b3b 564 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 565}
348be69d 566EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 567
26d9dd0d 568void dispc_mgr_go(enum omap_channel channel)
80c39712 569{
3c91ee8c
TV		 570 WARN_ON(dispc_mgr_is_enabled(channel) == false);
571 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 572
efa70b3b 573 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 574
efa70b3b 575 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 576}
348be69d 577EXPORT_SYMBOL(dispc_mgr_go);
80c39712 578
0b23e5b8
AT		 579bool dispc_wb_go_busy(void)
580{
581 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
582}
583
584void dispc_wb_go(void)
585{
586 enum omap_plane plane = OMAP_DSS_WB;
587 bool enable, go;
588
589 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
590
591 if (!enable)
592 return;
593
594 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
595 if (go) {
596 DSSERR("GO bit not down for WB\n");
597 return;
598 }
599
600 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
601}
602
f0e5caab 603static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 604{
9b372c2d 605 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 606}
607
f0e5caab 608static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 609{
9b372c2d 610 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 611}
612
f0e5caab 613static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 614{
9b372c2d 615 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 616}
617
f0e5caab 618static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 619{
620 BUG_ON(plane == OMAP_DSS_GFX);
621
622 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
623}
624
f0e5caab
TV		 625static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
626 u32 value)
ab5ca071
AJ		 627{
628 BUG_ON(plane == OMAP_DSS_GFX);
629
630 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
631}
632
f0e5caab 633static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 634{
635 BUG_ON(plane == OMAP_DSS_GFX);
636
637 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
638}
639
debd9074
CM		 640static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
641 int fir_vinc, int five_taps,
642 enum omap_color_component color_comp)
80c39712 643{
debd9074 644 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 645 int i;
646
debd9074
CM		 647 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
648 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 649
650 for (i = 0; i < 8; i++) {
651 u32 h, hv;
652
debd9074
CM		 653 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
654 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
655 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
656 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
657 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
658 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
659 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
660 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 661
0d66cbb5 662 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 663 dispc_ovl_write_firh_reg(plane, i, h);
664 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 665 } else {
f0e5caab
TV		 666 dispc_ovl_write_firh2_reg(plane, i, h);
667 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 668 }
669
80c39712
TV		 670 }
671
66be8f6c
GI		 672 if (five_taps) {
673 for (i = 0; i < 8; i++) {
674 u32 v;
debd9074
CM		 675 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
676 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 677 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 678 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 679 else
f0e5caab 680 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 681 }
80c39712
TV		 682 }
683}
684
80c39712 685
6e5264b0
AT		 686static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
687 const struct color_conv_coef *ct)
688{
80c39712
TV		 689#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
690
6e5264b0
AT		 691 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
692 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
694 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 696
6e5264b0 697 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 698
699#undef CVAL
80c39712
TV		 700}
701
6e5264b0
AT		 702static void dispc_setup_color_conv_coef(void)
703{
704 int i;
705 int num_ovl = dss_feat_get_num_ovls();
706 int num_wb = dss_feat_get_num_wbs();
707 const struct color_conv_coef ctbl_bt601_5_ovl = {
708 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
709 };
710 const struct color_conv_coef ctbl_bt601_5_wb = {
711 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
712 };
713
714 for (i = 1; i < num_ovl; i++)
715 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
716
717 for (; i < num_wb; i++)
718 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
719}
80c39712 720
f0e5caab 721static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 722{
9b372c2d 723 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 724}
725
f0e5caab 726static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 727{
9b372c2d 728 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 729}
730
f0e5caab 731static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 732{
733 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
734}
735
f0e5caab 736static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 737{
738 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
739}
740
d79db853
AT		 741static void dispc_ovl_set_pos(enum omap_plane plane,
742 enum omap_overlay_caps caps, int x, int y)
80c39712 743{
d79db853
AT		 744 u32 val;
745
746 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
747 return;
748
749 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 750
751 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 752}
753
78b687fc
AT		 754static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
755 int height)
80c39712 756{
80c39712 757 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 758
36d87d95 759 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 760 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
761 else
762 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 763}
764
78b687fc
AT		 765static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
766 int height)
80c39712
TV		 767{
768 u32 val;
80c39712
TV		 769
770 BUG_ON(plane == OMAP_DSS_GFX);
771
772 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 773
36d87d95
AT		 774 if (plane == OMAP_DSS_WB)
775 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
776 else
777 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 778}
779
5b54ed3e
AT		 780static void dispc_ovl_set_zorder(enum omap_plane plane,
781 enum omap_overlay_caps caps, u8 zorder)
54128701 782{
5b54ed3e 783 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 784 return;
785
786 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
787}
788
789static void dispc_ovl_enable_zorder_planes(void)
790{
791 int i;
792
793 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
794 return;
795
796 for (i = 0; i < dss_feat_get_num_ovls(); i++)
797 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
798}
799
5b54ed3e
AT		 800static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
801 enum omap_overlay_caps caps, bool enable)
fd28a390 802{
5b54ed3e 803 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 804 return;
805
9b372c2d 806 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 807}
808
5b54ed3e
AT		 809static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
810 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 811{
b8c095b4 812 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 813 int shift;
814
5b54ed3e 815 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 816 return;
a0acb557 817
fe3cc9d6
TV		 818 shift = shifts[plane];
819 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 820}
821
f0e5caab 822static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 823{
9b372c2d 824 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 825}
826
f0e5caab 827static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 828{
9b372c2d 829 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 830}
831
f0e5caab 832static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 833 enum omap_color_mode color_mode)
834{
835 u32 m = 0;
f20e4220
AJ		 836 if (plane != OMAP_DSS_GFX) {
837 switch (color_mode) {
838 case OMAP_DSS_COLOR_NV12:
839 m = 0x0; break;
08f3267e 840 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 841 m = 0x1; break;
842 case OMAP_DSS_COLOR_RGBA16:
843 m = 0x2; break;
08f3267e 844 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 845 m = 0x4; break;
846 case OMAP_DSS_COLOR_ARGB16:
847 m = 0x5; break;
848 case OMAP_DSS_COLOR_RGB16:
849 m = 0x6; break;
850 case OMAP_DSS_COLOR_ARGB16_1555:
851 m = 0x7; break;
852 case OMAP_DSS_COLOR_RGB24U:
853 m = 0x8; break;
854 case OMAP_DSS_COLOR_RGB24P:
855 m = 0x9; break;
856 case OMAP_DSS_COLOR_YUV2:
857 m = 0xa; break;
858 case OMAP_DSS_COLOR_UYVY:
859 m = 0xb; break;
860 case OMAP_DSS_COLOR_ARGB32:
861 m = 0xc; break;
862 case OMAP_DSS_COLOR_RGBA32:
863 m = 0xd; break;
864 case OMAP_DSS_COLOR_RGBX32:
865 m = 0xe; break;
866 case OMAP_DSS_COLOR_XRGB16_1555:
867 m = 0xf; break;
868 default:
c6eee968 869 BUG(); return;
f20e4220
AJ		 870 }
871 } else {
872 switch (color_mode) {
873 case OMAP_DSS_COLOR_CLUT1:
874 m = 0x0; break;
875 case OMAP_DSS_COLOR_CLUT2:
876 m = 0x1; break;
877 case OMAP_DSS_COLOR_CLUT4:
878 m = 0x2; break;
879 case OMAP_DSS_COLOR_CLUT8:
880 m = 0x3; break;
881 case OMAP_DSS_COLOR_RGB12U:
882 m = 0x4; break;
883 case OMAP_DSS_COLOR_ARGB16:
884 m = 0x5; break;
885 case OMAP_DSS_COLOR_RGB16:
886 m = 0x6; break;
887 case OMAP_DSS_COLOR_ARGB16_1555:
888 m = 0x7; break;
889 case OMAP_DSS_COLOR_RGB24U:
890 m = 0x8; break;
891 case OMAP_DSS_COLOR_RGB24P:
892 m = 0x9; break;
08f3267e 893 case OMAP_DSS_COLOR_RGBX16:
f20e4220 894 m = 0xa; break;
08f3267e 895 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 896 m = 0xb; break;
897 case OMAP_DSS_COLOR_ARGB32:
898 m = 0xc; break;
899 case OMAP_DSS_COLOR_RGBA32:
900 m = 0xd; break;
901 case OMAP_DSS_COLOR_RGBX32:
902 m = 0xe; break;
903 case OMAP_DSS_COLOR_XRGB16_1555:
904 m = 0xf; break;
905 default:
c6eee968 906 BUG(); return;
f20e4220 907 }
80c39712
TV		 908 }
909
9b372c2d 910 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 911}
912
65e006ff
CM		 913static void dispc_ovl_configure_burst_type(enum omap_plane plane,
914 enum omap_dss_rotation_type rotation_type)
915{
916 if (dss_has_feature(FEAT_BURST_2D) == 0)
917 return;
918
919 if (rotation_type == OMAP_DSS_ROT_TILER)
920 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
921 else
922 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
923}
924
f427984e 925void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 926{
927 int shift;
928 u32 val;
2a205f34 929 int chan = 0, chan2 = 0;
80c39712
TV		 930
931 switch (plane) {
932 case OMAP_DSS_GFX:
933 shift = 8;
934 break;
935 case OMAP_DSS_VIDEO1:
936 case OMAP_DSS_VIDEO2:
b8c095b4 937 case OMAP_DSS_VIDEO3:
80c39712
TV		 938 shift = 16;
939 break;
940 default:
941 BUG();
942 return;
943 }
944
9b372c2d 945 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 946 if (dss_has_feature(FEAT_MGR_LCD2)) {
947 switch (channel) {
948 case OMAP_DSS_CHANNEL_LCD:
949 chan = 0;
950 chan2 = 0;
951 break;
952 case OMAP_DSS_CHANNEL_DIGIT:
953 chan = 1;
954 chan2 = 0;
955 break;
956 case OMAP_DSS_CHANNEL_LCD2:
957 chan = 0;
958 chan2 = 1;
959 break;
e86d456a
CM		 960 case OMAP_DSS_CHANNEL_LCD3:
961 if (dss_has_feature(FEAT_MGR_LCD3)) {
962 chan = 0;
963 chan2 = 2;
964 } else {
965 BUG();
966 return;
967 }
968 break;
2a205f34
SS		 969 default:
970 BUG();
c6eee968 971 return;
2a205f34
SS		 972 }
973
974 val = FLD_MOD(val, chan, shift, shift);
975 val = FLD_MOD(val, chan2, 31, 30);
976 } else {
977 val = FLD_MOD(val, channel, shift, shift);
978 }
9b372c2d 979 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 980}
348be69d 981EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 982
2cc5d1af
TV		 983static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
984{
985 int shift;
986 u32 val;
987 enum omap_channel channel;
988
989 switch (plane) {
990 case OMAP_DSS_GFX:
991 shift = 8;
992 break;
993 case OMAP_DSS_VIDEO1:
994 case OMAP_DSS_VIDEO2:
995 case OMAP_DSS_VIDEO3:
996 shift = 16;
997 break;
998 default:
999 BUG();
c6eee968 1000 return 0;
2cc5d1af
TV		 1001 }
1002
1003 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1004
e86d456a
CM		 1005 if (dss_has_feature(FEAT_MGR_LCD3)) {
1006 if (FLD_GET(val, 31, 30) == 0)
1007 channel = FLD_GET(val, shift, shift);
1008 else if (FLD_GET(val, 31, 30) == 1)
1009 channel = OMAP_DSS_CHANNEL_LCD2;
1010 else
1011 channel = OMAP_DSS_CHANNEL_LCD3;
1012 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1013 if (FLD_GET(val, 31, 30) == 0)
1014 channel = FLD_GET(val, shift, shift);
1015 else
1016 channel = OMAP_DSS_CHANNEL_LCD2;
1017 } else {
1018 channel = FLD_GET(val, shift, shift);
1019 }
1020
1021 return channel;
1022}
1023
d9ac773c
AT		 1024void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1025{
1026 enum omap_plane plane = OMAP_DSS_WB;
1027
1028 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029}
1030
f0e5caab 1031static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1032 enum omap_burst_size burst_size)
1033{
8bbe09ee 1034 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1035 int shift;
80c39712 1036
fe3cc9d6 1037 shift = shifts[plane];
5ed8cf5b 1038 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1039}
1040
5ed8cf5b
TV		 1041static void dispc_configure_burst_sizes(void)
1042{
1043 int i;
1044 const int burst_size = BURST_SIZE_X8;
1045
1046 /* Configure burst size always to maximum size */
392faa0e 1047 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1048 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1049}
1050
83fa2f2e 1051static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1052{
1053 unsigned unit = dss_feat_get_burst_size_unit();
1054 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1055 return unit * 8;
1056}
1057
d3862610
M		 1058void dispc_enable_gamma_table(bool enable)
1059{
1060 /*
1061 * This is partially implemented to support only disabling of
1062 * the gamma table.
1063 */
1064 if (enable) {
1065 DSSWARN("Gamma table enabling for TV not yet supported");
1066 return;
1067 }
1068
1069 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070}
1071
c64dca40 1072static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1073{
efa70b3b 1074 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1075 return;
1076
efa70b3b 1077 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1078}
1079
c64dca40 1080static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1081 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1082{
1083 u32 coef_r, coef_g, coef_b;
1084
dd88b7a6 1085 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1086 return;
1087
1088 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1089 FLD_VAL(coefs->rb, 9, 0);
1090 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1091 FLD_VAL(coefs->gb, 9, 0);
1092 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1093 FLD_VAL(coefs->bb, 9, 0);
1094
1095 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1096 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1097 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098}
1099
f0e5caab 1100static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1101{
1102 u32 val;
1103
1104 BUG_ON(plane == OMAP_DSS_GFX);
1105
9b372c2d 1106 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1107 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1108 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1109}
1110
d79db853
AT		 1111static void dispc_ovl_enable_replication(enum omap_plane plane,
1112 enum omap_overlay_caps caps, bool enable)
80c39712 1113{
b8c095b4 1114 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1115 int shift;
80c39712 1116
d79db853
AT		 1117 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118 return;
1119
fe3cc9d6
TV		 1120 shift = shifts[plane];
1121 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1122}
1123
8f366162 1124static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1125 u16 height)
80c39712
TV		 1126{
1127 u32 val;
80c39712 1128
33b89928
AT		 1129 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1130 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1131
8f366162 1132 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1133}
1134
42a6961c 1135static void dispc_init_fifos(void)
80c39712 1136{
80c39712 1137 u32 size;
42a6961c 1138 int fifo;
a0acb557 1139 u8 start, end;
5ed8cf5b 1140 u32 unit;
47fc469b 1141 int i;
5ed8cf5b
TV		 1142
1143 unit = dss_feat_get_buffer_size_unit();
80c39712 1144
a0acb557 1145 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1146
42a6961c
TV		 1147 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1148 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1149 size *= unit;
42a6961c
TV		 1150 dispc.fifo_size[fifo] = size;
1151
1152 /*
1153 * By default fifos are mapped directly to overlays, fifo 0 to
1154 * ovl 0, fifo 1 to ovl 1, etc.
1155 */
1156 dispc.fifo_assignment[fifo] = fifo;
80c39712 1157 }
66a0f9e4
TV		 1158
1159 /*
1160 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1161 * causes problems with certain use cases, like using the tiler in 2D
1162 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1163 * giving GFX plane a larger fifo. WB but should work fine with a
1164 * smaller fifo.
1165 */
1166 if (dispc.feat->gfx_fifo_workaround) {
1167 u32 v;
1168
1169 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1170
1171 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1172 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1173 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1174 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1175
1176 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1177
1178 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1179 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1180 }
47fc469b
TV		 1181
1182 /*
1183 * Setup default fifo thresholds.
1184 */
1185 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1186 u32 low, high;
1187 const bool use_fifomerge = false;
1188 const bool manual_update = false;
1189
1190 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1191 use_fifomerge, manual_update);
1192
1193 dispc_ovl_set_fifo_threshold(i, low, high);
1194 }
80c39712
TV		 1195}
1196
83fa2f2e 1197static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1198{
42a6961c
TV		 1199 int fifo;
1200 u32 size = 0;
1201
1202 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1203 if (dispc.fifo_assignment[fifo] == plane)
1204 size += dispc.fifo_size[fifo];
1205 }
1206
1207 return size;
80c39712
TV		 1208}
1209
6f04e1bf 1210void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1211{
a0acb557 1212 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1213 u32 unit;
1214
1215 unit = dss_feat_get_buffer_size_unit();
1216
1217 WARN_ON(low % unit != 0);
1218 WARN_ON(high % unit != 0);
1219
1220 low /= unit;
1221 high /= unit;
a0acb557 1222
9b372c2d
AT		 1223 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1224 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1225
3cb5d966 1226 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1227 plane,
9b372c2d 1228 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1229 lo_start, lo_end) * unit,
9b372c2d 1230 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1231 hi_start, hi_end) * unit,
1232 low * unit, high * unit);
80c39712 1233
9b372c2d 1234 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1235 FLD_VAL(high, hi_start, hi_end) |
1236 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1237
1238 /*
1239 * configure the preload to the pipeline's high threhold, if HT it's too
1240 * large for the preload field, set the threshold to the maximum value
1241 * that can be held by the preload register
1242 */
1243 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1244 plane != OMAP_DSS_WB)
1245 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712 1246}
8ee5c842 1247EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
80c39712
TV		 1248
1249void dispc_enable_fifomerge(bool enable)
1250{
e6b0f884
TV		 1251 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1252 WARN_ON(enable);
1253 return;
1254 }
1255
80c39712
TV		 1256 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1257 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1258}
1259
83fa2f2e 1260void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1261 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1262 bool manual_update)
83fa2f2e
TV		 1263{
1264 /*
1265 * All sizes are in bytes. Both the buffer and burst are made of
1266 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1267 */
1268
1269 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1270 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1271 int i;
83fa2f2e
TV		 1272
1273 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1274 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1275
e0e405b9
TV		 1276 if (use_fifomerge) {
1277 total_fifo_size = 0;
392faa0e 1278 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1279 total_fifo_size += dispc_ovl_get_fifo_size(i);
1280 } else {
1281 total_fifo_size = ovl_fifo_size;
1282 }
1283
1284 /*
1285 * We use the same low threshold for both fifomerge and non-fifomerge
1286 * cases, but for fifomerge we calculate the high threshold using the
1287 * combined fifo size
1288 */
1289
3568f2a4 1290 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1291 *fifo_low = ovl_fifo_size - burst_size * 2;
1292 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1293 } else if (plane == OMAP_DSS_WB) {
1294 /*
1295 * Most optimal configuration for writeback is to push out data
1296 * to the interconnect the moment writeback pushes enough pixels
1297 * in the FIFO to form a burst
1298 */
1299 *fifo_low = 0;
1300 *fifo_high = burst_size;
e0e405b9
TV		 1301 } else {
1302 *fifo_low = ovl_fifo_size - burst_size;
1303 *fifo_high = total_fifo_size - buf_unit;
1304 }
83fa2f2e 1305}
8ee5c842 1306EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
83fa2f2e 1307
c64aa3a6
TV		 1308static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1309{
1310 int bit;
1311
1312 if (plane == OMAP_DSS_GFX)
1313 bit = 14;
1314 else
1315 bit = 23;
1316
1317 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1318}
1319
1320static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1321 int low, int high)
1322{
1323 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1324 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1325}
1326
1327static void dispc_init_mflag(void)
1328{
1329 int i;
1330
fe59e5cf
TV		 1331 /*
1332 * HACK: NV12 color format and MFLAG seem to have problems working
1333 * together: using two displays, and having an NV12 overlay on one of
1334 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1335 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1336 * remove the errors, but there doesn't seem to be a clear logic on
1337 * which values work and which not.
1338 *
1339 * As a work-around, set force MFLAG to always on.
1340 */
c64aa3a6 1341 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
fe59e5cf 1342 (1 << 0) | /* MFLAG_CTRL = force always on */
c64aa3a6
TV		 1343 (0 << 2)); /* MFLAG_START = disable */
1344
1345 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1346 u32 size = dispc_ovl_get_fifo_size(i);
1347 u32 unit = dss_feat_get_buffer_size_unit();
1348 u32 low, high;
1349
1350 dispc_ovl_set_mflag(i, true);
1351
1352 /*
1353 * Simulation team suggests below thesholds:
1354 * HT = fifosize * 5 / 8;
1355 * LT = fifosize * 4 / 8;
1356 */
1357
1358 low = size * 4 / 8 / unit;
1359 high = size * 5 / 8 / unit;
1360
1361 dispc_ovl_set_mflag_threshold(i, low, high);
1362 }
1363}
1364
f0e5caab 1365static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1366 int hinc, int vinc,
1367 enum omap_color_component color_comp)
80c39712
TV		 1368{
1369 u32 val;
80c39712 1370
0d66cbb5
AJ		 1371 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1372 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1373
0d66cbb5
AJ		 1374 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1375 &hinc_start, &hinc_end);
1376 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1377 &vinc_start, &vinc_end);
1378 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1379 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1380
0d66cbb5
AJ		 1381 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1382 } else {
1383 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1384 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1385 }
80c39712
TV		 1386}
1387
f0e5caab 1388static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1389{
1390 u32 val;
87a7484b 1391 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1392
87a7484b
AT		 1393 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1394 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1395
1396 val = FLD_VAL(vaccu, vert_start, vert_end) |
1397 FLD_VAL(haccu, hor_start, hor_end);
1398
9b372c2d 1399 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1400}
1401
f0e5caab 1402static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1403{
1404 u32 val;
87a7484b 1405 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1406
87a7484b
AT		 1407 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1408 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1409
1410 val = FLD_VAL(vaccu, vert_start, vert_end) |
1411 FLD_VAL(haccu, hor_start, hor_end);
1412
9b372c2d 1413 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1414}
1415
f0e5caab
TV		 1416static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1417 int vaccu)
ab5ca071
AJ		 1418{
1419 u32 val;
1420
1421 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1422 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1423}
1424
f0e5caab
TV		 1425static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1426 int vaccu)
ab5ca071
AJ		 1427{
1428 u32 val;
1429
1430 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1431 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1432}
80c39712 1433
f0e5caab 1434static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1435 u16 orig_width, u16 orig_height,
1436 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1437 bool five_taps, u8 rotation,
1438 enum omap_color_component color_comp)
80c39712 1439{
0d66cbb5 1440 int fir_hinc, fir_vinc;
80c39712 1441
ed14a3ce
AJ		 1442 fir_hinc = 1024 * orig_width / out_width;
1443 fir_vinc = 1024 * orig_height / out_height;
80c39712 1444
debd9074
CM		 1445 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1446 color_comp);
f0e5caab 1447 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1448}
1449
05dd0f53
CM		 1450static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1451 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1452 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1453{
1454 int h_accu2_0, h_accu2_1;
1455 int v_accu2_0, v_accu2_1;
1456 int chroma_hinc, chroma_vinc;
1457 int idx;
1458
1459 struct accu {
1460 s8 h0_m, h0_n;
1461 s8 h1_m, h1_n;
1462 s8 v0_m, v0_n;
1463 s8 v1_m, v1_n;
1464 };
1465
1466 const struct accu *accu_table;
1467 const struct accu *accu_val;
1468
1469 static const struct accu accu_nv12[4] = {
1470 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1471 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1472 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1473 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1474 };
1475
1476 static const struct accu accu_nv12_ilace[4] = {
1477 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1478 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1479 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1480 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1481 };
1482
1483 static const struct accu accu_yuv[4] = {
1484 { 0, 1, 0, 1, 0, 1, 0, 1 },
1485 { 0, 1, 0, 1, 0, 1, 0, 1 },
1486 { -1, 1, 0, 1, 0, 1, 0, 1 },
1487 { 0, 1, 0, 1, -1, 1, 0, 1 },
1488 };
1489
1490 switch (rotation) {
1491 case OMAP_DSS_ROT_0:
1492 idx = 0;
1493 break;
1494 case OMAP_DSS_ROT_90:
1495 idx = 1;
1496 break;
1497 case OMAP_DSS_ROT_180:
1498 idx = 2;
1499 break;
1500 case OMAP_DSS_ROT_270:
1501 idx = 3;
1502 break;
1503 default:
1504 BUG();
c6eee968 1505 return;
05dd0f53
CM		 1506 }
1507
1508 switch (color_mode) {
1509 case OMAP_DSS_COLOR_NV12:
1510 if (ilace)
1511 accu_table = accu_nv12_ilace;
1512 else
1513 accu_table = accu_nv12;
1514 break;
1515 case OMAP_DSS_COLOR_YUV2:
1516 case OMAP_DSS_COLOR_UYVY:
1517 accu_table = accu_yuv;
1518 break;
1519 default:
1520 BUG();
c6eee968 1521 return;
05dd0f53
CM		 1522 }
1523
1524 accu_val = &accu_table[idx];
1525
1526 chroma_hinc = 1024 * orig_width / out_width;
1527 chroma_vinc = 1024 * orig_height / out_height;
1528
1529 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1530 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1531 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1532 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1533
1534 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1535 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1536}
1537
f0e5caab 1538static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1539 u16 orig_width, u16 orig_height,
1540 u16 out_width, u16 out_height,
1541 bool ilace, bool five_taps,
1542 bool fieldmode, enum omap_color_mode color_mode,
1543 u8 rotation)
1544{
1545 int accu0 = 0;
1546 int accu1 = 0;
1547 u32 l;
80c39712 1548
f0e5caab 1549 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1550 out_width, out_height, five_taps,
1551 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1552 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1553
87a7484b
AT		 1554 /* RESIZEENABLE and VERTICALTAPS */
1555 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1556 l |= (orig_width != out_width) ? (1 << 5) : 0;
1557 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1558 l |= five_taps ? (1 << 21) : 0;
80c39712 1559
87a7484b
AT		 1560 /* VRESIZECONF and HRESIZECONF */
1561 if (dss_has_feature(FEAT_RESIZECONF)) {
1562 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1563 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1564 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1565 }
80c39712 1566
87a7484b
AT		 1567 /* LINEBUFFERSPLIT */
1568 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1569 l &= ~(0x1 << 22);
1570 l |= five_taps ? (1 << 22) : 0;
1571 }
80c39712 1572
9b372c2d 1573 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1574
1575 /*
1576 * field 0 = even field = bottom field
1577 * field 1 = odd field = top field
1578 */
1579 if (ilace && !fieldmode) {
1580 accu1 = 0;
0d66cbb5 1581 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1582 if (accu0 >= 1024/2) {
1583 accu1 = 1024/2;
1584 accu0 -= accu1;
1585 }
1586 }
1587
f0e5caab
TV		 1588 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1589 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1590}
1591
f0e5caab 1592static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1593 u16 orig_width, u16 orig_height,
1594 u16 out_width, u16 out_height,
1595 bool ilace, bool five_taps,
1596 bool fieldmode, enum omap_color_mode color_mode,
1597 u8 rotation)
1598{
1599 int scale_x = out_width != orig_width;
1600 int scale_y = out_height != orig_height;
f92afae2 1601 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1602
1603 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1604 return;
1605 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1606 color_mode != OMAP_DSS_COLOR_UYVY &&
1607 color_mode != OMAP_DSS_COLOR_NV12)) {
1608 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1609 if (plane != OMAP_DSS_WB)
1610 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1611 return;
1612 }
36377357
TV		 1613
1614 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1615 out_height, ilace, color_mode, rotation);
1616
0d66cbb5
AJ		 1617 switch (color_mode) {
1618 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1619 if (chroma_upscale) {
1620 /* UV is subsampled by 2 horizontally and vertically */
1621 orig_height >>= 1;
1622 orig_width >>= 1;
1623 } else {
1624 /* UV is downsampled by 2 horizontally and vertically */
1625 orig_height <<= 1;
1626 orig_width <<= 1;
1627 }
1628
0d66cbb5
AJ		 1629 break;
1630 case OMAP_DSS_COLOR_YUV2:
1631 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1632 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1633 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1634 rotation == OMAP_DSS_ROT_180) {
1635 if (chroma_upscale)
1636 /* UV is subsampled by 2 horizontally */
1637 orig_width >>= 1;
1638 else
1639 /* UV is downsampled by 2 horizontally */
1640 orig_width <<= 1;
1641 }
1642
0d66cbb5
AJ		 1643 /* must use FIR for YUV422 if rotated */
1644 if (rotation != OMAP_DSS_ROT_0)
1645 scale_x = scale_y = true;
20fbb50b 1646
0d66cbb5
AJ		 1647 break;
1648 default:
1649 BUG();
c6eee968 1650 return;
0d66cbb5
AJ		 1651 }
1652
1653 if (out_width != orig_width)
1654 scale_x = true;
1655 if (out_height != orig_height)
1656 scale_y = true;
1657
f0e5caab 1658 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1659 out_width, out_height, five_taps,
1660 rotation, DISPC_COLOR_COMPONENT_UV);
1661
2a5561b1
AT		 1662 if (plane != OMAP_DSS_WB)
1663 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1664 (scale_x || scale_y) ? 1 : 0, 8, 8);
1665
0d66cbb5
AJ		 1666 /* set H scaling */
1667 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1668 /* set V scaling */
1669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1670}
1671
f0e5caab 1672static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1673 u16 orig_width, u16 orig_height,
1674 u16 out_width, u16 out_height,
1675 bool ilace, bool five_taps,
1676 bool fieldmode, enum omap_color_mode color_mode,
1677 u8 rotation)
1678{
1679 BUG_ON(plane == OMAP_DSS_GFX);
1680
f0e5caab 1681 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1682 orig_width, orig_height,
1683 out_width, out_height,
1684 ilace, five_taps,
1685 fieldmode, color_mode,
1686 rotation);
1687
f0e5caab 1688 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1689 orig_width, orig_height,
1690 out_width, out_height,
1691 ilace, five_taps,
1692 fieldmode, color_mode,
1693 rotation);
1694}
1695
f0e5caab 1696static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1697 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1698 bool mirroring, enum omap_color_mode color_mode)
1699{
87a7484b
AT		 1700 bool row_repeat = false;
1701 int vidrot = 0;
1702
80c39712
TV		 1703 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1704 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1705
1706 if (mirroring) {
1707 switch (rotation) {
1708 case OMAP_DSS_ROT_0:
1709 vidrot = 2;
1710 break;
1711 case OMAP_DSS_ROT_90:
1712 vidrot = 1;
1713 break;
1714 case OMAP_DSS_ROT_180:
1715 vidrot = 0;
1716 break;
1717 case OMAP_DSS_ROT_270:
1718 vidrot = 3;
1719 break;
1720 }
1721 } else {
1722 switch (rotation) {
1723 case OMAP_DSS_ROT_0:
1724 vidrot = 0;
1725 break;
1726 case OMAP_DSS_ROT_90:
1727 vidrot = 1;
1728 break;
1729 case OMAP_DSS_ROT_180:
1730 vidrot = 2;
1731 break;
1732 case OMAP_DSS_ROT_270:
1733 vidrot = 3;
1734 break;
1735 }
1736 }
1737
80c39712 1738 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1739 row_repeat = true;
80c39712 1740 else
87a7484b 1741 row_repeat = false;
80c39712 1742 }
87a7484b 1743
3397cc6a
TV		 1744 /*
1745 * OMAP4/5 Errata i631:
1746 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1747 * rows beyond the framebuffer, which may cause OCP error.
1748 */
1749 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1750 rotation_type != OMAP_DSS_ROT_TILER)
1751 vidrot = 1;
1752
9b372c2d 1753 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1754 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1755 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1756 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1757
1758 if (color_mode == OMAP_DSS_COLOR_NV12) {
1759 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1760 (rotation == OMAP_DSS_ROT_0 ||
1761 rotation == OMAP_DSS_ROT_180);
1762 /* DOUBLESTRIDE */
1763 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1764 }
1765
80c39712
TV		 1766}
1767
1768static int color_mode_to_bpp(enum omap_color_mode color_mode)
1769{
1770 switch (color_mode) {
1771 case OMAP_DSS_COLOR_CLUT1:
1772 return 1;
1773 case OMAP_DSS_COLOR_CLUT2:
1774 return 2;
1775 case OMAP_DSS_COLOR_CLUT4:
1776 return 4;
1777 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1778 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1779 return 8;
1780 case OMAP_DSS_COLOR_RGB12U:
1781 case OMAP_DSS_COLOR_RGB16:
1782 case OMAP_DSS_COLOR_ARGB16:
1783 case OMAP_DSS_COLOR_YUV2:
1784 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1785 case OMAP_DSS_COLOR_RGBA16:
1786 case OMAP_DSS_COLOR_RGBX16:
1787 case OMAP_DSS_COLOR_ARGB16_1555:
1788 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1789 return 16;
1790 case OMAP_DSS_COLOR_RGB24P:
1791 return 24;
1792 case OMAP_DSS_COLOR_RGB24U:
1793 case OMAP_DSS_COLOR_ARGB32:
1794 case OMAP_DSS_COLOR_RGBA32:
1795 case OMAP_DSS_COLOR_RGBX32:
1796 return 32;
1797 default:
1798 BUG();
c6eee968 1799 return 0;
80c39712
TV		 1800 }
1801}
1802
1803static s32 pixinc(int pixels, u8 ps)
1804{
1805 if (pixels == 1)
1806 return 1;
1807 else if (pixels > 1)
1808 return 1 + (pixels - 1) * ps;
1809 else if (pixels < 0)
1810 return 1 - (-pixels + 1) * ps;
1811 else
1812 BUG();
c6eee968 1813 return 0;
80c39712
TV		 1814}
1815
1816static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1817 u16 screen_width,
1818 u16 width, u16 height,
1819 enum omap_color_mode color_mode, bool fieldmode,
1820 unsigned int field_offset,
1821 unsigned *offset0, unsigned *offset1,
aed74b55 1822 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1823{
1824 u8 ps;
1825
1826 /* FIXME CLUT formats */
1827 switch (color_mode) {
1828 case OMAP_DSS_COLOR_CLUT1:
1829 case OMAP_DSS_COLOR_CLUT2:
1830 case OMAP_DSS_COLOR_CLUT4:
1831 case OMAP_DSS_COLOR_CLUT8:
1832 BUG();
1833 return;
1834 case OMAP_DSS_COLOR_YUV2:
1835 case OMAP_DSS_COLOR_UYVY:
1836 ps = 4;
1837 break;
1838 default:
1839 ps = color_mode_to_bpp(color_mode) / 8;
1840 break;
1841 }
1842
1843 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1844 width, height);
1845
1846 /*
1847 * field 0 = even field = bottom field
1848 * field 1 = odd field = top field
1849 */
1850 switch (rotation + mirror * 4) {
1851 case OMAP_DSS_ROT_0:
1852 case OMAP_DSS_ROT_180:
1853 /*
1854 * If the pixel format is YUV or UYVY divide the width
1855 * of the image by 2 for 0 and 180 degree rotation.
1856 */
1857 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1858 color_mode == OMAP_DSS_COLOR_UYVY)
1859 width = width >> 1;
1860 case OMAP_DSS_ROT_90:
1861 case OMAP_DSS_ROT_270:
1862 *offset1 = 0;
1863 if (field_offset)
1864 *offset0 = field_offset * screen_width * ps;
1865 else
1866 *offset0 = 0;
1867
aed74b55
CM		 1868 *row_inc = pixinc(1 +
1869 (y_predecim * screen_width - x_predecim * width) +
1870 (fieldmode ? screen_width : 0), ps);
1871 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1872 break;
1873
1874 case OMAP_DSS_ROT_0 + 4:
1875 case OMAP_DSS_ROT_180 + 4:
1876 /* If the pixel format is YUV or UYVY divide the width
1877 * of the image by 2 for 0 degree and 180 degree
1878 */
1879 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1880 color_mode == OMAP_DSS_COLOR_UYVY)
1881 width = width >> 1;
1882 case OMAP_DSS_ROT_90 + 4:
1883 case OMAP_DSS_ROT_270 + 4:
1884 *offset1 = 0;
1885 if (field_offset)
1886 *offset0 = field_offset * screen_width * ps;
1887 else
1888 *offset0 = 0;
aed74b55
CM		 1889 *row_inc = pixinc(1 -
1890 (y_predecim * screen_width + x_predecim * width) -
1891 (fieldmode ? screen_width : 0), ps);
1892 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1893 break;
1894
1895 default:
1896 BUG();
c6eee968 1897 return;
80c39712
TV		 1898 }
1899}
1900
1901static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1902 u16 screen_width,
1903 u16 width, u16 height,
1904 enum omap_color_mode color_mode, bool fieldmode,
1905 unsigned int field_offset,
1906 unsigned *offset0, unsigned *offset1,
aed74b55 1907 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1908{
1909 u8 ps;
1910 u16 fbw, fbh;
1911
1912 /* FIXME CLUT formats */
1913 switch (color_mode) {
1914 case OMAP_DSS_COLOR_CLUT1:
1915 case OMAP_DSS_COLOR_CLUT2:
1916 case OMAP_DSS_COLOR_CLUT4:
1917 case OMAP_DSS_COLOR_CLUT8:
1918 BUG();
1919 return;
1920 default:
1921 ps = color_mode_to_bpp(color_mode) / 8;
1922 break;
1923 }
1924
1925 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1926 width, height);
1927
1928 /* width & height are overlay sizes, convert to fb sizes */
1929
1930 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1931 fbw = width;
1932 fbh = height;
1933 } else {
1934 fbw = height;
1935 fbh = width;
1936 }
1937
1938 /*
1939 * field 0 = even field = bottom field
1940 * field 1 = odd field = top field
1941 */
1942 switch (rotation + mirror * 4) {
1943 case OMAP_DSS_ROT_0:
1944 *offset1 = 0;
1945 if (field_offset)
1946 *offset0 = *offset1 + field_offset * screen_width * ps;
1947 else
1948 *offset0 = *offset1;
aed74b55
CM		 1949 *row_inc = pixinc(1 +
1950 (y_predecim * screen_width - fbw * x_predecim) +
1951 (fieldmode ? screen_width : 0), ps);
1952 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1953 color_mode == OMAP_DSS_COLOR_UYVY)
1954 *pix_inc = pixinc(x_predecim, 2 * ps);
1955 else
1956 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1957 break;
1958 case OMAP_DSS_ROT_90:
1959 *offset1 = screen_width * (fbh - 1) * ps;
1960 if (field_offset)
1961 *offset0 = *offset1 + field_offset * ps;
1962 else
1963 *offset0 = *offset1;
aed74b55
CM		 1964 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1965 y_predecim + (fieldmode ? 1 : 0), ps);
1966 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1967 break;
1968 case OMAP_DSS_ROT_180:
1969 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1970 if (field_offset)
1971 *offset0 = *offset1 - field_offset * screen_width * ps;
1972 else
1973 *offset0 = *offset1;
1974 *row_inc = pixinc(-1 -
aed74b55
CM		 1975 (y_predecim * screen_width - fbw * x_predecim) -
1976 (fieldmode ? screen_width : 0), ps);
1977 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1978 color_mode == OMAP_DSS_COLOR_UYVY)
1979 *pix_inc = pixinc(-x_predecim, 2 * ps);
1980 else
1981 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1982 break;
1983 case OMAP_DSS_ROT_270:
1984 *offset1 = (fbw - 1) * ps;
1985 if (field_offset)
1986 *offset0 = *offset1 - field_offset * ps;
1987 else
1988 *offset0 = *offset1;
aed74b55
CM		 1989 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1990 y_predecim - (fieldmode ? 1 : 0), ps);
1991 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1992 break;
1993
1994 /* mirroring */
1995 case OMAP_DSS_ROT_0 + 4:
1996 *offset1 = (fbw - 1) * ps;
1997 if (field_offset)
1998 *offset0 = *offset1 + field_offset * screen_width * ps;
1999 else
2000 *offset0 = *offset1;
aed74b55 2001 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 2002 (fieldmode ? screen_width : 0),
2003 ps);
aed74b55
CM		 2004 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2005 color_mode == OMAP_DSS_COLOR_UYVY)
2006 *pix_inc = pixinc(-x_predecim, 2 * ps);
2007 else
2008 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2009 break;
2010
2011 case OMAP_DSS_ROT_90 + 4:
2012 *offset1 = 0;
2013 if (field_offset)
2014 *offset0 = *offset1 + field_offset * ps;
2015 else
2016 *offset0 = *offset1;
aed74b55
CM		 2017 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2018 y_predecim + (fieldmode ? 1 : 0),
80c39712 2019 ps);
aed74b55 2020 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2021 break;
2022
2023 case OMAP_DSS_ROT_180 + 4:
2024 *offset1 = screen_width * (fbh - 1) * ps;
2025 if (field_offset)
2026 *offset0 = *offset1 - field_offset * screen_width * ps;
2027 else
2028 *offset0 = *offset1;
aed74b55 2029 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 2030 (fieldmode ? screen_width : 0),
2031 ps);
aed74b55
CM		 2032 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2033 color_mode == OMAP_DSS_COLOR_UYVY)
2034 *pix_inc = pixinc(x_predecim, 2 * ps);
2035 else
2036 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2037 break;
2038
2039 case OMAP_DSS_ROT_270 + 4:
2040 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2041 if (field_offset)
2042 *offset0 = *offset1 - field_offset * ps;
2043 else
2044 *offset0 = *offset1;
aed74b55
CM		 2045 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2046 y_predecim - (fieldmode ? 1 : 0),
80c39712 2047 ps);
aed74b55 2048 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2049 break;
2050
2051 default:
2052 BUG();
c6eee968 2053 return;
80c39712
TV		 2054 }
2055}
2056
65e006ff
CM		 2057static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2058 enum omap_color_mode color_mode, bool fieldmode,
2059 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2060 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2061{
2062 u8 ps;
2063
2064 switch (color_mode) {
2065 case OMAP_DSS_COLOR_CLUT1:
2066 case OMAP_DSS_COLOR_CLUT2:
2067 case OMAP_DSS_COLOR_CLUT4:
2068 case OMAP_DSS_COLOR_CLUT8:
2069 BUG();
2070 return;
2071 default:
2072 ps = color_mode_to_bpp(color_mode) / 8;
2073 break;
2074 }
2075
2076 DSSDBG("scrw %d, width %d\n", screen_width, width);
2077
2078 /*
2079 * field 0 = even field = bottom field
2080 * field 1 = odd field = top field
2081 */
2082 *offset1 = 0;
2083 if (field_offset)
2084 *offset0 = *offset1 + field_offset * screen_width * ps;
2085 else
2086 *offset0 = *offset1;
2087 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2088 (fieldmode ? screen_width : 0), ps);
2089 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2090 color_mode == OMAP_DSS_COLOR_UYVY)
2091 *pix_inc = pixinc(x_predecim, 2 * ps);
2092 else
2093 *pix_inc = pixinc(x_predecim, ps);
2094}
2095
7faa9233
CM		 2096/*
2097 * This function is used to avoid synclosts in OMAP3, because of some
2098 * undocumented horizontal position and timing related limitations.
2099 */
465ec13f 2100static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2101 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2102 u16 width, u16 height, u16 out_width, u16 out_height,
2103 bool five_taps)
7faa9233 2104{
230edc03 2105 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2106 unsigned long nonactive;
7faa9233
CM		 2107 static const u8 limits[3] = { 8, 10, 20 };
2108 u64 val, blank;
2109 int i;
2110
81ab95b7 2111 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2112
2113 i = 0;
2114 if (out_height < height)
2115 i++;
2116 if (out_width < width)
2117 i++;
81ab95b7 2118 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2119 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2120 if (blank <= limits[i])
2121 return -EINVAL;
2122
e4998634
ID		 2123 /* FIXME add checks for 3-tap filter once the limitations are known */
2124 if (!five_taps)
2125 return 0;
2126
7faa9233
CM		 2127 /*
2128 * Pixel data should be prepared before visible display point starts.
2129 * So, atleast DS-2 lines must have already been fetched by DISPC
2130 * during nonactive - pos_x period.
2131 */
2132 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2133 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2134 val, max(0, ds - 2) * width);
2135 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2136 return -EINVAL;
2137
2138 /*
2139 * All lines need to be refilled during the nonactive period of which
2140 * only one line can be loaded during the active period. So, atleast
2141 * DS - 1 lines should be loaded during nonactive period.
2142 */
2143 val = div_u64((u64)nonactive * lclk, pclk);
2144 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2145 val, max(0, ds - 1) * width);
2146 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2147 return -EINVAL;
2148
2149 return 0;
2150}
2151
8702ee50 2152static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2153 const struct omap_video_timings *mgr_timings, u16 width,
2154 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2155 enum omap_color_mode color_mode)
80c39712 2156{
8b53d991 2157 u32 core_clk = 0;
3e8a6ff2 2158 u64 tmp;
80c39712 2159
7282f1b7
CM		 2160 if (height <= out_height && width <= out_width)
2161 return (unsigned long) pclk;
2162
80c39712 2163 if (height > out_height) {
81ab95b7 2164 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2165
2166 tmp = pclk * height * out_width;
2167 do_div(tmp, 2 * out_height * ppl);
8b53d991 2168 core_clk = tmp;
80c39712 2169
2d9c5597
VS		 2170 if (height > 2 * out_height) {
2171 if (ppl == out_width)
2172 return 0;
2173
80c39712
TV		 2174 tmp = pclk * (height - 2 * out_height) * out_width;
2175 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2176 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2177 }
2178 }
2179
2180 if (width > out_width) {
2181 tmp = pclk * width;
2182 do_div(tmp, out_width);
8b53d991 2183 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2184
2185 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2186 core_clk <<= 1;
80c39712
TV		 2187 }
2188
8b53d991 2189 return core_clk;
80c39712
TV		 2190}
2191
8702ee50 2192static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2193 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2194{
dcbe765b
CM		 2195 if (height > out_height && width > out_width)
2196 return pclk * 4;
2197 else
2198 return pclk * 2;
2199}
2200
8702ee50 2201static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2202 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2203{
2204 unsigned int hf, vf;
2205
2206 /*
2207 * FIXME how to determine the 'A' factor
2208 * for the no downscaling case ?
2209 */
2210
2211 if (width > 3 * out_width)
2212 hf = 4;
2213 else if (width > 2 * out_width)
2214 hf = 3;
2215 else if (width > out_width)
2216 hf = 2;
2217 else
2218 hf = 1;
80c39712
TV		 2219 if (height > out_height)
2220 vf = 2;
2221 else
2222 vf = 1;
2223
dcbe765b
CM		 2224 return pclk * vf * hf;
2225}
2226
8702ee50 2227static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2228 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2229{
8ba85306
AT		 2230 /*
2231 * If the overlay/writeback is in mem to mem mode, there are no
2232 * downscaling limitations with respect to pixel clock, return 1 as
2233 * required core clock to represent that we have sufficient enough
2234 * core clock to do maximum downscaling
2235 */
2236 if (mem_to_mem)
2237 return 1;
2238
dcbe765b
CM		 2239 if (width > out_width)
2240 return DIV_ROUND_UP(pclk, out_width) * width;
2241 else
2242 return pclk;
2243}
2244
0c6921de 2245static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2246 const struct omap_video_timings *mgr_timings,
2247 u16 width, u16 height, u16 out_width, u16 out_height,
2248 enum omap_color_mode color_mode, bool *five_taps,
2249 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2250 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2251{
2252 int error;
2253 u16 in_width, in_height;
2254 int min_factor = min(*decim_x, *decim_y);
2255 const int maxsinglelinewidth =
2256 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2257
dcbe765b
CM		 2258 *five_taps = false;
2259
2260 do {
eec77da2
TV		 2261 in_height = height / *decim_y;
2262 in_width = width / *decim_x;
8702ee50 2263 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2264 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2265 error = (in_width > maxsinglelinewidth || !*core_clk ||
2266 *core_clk > dispc_core_clk_rate());
2267 if (error) {
2268 if (*decim_x == *decim_y) {
2269 *decim_x = min_factor;
2270 ++*decim_y;
2271 } else {
2272 swap(*decim_x, *decim_y);
2273 if (*decim_x < *decim_y)
2274 ++*decim_x;
2275 }
2276 }
2277 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2278
2279 if (in_width > maxsinglelinewidth) {
2280 DSSERR("Cannot scale max input width exceeded");
2281 return -EINVAL;
2282 }
2283 return 0;
2284}
2285
0c6921de 2286static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2287 const struct omap_video_timings *mgr_timings,
2288 u16 width, u16 height, u16 out_width, u16 out_height,
2289 enum omap_color_mode color_mode, bool *five_taps,
2290 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2291 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2292{
2293 int error;
2294 u16 in_width, in_height;
2295 int min_factor = min(*decim_x, *decim_y);
2296 const int maxsinglelinewidth =
2297 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2298
2299 do {
eec77da2
TV		 2300 in_height = height / *decim_y;
2301 in_width = width / *decim_x;
e4998634 2302 *five_taps = in_height > out_height;
dcbe765b
CM		 2303
2304 if (in_width > maxsinglelinewidth)
2305 if (in_height > out_height &&
2306 in_height < out_height * 2)
2307 *five_taps = false;
e4998634
ID		 2308again:
2309 if (*five_taps)
2310 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2311 in_width, in_height, out_width,
2312 out_height, color_mode);
2313 else
8702ee50 2314 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2315 in_height, out_width, out_height,
2316 mem_to_mem);
dcbe765b 2317
e4998634
ID		 2318 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2319 pos_x, in_width, in_height, out_width,
2320 out_height, *five_taps);
2321 if (error && *five_taps) {
2322 *five_taps = false;
2323 goto again;
2324 }
2325
dcbe765b
CM		 2326 error = (error || in_width > maxsinglelinewidth * 2 ||
2327 (in_width > maxsinglelinewidth && *five_taps) ||
2328 !*core_clk || *core_clk > dispc_core_clk_rate());
2329 if (error) {
2330 if (*decim_x == *decim_y) {
2331 *decim_x = min_factor;
2332 ++*decim_y;
2333 } else {
2334 swap(*decim_x, *decim_y);
2335 if (*decim_x < *decim_y)
2336 ++*decim_x;
2337 }
2338 }
2339 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2340
465ec13f 2341 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
e4998634 2342 height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2343 DSSERR("horizontal timing too tight\n");
2344 return -EINVAL;
7282f1b7 2345 }
dcbe765b
CM		 2346
2347 if (in_width > (maxsinglelinewidth * 2)) {
2348 DSSERR("Cannot setup scaling");
2349 DSSERR("width exceeds maximum width possible");
2350 return -EINVAL;
2351 }
2352
2353 if (in_width > maxsinglelinewidth && *five_taps) {
2354 DSSERR("cannot setup scaling with five taps");
2355 return -EINVAL;
2356 }
2357 return 0;
2358}
2359
0c6921de 2360static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2361 const struct omap_video_timings *mgr_timings,
2362 u16 width, u16 height, u16 out_width, u16 out_height,
2363 enum omap_color_mode color_mode, bool *five_taps,
2364 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2365 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2366{
2367 u16 in_width, in_width_max;
2368 int decim_x_min = *decim_x;
eec77da2 2369 u16 in_height = height / *decim_y;
dcbe765b
CM		 2370 const int maxsinglelinewidth =
2371 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2372 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2373
5d501085
AT		 2374 if (mem_to_mem) {
2375 in_width_max = out_width * maxdownscale;
2376 } else {
8ba85306
AT		 2377 in_width_max = dispc_core_clk_rate() /
2378 DIV_ROUND_UP(pclk, out_width);
5d501085 2379 }
dcbe765b 2380
dcbe765b
CM		 2381 *decim_x = DIV_ROUND_UP(width, in_width_max);
2382
2383 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2384 if (*decim_x > *x_predecim)
2385 return -EINVAL;
2386
2387 do {
eec77da2 2388 in_width = width / *decim_x;
dcbe765b
CM		 2389 } while (*decim_x <= *x_predecim &&
2390 in_width > maxsinglelinewidth && ++*decim_x);
2391
2392 if (in_width > maxsinglelinewidth) {
2393 DSSERR("Cannot scale width exceeds max line width");
2394 return -EINVAL;
2395 }
2396
8702ee50 2397 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2398 out_width, out_height, mem_to_mem);
dcbe765b 2399 return 0;
80c39712
TV		 2400}
2401
74e16458 2402static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2403 enum omap_overlay_caps caps,
81ab95b7
AT		 2404 const struct omap_video_timings *mgr_timings,
2405 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2406 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2407 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2408 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2409{
0373cac6 2410 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2411 const int max_decim_limit = 16;
8b53d991 2412 unsigned long core_clk = 0;
dcbe765b 2413 int decim_x, decim_y, ret;
79ad75f2 2414
f95cb5eb
TV		 2415 if (width == out_width && height == out_height)
2416 return 0;
2417
4e1d3ca0
TV		 2418 if (pclk == 0 || mgr_timings->pixelclock == 0) {
2419 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2420 return -EINVAL;
2421 }
2422
5b54ed3e 2423 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2424 return -EINVAL;
79ad75f2 2425
74e16458 2426 if (mem_to_mem) {
1c031441
AT		 2427 *x_predecim = *y_predecim = 1;
2428 } else {
2429 *x_predecim = max_decim_limit;
2430 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2431 dss_has_feature(FEAT_BURST_2D)) ?
2432 2 : max_decim_limit;
2433 }
aed74b55
CM		 2434
2435 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2436 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2437 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2438 color_mode == OMAP_DSS_COLOR_CLUT8) {
2439 *x_predecim = 1;
2440 *y_predecim = 1;
2441 *five_taps = false;
2442 return 0;
2443 }
2444
2445 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2446 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2447
aed74b55 2448 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2449 return -EINVAL;
2450
aed74b55 2451 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2452 return -EINVAL;
2453
0c6921de 2454 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2455 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2456 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2457 mem_to_mem);
dcbe765b
CM		 2458 if (ret)
2459 return ret;
79ad75f2 2460
8b53d991
CM		 2461 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2462 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2463
8b53d991 2464 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2465 DSSERR("failed to set up scaling, "
8b53d991
CM		 2466 "required core clk rate = %lu Hz, "
2467 "current core clk rate = %lu Hz\n",
2468 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2469 return -EINVAL;
2470 }
2471
aed74b55
CM		 2472 *x_predecim = decim_x;
2473 *y_predecim = decim_y;
79ad75f2
AT		 2474 return 0;
2475}
2476
f9b719b6
TV		 2477int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2478 const struct omap_overlay_info *oi,
2479 const struct omap_video_timings *timings,
2480 int *x_predecim, int *y_predecim)
2481{
2482 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2483 bool five_taps = true;
62a83183 2484 bool fieldmode = false;
f9b719b6
TV		 2485 u16 in_height = oi->height;
2486 u16 in_width = oi->width;
2487 bool ilace = timings->interlace;
2488 u16 out_width, out_height;
2489 int pos_x = oi->pos_x;
2490 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2491 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2492
2493 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2494 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2495
2496 if (ilace && oi->height == out_height)
62a83183 2497 fieldmode = true;
f9b719b6
TV		 2498
2499 if (ilace) {
2500 if (fieldmode)
2501 in_height /= 2;
2502 out_height /= 2;
2503
2504 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2505 in_height, out_height);
2506 }
2507
2508 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2509 return -EINVAL;
2510
2511 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2512 in_height, out_width, out_height, oi->color_mode,
2513 &five_taps, x_predecim, y_predecim, pos_x,
2514 oi->rotation_type, false);
2515}
348be69d 2516EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2517
84a880fd 2518static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2519 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2520 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2521 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2522 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2523 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2524 bool replication, const struct omap_video_timings *mgr_timings,
2525 bool mem_to_mem)
80c39712 2526{
7282f1b7 2527 bool five_taps = true;
62a83183 2528 bool fieldmode = false;
79ad75f2 2529 int r, cconv = 0;
80c39712
TV		 2530 unsigned offset0, offset1;
2531 s32 row_inc;
2532 s32 pix_inc;
6be0d73e 2533 u16 frame_width, frame_height;
80c39712 2534 unsigned int field_offset = 0;
84a880fd
AT		 2535 u16 in_height = height;
2536 u16 in_width = width;
aed74b55 2537 int x_predecim = 1, y_predecim = 1;
8050cbe4 2538 bool ilace = mgr_timings->interlace;
74e16458
TV		 2539 unsigned long pclk = dispc_plane_pclk_rate(plane);
2540 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2541
e566658f 2542 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2543 return -EINVAL;
2544
84a880fd
AT		 2545 out_width = out_width == 0 ? width : out_width;
2546 out_height = out_height == 0 ? height : out_height;
cf073668 2547
84a880fd 2548 if (ilace && height == out_height)
62a83183 2549 fieldmode = true;
80c39712
TV		 2550
2551 if (ilace) {
2552 if (fieldmode)
aed74b55 2553 in_height /= 2;
8eeb7019 2554 pos_y /= 2;
aed74b55 2555 out_height /= 2;
80c39712
TV		 2556
2557 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2558 "out_height %d\n", in_height, pos_y,
2559 out_height);
80c39712
TV		 2560 }
2561
84a880fd 2562 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2563 return -EINVAL;
2564
74e16458 2565 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2566 in_height, out_width, out_height, color_mode,
2567 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2568 rotation_type, mem_to_mem);
79ad75f2
AT		 2569 if (r)
2570 return r;
80c39712 2571
eec77da2
TV		 2572 in_width = in_width / x_predecim;
2573 in_height = in_height / y_predecim;
aed74b55 2574
84a880fd
AT		 2575 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2576 color_mode == OMAP_DSS_COLOR_UYVY ||
2577 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2578 cconv = 1;
80c39712
TV		 2579
2580 if (ilace && !fieldmode) {
2581 /*
2582 * when downscaling the bottom field may have to start several
2583 * source lines below the top field. Unfortunately ACCUI
2584 * registers will only hold the fractional part of the offset
2585 * so the integer part must be added to the base address of the
2586 * bottom field.
2587 */
aed74b55 2588 if (!in_height || in_height == out_height)
80c39712
TV		 2589 field_offset = 0;
2590 else
aed74b55 2591 field_offset = in_height / out_height / 2;
80c39712
TV		 2592 }
2593
2594 /* Fields are independent but interleaved in memory. */
2595 if (fieldmode)
2596 field_offset = 1;
2597
c6eee968
TV		 2598 offset0 = 0;
2599 offset1 = 0;
2600 row_inc = 0;
2601 pix_inc = 0;
2602
6be0d73e
AT		 2603 if (plane == OMAP_DSS_WB) {
2604 frame_width = out_width;
2605 frame_height = out_height;
2606 } else {
2607 frame_width = in_width;
2608 frame_height = height;
2609 }
2610
84a880fd 2611 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2612 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2613 color_mode, fieldmode, field_offset,
65e006ff
CM		 2614 &offset0, &offset1, &row_inc, &pix_inc,
2615 x_predecim, y_predecim);
84a880fd 2616 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2617 calc_dma_rotation_offset(rotation, mirror, screen_width,
2618 frame_width, frame_height,
84a880fd 2619 color_mode, fieldmode, field_offset,
aed74b55
CM		 2620 &offset0, &offset1, &row_inc, &pix_inc,
2621 x_predecim, y_predecim);
80c39712 2622 else
84a880fd 2623 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2624 screen_width, frame_width, frame_height,
84a880fd 2625 color_mode, fieldmode, field_offset,
aed74b55
CM		 2626 &offset0, &offset1, &row_inc, &pix_inc,
2627 x_predecim, y_predecim);
80c39712
TV		 2628
2629 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2630 offset0, offset1, row_inc, pix_inc);
2631
84a880fd 2632 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2633
84a880fd 2634 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2635
84a880fd
AT		 2636 dispc_ovl_set_ba0(plane, paddr + offset0);
2637 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2638
84a880fd
AT		 2639 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2640 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2641 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2642 }
2643
f0e5caab
TV		 2644 dispc_ovl_set_row_inc(plane, row_inc);
2645 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2646
84a880fd 2647 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2648 in_height, out_width, out_height);
80c39712 2649
84a880fd 2650 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2651
78b687fc 2652 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2653
5b54ed3e 2654 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2655 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2656 out_height, ilace, five_taps, fieldmode,
84a880fd 2657 color_mode, rotation);
78b687fc 2658 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2659 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2660 }
2661
c35eeb2e
AT		 2662 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2663 color_mode);
80c39712 2664
84a880fd
AT		 2665 dispc_ovl_set_zorder(plane, caps, zorder);
2666 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2667 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2668
d79db853 2669 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2670
80c39712
TV		 2671 return 0;
2672}
2673
84a880fd 2674int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2675 bool replication, const struct omap_video_timings *mgr_timings,
2676 bool mem_to_mem)
84a880fd
AT		 2677{
2678 int r;
16bf20c7 2679 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2680 enum omap_channel channel;
2681
2682 channel = dispc_ovl_get_channel_out(plane);
2683
24f13a66
AB		 2684 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2685 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2686 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd
AT		 2687 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2688 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2689
16bf20c7 2690 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2691 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2692 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2693 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2694 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2695
2696 return r;
2697}
348be69d 2698EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2699
749feffa 2700int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2701 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2702{
2703 int r;
9e4a0fc7 2704 u32 l;
749feffa
AT		 2705 enum omap_plane plane = OMAP_DSS_WB;
2706 const int pos_x = 0, pos_y = 0;
2707 const u8 zorder = 0, global_alpha = 0;
2708 const bool replication = false;
9e4a0fc7 2709 bool truncation;
749feffa
AT		 2710 int in_width = mgr_timings->x_res;
2711 int in_height = mgr_timings->y_res;
2712 enum omap_overlay_caps caps =
2713 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2714
2715 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2716 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2717 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2718 wi->mirror);
2719
2720 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2721 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2722 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2723 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2724 replication, mgr_timings, mem_to_mem);
2725
2726 switch (wi->color_mode) {
2727 case OMAP_DSS_COLOR_RGB16:
2728 case OMAP_DSS_COLOR_RGB24P:
2729 case OMAP_DSS_COLOR_ARGB16:
2730 case OMAP_DSS_COLOR_RGBA16:
2731 case OMAP_DSS_COLOR_RGB12U:
2732 case OMAP_DSS_COLOR_ARGB16_1555:
2733 case OMAP_DSS_COLOR_XRGB16_1555:
2734 case OMAP_DSS_COLOR_RGBX16:
2735 truncation = true;
2736 break;
2737 default:
2738 truncation = false;
2739 break;
2740 }
2741
2742 /* setup extra DISPC_WB_ATTRIBUTES */
2743 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2744 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2745 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2746 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2747
2748 return r;
2749}
2750
f0e5caab 2751int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2752{
e6d80f95
TV		 2753 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2754
9b372c2d 2755 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2756
2757 return 0;
80c39712 2758}
348be69d 2759EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2760
04bd8ac1
TV		 2761bool dispc_ovl_enabled(enum omap_plane plane)
2762{
2763 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2764}
348be69d 2765EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2766
f1a813d3 2767void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2768{
efa70b3b
CM		 2769 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2770 /* flush posted write */
2771 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2772}
348be69d 2773EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2774
65398511
TV		 2775bool dispc_mgr_is_enabled(enum omap_channel channel)
2776{
2777 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2778}
348be69d 2779EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2780
0b23e5b8
AT		 2781void dispc_wb_enable(bool enable)
2782{
916188a4 2783 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2784}
2785
2786bool dispc_wb_is_enabled(void)
2787{
916188a4 2788 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2789}
2790
fb2cec1f 2791static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2792{
6ced40bf
AT		 2793 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2794 return;
2795
80c39712 2796 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2797}
2798
2799void dispc_lcd_enable_signal(bool enable)
2800{
6ced40bf
AT		 2801 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2802 return;
2803
80c39712 2804 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2805}
2806
2807void dispc_pck_free_enable(bool enable)
2808{
6ced40bf
AT		 2809 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2810 return;
2811
80c39712 2812 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2813}
2814
fb2cec1f 2815static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2816{
efa70b3b 2817 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2818}
2819
2820
fb2cec1f 2821static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2822{
d21f43bc 2823 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2824}
2825
2826void dispc_set_loadmode(enum omap_dss_load_mode mode)
2827{
80c39712 2828 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2829}
2830
2831
c64dca40 2832static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2833{
8613b000 2834 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2835}
2836
c64dca40 2837static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2838 enum omap_dss_trans_key_type type,
2839 u32 trans_key)
2840{
efa70b3b 2841 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2842
8613b000 2843 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2844}
2845
c64dca40 2846static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2847{
efa70b3b 2848 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2849}
11354dd5 2850
c64dca40
TV		 2851static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2852 bool enable)
80c39712 2853{
11354dd5 2854 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2855 return;
2856
80c39712
TV		 2857 if (ch == OMAP_DSS_CHANNEL_LCD)
2858 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2859 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2860 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2861}
11354dd5 2862
c64dca40 2863void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2864 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2865{
2866 dispc_mgr_set_default_color(channel, info->default_color);
2867 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2868 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2869 dispc_mgr_enable_alpha_fixed_zorder(channel,
2870 info->partial_alpha_enabled);
2871 if (dss_has_feature(FEAT_CPR)) {
2872 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2873 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2874 }
2875}
348be69d 2876EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2877
fb2cec1f 2878static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2879{
2880 int code;
2881
2882 switch (data_lines) {
2883 case 12:
2884 code = 0;
2885 break;
2886 case 16:
2887 code = 1;
2888 break;
2889 case 18:
2890 code = 2;
2891 break;
2892 case 24:
2893 code = 3;
2894 break;
2895 default:
2896 BUG();
2897 return;
2898 }
2899
efa70b3b 2900 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2901}
2902
fb2cec1f 2903static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2904{
2905 u32 l;
569969d6 2906 int gpout0, gpout1;
80c39712
TV		 2907
2908 switch (mode) {
569969d6
AT		 2909 case DSS_IO_PAD_MODE_RESET:
2910 gpout0 = 0;
2911 gpout1 = 0;
80c39712 2912 break;
569969d6
AT		 2913 case DSS_IO_PAD_MODE_RFBI:
2914 gpout0 = 1;
80c39712
TV		 2915 gpout1 = 0;
2916 break;
569969d6
AT		 2917 case DSS_IO_PAD_MODE_BYPASS:
2918 gpout0 = 1;
80c39712
TV		 2919 gpout1 = 1;
2920 break;
80c39712
TV		 2921 default:
2922 BUG();
2923 return;
2924 }
2925
569969d6
AT		 2926 l = dispc_read_reg(DISPC_CONTROL);
2927 l = FLD_MOD(l, gpout0, 15, 15);
2928 l = FLD_MOD(l, gpout1, 16, 16);
2929 dispc_write_reg(DISPC_CONTROL, l);
2930}
2931
fb2cec1f 2932static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2933{
efa70b3b 2934 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2935}
2936
fb2cec1f
TV		 2937void dispc_mgr_set_lcd_config(enum omap_channel channel,
2938 const struct dss_lcd_mgr_config *config)
2939{
2940 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2941
2942 dispc_mgr_enable_stallmode(channel, config->stallmode);
2943 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2944
2945 dispc_mgr_set_clock_div(channel, &config->clock_info);
2946
2947 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2948
2949 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2950
2951 dispc_mgr_set_lcd_type_tft(channel);
2952}
348be69d 2953EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 2954
8f366162
AT		 2955static bool _dispc_mgr_size_ok(u16 width, u16 height)
2956{
33b89928
AT		 2957 return width <= dispc.feat->mgr_width_max &&
2958 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2959}
2960
80c39712
TV		 2961static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2962 int vsw, int vfp, int vbp)
2963{
dcbe765b
CM		 2964 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2965 hfp < 1 || hfp > dispc.feat->hp_max ||
2966 hbp < 1 || hbp > dispc.feat->hp_max ||
2967 vsw < 1 || vsw > dispc.feat->sw_max ||
2968 vfp < 0 || vfp > dispc.feat->vp_max ||
2969 vbp < 0 || vbp > dispc.feat->vp_max)
2970 return false;
80c39712
TV		 2971 return true;
2972}
2973
ca5ca69c
AT		 2974static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2975 unsigned long pclk)
2976{
2977 if (dss_mgr_is_lcd(channel))
2978 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2979 else
2980 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2981}
2982
8f366162 2983bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2984 const struct omap_video_timings *timings)
80c39712 2985{
eadd33bb
TV		 2986 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
2987 return false;
8f366162 2988
eadd33bb
TV		 2989 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
2990 return false;
ca5ca69c
AT		 2991
2992 if (dss_mgr_is_lcd(channel)) {
beb8384d 2993 /* TODO: OMAP4+ supports interlace for LCD outputs */
eadd33bb
TV		 2994 if (timings->interlace)
2995 return false;
beb8384d 2996
eadd33bb 2997 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
ca5ca69c 2998 timings->hbp, timings->vsw, timings->vfp,
eadd33bb
TV		 2999 timings->vbp))
3000 return false;
ca5ca69c 3001 }
8f366162 3002
eadd33bb 3003 return true;
80c39712
TV		 3004}
3005
26d9dd0d 3006static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3007 int hfp, int hbp, int vsw, int vfp, int vbp,
3008 enum omap_dss_signal_level vsync_level,
3009 enum omap_dss_signal_level hsync_level,
3010 enum omap_dss_signal_edge data_pclk_edge,
3011 enum omap_dss_signal_level de_level,
3012 enum omap_dss_signal_edge sync_pclk_edge)
3013
80c39712 3014{
655e2941 3015 u32 timing_h, timing_v, l;
ed351881 3016 bool onoff, rf, ipc, vs, hs, de;
80c39712 3017
dcbe765b
CM		 3018 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3019 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3020 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3021 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3022 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3023 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3024
64ba4f74
SS		 3025 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3026 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 3027
ed351881
TV		 3028 switch (vsync_level) {
3029 case OMAPDSS_SIG_ACTIVE_LOW:
3030 vs = true;
3031 break;
3032 case OMAPDSS_SIG_ACTIVE_HIGH:
3033 vs = false;
3034 break;
3035 default:
3036 BUG();
3037 }
3038
3039 switch (hsync_level) {
3040 case OMAPDSS_SIG_ACTIVE_LOW:
3041 hs = true;
3042 break;
3043 case OMAPDSS_SIG_ACTIVE_HIGH:
3044 hs = false;
3045 break;
3046 default:
3047 BUG();
3048 }
3049
3050 switch (de_level) {
3051 case OMAPDSS_SIG_ACTIVE_LOW:
3052 de = true;
3053 break;
3054 case OMAPDSS_SIG_ACTIVE_HIGH:
3055 de = false;
3056 break;
3057 default:
3058 BUG();
3059 }
3060
655e2941
AT		 3061 switch (data_pclk_edge) {
3062 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3063 ipc = false;
3064 break;
3065 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3066 ipc = true;
3067 break;
655e2941
AT		 3068 default:
3069 BUG();
3070 }
3071
7a16360d
TV		 3072 /* always use the 'rf' setting */
3073 onoff = true;
3074
655e2941 3075 switch (sync_pclk_edge) {
655e2941 3076 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
655e2941
AT		 3077 rf = false;
3078 break;
3079 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
655e2941
AT		 3080 rf = true;
3081 break;
3082 default:
3083 BUG();
cf6ac4ce 3084 }
655e2941 3085
d80e02ef
TV		 3086 l = FLD_VAL(onoff, 17, 17) |
3087 FLD_VAL(rf, 16, 16) |
ed351881 3088 FLD_VAL(de, 15, 15) |
d80e02ef 3089 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 3090 FLD_VAL(hs, 13, 13) |
3091 FLD_VAL(vs, 12, 12);
d80e02ef 3092
655e2941 3093 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 3094
3095 if (dispc.syscon_pol) {
3096 const int shifts[] = {
3097 [OMAP_DSS_CHANNEL_LCD] = 0,
3098 [OMAP_DSS_CHANNEL_LCD2] = 1,
3099 [OMAP_DSS_CHANNEL_LCD3] = 2,
3100 };
3101
3102 u32 mask, val;
3103
3104 mask = (1 << 0) | (1 << 3) | (1 << 6);
3105 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3106
3107 mask <<= 16 + shifts[channel];
3108 val <<= 16 + shifts[channel];
3109
3110 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3111 mask, val);
3112 }
80c39712
TV		 3113}
3114
3115/* change name to mode? */
c51d921a 3116void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3117 const struct omap_video_timings *timings)
80c39712
TV		 3118{
3119 unsigned xtot, ytot;
3120 unsigned long ht, vt;
2aefad49 3121 struct omap_video_timings t = *timings;
80c39712 3122
2aefad49 3123 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3124
2aefad49 3125 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3126 BUG();
c6eee968
TV		 3127 return;
3128 }
80c39712 3129
dd88b7a6 3130 if (dss_mgr_is_lcd(channel)) {
2aefad49 3131 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3132 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3133 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3134
2aefad49
AT		 3135 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3136 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3137
d8d78941
TV		 3138 ht = timings->pixelclock / xtot;
3139 vt = timings->pixelclock / xtot / ytot;
c51d921a 3140
d8d78941 3141 DSSDBG("pck %u\n", timings->pixelclock);
c51d921a 3142 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3143 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3144 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3145 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3146 t.de_level, t.sync_pclk_edge);
80c39712 3147
c51d921a 3148 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3149 } else {
23c8f88e 3150 if (t.interlace == true)
2aefad49 3151 t.y_res /= 2;
c51d921a 3152 }
8f366162 3153
2aefad49 3154 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 3155}
348be69d 3156EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3157
26d9dd0d 3158static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3159 u16 pck_div)
80c39712
TV		 3160{
3161 BUG_ON(lck_div < 1);
9eaaf207 3162 BUG_ON(pck_div < 1);
80c39712 3163
ce7fa5eb 3164 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3165 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 3166
3167 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3168 channel == OMAP_DSS_CHANNEL_LCD)
3169 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3170}
3171
26d9dd0d 3172static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3173 int *pck_div)
80c39712
TV		 3174{
3175 u32 l;
ce7fa5eb 3176 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3177 *lck_div = FLD_GET(l, 23, 16);
3178 *pck_div = FLD_GET(l, 7, 0);
3179}
3180
3181unsigned long dispc_fclk_rate(void)
3182{
2daea7af 3183 struct dss_pll *pll;
80c39712
TV		 3184 unsigned long r = 0;
3185
66534e8e 3186 switch (dss_get_dispc_clk_source()) {
89a35e51 3187 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3188 r = dss_get_dispc_clk_rate();
66534e8e 3189 break;
89a35e51 3190 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3191 pll = dss_pll_find("dsi0");
93550927
TV		 3192 if (!pll)
3193 pll = dss_pll_find("video0");
3194
2daea7af 3195 r = pll->cinfo.clkout[0];
66534e8e 3196 break;
5a8b572d 3197 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3198 pll = dss_pll_find("dsi1");
93550927
TV		 3199 if (!pll)
3200 pll = dss_pll_find("video1");
3201
2daea7af 3202 r = pll->cinfo.clkout[0];
5a8b572d 3203 break;
66534e8e
TA		 3204 default:
3205 BUG();
c6eee968 3206 return 0;
66534e8e
TA		 3207 }
3208
80c39712
TV		 3209 return r;
3210}
3211
26d9dd0d 3212unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3213{
2daea7af 3214 struct dss_pll *pll;
80c39712
TV		 3215 int lcd;
3216 unsigned long r;
3217 u32 l;
3218
c31cba8a
TV		 3219 if (dss_mgr_is_lcd(channel)) {
3220 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3221
c31cba8a 3222 lcd = FLD_GET(l, 23, 16);
80c39712 3223
c31cba8a
TV		 3224 switch (dss_get_lcd_clk_source(channel)) {
3225 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3226 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3227 break;
3228 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3229 pll = dss_pll_find("dsi0");
93550927
TV		 3230 if (!pll)
3231 pll = dss_pll_find("video0");
3232
2daea7af 3233 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3234 break;
3235 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3236 pll = dss_pll_find("dsi1");
93550927
TV		 3237 if (!pll)
3238 pll = dss_pll_find("video1");
3239
2daea7af 3240 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3241 break;
3242 default:
3243 BUG();
3244 return 0;
3245 }
80c39712 3246
c31cba8a
TV		 3247 return r / lcd;
3248 } else {
3249 return dispc_fclk_rate();
3250 }
80c39712
TV		 3251}
3252
26d9dd0d 3253unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3254{
80c39712 3255 unsigned long r;
80c39712 3256
dd88b7a6 3257 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3258 int pcd;
3259 u32 l;
80c39712 3260
c3dc6a7a 3261 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3262
c3dc6a7a 3263 pcd = FLD_GET(l, 7, 0);
80c39712 3264
c3dc6a7a
AT		 3265 r = dispc_mgr_lclk_rate(channel);
3266
3267 return r / pcd;
3268 } else {
5391e87d 3269 return dispc.tv_pclk_rate;
c3dc6a7a 3270 }
80c39712
TV		 3271}
3272
5391e87d
TV		 3273void dispc_set_tv_pclk(unsigned long pclk)
3274{
3275 dispc.tv_pclk_rate = pclk;
3276}
3277
8b53d991
CM		 3278unsigned long dispc_core_clk_rate(void)
3279{
7b3926b3 3280 return dispc.core_clk_rate;
8b53d991
CM		 3281}
3282
3e8a6ff2
AT		 3283static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3284{
251886d8
TV		 3285 enum omap_channel channel;
3286
3287 if (plane == OMAP_DSS_WB)
3288 return 0;
3289
3290 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3291
3292 return dispc_mgr_pclk_rate(channel);
3293}
3294
3295static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3296{
251886d8
TV		 3297 enum omap_channel channel;
3298
3299 if (plane == OMAP_DSS_WB)
3300 return 0;
3301
3302 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3303
c31cba8a 3304 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3305}
c31cba8a 3306
6f1891fc 3307static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3308{
3309 int lcd, pcd;
6f1891fc
CM		 3310 enum omap_dss_clk_source lcd_clk_src;
3311
3312 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3313
3314 lcd_clk_src = dss_get_lcd_clk_source(channel);
3315
3316 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3317 dss_get_generic_clk_source_name(lcd_clk_src),
3318 dss_feat_get_clk_source_name(lcd_clk_src));
3319
3320 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3321
3322 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3323 dispc_mgr_lclk_rate(channel), lcd);
3324 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3325 dispc_mgr_pclk_rate(channel), pcd);
3326}
3327
3328void dispc_dump_clocks(struct seq_file *s)
3329{
3330 int lcd;
0cf35df3 3331 u32 l;
89a35e51 3332 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3333
4fbafaf3
TV		 3334 if (dispc_runtime_get())
3335 return;
80c39712 3336
80c39712
TV		 3337 seq_printf(s, "- DISPC -\n");
3338
067a57e4
AT		 3339 seq_printf(s, "dispc fclk source = %s (%s)\n",
3340 dss_get_generic_clk_source_name(dispc_clk_src),
3341 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3342
3343 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3344
0cf35df3
MR		 3345 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3346 seq_printf(s, "- DISPC-CORE-CLK -\n");
3347 l = dispc_read_reg(DISPC_DIVISOR);
3348 lcd = FLD_GET(l, 23, 16);
3349
3350 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3351 (dispc_fclk_rate()/lcd), lcd);
3352 }
2a205f34 3353
6f1891fc 3354 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3355
6f1891fc
CM		 3356 if (dss_has_feature(FEAT_MGR_LCD2))
3357 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3358 if (dss_has_feature(FEAT_MGR_LCD3))
3359 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3360
3361 dispc_runtime_put();
80c39712
TV		 3362}
3363
e40402cf 3364static void dispc_dump_regs(struct seq_file *s)
80c39712 3365{
4dd2da15
AT		 3366 int i, j;
3367 const char *mgr_names[] = {
3368 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3369 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3370 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3371 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3372 };
3373 const char *ovl_names[] = {
3374 [OMAP_DSS_GFX] = "GFX",
3375 [OMAP_DSS_VIDEO1] = "VID1",
3376 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3377 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3378 };
3379 const char **p_names;
3380
9b372c2d 3381#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3382
4fbafaf3
TV		 3383 if (dispc_runtime_get())
3384 return;
80c39712 3385
5010be80 3386 /* DISPC common registers */
80c39712
TV		 3387 DUMPREG(DISPC_REVISION);
3388 DUMPREG(DISPC_SYSCONFIG);
3389 DUMPREG(DISPC_SYSSTATUS);
3390 DUMPREG(DISPC_IRQSTATUS);
3391 DUMPREG(DISPC_IRQENABLE);
3392 DUMPREG(DISPC_CONTROL);
3393 DUMPREG(DISPC_CONFIG);
3394 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3395 DUMPREG(DISPC_LINE_STATUS);
3396 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3397 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3398 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3399 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3400 if (dss_has_feature(FEAT_MGR_LCD2)) {
3401 DUMPREG(DISPC_CONTROL2);
3402 DUMPREG(DISPC_CONFIG2);
5010be80 3403 }
6f1891fc
CM		 3404 if (dss_has_feature(FEAT_MGR_LCD3)) {
3405 DUMPREG(DISPC_CONTROL3);
3406 DUMPREG(DISPC_CONFIG3);
3407 }
29fceeeb
TV		 3408 if (dss_has_feature(FEAT_MFLAG))
3409 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3410
3411#undef DUMPREG
3412
3413#define DISPC_REG(i, name) name(i)
4dd2da15 3414#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3415 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3416 dispc_read_reg(DISPC_REG(i, r)))
3417
4dd2da15 3418 p_names = mgr_names;
5010be80 3419
4dd2da15
AT		 3420 /* DISPC channel specific registers */
3421 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3422 DUMPREG(i, DISPC_DEFAULT_COLOR);
3423 DUMPREG(i, DISPC_TRANS_COLOR);
3424 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3425
4dd2da15
AT		 3426 if (i == OMAP_DSS_CHANNEL_DIGIT)
3427 continue;
5010be80 3428
4dd2da15
AT		 3429 DUMPREG(i, DISPC_TIMING_H);
3430 DUMPREG(i, DISPC_TIMING_V);
3431 DUMPREG(i, DISPC_POL_FREQ);
3432 DUMPREG(i, DISPC_DIVISORo);
5010be80 3433
4dd2da15
AT		 3434 DUMPREG(i, DISPC_DATA_CYCLE1);
3435 DUMPREG(i, DISPC_DATA_CYCLE2);
3436 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3437
332e9d70 3438 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3439 DUMPREG(i, DISPC_CPR_COEF_R);
3440 DUMPREG(i, DISPC_CPR_COEF_G);
3441 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3442 }
2a205f34 3443 }
80c39712 3444
4dd2da15
AT		 3445 p_names = ovl_names;
3446
3447 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3448 DUMPREG(i, DISPC_OVL_BA0);
3449 DUMPREG(i, DISPC_OVL_BA1);
3450 DUMPREG(i, DISPC_OVL_POSITION);
3451 DUMPREG(i, DISPC_OVL_SIZE);
3452 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3453 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3454 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3455 DUMPREG(i, DISPC_OVL_ROW_INC);
3456 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3457
4dd2da15
AT		 3458 if (dss_has_feature(FEAT_PRELOAD))
3459 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3460 if (dss_has_feature(FEAT_MFLAG))
3461 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3462
3463 if (i == OMAP_DSS_GFX) {
3464 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3465 DUMPREG(i, DISPC_OVL_TABLE_BA);
3466 continue;
3467 }
3468
3469 DUMPREG(i, DISPC_OVL_FIR);
3470 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3471 DUMPREG(i, DISPC_OVL_ACCU0);
3472 DUMPREG(i, DISPC_OVL_ACCU1);
3473 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3474 DUMPREG(i, DISPC_OVL_BA0_UV);
3475 DUMPREG(i, DISPC_OVL_BA1_UV);
3476 DUMPREG(i, DISPC_OVL_FIR2);
3477 DUMPREG(i, DISPC_OVL_ACCU2_0);
3478 DUMPREG(i, DISPC_OVL_ACCU2_1);
3479 }
3480 if (dss_has_feature(FEAT_ATTR2))
3481 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3482 }
5010be80
AT		 3483
3484#undef DISPC_REG
3485#undef DUMPREG
3486
3487#define DISPC_REG(plane, name, i) name(plane, i)
3488#define DUMPREG(plane, name, i) \
4dd2da15 3489 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3490 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3491 dispc_read_reg(DISPC_REG(plane, name, i)))
3492
4dd2da15 3493 /* Video pipeline coefficient registers */
332e9d70 3494
4dd2da15
AT		 3495 /* start from OMAP_DSS_VIDEO1 */
3496 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3497 for (j = 0; j < 8; j++)
3498 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3499
4dd2da15
AT		 3500 for (j = 0; j < 8; j++)
3501 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3502
4dd2da15
AT		 3503 for (j = 0; j < 5; j++)
3504 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3505
4dd2da15
AT		 3506 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3507 for (j = 0; j < 8; j++)
3508 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3509 }
3510
3511 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3512 for (j = 0; j < 8; j++)
3513 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3514
3515 for (j = 0; j < 8; j++)
3516 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3517
3518 for (j = 0; j < 8; j++)
3519 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3520 }
332e9d70 3521 }
80c39712 3522
4fbafaf3 3523 dispc_runtime_put();
5010be80
AT		 3524
3525#undef DISPC_REG
80c39712
TV		 3526#undef DUMPREG
3527}
3528
80c39712
TV		 3529/* calculate clock rates using dividers in cinfo */
3530int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3531 struct dispc_clock_info *cinfo)
3532{
80c39712
TV		 3533 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3534 return -EINVAL;
9eaaf207 3535 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3536 return -EINVAL;
80c39712 3537
80c39712
TV		 3538 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3539 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3540
80c39712
TV		 3541 return 0;
3542}
80c39712 3543
7c284e6e
TV		 3544bool dispc_div_calc(unsigned long dispc,
3545 unsigned long pck_min, unsigned long pck_max,
3546 dispc_div_calc_func func, void *data)
3547{
3548 int lckd, lckd_start, lckd_stop;
3549 int pckd, pckd_start, pckd_stop;
3550 unsigned long pck, lck;
3551 unsigned long lck_max;
3552 unsigned long pckd_hw_min, pckd_hw_max;
3553 unsigned min_fck_per_pck;
3554 unsigned long fck;
80c39712 3555
7c284e6e
TV		 3556#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3557 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3558#else
3559 min_fck_per_pck = 0;
3560#endif
80c39712 3561
7c284e6e
TV		 3562 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3563 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3564
7c284e6e 3565 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3566
7c284e6e
TV		 3567 pck_min = pck_min ? pck_min : 1;
3568 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3569
7c284e6e
TV		 3570 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3571 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3572
7c284e6e
TV		 3573 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3574 lck = dispc / lckd;
80c39712 3575
7c284e6e
TV		 3576 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3577 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3578
7c284e6e
TV		 3579 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3580 pck = lck / pckd;
80c39712 3581
7c284e6e
TV		 3582 /*
3583 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3584 * clock, which means we're configuring DISPC fclk here
3585 * also. Thus we need to use the calculated lck. For
3586 * OMAP4+ the DISPC fclk is a separate clock.
3587 */
3588 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3589 fck = dispc_core_clk_rate();
3590 else
3591 fck = lck;
3592
3593 if (fck < pck * min_fck_per_pck)
3594 continue;
3595
3596 if (func(lckd, pckd, lck, pck, data))
3597 return true;
3598 }
3599 }
3600
3601 return false;
80c39712
TV		 3602}
3603
f0d08f89 3604void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3605 const struct dispc_clock_info *cinfo)
80c39712
TV		 3606{
3607 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3608 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3609
26d9dd0d 3610 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3611}
3612
26d9dd0d 3613int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3614 struct dispc_clock_info *cinfo)
80c39712
TV		 3615{
3616 unsigned long fck;
3617
3618 fck = dispc_fclk_rate();
3619
ce7fa5eb
MR		 3620 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3621 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3622
3623 cinfo->lck = fck / cinfo->lck_div;
3624 cinfo->pck = cinfo->lck / cinfo->pck_div;
3625
3626 return 0;
3627}
3628
4e0397cf
TV		 3629u32 dispc_read_irqstatus(void)
3630{
3631 return dispc_read_reg(DISPC_IRQSTATUS);
3632}
348be69d 3633EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3634
3635void dispc_clear_irqstatus(u32 mask)
3636{
3637 dispc_write_reg(DISPC_IRQSTATUS, mask);
3638}
348be69d 3639EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3640
3641u32 dispc_read_irqenable(void)
3642{
3643 return dispc_read_reg(DISPC_IRQENABLE);
3644}
348be69d 3645EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3646
3647void dispc_write_irqenable(u32 mask)
3648{
3649 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3650
3651 /* clear the irqstatus for newly enabled irqs */
3652 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3653
3654 dispc_write_reg(DISPC_IRQENABLE, mask);
3655}
348be69d 3656EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3657
80c39712
TV		 3658void dispc_enable_sidle(void)
3659{
3660 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3661}
3662
3663void dispc_disable_sidle(void)
3664{
3665 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3666}
3667
3668static void _omap_dispc_initial_config(void)
3669{
3670 u32 l;
3671
0cf35df3
MR		 3672 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3673 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3674 l = dispc_read_reg(DISPC_DIVISOR);
3675 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3676 l = FLD_MOD(l, 1, 0, 0);
3677 l = FLD_MOD(l, 1, 23, 16);
3678 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3679
3680 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3681 }
3682
80c39712 3683 /* FUNCGATED */
6ced40bf
AT		 3684 if (dss_has_feature(FEAT_FUNCGATED))
3685 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3686
6e5264b0 3687 dispc_setup_color_conv_coef();
80c39712
TV		 3688
3689 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3690
42a6961c 3691 dispc_init_fifos();
5ed8cf5b
TV		 3692
3693 dispc_configure_burst_sizes();
54128701
AT		 3694
3695 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3696
3697 if (dispc.feat->mstandby_workaround)
3698 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
c64aa3a6
TV		 3699
3700 if (dss_has_feature(FEAT_MFLAG))
3701 dispc_init_mflag();
80c39712
TV		 3702}
3703
dcbe765b
CM		 3704static const struct dispc_features omap24xx_dispc_feats __initconst = {
3705 .sw_start = 5,
3706 .fp_start = 15,
3707 .bp_start = 27,
3708 .sw_max = 64,
3709 .vp_max = 255,
3710 .hp_max = 256,
33b89928
AT		 3711 .mgr_width_start = 10,
3712 .mgr_height_start = 26,
3713 .mgr_width_max = 2048,
3714 .mgr_height_max = 2048,
ca5ca69c 3715 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3716 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3717 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3718 .num_fifos = 3,
cffa947d 3719 .no_framedone_tv = true,
8bc65552 3720 .set_max_preload = false,
dcbe765b
CM		 3721};
3722
3723static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3724 .sw_start = 5,
3725 .fp_start = 15,
3726 .bp_start = 27,
3727 .sw_max = 64,
3728 .vp_max = 255,
3729 .hp_max = 256,
33b89928
AT		 3730 .mgr_width_start = 10,
3731 .mgr_height_start = 26,
3732 .mgr_width_max = 2048,
3733 .mgr_height_max = 2048,
ca5ca69c
AT		 3734 .max_lcd_pclk = 173000000,
3735 .max_tv_pclk = 59000000,
dcbe765b
CM		 3736 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3737 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3738 .num_fifos = 3,
cffa947d 3739 .no_framedone_tv = true,
8bc65552 3740 .set_max_preload = false,
dcbe765b
CM		 3741};
3742
3743static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3744 .sw_start = 7,
3745 .fp_start = 19,
3746 .bp_start = 31,
3747 .sw_max = 256,
3748 .vp_max = 4095,
3749 .hp_max = 4096,
33b89928
AT		 3750 .mgr_width_start = 10,
3751 .mgr_height_start = 26,
3752 .mgr_width_max = 2048,
3753 .mgr_height_max = 2048,
ca5ca69c
AT		 3754 .max_lcd_pclk = 173000000,
3755 .max_tv_pclk = 59000000,
dcbe765b
CM		 3756 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3757 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3758 .num_fifos = 3,
cffa947d 3759 .no_framedone_tv = true,
8bc65552 3760 .set_max_preload = false,
dcbe765b
CM		 3761};
3762
3763static const struct dispc_features omap44xx_dispc_feats __initconst = {
3764 .sw_start = 7,
3765 .fp_start = 19,
3766 .bp_start = 31,
3767 .sw_max = 256,
3768 .vp_max = 4095,
3769 .hp_max = 4096,
33b89928
AT		 3770 .mgr_width_start = 10,
3771 .mgr_height_start = 26,
3772 .mgr_width_max = 2048,
3773 .mgr_height_max = 2048,
ca5ca69c
AT		 3774 .max_lcd_pclk = 170000000,
3775 .max_tv_pclk = 185625000,
dcbe765b
CM		 3776 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3777 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3778 .num_fifos = 5,
66a0f9e4 3779 .gfx_fifo_workaround = true,
8bc65552 3780 .set_max_preload = true,
dcbe765b
CM		 3781};
3782
264236f8
AT		 3783static const struct dispc_features omap54xx_dispc_feats __initconst = {
3784 .sw_start = 7,
3785 .fp_start = 19,
3786 .bp_start = 31,
3787 .sw_max = 256,
3788 .vp_max = 4095,
3789 .hp_max = 4096,
3790 .mgr_width_start = 11,
3791 .mgr_height_start = 27,
3792 .mgr_width_max = 4096,
3793 .mgr_height_max = 4096,
ca5ca69c
AT		 3794 .max_lcd_pclk = 170000000,
3795 .max_tv_pclk = 186000000,
264236f8
AT		 3796 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3797 .calc_core_clk = calc_core_clk_44xx,
3798 .num_fifos = 5,
3799 .gfx_fifo_workaround = true,
d0df9a2c 3800 .mstandby_workaround = true,
8bc65552 3801 .set_max_preload = true,
264236f8
AT		 3802};
3803
84b47623 3804static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3805{
3806 const struct dispc_features *src;
3807 struct dispc_features *dst;
3808
84b47623 3809 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3810 if (!dst) {
84b47623 3811 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3812 return -ENOMEM;
3813 }
3814
b2c7d54f 3815 switch (omapdss_get_version()) {
84b47623 3816 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3817 src = &omap24xx_dispc_feats;
84b47623
TV		 3818 break;
3819
3820 case OMAPDSS_VER_OMAP34xx_ES1:
3821 src = &omap34xx_rev1_0_dispc_feats;
3822 break;
3823
3824 case OMAPDSS_VER_OMAP34xx_ES3:
3825 case OMAPDSS_VER_OMAP3630:
3826 case OMAPDSS_VER_AM35xx:
d6279d4a 3827 case OMAPDSS_VER_AM43xx:
84b47623
TV		 3828 src = &omap34xx_rev3_0_dispc_feats;
3829 break;
3830
3831 case OMAPDSS_VER_OMAP4430_ES1:
3832 case OMAPDSS_VER_OMAP4430_ES2:
3833 case OMAPDSS_VER_OMAP4:
dcbe765b 3834 src = &omap44xx_dispc_feats;
84b47623
TV		 3835 break;
3836
3837 case OMAPDSS_VER_OMAP5:
93550927 3838 case OMAPDSS_VER_DRA7xx:
264236f8 3839 src = &omap54xx_dispc_feats;
84b47623
TV		 3840 break;
3841
3842 default:
dcbe765b
CM		 3843 return -ENODEV;
3844 }
3845
3846 memcpy(dst, src, sizeof(*dst));
3847 dispc.feat = dst;
3848
3849 return 0;
3850}
3851
0925afc9
TV		 3852static irqreturn_t dispc_irq_handler(int irq, void *arg)
3853{
3854 if (!dispc.is_enabled)
3855 return IRQ_NONE;
3856
3857 return dispc.user_handler(irq, dispc.user_data);
3858}
3859
96e2e637
TV		 3860int dispc_request_irq(irq_handler_t handler, void *dev_id)
3861{
0925afc9
TV		 3862 int r;
3863
3864 if (dispc.user_handler != NULL)
3865 return -EBUSY;
3866
3867 dispc.user_handler = handler;
3868 dispc.user_data = dev_id;
3869
3870 /* ensure the dispc_irq_handler sees the values above */
3871 smp_wmb();
3872
3873 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3874 IRQF_SHARED, "OMAP DISPC", &dispc);
3875 if (r) {
3876 dispc.user_handler = NULL;
3877 dispc.user_data = NULL;
3878 }
3879
3880 return r;
96e2e637 3881}
348be69d 3882EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 3883
3884void dispc_free_irq(void *dev_id)
3885{
0925afc9
TV		 3886 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3887
3888 dispc.user_handler = NULL;
3889 dispc.user_data = NULL;
96e2e637 3890}
348be69d 3891EXPORT_SYMBOL(dispc_free_irq);
96e2e637 3892
060b6d9c 3893/* DISPC HW IP initialisation */
6e7e8f06 3894static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3895{
3896 u32 rev;
affe360d 3897 int r = 0;
ea9da36a 3898 struct resource *dispc_mem;
0006fd63 3899 struct device_node *np = pdev->dev.of_node;
ea9da36a 3900
060b6d9c
SG		 3901 dispc.pdev = pdev;
3902
d49cd155
TV		 3903 spin_lock_init(&dispc.control_lock);
3904
84b47623 3905 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 3906 if (r)
3907 return r;
3908
ea9da36a
SG		 3909 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3910 if (!dispc_mem) {
3911 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3912 return -EINVAL;
ea9da36a 3913 }
cd3b3449 3914
6e2a14d2
JL		 3915 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3916 resource_size(dispc_mem));
060b6d9c
SG		 3917 if (!dispc.base) {
3918 DSSERR("can't ioremap DISPC\n");
cd3b3449 3919 return -ENOMEM;
affe360d 3920 }
cd3b3449 3921
affe360d 3922 dispc.irq = platform_get_irq(dispc.pdev, 0);
3923 if (dispc.irq < 0) {
3924 DSSERR("platform_get_irq failed\n");
cd3b3449 3925 return -ENODEV;
affe360d 3926 }
3927
0006fd63
TV		 3928 if (np && of_property_read_bool(np, "syscon-pol")) {
3929 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3930 if (IS_ERR(dispc.syscon_pol)) {
3931 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3932 return PTR_ERR(dispc.syscon_pol);
3933 }
3934
3935 if (of_property_read_u32_index(np, "syscon-pol", 1,
3936 &dispc.syscon_pol_offset)) {
3937 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3938 return -EINVAL;
3939 }
3940 }
3941
4fbafaf3
TV		 3942 pm_runtime_enable(&pdev->dev);
3943
3944 r = dispc_runtime_get();
3945 if (r)
3946 goto err_runtime_get;
060b6d9c
SG		 3947
3948 _omap_dispc_initial_config();
3949
060b6d9c 3950 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3951 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3952 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3953
4fbafaf3 3954 dispc_runtime_put();
060b6d9c 3955
04b1fc02
TV		 3956 dss_init_overlay_managers();
3957
e40402cf
TV		 3958 dss_debugfs_create_file("dispc", dispc_dump_regs);
3959
060b6d9c 3960 return 0;
4fbafaf3
TV		 3961
3962err_runtime_get:
3963 pm_runtime_disable(&pdev->dev);
affe360d 3964 return r;
060b6d9c
SG		 3965}
3966
6e7e8f06 3967static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3968{
4fbafaf3
TV		 3969 pm_runtime_disable(&pdev->dev);
3970
04b1fc02
TV		 3971 dss_uninit_overlay_managers();
3972
060b6d9c
SG		 3973 return 0;
3974}
3975
4fbafaf3
TV		 3976static int dispc_runtime_suspend(struct device *dev)
3977{
0925afc9
TV		 3978 dispc.is_enabled = false;
3979 /* ensure the dispc_irq_handler sees the is_enabled value */
3980 smp_wmb();
3981 /* wait for current handler to finish before turning the DISPC off */
3982 synchronize_irq(dispc.irq);
3983
4fbafaf3 3984 dispc_save_context();
4fbafaf3
TV		 3985
3986 return 0;
3987}
3988
3989static int dispc_runtime_resume(struct device *dev)
3990{
9229b516
TV		 3991 /*
3992 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3993 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3994 * _omap_dispc_initial_config(). We can thus use it to detect if
3995 * we have lost register context.
3996 */
0925afc9
TV		 3997 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
3998 _omap_dispc_initial_config();
9229b516 3999
0925afc9
TV		 4000 dispc_restore_context();
4001 }
be07dcd7 4002
0925afc9
TV		 4003 dispc.is_enabled = true;
4004 /* ensure the dispc_irq_handler sees the is_enabled value */
4005 smp_wmb();
4fbafaf3
TV		 4006
4007 return 0;
4008}
4009
4010static const struct dev_pm_ops dispc_pm_ops = {
4011 .runtime_suspend = dispc_runtime_suspend,
4012 .runtime_resume = dispc_runtime_resume,
4013};
4014
d7977f88
TV		 4015static const struct of_device_id dispc_of_match[] = {
4016 { .compatible = "ti,omap2-dispc", },
4017 { .compatible = "ti,omap3-dispc", },
4018 { .compatible = "ti,omap4-dispc", },
2e7e6b68 4019 { .compatible = "ti,omap5-dispc", },
93550927 4020 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 4021 {},
4022};
4023
060b6d9c 4024static struct platform_driver omap_dispchw_driver = {
6e7e8f06 4025 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 4026 .driver = {
4027 .name = "omapdss_dispc",
4fbafaf3 4028 .pm = &dispc_pm_ops,
d7977f88 4029 .of_match_table = dispc_of_match,
422ccbd5 4030 .suppress_bind_attrs = true,
060b6d9c
SG		 4031 },
4032};
4033
6e7e8f06 4034int __init dispc_init_platform_driver(void)
060b6d9c 4035{
11436e1d 4036 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 4037}
4038
6e7e8f06 4039void __exit dispc_uninit_platform_driver(void)
060b6d9c 4040{
04c742c3 4041 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4042}
Linux kernel - Deliverables
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