Commit | Line | Data |
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80c39712 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dispc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DISPC" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/vmalloc.h> | |
a8a35931 | 28 | #include <linux/export.h> |
80c39712 TV |
29 | #include <linux/clk.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/workqueue.h> | |
ab83b14c | 35 | #include <linux/hardirq.h> |
24e6289c | 36 | #include <linux/platform_device.h> |
4fbafaf3 | 37 | #include <linux/pm_runtime.h> |
33366d0e | 38 | #include <linux/sizes.h> |
0006fd63 TV |
39 | #include <linux/mfd/syscon.h> |
40 | #include <linux/regmap.h> | |
41 | #include <linux/of.h> | |
736e60dd | 42 | #include <linux/component.h> |
80c39712 | 43 | |
a0b38cc4 | 44 | #include <video/omapdss.h> |
80c39712 TV |
45 | |
46 | #include "dss.h" | |
a0acb557 | 47 | #include "dss_features.h" |
9b372c2d | 48 | #include "dispc.h" |
80c39712 TV |
49 | |
50 | /* DISPC */ | |
8613b000 | 51 | #define DISPC_SZ_REGS SZ_4K |
80c39712 | 52 | |
5ed8cf5b TV |
53 | enum omap_burst_size { |
54 | BURST_SIZE_X2 = 0, | |
55 | BURST_SIZE_X4 = 1, | |
56 | BURST_SIZE_X8 = 2, | |
57 | }; | |
58 | ||
80c39712 TV |
59 | #define REG_GET(idx, start, end) \ |
60 | FLD_GET(dispc_read_reg(idx), start, end) | |
61 | ||
62 | #define REG_FLD_MOD(idx, val, start, end) \ | |
63 | dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) | |
64 | ||
dcbe765b CM |
65 | struct dispc_features { |
66 | u8 sw_start; | |
67 | u8 fp_start; | |
68 | u8 bp_start; | |
69 | u16 sw_max; | |
70 | u16 vp_max; | |
71 | u16 hp_max; | |
33b89928 AT |
72 | u8 mgr_width_start; |
73 | u8 mgr_height_start; | |
74 | u16 mgr_width_max; | |
75 | u16 mgr_height_max; | |
ca5ca69c AT |
76 | unsigned long max_lcd_pclk; |
77 | unsigned long max_tv_pclk; | |
0c6921de | 78 | int (*calc_scaling) (unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
79 | const struct omap_video_timings *mgr_timings, |
80 | u16 width, u16 height, u16 out_width, u16 out_height, | |
81 | enum omap_color_mode color_mode, bool *five_taps, | |
82 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 83 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem); |
8702ee50 | 84 | unsigned long (*calc_core_clk) (unsigned long pclk, |
8ba85306 AT |
85 | u16 width, u16 height, u16 out_width, u16 out_height, |
86 | bool mem_to_mem); | |
42a6961c | 87 | u8 num_fifos; |
66a0f9e4 TV |
88 | |
89 | /* swap GFX & WB fifos */ | |
90 | bool gfx_fifo_workaround:1; | |
cffa947d TV |
91 | |
92 | /* no DISPC_IRQ_FRAMEDONETV on this SoC */ | |
93 | bool no_framedone_tv:1; | |
d0df9a2c AT |
94 | |
95 | /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ | |
96 | bool mstandby_workaround:1; | |
8bc65552 AT |
97 | |
98 | bool set_max_preload:1; | |
f2aee319 TV |
99 | |
100 | /* PIXEL_INC is not added to the last pixel of a line */ | |
101 | bool last_pixel_inc_missing:1; | |
dcbe765b CM |
102 | }; |
103 | ||
42a6961c TV |
104 | #define DISPC_MAX_NR_FIFOS 5 |
105 | ||
80c39712 | 106 | static struct { |
060b6d9c | 107 | struct platform_device *pdev; |
80c39712 | 108 | void __iomem *base; |
4fbafaf3 | 109 | |
affe360d | 110 | int irq; |
0925afc9 TV |
111 | irq_handler_t user_handler; |
112 | void *user_data; | |
80c39712 | 113 | |
7b3926b3 | 114 | unsigned long core_clk_rate; |
5391e87d | 115 | unsigned long tv_pclk_rate; |
7b3926b3 | 116 | |
42a6961c TV |
117 | u32 fifo_size[DISPC_MAX_NR_FIFOS]; |
118 | /* maps which plane is using a fifo. fifo-id -> plane-id */ | |
119 | int fifo_assignment[DISPC_MAX_NR_FIFOS]; | |
80c39712 | 120 | |
49ea86f3 | 121 | bool ctx_valid; |
80c39712 | 122 | u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; |
dfc0fd8d | 123 | |
dcbe765b | 124 | const struct dispc_features *feat; |
0925afc9 TV |
125 | |
126 | bool is_enabled; | |
0006fd63 TV |
127 | |
128 | struct regmap *syscon_pol; | |
129 | u32 syscon_pol_offset; | |
d49cd155 TV |
130 | |
131 | /* DISPC_CONTROL & DISPC_CONFIG lock*/ | |
132 | spinlock_t control_lock; | |
80c39712 TV |
133 | } dispc; |
134 | ||
0d66cbb5 AJ |
135 | enum omap_color_component { |
136 | /* used for all color formats for OMAP3 and earlier | |
137 | * and for RGB and Y color component on OMAP4 | |
138 | */ | |
139 | DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, | |
140 | /* used for UV component for | |
141 | * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 | |
142 | * color formats on OMAP4 | |
143 | */ | |
144 | DISPC_COLOR_COMPONENT_UV = 1 << 1, | |
145 | }; | |
146 | ||
efa70b3b CM |
147 | enum mgr_reg_fields { |
148 | DISPC_MGR_FLD_ENABLE, | |
149 | DISPC_MGR_FLD_STNTFT, | |
150 | DISPC_MGR_FLD_GO, | |
151 | DISPC_MGR_FLD_TFTDATALINES, | |
152 | DISPC_MGR_FLD_STALLMODE, | |
153 | DISPC_MGR_FLD_TCKENABLE, | |
154 | DISPC_MGR_FLD_TCKSELECTION, | |
155 | DISPC_MGR_FLD_CPR, | |
156 | DISPC_MGR_FLD_FIFOHANDCHECK, | |
157 | /* used to maintain a count of the above fields */ | |
158 | DISPC_MGR_FLD_NUM, | |
159 | }; | |
160 | ||
5c348ba9 JS |
161 | struct dispc_reg_field { |
162 | u16 reg; | |
163 | u8 high; | |
164 | u8 low; | |
165 | }; | |
166 | ||
efa70b3b CM |
167 | static const struct { |
168 | const char *name; | |
169 | u32 vsync_irq; | |
170 | u32 framedone_irq; | |
171 | u32 sync_lost_irq; | |
5c348ba9 | 172 | struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; |
efa70b3b CM |
173 | } mgr_desc[] = { |
174 | [OMAP_DSS_CHANNEL_LCD] = { | |
175 | .name = "LCD", | |
176 | .vsync_irq = DISPC_IRQ_VSYNC, | |
177 | .framedone_irq = DISPC_IRQ_FRAMEDONE, | |
178 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST, | |
179 | .reg_desc = { | |
180 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, | |
181 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, | |
182 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, | |
183 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, | |
184 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, | |
185 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, | |
186 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, | |
187 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, | |
188 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
189 | }, | |
190 | }, | |
191 | [OMAP_DSS_CHANNEL_DIGIT] = { | |
192 | .name = "DIGIT", | |
193 | .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, | |
cffa947d | 194 | .framedone_irq = DISPC_IRQ_FRAMEDONETV, |
efa70b3b CM |
195 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, |
196 | .reg_desc = { | |
197 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, | |
198 | [DISPC_MGR_FLD_STNTFT] = { }, | |
199 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, | |
200 | [DISPC_MGR_FLD_TFTDATALINES] = { }, | |
201 | [DISPC_MGR_FLD_STALLMODE] = { }, | |
202 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, | |
203 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, | |
204 | [DISPC_MGR_FLD_CPR] = { }, | |
205 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
206 | }, | |
207 | }, | |
208 | [OMAP_DSS_CHANNEL_LCD2] = { | |
209 | .name = "LCD2", | |
210 | .vsync_irq = DISPC_IRQ_VSYNC2, | |
211 | .framedone_irq = DISPC_IRQ_FRAMEDONE2, | |
212 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, | |
213 | .reg_desc = { | |
214 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, | |
215 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, | |
216 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, | |
217 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, | |
218 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, | |
219 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, | |
220 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, | |
221 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, | |
222 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, | |
223 | }, | |
224 | }, | |
e86d456a CM |
225 | [OMAP_DSS_CHANNEL_LCD3] = { |
226 | .name = "LCD3", | |
227 | .vsync_irq = DISPC_IRQ_VSYNC3, | |
228 | .framedone_irq = DISPC_IRQ_FRAMEDONE3, | |
229 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, | |
230 | .reg_desc = { | |
231 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, | |
232 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, | |
233 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, | |
234 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, | |
235 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, | |
236 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, | |
237 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, | |
238 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, | |
239 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, | |
240 | }, | |
241 | }, | |
efa70b3b CM |
242 | }; |
243 | ||
6e5264b0 AT |
244 | struct color_conv_coef { |
245 | int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; | |
246 | int full_range; | |
247 | }; | |
248 | ||
3e8a6ff2 AT |
249 | static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); |
250 | static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); | |
80c39712 | 251 | |
55978cc2 | 252 | static inline void dispc_write_reg(const u16 idx, u32 val) |
80c39712 | 253 | { |
55978cc2 | 254 | __raw_writel(val, dispc.base + idx); |
80c39712 TV |
255 | } |
256 | ||
55978cc2 | 257 | static inline u32 dispc_read_reg(const u16 idx) |
80c39712 | 258 | { |
55978cc2 | 259 | return __raw_readl(dispc.base + idx); |
80c39712 TV |
260 | } |
261 | ||
efa70b3b CM |
262 | static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) |
263 | { | |
5c348ba9 | 264 | const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; |
efa70b3b CM |
265 | return REG_GET(rfld.reg, rfld.high, rfld.low); |
266 | } | |
267 | ||
268 | static void mgr_fld_write(enum omap_channel channel, | |
269 | enum mgr_reg_fields regfld, int val) { | |
5c348ba9 | 270 | const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; |
d49cd155 TV |
271 | const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; |
272 | unsigned long flags; | |
273 | ||
274 | if (need_lock) | |
275 | spin_lock_irqsave(&dispc.control_lock, flags); | |
276 | ||
efa70b3b | 277 | REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); |
d49cd155 TV |
278 | |
279 | if (need_lock) | |
280 | spin_unlock_irqrestore(&dispc.control_lock, flags); | |
efa70b3b CM |
281 | } |
282 | ||
80c39712 | 283 | #define SR(reg) \ |
55978cc2 | 284 | dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) |
80c39712 | 285 | #define RR(reg) \ |
55978cc2 | 286 | dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) |
80c39712 | 287 | |
4fbafaf3 | 288 | static void dispc_save_context(void) |
80c39712 | 289 | { |
c6104b8e | 290 | int i, j; |
80c39712 | 291 | |
4fbafaf3 TV |
292 | DSSDBG("dispc_save_context\n"); |
293 | ||
80c39712 TV |
294 | SR(IRQENABLE); |
295 | SR(CONTROL); | |
296 | SR(CONFIG); | |
80c39712 | 297 | SR(LINE_NUMBER); |
11354dd5 AT |
298 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
299 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 300 | SR(GLOBAL_ALPHA); |
2a205f34 SS |
301 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
302 | SR(CONTROL2); | |
2a205f34 SS |
303 | SR(CONFIG2); |
304 | } | |
e86d456a CM |
305 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
306 | SR(CONTROL3); | |
307 | SR(CONFIG3); | |
308 | } | |
80c39712 | 309 | |
c6104b8e AT |
310 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
311 | SR(DEFAULT_COLOR(i)); | |
312 | SR(TRANS_COLOR(i)); | |
313 | SR(SIZE_MGR(i)); | |
314 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
315 | continue; | |
316 | SR(TIMING_H(i)); | |
317 | SR(TIMING_V(i)); | |
318 | SR(POL_FREQ(i)); | |
319 | SR(DIVISORo(i)); | |
320 | ||
321 | SR(DATA_CYCLE1(i)); | |
322 | SR(DATA_CYCLE2(i)); | |
323 | SR(DATA_CYCLE3(i)); | |
324 | ||
332e9d70 | 325 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
326 | SR(CPR_COEF_R(i)); |
327 | SR(CPR_COEF_G(i)); | |
328 | SR(CPR_COEF_B(i)); | |
332e9d70 | 329 | } |
2a205f34 | 330 | } |
80c39712 | 331 | |
c6104b8e AT |
332 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
333 | SR(OVL_BA0(i)); | |
334 | SR(OVL_BA1(i)); | |
335 | SR(OVL_POSITION(i)); | |
336 | SR(OVL_SIZE(i)); | |
337 | SR(OVL_ATTRIBUTES(i)); | |
338 | SR(OVL_FIFO_THRESHOLD(i)); | |
339 | SR(OVL_ROW_INC(i)); | |
340 | SR(OVL_PIXEL_INC(i)); | |
341 | if (dss_has_feature(FEAT_PRELOAD)) | |
342 | SR(OVL_PRELOAD(i)); | |
343 | if (i == OMAP_DSS_GFX) { | |
344 | SR(OVL_WINDOW_SKIP(i)); | |
345 | SR(OVL_TABLE_BA(i)); | |
346 | continue; | |
347 | } | |
348 | SR(OVL_FIR(i)); | |
349 | SR(OVL_PICTURE_SIZE(i)); | |
350 | SR(OVL_ACCU0(i)); | |
351 | SR(OVL_ACCU1(i)); | |
9b372c2d | 352 | |
c6104b8e AT |
353 | for (j = 0; j < 8; j++) |
354 | SR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 355 | |
c6104b8e AT |
356 | for (j = 0; j < 8; j++) |
357 | SR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 358 | |
c6104b8e AT |
359 | for (j = 0; j < 5; j++) |
360 | SR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 361 | |
c6104b8e AT |
362 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
363 | for (j = 0; j < 8; j++) | |
364 | SR(OVL_FIR_COEF_V(i, j)); | |
365 | } | |
9b372c2d | 366 | |
c6104b8e AT |
367 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
368 | SR(OVL_BA0_UV(i)); | |
369 | SR(OVL_BA1_UV(i)); | |
370 | SR(OVL_FIR2(i)); | |
371 | SR(OVL_ACCU2_0(i)); | |
372 | SR(OVL_ACCU2_1(i)); | |
ab5ca071 | 373 | |
c6104b8e AT |
374 | for (j = 0; j < 8; j++) |
375 | SR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 376 | |
c6104b8e AT |
377 | for (j = 0; j < 8; j++) |
378 | SR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 379 | |
c6104b8e AT |
380 | for (j = 0; j < 8; j++) |
381 | SR(OVL_FIR_COEF_V2(i, j)); | |
382 | } | |
383 | if (dss_has_feature(FEAT_ATTR2)) | |
384 | SR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 385 | } |
0cf35df3 MR |
386 | |
387 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
388 | SR(DIVISOR); | |
49ea86f3 | 389 | |
49ea86f3 TV |
390 | dispc.ctx_valid = true; |
391 | ||
9229b516 | 392 | DSSDBG("context saved\n"); |
80c39712 TV |
393 | } |
394 | ||
4fbafaf3 | 395 | static void dispc_restore_context(void) |
80c39712 | 396 | { |
9229b516 | 397 | int i, j; |
4fbafaf3 TV |
398 | |
399 | DSSDBG("dispc_restore_context\n"); | |
400 | ||
49ea86f3 TV |
401 | if (!dispc.ctx_valid) |
402 | return; | |
403 | ||
75c7d59d | 404 | /*RR(IRQENABLE);*/ |
80c39712 TV |
405 | /*RR(CONTROL);*/ |
406 | RR(CONFIG); | |
80c39712 | 407 | RR(LINE_NUMBER); |
11354dd5 AT |
408 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
409 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 410 | RR(GLOBAL_ALPHA); |
c6104b8e | 411 | if (dss_has_feature(FEAT_MGR_LCD2)) |
2a205f34 | 412 | RR(CONFIG2); |
e86d456a CM |
413 | if (dss_has_feature(FEAT_MGR_LCD3)) |
414 | RR(CONFIG3); | |
80c39712 | 415 | |
c6104b8e AT |
416 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
417 | RR(DEFAULT_COLOR(i)); | |
418 | RR(TRANS_COLOR(i)); | |
419 | RR(SIZE_MGR(i)); | |
420 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
421 | continue; | |
422 | RR(TIMING_H(i)); | |
423 | RR(TIMING_V(i)); | |
424 | RR(POL_FREQ(i)); | |
425 | RR(DIVISORo(i)); | |
426 | ||
427 | RR(DATA_CYCLE1(i)); | |
428 | RR(DATA_CYCLE2(i)); | |
429 | RR(DATA_CYCLE3(i)); | |
2a205f34 | 430 | |
332e9d70 | 431 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
432 | RR(CPR_COEF_R(i)); |
433 | RR(CPR_COEF_G(i)); | |
434 | RR(CPR_COEF_B(i)); | |
332e9d70 | 435 | } |
2a205f34 | 436 | } |
80c39712 | 437 | |
c6104b8e AT |
438 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
439 | RR(OVL_BA0(i)); | |
440 | RR(OVL_BA1(i)); | |
441 | RR(OVL_POSITION(i)); | |
442 | RR(OVL_SIZE(i)); | |
443 | RR(OVL_ATTRIBUTES(i)); | |
444 | RR(OVL_FIFO_THRESHOLD(i)); | |
445 | RR(OVL_ROW_INC(i)); | |
446 | RR(OVL_PIXEL_INC(i)); | |
447 | if (dss_has_feature(FEAT_PRELOAD)) | |
448 | RR(OVL_PRELOAD(i)); | |
449 | if (i == OMAP_DSS_GFX) { | |
450 | RR(OVL_WINDOW_SKIP(i)); | |
451 | RR(OVL_TABLE_BA(i)); | |
452 | continue; | |
453 | } | |
454 | RR(OVL_FIR(i)); | |
455 | RR(OVL_PICTURE_SIZE(i)); | |
456 | RR(OVL_ACCU0(i)); | |
457 | RR(OVL_ACCU1(i)); | |
9b372c2d | 458 | |
c6104b8e AT |
459 | for (j = 0; j < 8; j++) |
460 | RR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 461 | |
c6104b8e AT |
462 | for (j = 0; j < 8; j++) |
463 | RR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 464 | |
c6104b8e AT |
465 | for (j = 0; j < 5; j++) |
466 | RR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 467 | |
c6104b8e AT |
468 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
469 | for (j = 0; j < 8; j++) | |
470 | RR(OVL_FIR_COEF_V(i, j)); | |
471 | } | |
9b372c2d | 472 | |
c6104b8e AT |
473 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
474 | RR(OVL_BA0_UV(i)); | |
475 | RR(OVL_BA1_UV(i)); | |
476 | RR(OVL_FIR2(i)); | |
477 | RR(OVL_ACCU2_0(i)); | |
478 | RR(OVL_ACCU2_1(i)); | |
ab5ca071 | 479 | |
c6104b8e AT |
480 | for (j = 0; j < 8; j++) |
481 | RR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 482 | |
c6104b8e AT |
483 | for (j = 0; j < 8; j++) |
484 | RR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 485 | |
c6104b8e AT |
486 | for (j = 0; j < 8; j++) |
487 | RR(OVL_FIR_COEF_V2(i, j)); | |
488 | } | |
489 | if (dss_has_feature(FEAT_ATTR2)) | |
490 | RR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 491 | } |
80c39712 | 492 | |
0cf35df3 MR |
493 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) |
494 | RR(DIVISOR); | |
495 | ||
80c39712 TV |
496 | /* enable last, because LCD & DIGIT enable are here */ |
497 | RR(CONTROL); | |
2a205f34 SS |
498 | if (dss_has_feature(FEAT_MGR_LCD2)) |
499 | RR(CONTROL2); | |
e86d456a CM |
500 | if (dss_has_feature(FEAT_MGR_LCD3)) |
501 | RR(CONTROL3); | |
75c7d59d | 502 | /* clear spurious SYNC_LOST_DIGIT interrupts */ |
4e0397cf | 503 | dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); |
75c7d59d VS |
504 | |
505 | /* | |
506 | * enable last so IRQs won't trigger before | |
507 | * the context is fully restored | |
508 | */ | |
509 | RR(IRQENABLE); | |
49ea86f3 TV |
510 | |
511 | DSSDBG("context restored\n"); | |
80c39712 TV |
512 | } |
513 | ||
514 | #undef SR | |
515 | #undef RR | |
516 | ||
4fbafaf3 TV |
517 | int dispc_runtime_get(void) |
518 | { | |
519 | int r; | |
520 | ||
521 | DSSDBG("dispc_runtime_get\n"); | |
522 | ||
523 | r = pm_runtime_get_sync(&dispc.pdev->dev); | |
524 | WARN_ON(r < 0); | |
525 | return r < 0 ? r : 0; | |
526 | } | |
348be69d | 527 | EXPORT_SYMBOL(dispc_runtime_get); |
4fbafaf3 TV |
528 | |
529 | void dispc_runtime_put(void) | |
530 | { | |
531 | int r; | |
532 | ||
533 | DSSDBG("dispc_runtime_put\n"); | |
534 | ||
0eaf9f52 | 535 | r = pm_runtime_put_sync(&dispc.pdev->dev); |
5be3aebd | 536 | WARN_ON(r < 0 && r != -ENOSYS); |
80c39712 | 537 | } |
348be69d | 538 | EXPORT_SYMBOL(dispc_runtime_put); |
80c39712 | 539 | |
3dcec4d6 TV |
540 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) |
541 | { | |
efa70b3b | 542 | return mgr_desc[channel].vsync_irq; |
3dcec4d6 | 543 | } |
348be69d | 544 | EXPORT_SYMBOL(dispc_mgr_get_vsync_irq); |
3dcec4d6 | 545 | |
7d1365c9 TV |
546 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) |
547 | { | |
cffa947d TV |
548 | if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) |
549 | return 0; | |
550 | ||
efa70b3b | 551 | return mgr_desc[channel].framedone_irq; |
7d1365c9 | 552 | } |
348be69d | 553 | EXPORT_SYMBOL(dispc_mgr_get_framedone_irq); |
7d1365c9 | 554 | |
cb699200 TV |
555 | u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) |
556 | { | |
557 | return mgr_desc[channel].sync_lost_irq; | |
558 | } | |
348be69d | 559 | EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq); |
cb699200 | 560 | |
0b23e5b8 AT |
561 | u32 dispc_wb_get_framedone_irq(void) |
562 | { | |
563 | return DISPC_IRQ_FRAMEDONEWB; | |
564 | } | |
565 | ||
26d9dd0d | 566 | bool dispc_mgr_go_busy(enum omap_channel channel) |
80c39712 | 567 | { |
efa70b3b | 568 | return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; |
80c39712 | 569 | } |
348be69d | 570 | EXPORT_SYMBOL(dispc_mgr_go_busy); |
80c39712 | 571 | |
26d9dd0d | 572 | void dispc_mgr_go(enum omap_channel channel) |
80c39712 | 573 | { |
3c91ee8c TV |
574 | WARN_ON(dispc_mgr_is_enabled(channel) == false); |
575 | WARN_ON(dispc_mgr_go_busy(channel)); | |
80c39712 | 576 | |
efa70b3b | 577 | DSSDBG("GO %s\n", mgr_desc[channel].name); |
80c39712 | 578 | |
efa70b3b | 579 | mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); |
80c39712 | 580 | } |
348be69d | 581 | EXPORT_SYMBOL(dispc_mgr_go); |
80c39712 | 582 | |
0b23e5b8 AT |
583 | bool dispc_wb_go_busy(void) |
584 | { | |
585 | return REG_GET(DISPC_CONTROL2, 6, 6) == 1; | |
586 | } | |
587 | ||
588 | void dispc_wb_go(void) | |
589 | { | |
590 | enum omap_plane plane = OMAP_DSS_WB; | |
591 | bool enable, go; | |
592 | ||
593 | enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; | |
594 | ||
595 | if (!enable) | |
596 | return; | |
597 | ||
598 | go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; | |
599 | if (go) { | |
600 | DSSERR("GO bit not down for WB\n"); | |
601 | return; | |
602 | } | |
603 | ||
604 | REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); | |
605 | } | |
606 | ||
f0e5caab | 607 | static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 608 | { |
9b372c2d | 609 | dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); |
80c39712 TV |
610 | } |
611 | ||
f0e5caab | 612 | static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 613 | { |
9b372c2d | 614 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); |
80c39712 TV |
615 | } |
616 | ||
f0e5caab | 617 | static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 618 | { |
9b372c2d | 619 | dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); |
80c39712 TV |
620 | } |
621 | ||
f0e5caab | 622 | static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
623 | { |
624 | BUG_ON(plane == OMAP_DSS_GFX); | |
625 | ||
626 | dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); | |
627 | } | |
628 | ||
f0e5caab TV |
629 | static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, |
630 | u32 value) | |
ab5ca071 AJ |
631 | { |
632 | BUG_ON(plane == OMAP_DSS_GFX); | |
633 | ||
634 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); | |
635 | } | |
636 | ||
f0e5caab | 637 | static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
638 | { |
639 | BUG_ON(plane == OMAP_DSS_GFX); | |
640 | ||
641 | dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); | |
642 | } | |
643 | ||
debd9074 CM |
644 | static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, |
645 | int fir_vinc, int five_taps, | |
646 | enum omap_color_component color_comp) | |
80c39712 | 647 | { |
debd9074 | 648 | const struct dispc_coef *h_coef, *v_coef; |
80c39712 TV |
649 | int i; |
650 | ||
debd9074 CM |
651 | h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); |
652 | v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); | |
80c39712 TV |
653 | |
654 | for (i = 0; i < 8; i++) { | |
655 | u32 h, hv; | |
656 | ||
debd9074 CM |
657 | h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) |
658 | | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) | |
659 | | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) | |
660 | | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); | |
661 | hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) | |
662 | | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) | |
663 | | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) | |
664 | | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); | |
80c39712 | 665 | |
0d66cbb5 | 666 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
f0e5caab TV |
667 | dispc_ovl_write_firh_reg(plane, i, h); |
668 | dispc_ovl_write_firhv_reg(plane, i, hv); | |
0d66cbb5 | 669 | } else { |
f0e5caab TV |
670 | dispc_ovl_write_firh2_reg(plane, i, h); |
671 | dispc_ovl_write_firhv2_reg(plane, i, hv); | |
0d66cbb5 AJ |
672 | } |
673 | ||
80c39712 TV |
674 | } |
675 | ||
66be8f6c GI |
676 | if (five_taps) { |
677 | for (i = 0; i < 8; i++) { | |
678 | u32 v; | |
debd9074 CM |
679 | v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) |
680 | | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); | |
0d66cbb5 | 681 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) |
f0e5caab | 682 | dispc_ovl_write_firv_reg(plane, i, v); |
0d66cbb5 | 683 | else |
f0e5caab | 684 | dispc_ovl_write_firv2_reg(plane, i, v); |
66be8f6c | 685 | } |
80c39712 TV |
686 | } |
687 | } | |
688 | ||
80c39712 | 689 | |
6e5264b0 AT |
690 | static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, |
691 | const struct color_conv_coef *ct) | |
692 | { | |
80c39712 TV |
693 | #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) |
694 | ||
6e5264b0 AT |
695 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); |
696 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); | |
697 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); | |
698 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); | |
699 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); | |
80c39712 | 700 | |
6e5264b0 | 701 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); |
80c39712 TV |
702 | |
703 | #undef CVAL | |
80c39712 TV |
704 | } |
705 | ||
6e5264b0 AT |
706 | static void dispc_setup_color_conv_coef(void) |
707 | { | |
708 | int i; | |
709 | int num_ovl = dss_feat_get_num_ovls(); | |
710 | int num_wb = dss_feat_get_num_wbs(); | |
711 | const struct color_conv_coef ctbl_bt601_5_ovl = { | |
712 | 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, | |
713 | }; | |
714 | const struct color_conv_coef ctbl_bt601_5_wb = { | |
715 | 66, 112, -38, 129, -94, -74, 25, -18, 112, 0, | |
716 | }; | |
717 | ||
718 | for (i = 1; i < num_ovl; i++) | |
719 | dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); | |
720 | ||
721 | for (; i < num_wb; i++) | |
722 | dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb); | |
723 | } | |
80c39712 | 724 | |
f0e5caab | 725 | static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) |
80c39712 | 726 | { |
9b372c2d | 727 | dispc_write_reg(DISPC_OVL_BA0(plane), paddr); |
80c39712 TV |
728 | } |
729 | ||
f0e5caab | 730 | static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) |
80c39712 | 731 | { |
9b372c2d | 732 | dispc_write_reg(DISPC_OVL_BA1(plane), paddr); |
80c39712 TV |
733 | } |
734 | ||
f0e5caab | 735 | static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
736 | { |
737 | dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); | |
738 | } | |
739 | ||
f0e5caab | 740 | static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
741 | { |
742 | dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); | |
743 | } | |
744 | ||
d79db853 AT |
745 | static void dispc_ovl_set_pos(enum omap_plane plane, |
746 | enum omap_overlay_caps caps, int x, int y) | |
80c39712 | 747 | { |
d79db853 AT |
748 | u32 val; |
749 | ||
750 | if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) | |
751 | return; | |
752 | ||
753 | val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); | |
9b372c2d AT |
754 | |
755 | dispc_write_reg(DISPC_OVL_POSITION(plane), val); | |
80c39712 TV |
756 | } |
757 | ||
78b687fc AT |
758 | static void dispc_ovl_set_input_size(enum omap_plane plane, int width, |
759 | int height) | |
80c39712 | 760 | { |
80c39712 | 761 | u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
9b372c2d | 762 | |
36d87d95 | 763 | if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) |
9b372c2d AT |
764 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); |
765 | else | |
766 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
80c39712 TV |
767 | } |
768 | ||
78b687fc AT |
769 | static void dispc_ovl_set_output_size(enum omap_plane plane, int width, |
770 | int height) | |
80c39712 TV |
771 | { |
772 | u32 val; | |
80c39712 TV |
773 | |
774 | BUG_ON(plane == OMAP_DSS_GFX); | |
775 | ||
776 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); | |
9b372c2d | 777 | |
36d87d95 AT |
778 | if (plane == OMAP_DSS_WB) |
779 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
780 | else | |
781 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); | |
80c39712 TV |
782 | } |
783 | ||
5b54ed3e AT |
784 | static void dispc_ovl_set_zorder(enum omap_plane plane, |
785 | enum omap_overlay_caps caps, u8 zorder) | |
54128701 | 786 | { |
5b54ed3e | 787 | if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) |
54128701 AT |
788 | return; |
789 | ||
790 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); | |
791 | } | |
792 | ||
793 | static void dispc_ovl_enable_zorder_planes(void) | |
794 | { | |
795 | int i; | |
796 | ||
797 | if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
798 | return; | |
799 | ||
800 | for (i = 0; i < dss_feat_get_num_ovls(); i++) | |
801 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); | |
802 | } | |
803 | ||
5b54ed3e AT |
804 | static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, |
805 | enum omap_overlay_caps caps, bool enable) | |
fd28a390 | 806 | { |
5b54ed3e | 807 | if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) |
fd28a390 R |
808 | return; |
809 | ||
9b372c2d | 810 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); |
fd28a390 R |
811 | } |
812 | ||
5b54ed3e AT |
813 | static void dispc_ovl_setup_global_alpha(enum omap_plane plane, |
814 | enum omap_overlay_caps caps, u8 global_alpha) | |
80c39712 | 815 | { |
b8c095b4 | 816 | static const unsigned shifts[] = { 0, 8, 16, 24, }; |
fe3cc9d6 TV |
817 | int shift; |
818 | ||
5b54ed3e | 819 | if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) |
fd28a390 | 820 | return; |
a0acb557 | 821 | |
fe3cc9d6 TV |
822 | shift = shifts[plane]; |
823 | REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); | |
80c39712 TV |
824 | } |
825 | ||
f0e5caab | 826 | static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) |
80c39712 | 827 | { |
9b372c2d | 828 | dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); |
80c39712 TV |
829 | } |
830 | ||
f0e5caab | 831 | static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) |
80c39712 | 832 | { |
9b372c2d | 833 | dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); |
80c39712 TV |
834 | } |
835 | ||
f0e5caab | 836 | static void dispc_ovl_set_color_mode(enum omap_plane plane, |
80c39712 TV |
837 | enum omap_color_mode color_mode) |
838 | { | |
839 | u32 m = 0; | |
f20e4220 AJ |
840 | if (plane != OMAP_DSS_GFX) { |
841 | switch (color_mode) { | |
842 | case OMAP_DSS_COLOR_NV12: | |
843 | m = 0x0; break; | |
08f3267e | 844 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 AJ |
845 | m = 0x1; break; |
846 | case OMAP_DSS_COLOR_RGBA16: | |
847 | m = 0x2; break; | |
08f3267e | 848 | case OMAP_DSS_COLOR_RGB12U: |
f20e4220 AJ |
849 | m = 0x4; break; |
850 | case OMAP_DSS_COLOR_ARGB16: | |
851 | m = 0x5; break; | |
852 | case OMAP_DSS_COLOR_RGB16: | |
853 | m = 0x6; break; | |
854 | case OMAP_DSS_COLOR_ARGB16_1555: | |
855 | m = 0x7; break; | |
856 | case OMAP_DSS_COLOR_RGB24U: | |
857 | m = 0x8; break; | |
858 | case OMAP_DSS_COLOR_RGB24P: | |
859 | m = 0x9; break; | |
860 | case OMAP_DSS_COLOR_YUV2: | |
861 | m = 0xa; break; | |
862 | case OMAP_DSS_COLOR_UYVY: | |
863 | m = 0xb; break; | |
864 | case OMAP_DSS_COLOR_ARGB32: | |
865 | m = 0xc; break; | |
866 | case OMAP_DSS_COLOR_RGBA32: | |
867 | m = 0xd; break; | |
868 | case OMAP_DSS_COLOR_RGBX32: | |
869 | m = 0xe; break; | |
870 | case OMAP_DSS_COLOR_XRGB16_1555: | |
871 | m = 0xf; break; | |
872 | default: | |
c6eee968 | 873 | BUG(); return; |
f20e4220 AJ |
874 | } |
875 | } else { | |
876 | switch (color_mode) { | |
877 | case OMAP_DSS_COLOR_CLUT1: | |
878 | m = 0x0; break; | |
879 | case OMAP_DSS_COLOR_CLUT2: | |
880 | m = 0x1; break; | |
881 | case OMAP_DSS_COLOR_CLUT4: | |
882 | m = 0x2; break; | |
883 | case OMAP_DSS_COLOR_CLUT8: | |
884 | m = 0x3; break; | |
885 | case OMAP_DSS_COLOR_RGB12U: | |
886 | m = 0x4; break; | |
887 | case OMAP_DSS_COLOR_ARGB16: | |
888 | m = 0x5; break; | |
889 | case OMAP_DSS_COLOR_RGB16: | |
890 | m = 0x6; break; | |
891 | case OMAP_DSS_COLOR_ARGB16_1555: | |
892 | m = 0x7; break; | |
893 | case OMAP_DSS_COLOR_RGB24U: | |
894 | m = 0x8; break; | |
895 | case OMAP_DSS_COLOR_RGB24P: | |
896 | m = 0x9; break; | |
08f3267e | 897 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 | 898 | m = 0xa; break; |
08f3267e | 899 | case OMAP_DSS_COLOR_RGBA16: |
f20e4220 AJ |
900 | m = 0xb; break; |
901 | case OMAP_DSS_COLOR_ARGB32: | |
902 | m = 0xc; break; | |
903 | case OMAP_DSS_COLOR_RGBA32: | |
904 | m = 0xd; break; | |
905 | case OMAP_DSS_COLOR_RGBX32: | |
906 | m = 0xe; break; | |
907 | case OMAP_DSS_COLOR_XRGB16_1555: | |
908 | m = 0xf; break; | |
909 | default: | |
c6eee968 | 910 | BUG(); return; |
f20e4220 | 911 | } |
80c39712 TV |
912 | } |
913 | ||
9b372c2d | 914 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); |
80c39712 TV |
915 | } |
916 | ||
65e006ff CM |
917 | static void dispc_ovl_configure_burst_type(enum omap_plane plane, |
918 | enum omap_dss_rotation_type rotation_type) | |
919 | { | |
920 | if (dss_has_feature(FEAT_BURST_2D) == 0) | |
921 | return; | |
922 | ||
923 | if (rotation_type == OMAP_DSS_ROT_TILER) | |
924 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); | |
925 | else | |
926 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); | |
927 | } | |
928 | ||
f427984e | 929 | void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) |
80c39712 TV |
930 | { |
931 | int shift; | |
932 | u32 val; | |
2a205f34 | 933 | int chan = 0, chan2 = 0; |
80c39712 TV |
934 | |
935 | switch (plane) { | |
936 | case OMAP_DSS_GFX: | |
937 | shift = 8; | |
938 | break; | |
939 | case OMAP_DSS_VIDEO1: | |
940 | case OMAP_DSS_VIDEO2: | |
b8c095b4 | 941 | case OMAP_DSS_VIDEO3: |
80c39712 TV |
942 | shift = 16; |
943 | break; | |
944 | default: | |
945 | BUG(); | |
946 | return; | |
947 | } | |
948 | ||
9b372c2d | 949 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
2a205f34 SS |
950 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
951 | switch (channel) { | |
952 | case OMAP_DSS_CHANNEL_LCD: | |
953 | chan = 0; | |
954 | chan2 = 0; | |
955 | break; | |
956 | case OMAP_DSS_CHANNEL_DIGIT: | |
957 | chan = 1; | |
958 | chan2 = 0; | |
959 | break; | |
960 | case OMAP_DSS_CHANNEL_LCD2: | |
961 | chan = 0; | |
962 | chan2 = 1; | |
963 | break; | |
e86d456a CM |
964 | case OMAP_DSS_CHANNEL_LCD3: |
965 | if (dss_has_feature(FEAT_MGR_LCD3)) { | |
966 | chan = 0; | |
967 | chan2 = 2; | |
968 | } else { | |
969 | BUG(); | |
970 | return; | |
971 | } | |
972 | break; | |
2a205f34 SS |
973 | default: |
974 | BUG(); | |
c6eee968 | 975 | return; |
2a205f34 SS |
976 | } |
977 | ||
978 | val = FLD_MOD(val, chan, shift, shift); | |
979 | val = FLD_MOD(val, chan2, 31, 30); | |
980 | } else { | |
981 | val = FLD_MOD(val, channel, shift, shift); | |
982 | } | |
9b372c2d | 983 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 | 984 | } |
348be69d | 985 | EXPORT_SYMBOL(dispc_ovl_set_channel_out); |
80c39712 | 986 | |
2cc5d1af TV |
987 | static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) |
988 | { | |
989 | int shift; | |
990 | u32 val; | |
991 | enum omap_channel channel; | |
992 | ||
993 | switch (plane) { | |
994 | case OMAP_DSS_GFX: | |
995 | shift = 8; | |
996 | break; | |
997 | case OMAP_DSS_VIDEO1: | |
998 | case OMAP_DSS_VIDEO2: | |
999 | case OMAP_DSS_VIDEO3: | |
1000 | shift = 16; | |
1001 | break; | |
1002 | default: | |
1003 | BUG(); | |
c6eee968 | 1004 | return 0; |
2cc5d1af TV |
1005 | } |
1006 | ||
1007 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
1008 | ||
e86d456a CM |
1009 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
1010 | if (FLD_GET(val, 31, 30) == 0) | |
1011 | channel = FLD_GET(val, shift, shift); | |
1012 | else if (FLD_GET(val, 31, 30) == 1) | |
1013 | channel = OMAP_DSS_CHANNEL_LCD2; | |
1014 | else | |
1015 | channel = OMAP_DSS_CHANNEL_LCD3; | |
1016 | } else if (dss_has_feature(FEAT_MGR_LCD2)) { | |
2cc5d1af TV |
1017 | if (FLD_GET(val, 31, 30) == 0) |
1018 | channel = FLD_GET(val, shift, shift); | |
1019 | else | |
1020 | channel = OMAP_DSS_CHANNEL_LCD2; | |
1021 | } else { | |
1022 | channel = FLD_GET(val, shift, shift); | |
1023 | } | |
1024 | ||
1025 | return channel; | |
1026 | } | |
1027 | ||
d9ac773c AT |
1028 | void dispc_wb_set_channel_in(enum dss_writeback_channel channel) |
1029 | { | |
1030 | enum omap_plane plane = OMAP_DSS_WB; | |
1031 | ||
1032 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); | |
1033 | } | |
1034 | ||
f0e5caab | 1035 | static void dispc_ovl_set_burst_size(enum omap_plane plane, |
80c39712 TV |
1036 | enum omap_burst_size burst_size) |
1037 | { | |
8bbe09ee | 1038 | static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; |
80c39712 | 1039 | int shift; |
80c39712 | 1040 | |
fe3cc9d6 | 1041 | shift = shifts[plane]; |
5ed8cf5b | 1042 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); |
80c39712 TV |
1043 | } |
1044 | ||
5ed8cf5b TV |
1045 | static void dispc_configure_burst_sizes(void) |
1046 | { | |
1047 | int i; | |
1048 | const int burst_size = BURST_SIZE_X8; | |
1049 | ||
1050 | /* Configure burst size always to maximum size */ | |
392faa0e | 1051 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) |
f0e5caab | 1052 | dispc_ovl_set_burst_size(i, burst_size); |
5ed8cf5b TV |
1053 | } |
1054 | ||
83fa2f2e | 1055 | static u32 dispc_ovl_get_burst_size(enum omap_plane plane) |
5ed8cf5b TV |
1056 | { |
1057 | unsigned unit = dss_feat_get_burst_size_unit(); | |
1058 | /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ | |
1059 | return unit * 8; | |
1060 | } | |
1061 | ||
d3862610 M |
1062 | void dispc_enable_gamma_table(bool enable) |
1063 | { | |
1064 | /* | |
1065 | * This is partially implemented to support only disabling of | |
1066 | * the gamma table. | |
1067 | */ | |
1068 | if (enable) { | |
1069 | DSSWARN("Gamma table enabling for TV not yet supported"); | |
1070 | return; | |
1071 | } | |
1072 | ||
1073 | REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); | |
1074 | } | |
1075 | ||
c64dca40 | 1076 | static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) |
3c07cae2 | 1077 | { |
efa70b3b | 1078 | if (channel == OMAP_DSS_CHANNEL_DIGIT) |
3c07cae2 TV |
1079 | return; |
1080 | ||
efa70b3b | 1081 | mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); |
3c07cae2 TV |
1082 | } |
1083 | ||
c64dca40 | 1084 | static void dispc_mgr_set_cpr_coef(enum omap_channel channel, |
a8f3fcd1 | 1085 | const struct omap_dss_cpr_coefs *coefs) |
3c07cae2 TV |
1086 | { |
1087 | u32 coef_r, coef_g, coef_b; | |
1088 | ||
dd88b7a6 | 1089 | if (!dss_mgr_is_lcd(channel)) |
3c07cae2 TV |
1090 | return; |
1091 | ||
1092 | coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | | |
1093 | FLD_VAL(coefs->rb, 9, 0); | |
1094 | coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | | |
1095 | FLD_VAL(coefs->gb, 9, 0); | |
1096 | coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | | |
1097 | FLD_VAL(coefs->bb, 9, 0); | |
1098 | ||
1099 | dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); | |
1100 | dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); | |
1101 | dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); | |
1102 | } | |
1103 | ||
f0e5caab | 1104 | static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) |
80c39712 TV |
1105 | { |
1106 | u32 val; | |
1107 | ||
1108 | BUG_ON(plane == OMAP_DSS_GFX); | |
1109 | ||
9b372c2d | 1110 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1111 | val = FLD_MOD(val, enable, 9, 9); |
9b372c2d | 1112 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 TV |
1113 | } |
1114 | ||
d79db853 AT |
1115 | static void dispc_ovl_enable_replication(enum omap_plane plane, |
1116 | enum omap_overlay_caps caps, bool enable) | |
80c39712 | 1117 | { |
b8c095b4 | 1118 | static const unsigned shifts[] = { 5, 10, 10, 10 }; |
fe3cc9d6 | 1119 | int shift; |
80c39712 | 1120 | |
d79db853 AT |
1121 | if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) |
1122 | return; | |
1123 | ||
fe3cc9d6 TV |
1124 | shift = shifts[plane]; |
1125 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); | |
80c39712 TV |
1126 | } |
1127 | ||
8f366162 | 1128 | static void dispc_mgr_set_size(enum omap_channel channel, u16 width, |
e5c09e06 | 1129 | u16 height) |
80c39712 TV |
1130 | { |
1131 | u32 val; | |
80c39712 | 1132 | |
33b89928 AT |
1133 | val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | |
1134 | FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); | |
1135 | ||
8f366162 | 1136 | dispc_write_reg(DISPC_SIZE_MGR(channel), val); |
80c39712 TV |
1137 | } |
1138 | ||
42a6961c | 1139 | static void dispc_init_fifos(void) |
80c39712 | 1140 | { |
80c39712 | 1141 | u32 size; |
42a6961c | 1142 | int fifo; |
a0acb557 | 1143 | u8 start, end; |
5ed8cf5b | 1144 | u32 unit; |
47fc469b | 1145 | int i; |
5ed8cf5b TV |
1146 | |
1147 | unit = dss_feat_get_buffer_size_unit(); | |
80c39712 | 1148 | |
a0acb557 | 1149 | dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); |
80c39712 | 1150 | |
42a6961c TV |
1151 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { |
1152 | size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); | |
5ed8cf5b | 1153 | size *= unit; |
42a6961c TV |
1154 | dispc.fifo_size[fifo] = size; |
1155 | ||
1156 | /* | |
1157 | * By default fifos are mapped directly to overlays, fifo 0 to | |
1158 | * ovl 0, fifo 1 to ovl 1, etc. | |
1159 | */ | |
1160 | dispc.fifo_assignment[fifo] = fifo; | |
80c39712 | 1161 | } |
66a0f9e4 TV |
1162 | |
1163 | /* | |
1164 | * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo | |
1165 | * causes problems with certain use cases, like using the tiler in 2D | |
1166 | * mode. The below hack swaps the fifos of GFX and WB planes, thus | |
1167 | * giving GFX plane a larger fifo. WB but should work fine with a | |
1168 | * smaller fifo. | |
1169 | */ | |
1170 | if (dispc.feat->gfx_fifo_workaround) { | |
1171 | u32 v; | |
1172 | ||
1173 | v = dispc_read_reg(DISPC_GLOBAL_BUFFER); | |
1174 | ||
1175 | v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ | |
1176 | v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ | |
1177 | v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ | |
1178 | v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ | |
1179 | ||
1180 | dispc_write_reg(DISPC_GLOBAL_BUFFER, v); | |
1181 | ||
1182 | dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; | |
1183 | dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; | |
1184 | } | |
47fc469b TV |
1185 | |
1186 | /* | |
1187 | * Setup default fifo thresholds. | |
1188 | */ | |
1189 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) { | |
1190 | u32 low, high; | |
1191 | const bool use_fifomerge = false; | |
1192 | const bool manual_update = false; | |
1193 | ||
1194 | dispc_ovl_compute_fifo_thresholds(i, &low, &high, | |
1195 | use_fifomerge, manual_update); | |
1196 | ||
1197 | dispc_ovl_set_fifo_threshold(i, low, high); | |
1198 | } | |
80c39712 TV |
1199 | } |
1200 | ||
83fa2f2e | 1201 | static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) |
80c39712 | 1202 | { |
42a6961c TV |
1203 | int fifo; |
1204 | u32 size = 0; | |
1205 | ||
1206 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { | |
1207 | if (dispc.fifo_assignment[fifo] == plane) | |
1208 | size += dispc.fifo_size[fifo]; | |
1209 | } | |
1210 | ||
1211 | return size; | |
80c39712 TV |
1212 | } |
1213 | ||
6f04e1bf | 1214 | void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) |
80c39712 | 1215 | { |
a0acb557 | 1216 | u8 hi_start, hi_end, lo_start, lo_end; |
5ed8cf5b TV |
1217 | u32 unit; |
1218 | ||
1219 | unit = dss_feat_get_buffer_size_unit(); | |
1220 | ||
1221 | WARN_ON(low % unit != 0); | |
1222 | WARN_ON(high % unit != 0); | |
1223 | ||
1224 | low /= unit; | |
1225 | high /= unit; | |
a0acb557 | 1226 | |
9b372c2d AT |
1227 | dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); |
1228 | dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); | |
1229 | ||
3cb5d966 | 1230 | DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", |
80c39712 | 1231 | plane, |
9b372c2d | 1232 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 | 1233 | lo_start, lo_end) * unit, |
9b372c2d | 1234 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 TV |
1235 | hi_start, hi_end) * unit, |
1236 | low * unit, high * unit); | |
80c39712 | 1237 | |
9b372c2d | 1238 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), |
a0acb557 AT |
1239 | FLD_VAL(high, hi_start, hi_end) | |
1240 | FLD_VAL(low, lo_start, lo_end)); | |
8bc65552 AT |
1241 | |
1242 | /* | |
1243 | * configure the preload to the pipeline's high threhold, if HT it's too | |
1244 | * large for the preload field, set the threshold to the maximum value | |
1245 | * that can be held by the preload register | |
1246 | */ | |
1247 | if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && | |
1248 | plane != OMAP_DSS_WB) | |
1249 | dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); | |
80c39712 | 1250 | } |
8ee5c842 | 1251 | EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold); |
80c39712 TV |
1252 | |
1253 | void dispc_enable_fifomerge(bool enable) | |
1254 | { | |
e6b0f884 TV |
1255 | if (!dss_has_feature(FEAT_FIFO_MERGE)) { |
1256 | WARN_ON(enable); | |
1257 | return; | |
1258 | } | |
1259 | ||
80c39712 TV |
1260 | DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); |
1261 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); | |
80c39712 TV |
1262 | } |
1263 | ||
83fa2f2e | 1264 | void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, |
3568f2a4 TV |
1265 | u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, |
1266 | bool manual_update) | |
83fa2f2e TV |
1267 | { |
1268 | /* | |
1269 | * All sizes are in bytes. Both the buffer and burst are made of | |
1270 | * buffer_units, and the fifo thresholds must be buffer_unit aligned. | |
1271 | */ | |
1272 | ||
1273 | unsigned buf_unit = dss_feat_get_buffer_size_unit(); | |
e0e405b9 TV |
1274 | unsigned ovl_fifo_size, total_fifo_size, burst_size; |
1275 | int i; | |
83fa2f2e TV |
1276 | |
1277 | burst_size = dispc_ovl_get_burst_size(plane); | |
e0e405b9 | 1278 | ovl_fifo_size = dispc_ovl_get_fifo_size(plane); |
83fa2f2e | 1279 | |
e0e405b9 TV |
1280 | if (use_fifomerge) { |
1281 | total_fifo_size = 0; | |
392faa0e | 1282 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) |
e0e405b9 TV |
1283 | total_fifo_size += dispc_ovl_get_fifo_size(i); |
1284 | } else { | |
1285 | total_fifo_size = ovl_fifo_size; | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * We use the same low threshold for both fifomerge and non-fifomerge | |
1290 | * cases, but for fifomerge we calculate the high threshold using the | |
1291 | * combined fifo size | |
1292 | */ | |
1293 | ||
3568f2a4 | 1294 | if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { |
e0e405b9 TV |
1295 | *fifo_low = ovl_fifo_size - burst_size * 2; |
1296 | *fifo_high = total_fifo_size - burst_size; | |
8bbe09ee AT |
1297 | } else if (plane == OMAP_DSS_WB) { |
1298 | /* | |
1299 | * Most optimal configuration for writeback is to push out data | |
1300 | * to the interconnect the moment writeback pushes enough pixels | |
1301 | * in the FIFO to form a burst | |
1302 | */ | |
1303 | *fifo_low = 0; | |
1304 | *fifo_high = burst_size; | |
e0e405b9 TV |
1305 | } else { |
1306 | *fifo_low = ovl_fifo_size - burst_size; | |
1307 | *fifo_high = total_fifo_size - buf_unit; | |
1308 | } | |
83fa2f2e | 1309 | } |
8ee5c842 | 1310 | EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds); |
83fa2f2e | 1311 | |
c64aa3a6 TV |
1312 | static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) |
1313 | { | |
1314 | int bit; | |
1315 | ||
1316 | if (plane == OMAP_DSS_GFX) | |
1317 | bit = 14; | |
1318 | else | |
1319 | bit = 23; | |
1320 | ||
1321 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); | |
1322 | } | |
1323 | ||
1324 | static void dispc_ovl_set_mflag_threshold(enum omap_plane plane, | |
1325 | int low, int high) | |
1326 | { | |
1327 | dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), | |
1328 | FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); | |
1329 | } | |
1330 | ||
1331 | static void dispc_init_mflag(void) | |
1332 | { | |
1333 | int i; | |
1334 | ||
fe59e5cf TV |
1335 | /* |
1336 | * HACK: NV12 color format and MFLAG seem to have problems working | |
1337 | * together: using two displays, and having an NV12 overlay on one of | |
1338 | * the displays will cause underflows/synclosts when MFLAG_CTRL=2. | |
1339 | * Changing MFLAG thresholds and PRELOAD to certain values seem to | |
1340 | * remove the errors, but there doesn't seem to be a clear logic on | |
1341 | * which values work and which not. | |
1342 | * | |
1343 | * As a work-around, set force MFLAG to always on. | |
1344 | */ | |
c64aa3a6 | 1345 | dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, |
fe59e5cf | 1346 | (1 << 0) | /* MFLAG_CTRL = force always on */ |
c64aa3a6 TV |
1347 | (0 << 2)); /* MFLAG_START = disable */ |
1348 | ||
1349 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) { | |
1350 | u32 size = dispc_ovl_get_fifo_size(i); | |
1351 | u32 unit = dss_feat_get_buffer_size_unit(); | |
1352 | u32 low, high; | |
1353 | ||
1354 | dispc_ovl_set_mflag(i, true); | |
1355 | ||
1356 | /* | |
1357 | * Simulation team suggests below thesholds: | |
1358 | * HT = fifosize * 5 / 8; | |
1359 | * LT = fifosize * 4 / 8; | |
1360 | */ | |
1361 | ||
1362 | low = size * 4 / 8 / unit; | |
1363 | high = size * 5 / 8 / unit; | |
1364 | ||
1365 | dispc_ovl_set_mflag_threshold(i, low, high); | |
1366 | } | |
1367 | } | |
1368 | ||
f0e5caab | 1369 | static void dispc_ovl_set_fir(enum omap_plane plane, |
0d66cbb5 AJ |
1370 | int hinc, int vinc, |
1371 | enum omap_color_component color_comp) | |
80c39712 TV |
1372 | { |
1373 | u32 val; | |
80c39712 | 1374 | |
0d66cbb5 AJ |
1375 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
1376 | u8 hinc_start, hinc_end, vinc_start, vinc_end; | |
a0acb557 | 1377 | |
0d66cbb5 AJ |
1378 | dss_feat_get_reg_field(FEAT_REG_FIRHINC, |
1379 | &hinc_start, &hinc_end); | |
1380 | dss_feat_get_reg_field(FEAT_REG_FIRVINC, | |
1381 | &vinc_start, &vinc_end); | |
1382 | val = FLD_VAL(vinc, vinc_start, vinc_end) | | |
1383 | FLD_VAL(hinc, hinc_start, hinc_end); | |
a0acb557 | 1384 | |
0d66cbb5 AJ |
1385 | dispc_write_reg(DISPC_OVL_FIR(plane), val); |
1386 | } else { | |
1387 | val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); | |
1388 | dispc_write_reg(DISPC_OVL_FIR2(plane), val); | |
1389 | } | |
80c39712 TV |
1390 | } |
1391 | ||
f0e5caab | 1392 | static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1393 | { |
1394 | u32 val; | |
87a7484b | 1395 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1396 | |
87a7484b AT |
1397 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1398 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1399 | ||
1400 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1401 | FLD_VAL(haccu, hor_start, hor_end); | |
1402 | ||
9b372c2d | 1403 | dispc_write_reg(DISPC_OVL_ACCU0(plane), val); |
80c39712 TV |
1404 | } |
1405 | ||
f0e5caab | 1406 | static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1407 | { |
1408 | u32 val; | |
87a7484b | 1409 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1410 | |
87a7484b AT |
1411 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1412 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1413 | ||
1414 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1415 | FLD_VAL(haccu, hor_start, hor_end); | |
1416 | ||
9b372c2d | 1417 | dispc_write_reg(DISPC_OVL_ACCU1(plane), val); |
80c39712 TV |
1418 | } |
1419 | ||
f0e5caab TV |
1420 | static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, |
1421 | int vaccu) | |
ab5ca071 AJ |
1422 | { |
1423 | u32 val; | |
1424 | ||
1425 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1426 | dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); | |
1427 | } | |
1428 | ||
f0e5caab TV |
1429 | static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, |
1430 | int vaccu) | |
ab5ca071 AJ |
1431 | { |
1432 | u32 val; | |
1433 | ||
1434 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1435 | dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); | |
1436 | } | |
80c39712 | 1437 | |
f0e5caab | 1438 | static void dispc_ovl_set_scale_param(enum omap_plane plane, |
80c39712 TV |
1439 | u16 orig_width, u16 orig_height, |
1440 | u16 out_width, u16 out_height, | |
0d66cbb5 AJ |
1441 | bool five_taps, u8 rotation, |
1442 | enum omap_color_component color_comp) | |
80c39712 | 1443 | { |
0d66cbb5 | 1444 | int fir_hinc, fir_vinc; |
80c39712 | 1445 | |
ed14a3ce AJ |
1446 | fir_hinc = 1024 * orig_width / out_width; |
1447 | fir_vinc = 1024 * orig_height / out_height; | |
80c39712 | 1448 | |
debd9074 CM |
1449 | dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, |
1450 | color_comp); | |
f0e5caab | 1451 | dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); |
0d66cbb5 AJ |
1452 | } |
1453 | ||
05dd0f53 CM |
1454 | static void dispc_ovl_set_accu_uv(enum omap_plane plane, |
1455 | u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, | |
1456 | bool ilace, enum omap_color_mode color_mode, u8 rotation) | |
1457 | { | |
1458 | int h_accu2_0, h_accu2_1; | |
1459 | int v_accu2_0, v_accu2_1; | |
1460 | int chroma_hinc, chroma_vinc; | |
1461 | int idx; | |
1462 | ||
1463 | struct accu { | |
1464 | s8 h0_m, h0_n; | |
1465 | s8 h1_m, h1_n; | |
1466 | s8 v0_m, v0_n; | |
1467 | s8 v1_m, v1_n; | |
1468 | }; | |
1469 | ||
1470 | const struct accu *accu_table; | |
1471 | const struct accu *accu_val; | |
1472 | ||
1473 | static const struct accu accu_nv12[4] = { | |
1474 | { 0, 1, 0, 1 , -1, 2, 0, 1 }, | |
1475 | { 1, 2, -3, 4 , 0, 1, 0, 1 }, | |
1476 | { -1, 1, 0, 1 , -1, 2, 0, 1 }, | |
1477 | { -1, 2, -1, 2 , -1, 1, 0, 1 }, | |
1478 | }; | |
1479 | ||
1480 | static const struct accu accu_nv12_ilace[4] = { | |
1481 | { 0, 1, 0, 1 , -3, 4, -1, 4 }, | |
1482 | { -1, 4, -3, 4 , 0, 1, 0, 1 }, | |
1483 | { -1, 1, 0, 1 , -1, 4, -3, 4 }, | |
1484 | { -3, 4, -3, 4 , -1, 1, 0, 1 }, | |
1485 | }; | |
1486 | ||
1487 | static const struct accu accu_yuv[4] = { | |
1488 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1489 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1490 | { -1, 1, 0, 1, 0, 1, 0, 1 }, | |
1491 | { 0, 1, 0, 1, -1, 1, 0, 1 }, | |
1492 | }; | |
1493 | ||
1494 | switch (rotation) { | |
1495 | case OMAP_DSS_ROT_0: | |
1496 | idx = 0; | |
1497 | break; | |
1498 | case OMAP_DSS_ROT_90: | |
1499 | idx = 1; | |
1500 | break; | |
1501 | case OMAP_DSS_ROT_180: | |
1502 | idx = 2; | |
1503 | break; | |
1504 | case OMAP_DSS_ROT_270: | |
1505 | idx = 3; | |
1506 | break; | |
1507 | default: | |
1508 | BUG(); | |
c6eee968 | 1509 | return; |
05dd0f53 CM |
1510 | } |
1511 | ||
1512 | switch (color_mode) { | |
1513 | case OMAP_DSS_COLOR_NV12: | |
1514 | if (ilace) | |
1515 | accu_table = accu_nv12_ilace; | |
1516 | else | |
1517 | accu_table = accu_nv12; | |
1518 | break; | |
1519 | case OMAP_DSS_COLOR_YUV2: | |
1520 | case OMAP_DSS_COLOR_UYVY: | |
1521 | accu_table = accu_yuv; | |
1522 | break; | |
1523 | default: | |
1524 | BUG(); | |
c6eee968 | 1525 | return; |
05dd0f53 CM |
1526 | } |
1527 | ||
1528 | accu_val = &accu_table[idx]; | |
1529 | ||
1530 | chroma_hinc = 1024 * orig_width / out_width; | |
1531 | chroma_vinc = 1024 * orig_height / out_height; | |
1532 | ||
1533 | h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; | |
1534 | h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; | |
1535 | v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; | |
1536 | v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; | |
1537 | ||
1538 | dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); | |
1539 | dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); | |
1540 | } | |
1541 | ||
f0e5caab | 1542 | static void dispc_ovl_set_scaling_common(enum omap_plane plane, |
0d66cbb5 AJ |
1543 | u16 orig_width, u16 orig_height, |
1544 | u16 out_width, u16 out_height, | |
1545 | bool ilace, bool five_taps, | |
1546 | bool fieldmode, enum omap_color_mode color_mode, | |
1547 | u8 rotation) | |
1548 | { | |
1549 | int accu0 = 0; | |
1550 | int accu1 = 0; | |
1551 | u32 l; | |
80c39712 | 1552 | |
f0e5caab | 1553 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1554 | out_width, out_height, five_taps, |
1555 | rotation, DISPC_COLOR_COMPONENT_RGB_Y); | |
9b372c2d | 1556 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1557 | |
87a7484b AT |
1558 | /* RESIZEENABLE and VERTICALTAPS */ |
1559 | l &= ~((0x3 << 5) | (0x1 << 21)); | |
ed14a3ce AJ |
1560 | l |= (orig_width != out_width) ? (1 << 5) : 0; |
1561 | l |= (orig_height != out_height) ? (1 << 6) : 0; | |
87a7484b | 1562 | l |= five_taps ? (1 << 21) : 0; |
80c39712 | 1563 | |
87a7484b AT |
1564 | /* VRESIZECONF and HRESIZECONF */ |
1565 | if (dss_has_feature(FEAT_RESIZECONF)) { | |
1566 | l &= ~(0x3 << 7); | |
0d66cbb5 AJ |
1567 | l |= (orig_width <= out_width) ? 0 : (1 << 7); |
1568 | l |= (orig_height <= out_height) ? 0 : (1 << 8); | |
87a7484b | 1569 | } |
80c39712 | 1570 | |
87a7484b AT |
1571 | /* LINEBUFFERSPLIT */ |
1572 | if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { | |
1573 | l &= ~(0x1 << 22); | |
1574 | l |= five_taps ? (1 << 22) : 0; | |
1575 | } | |
80c39712 | 1576 | |
9b372c2d | 1577 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); |
80c39712 TV |
1578 | |
1579 | /* | |
1580 | * field 0 = even field = bottom field | |
1581 | * field 1 = odd field = top field | |
1582 | */ | |
1583 | if (ilace && !fieldmode) { | |
1584 | accu1 = 0; | |
0d66cbb5 | 1585 | accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; |
80c39712 TV |
1586 | if (accu0 >= 1024/2) { |
1587 | accu1 = 1024/2; | |
1588 | accu0 -= accu1; | |
1589 | } | |
1590 | } | |
1591 | ||
f0e5caab TV |
1592 | dispc_ovl_set_vid_accu0(plane, 0, accu0); |
1593 | dispc_ovl_set_vid_accu1(plane, 0, accu1); | |
80c39712 TV |
1594 | } |
1595 | ||
f0e5caab | 1596 | static void dispc_ovl_set_scaling_uv(enum omap_plane plane, |
0d66cbb5 AJ |
1597 | u16 orig_width, u16 orig_height, |
1598 | u16 out_width, u16 out_height, | |
1599 | bool ilace, bool five_taps, | |
1600 | bool fieldmode, enum omap_color_mode color_mode, | |
1601 | u8 rotation) | |
1602 | { | |
1603 | int scale_x = out_width != orig_width; | |
1604 | int scale_y = out_height != orig_height; | |
f92afae2 | 1605 | bool chroma_upscale = plane != OMAP_DSS_WB ? true : false; |
0d66cbb5 AJ |
1606 | |
1607 | if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) | |
1608 | return; | |
1609 | if ((color_mode != OMAP_DSS_COLOR_YUV2 && | |
1610 | color_mode != OMAP_DSS_COLOR_UYVY && | |
1611 | color_mode != OMAP_DSS_COLOR_NV12)) { | |
1612 | /* reset chroma resampling for RGB formats */ | |
2a5561b1 AT |
1613 | if (plane != OMAP_DSS_WB) |
1614 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); | |
0d66cbb5 AJ |
1615 | return; |
1616 | } | |
36377357 TV |
1617 | |
1618 | dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, | |
1619 | out_height, ilace, color_mode, rotation); | |
1620 | ||
0d66cbb5 AJ |
1621 | switch (color_mode) { |
1622 | case OMAP_DSS_COLOR_NV12: | |
20fbb50b AT |
1623 | if (chroma_upscale) { |
1624 | /* UV is subsampled by 2 horizontally and vertically */ | |
1625 | orig_height >>= 1; | |
1626 | orig_width >>= 1; | |
1627 | } else { | |
1628 | /* UV is downsampled by 2 horizontally and vertically */ | |
1629 | orig_height <<= 1; | |
1630 | orig_width <<= 1; | |
1631 | } | |
1632 | ||
0d66cbb5 AJ |
1633 | break; |
1634 | case OMAP_DSS_COLOR_YUV2: | |
1635 | case OMAP_DSS_COLOR_UYVY: | |
20fbb50b | 1636 | /* For YUV422 with 90/270 rotation, we don't upsample chroma */ |
0d66cbb5 | 1637 | if (rotation == OMAP_DSS_ROT_0 || |
20fbb50b AT |
1638 | rotation == OMAP_DSS_ROT_180) { |
1639 | if (chroma_upscale) | |
1640 | /* UV is subsampled by 2 horizontally */ | |
1641 | orig_width >>= 1; | |
1642 | else | |
1643 | /* UV is downsampled by 2 horizontally */ | |
1644 | orig_width <<= 1; | |
1645 | } | |
1646 | ||
0d66cbb5 AJ |
1647 | /* must use FIR for YUV422 if rotated */ |
1648 | if (rotation != OMAP_DSS_ROT_0) | |
1649 | scale_x = scale_y = true; | |
20fbb50b | 1650 | |
0d66cbb5 AJ |
1651 | break; |
1652 | default: | |
1653 | BUG(); | |
c6eee968 | 1654 | return; |
0d66cbb5 AJ |
1655 | } |
1656 | ||
1657 | if (out_width != orig_width) | |
1658 | scale_x = true; | |
1659 | if (out_height != orig_height) | |
1660 | scale_y = true; | |
1661 | ||
f0e5caab | 1662 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1663 | out_width, out_height, five_taps, |
1664 | rotation, DISPC_COLOR_COMPONENT_UV); | |
1665 | ||
2a5561b1 AT |
1666 | if (plane != OMAP_DSS_WB) |
1667 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), | |
1668 | (scale_x || scale_y) ? 1 : 0, 8, 8); | |
1669 | ||
0d66cbb5 AJ |
1670 | /* set H scaling */ |
1671 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); | |
1672 | /* set V scaling */ | |
1673 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); | |
0d66cbb5 AJ |
1674 | } |
1675 | ||
f0e5caab | 1676 | static void dispc_ovl_set_scaling(enum omap_plane plane, |
0d66cbb5 AJ |
1677 | u16 orig_width, u16 orig_height, |
1678 | u16 out_width, u16 out_height, | |
1679 | bool ilace, bool five_taps, | |
1680 | bool fieldmode, enum omap_color_mode color_mode, | |
1681 | u8 rotation) | |
1682 | { | |
1683 | BUG_ON(plane == OMAP_DSS_GFX); | |
1684 | ||
f0e5caab | 1685 | dispc_ovl_set_scaling_common(plane, |
0d66cbb5 AJ |
1686 | orig_width, orig_height, |
1687 | out_width, out_height, | |
1688 | ilace, five_taps, | |
1689 | fieldmode, color_mode, | |
1690 | rotation); | |
1691 | ||
f0e5caab | 1692 | dispc_ovl_set_scaling_uv(plane, |
0d66cbb5 AJ |
1693 | orig_width, orig_height, |
1694 | out_width, out_height, | |
1695 | ilace, five_taps, | |
1696 | fieldmode, color_mode, | |
1697 | rotation); | |
1698 | } | |
1699 | ||
f0e5caab | 1700 | static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, |
c35eeb2e | 1701 | enum omap_dss_rotation_type rotation_type, |
80c39712 TV |
1702 | bool mirroring, enum omap_color_mode color_mode) |
1703 | { | |
87a7484b AT |
1704 | bool row_repeat = false; |
1705 | int vidrot = 0; | |
1706 | ||
80c39712 TV |
1707 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1708 | color_mode == OMAP_DSS_COLOR_UYVY) { | |
80c39712 TV |
1709 | |
1710 | if (mirroring) { | |
1711 | switch (rotation) { | |
1712 | case OMAP_DSS_ROT_0: | |
1713 | vidrot = 2; | |
1714 | break; | |
1715 | case OMAP_DSS_ROT_90: | |
1716 | vidrot = 1; | |
1717 | break; | |
1718 | case OMAP_DSS_ROT_180: | |
1719 | vidrot = 0; | |
1720 | break; | |
1721 | case OMAP_DSS_ROT_270: | |
1722 | vidrot = 3; | |
1723 | break; | |
1724 | } | |
1725 | } else { | |
1726 | switch (rotation) { | |
1727 | case OMAP_DSS_ROT_0: | |
1728 | vidrot = 0; | |
1729 | break; | |
1730 | case OMAP_DSS_ROT_90: | |
1731 | vidrot = 1; | |
1732 | break; | |
1733 | case OMAP_DSS_ROT_180: | |
1734 | vidrot = 2; | |
1735 | break; | |
1736 | case OMAP_DSS_ROT_270: | |
1737 | vidrot = 3; | |
1738 | break; | |
1739 | } | |
1740 | } | |
1741 | ||
80c39712 | 1742 | if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) |
87a7484b | 1743 | row_repeat = true; |
80c39712 | 1744 | else |
87a7484b | 1745 | row_repeat = false; |
80c39712 | 1746 | } |
87a7484b | 1747 | |
3397cc6a TV |
1748 | /* |
1749 | * OMAP4/5 Errata i631: | |
1750 | * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra | |
1751 | * rows beyond the framebuffer, which may cause OCP error. | |
1752 | */ | |
1753 | if (color_mode == OMAP_DSS_COLOR_NV12 && | |
1754 | rotation_type != OMAP_DSS_ROT_TILER) | |
1755 | vidrot = 1; | |
1756 | ||
9b372c2d | 1757 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); |
87a7484b | 1758 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) |
9b372c2d AT |
1759 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), |
1760 | row_repeat ? 1 : 0, 18, 18); | |
c35eeb2e AT |
1761 | |
1762 | if (color_mode == OMAP_DSS_COLOR_NV12) { | |
1763 | bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) && | |
1764 | (rotation == OMAP_DSS_ROT_0 || | |
1765 | rotation == OMAP_DSS_ROT_180); | |
1766 | /* DOUBLESTRIDE */ | |
1767 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); | |
1768 | } | |
1769 | ||
80c39712 TV |
1770 | } |
1771 | ||
1772 | static int color_mode_to_bpp(enum omap_color_mode color_mode) | |
1773 | { | |
1774 | switch (color_mode) { | |
1775 | case OMAP_DSS_COLOR_CLUT1: | |
1776 | return 1; | |
1777 | case OMAP_DSS_COLOR_CLUT2: | |
1778 | return 2; | |
1779 | case OMAP_DSS_COLOR_CLUT4: | |
1780 | return 4; | |
1781 | case OMAP_DSS_COLOR_CLUT8: | |
f20e4220 | 1782 | case OMAP_DSS_COLOR_NV12: |
80c39712 TV |
1783 | return 8; |
1784 | case OMAP_DSS_COLOR_RGB12U: | |
1785 | case OMAP_DSS_COLOR_RGB16: | |
1786 | case OMAP_DSS_COLOR_ARGB16: | |
1787 | case OMAP_DSS_COLOR_YUV2: | |
1788 | case OMAP_DSS_COLOR_UYVY: | |
f20e4220 AJ |
1789 | case OMAP_DSS_COLOR_RGBA16: |
1790 | case OMAP_DSS_COLOR_RGBX16: | |
1791 | case OMAP_DSS_COLOR_ARGB16_1555: | |
1792 | case OMAP_DSS_COLOR_XRGB16_1555: | |
80c39712 TV |
1793 | return 16; |
1794 | case OMAP_DSS_COLOR_RGB24P: | |
1795 | return 24; | |
1796 | case OMAP_DSS_COLOR_RGB24U: | |
1797 | case OMAP_DSS_COLOR_ARGB32: | |
1798 | case OMAP_DSS_COLOR_RGBA32: | |
1799 | case OMAP_DSS_COLOR_RGBX32: | |
1800 | return 32; | |
1801 | default: | |
1802 | BUG(); | |
c6eee968 | 1803 | return 0; |
80c39712 TV |
1804 | } |
1805 | } | |
1806 | ||
1807 | static s32 pixinc(int pixels, u8 ps) | |
1808 | { | |
1809 | if (pixels == 1) | |
1810 | return 1; | |
1811 | else if (pixels > 1) | |
1812 | return 1 + (pixels - 1) * ps; | |
1813 | else if (pixels < 0) | |
1814 | return 1 - (-pixels + 1) * ps; | |
1815 | else | |
1816 | BUG(); | |
c6eee968 | 1817 | return 0; |
80c39712 TV |
1818 | } |
1819 | ||
1820 | static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, | |
1821 | u16 screen_width, | |
1822 | u16 width, u16 height, | |
1823 | enum omap_color_mode color_mode, bool fieldmode, | |
1824 | unsigned int field_offset, | |
1825 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1826 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1827 | { |
1828 | u8 ps; | |
1829 | ||
1830 | /* FIXME CLUT formats */ | |
1831 | switch (color_mode) { | |
1832 | case OMAP_DSS_COLOR_CLUT1: | |
1833 | case OMAP_DSS_COLOR_CLUT2: | |
1834 | case OMAP_DSS_COLOR_CLUT4: | |
1835 | case OMAP_DSS_COLOR_CLUT8: | |
1836 | BUG(); | |
1837 | return; | |
1838 | case OMAP_DSS_COLOR_YUV2: | |
1839 | case OMAP_DSS_COLOR_UYVY: | |
1840 | ps = 4; | |
1841 | break; | |
1842 | default: | |
1843 | ps = color_mode_to_bpp(color_mode) / 8; | |
1844 | break; | |
1845 | } | |
1846 | ||
1847 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1848 | width, height); | |
1849 | ||
1850 | /* | |
1851 | * field 0 = even field = bottom field | |
1852 | * field 1 = odd field = top field | |
1853 | */ | |
1854 | switch (rotation + mirror * 4) { | |
1855 | case OMAP_DSS_ROT_0: | |
1856 | case OMAP_DSS_ROT_180: | |
1857 | /* | |
1858 | * If the pixel format is YUV or UYVY divide the width | |
1859 | * of the image by 2 for 0 and 180 degree rotation. | |
1860 | */ | |
1861 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1862 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1863 | width = width >> 1; | |
1864 | case OMAP_DSS_ROT_90: | |
1865 | case OMAP_DSS_ROT_270: | |
1866 | *offset1 = 0; | |
1867 | if (field_offset) | |
1868 | *offset0 = field_offset * screen_width * ps; | |
1869 | else | |
1870 | *offset0 = 0; | |
1871 | ||
aed74b55 CM |
1872 | *row_inc = pixinc(1 + |
1873 | (y_predecim * screen_width - x_predecim * width) + | |
1874 | (fieldmode ? screen_width : 0), ps); | |
1875 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1876 | break; |
1877 | ||
1878 | case OMAP_DSS_ROT_0 + 4: | |
1879 | case OMAP_DSS_ROT_180 + 4: | |
1880 | /* If the pixel format is YUV or UYVY divide the width | |
1881 | * of the image by 2 for 0 degree and 180 degree | |
1882 | */ | |
1883 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1884 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1885 | width = width >> 1; | |
1886 | case OMAP_DSS_ROT_90 + 4: | |
1887 | case OMAP_DSS_ROT_270 + 4: | |
1888 | *offset1 = 0; | |
1889 | if (field_offset) | |
1890 | *offset0 = field_offset * screen_width * ps; | |
1891 | else | |
1892 | *offset0 = 0; | |
aed74b55 CM |
1893 | *row_inc = pixinc(1 - |
1894 | (y_predecim * screen_width + x_predecim * width) - | |
1895 | (fieldmode ? screen_width : 0), ps); | |
1896 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1897 | break; |
1898 | ||
1899 | default: | |
1900 | BUG(); | |
c6eee968 | 1901 | return; |
80c39712 TV |
1902 | } |
1903 | } | |
1904 | ||
1905 | static void calc_dma_rotation_offset(u8 rotation, bool mirror, | |
1906 | u16 screen_width, | |
1907 | u16 width, u16 height, | |
1908 | enum omap_color_mode color_mode, bool fieldmode, | |
1909 | unsigned int field_offset, | |
1910 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1911 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1912 | { |
1913 | u8 ps; | |
1914 | u16 fbw, fbh; | |
1915 | ||
1916 | /* FIXME CLUT formats */ | |
1917 | switch (color_mode) { | |
1918 | case OMAP_DSS_COLOR_CLUT1: | |
1919 | case OMAP_DSS_COLOR_CLUT2: | |
1920 | case OMAP_DSS_COLOR_CLUT4: | |
1921 | case OMAP_DSS_COLOR_CLUT8: | |
1922 | BUG(); | |
1923 | return; | |
1924 | default: | |
1925 | ps = color_mode_to_bpp(color_mode) / 8; | |
1926 | break; | |
1927 | } | |
1928 | ||
1929 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1930 | width, height); | |
1931 | ||
1932 | /* width & height are overlay sizes, convert to fb sizes */ | |
1933 | ||
1934 | if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { | |
1935 | fbw = width; | |
1936 | fbh = height; | |
1937 | } else { | |
1938 | fbw = height; | |
1939 | fbh = width; | |
1940 | } | |
1941 | ||
1942 | /* | |
1943 | * field 0 = even field = bottom field | |
1944 | * field 1 = odd field = top field | |
1945 | */ | |
1946 | switch (rotation + mirror * 4) { | |
1947 | case OMAP_DSS_ROT_0: | |
1948 | *offset1 = 0; | |
1949 | if (field_offset) | |
1950 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1951 | else | |
1952 | *offset0 = *offset1; | |
aed74b55 CM |
1953 | *row_inc = pixinc(1 + |
1954 | (y_predecim * screen_width - fbw * x_predecim) + | |
1955 | (fieldmode ? screen_width : 0), ps); | |
1956 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1957 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1958 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
1959 | else | |
1960 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1961 | break; |
1962 | case OMAP_DSS_ROT_90: | |
1963 | *offset1 = screen_width * (fbh - 1) * ps; | |
1964 | if (field_offset) | |
1965 | *offset0 = *offset1 + field_offset * ps; | |
1966 | else | |
1967 | *offset0 = *offset1; | |
aed74b55 CM |
1968 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + |
1969 | y_predecim + (fieldmode ? 1 : 0), ps); | |
1970 | *pix_inc = pixinc(-x_predecim * screen_width, ps); | |
80c39712 TV |
1971 | break; |
1972 | case OMAP_DSS_ROT_180: | |
1973 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
1974 | if (field_offset) | |
1975 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
1976 | else | |
1977 | *offset0 = *offset1; | |
1978 | *row_inc = pixinc(-1 - | |
aed74b55 CM |
1979 | (y_predecim * screen_width - fbw * x_predecim) - |
1980 | (fieldmode ? screen_width : 0), ps); | |
1981 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1982 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1983 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
1984 | else | |
1985 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
1986 | break; |
1987 | case OMAP_DSS_ROT_270: | |
1988 | *offset1 = (fbw - 1) * ps; | |
1989 | if (field_offset) | |
1990 | *offset0 = *offset1 - field_offset * ps; | |
1991 | else | |
1992 | *offset0 = *offset1; | |
aed74b55 CM |
1993 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - |
1994 | y_predecim - (fieldmode ? 1 : 0), ps); | |
1995 | *pix_inc = pixinc(x_predecim * screen_width, ps); | |
80c39712 TV |
1996 | break; |
1997 | ||
1998 | /* mirroring */ | |
1999 | case OMAP_DSS_ROT_0 + 4: | |
2000 | *offset1 = (fbw - 1) * ps; | |
2001 | if (field_offset) | |
2002 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
2003 | else | |
2004 | *offset0 = *offset1; | |
aed74b55 | 2005 | *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + |
80c39712 TV |
2006 | (fieldmode ? screen_width : 0), |
2007 | ps); | |
aed74b55 CM |
2008 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2009 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2010 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
2011 | else | |
2012 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
2013 | break; |
2014 | ||
2015 | case OMAP_DSS_ROT_90 + 4: | |
2016 | *offset1 = 0; | |
2017 | if (field_offset) | |
2018 | *offset0 = *offset1 + field_offset * ps; | |
2019 | else | |
2020 | *offset0 = *offset1; | |
aed74b55 CM |
2021 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + |
2022 | y_predecim + (fieldmode ? 1 : 0), | |
80c39712 | 2023 | ps); |
aed74b55 | 2024 | *pix_inc = pixinc(x_predecim * screen_width, ps); |
80c39712 TV |
2025 | break; |
2026 | ||
2027 | case OMAP_DSS_ROT_180 + 4: | |
2028 | *offset1 = screen_width * (fbh - 1) * ps; | |
2029 | if (field_offset) | |
2030 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
2031 | else | |
2032 | *offset0 = *offset1; | |
aed74b55 | 2033 | *row_inc = pixinc(1 - y_predecim * screen_width * 2 - |
80c39712 TV |
2034 | (fieldmode ? screen_width : 0), |
2035 | ps); | |
aed74b55 CM |
2036 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2037 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2038 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
2039 | else | |
2040 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
2041 | break; |
2042 | ||
2043 | case OMAP_DSS_ROT_270 + 4: | |
2044 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
2045 | if (field_offset) | |
2046 | *offset0 = *offset1 - field_offset * ps; | |
2047 | else | |
2048 | *offset0 = *offset1; | |
aed74b55 CM |
2049 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - |
2050 | y_predecim - (fieldmode ? 1 : 0), | |
80c39712 | 2051 | ps); |
aed74b55 | 2052 | *pix_inc = pixinc(-x_predecim * screen_width, ps); |
80c39712 TV |
2053 | break; |
2054 | ||
2055 | default: | |
2056 | BUG(); | |
c6eee968 | 2057 | return; |
80c39712 TV |
2058 | } |
2059 | } | |
2060 | ||
65e006ff CM |
2061 | static void calc_tiler_rotation_offset(u16 screen_width, u16 width, |
2062 | enum omap_color_mode color_mode, bool fieldmode, | |
2063 | unsigned int field_offset, unsigned *offset0, unsigned *offset1, | |
2064 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) | |
2065 | { | |
2066 | u8 ps; | |
2067 | ||
2068 | switch (color_mode) { | |
2069 | case OMAP_DSS_COLOR_CLUT1: | |
2070 | case OMAP_DSS_COLOR_CLUT2: | |
2071 | case OMAP_DSS_COLOR_CLUT4: | |
2072 | case OMAP_DSS_COLOR_CLUT8: | |
2073 | BUG(); | |
2074 | return; | |
2075 | default: | |
2076 | ps = color_mode_to_bpp(color_mode) / 8; | |
2077 | break; | |
2078 | } | |
2079 | ||
2080 | DSSDBG("scrw %d, width %d\n", screen_width, width); | |
2081 | ||
2082 | /* | |
2083 | * field 0 = even field = bottom field | |
2084 | * field 1 = odd field = top field | |
2085 | */ | |
2086 | *offset1 = 0; | |
2087 | if (field_offset) | |
2088 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
2089 | else | |
2090 | *offset0 = *offset1; | |
2091 | *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + | |
2092 | (fieldmode ? screen_width : 0), ps); | |
2093 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
2094 | color_mode == OMAP_DSS_COLOR_UYVY) | |
2095 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
2096 | else | |
2097 | *pix_inc = pixinc(x_predecim, ps); | |
2098 | } | |
2099 | ||
7faa9233 CM |
2100 | /* |
2101 | * This function is used to avoid synclosts in OMAP3, because of some | |
2102 | * undocumented horizontal position and timing related limitations. | |
2103 | */ | |
465ec13f | 2104 | static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, |
81ab95b7 | 2105 | const struct omap_video_timings *t, u16 pos_x, |
e4998634 ID |
2106 | u16 width, u16 height, u16 out_width, u16 out_height, |
2107 | bool five_taps) | |
7faa9233 | 2108 | { |
230edc03 | 2109 | const int ds = DIV_ROUND_UP(height, out_height); |
3e8a6ff2 | 2110 | unsigned long nonactive; |
7faa9233 CM |
2111 | static const u8 limits[3] = { 8, 10, 20 }; |
2112 | u64 val, blank; | |
2113 | int i; | |
2114 | ||
81ab95b7 | 2115 | nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; |
7faa9233 CM |
2116 | |
2117 | i = 0; | |
2118 | if (out_height < height) | |
2119 | i++; | |
2120 | if (out_width < width) | |
2121 | i++; | |
81ab95b7 | 2122 | blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); |
7faa9233 CM |
2123 | DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); |
2124 | if (blank <= limits[i]) | |
2125 | return -EINVAL; | |
2126 | ||
e4998634 ID |
2127 | /* FIXME add checks for 3-tap filter once the limitations are known */ |
2128 | if (!five_taps) | |
2129 | return 0; | |
2130 | ||
7faa9233 CM |
2131 | /* |
2132 | * Pixel data should be prepared before visible display point starts. | |
2133 | * So, atleast DS-2 lines must have already been fetched by DISPC | |
2134 | * during nonactive - pos_x period. | |
2135 | */ | |
2136 | val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); | |
2137 | DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", | |
230edc03 TV |
2138 | val, max(0, ds - 2) * width); |
2139 | if (val < max(0, ds - 2) * width) | |
7faa9233 CM |
2140 | return -EINVAL; |
2141 | ||
2142 | /* | |
2143 | * All lines need to be refilled during the nonactive period of which | |
2144 | * only one line can be loaded during the active period. So, atleast | |
2145 | * DS - 1 lines should be loaded during nonactive period. | |
2146 | */ | |
2147 | val = div_u64((u64)nonactive * lclk, pclk); | |
2148 | DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", | |
230edc03 TV |
2149 | val, max(0, ds - 1) * width); |
2150 | if (val < max(0, ds - 1) * width) | |
7faa9233 CM |
2151 | return -EINVAL; |
2152 | ||
2153 | return 0; | |
2154 | } | |
2155 | ||
8702ee50 | 2156 | static unsigned long calc_core_clk_five_taps(unsigned long pclk, |
81ab95b7 AT |
2157 | const struct omap_video_timings *mgr_timings, u16 width, |
2158 | u16 height, u16 out_width, u16 out_height, | |
ff1b2cde | 2159 | enum omap_color_mode color_mode) |
80c39712 | 2160 | { |
8b53d991 | 2161 | u32 core_clk = 0; |
3e8a6ff2 | 2162 | u64 tmp; |
80c39712 | 2163 | |
7282f1b7 CM |
2164 | if (height <= out_height && width <= out_width) |
2165 | return (unsigned long) pclk; | |
2166 | ||
80c39712 | 2167 | if (height > out_height) { |
81ab95b7 | 2168 | unsigned int ppl = mgr_timings->x_res; |
80c39712 | 2169 | |
c582935c | 2170 | tmp = (u64)pclk * height * out_width; |
80c39712 | 2171 | do_div(tmp, 2 * out_height * ppl); |
8b53d991 | 2172 | core_clk = tmp; |
80c39712 | 2173 | |
2d9c5597 VS |
2174 | if (height > 2 * out_height) { |
2175 | if (ppl == out_width) | |
2176 | return 0; | |
2177 | ||
c582935c | 2178 | tmp = (u64)pclk * (height - 2 * out_height) * out_width; |
80c39712 | 2179 | do_div(tmp, 2 * out_height * (ppl - out_width)); |
8b53d991 | 2180 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
2181 | } |
2182 | } | |
2183 | ||
2184 | if (width > out_width) { | |
c582935c | 2185 | tmp = (u64)pclk * width; |
80c39712 | 2186 | do_div(tmp, out_width); |
8b53d991 | 2187 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
2188 | |
2189 | if (color_mode == OMAP_DSS_COLOR_RGB24U) | |
8b53d991 | 2190 | core_clk <<= 1; |
80c39712 TV |
2191 | } |
2192 | ||
8b53d991 | 2193 | return core_clk; |
80c39712 TV |
2194 | } |
2195 | ||
8702ee50 | 2196 | static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, |
8ba85306 | 2197 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
dcbe765b | 2198 | { |
dcbe765b CM |
2199 | if (height > out_height && width > out_width) |
2200 | return pclk * 4; | |
2201 | else | |
2202 | return pclk * 2; | |
2203 | } | |
2204 | ||
8702ee50 | 2205 | static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, |
8ba85306 | 2206 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
80c39712 TV |
2207 | { |
2208 | unsigned int hf, vf; | |
2209 | ||
2210 | /* | |
2211 | * FIXME how to determine the 'A' factor | |
2212 | * for the no downscaling case ? | |
2213 | */ | |
2214 | ||
2215 | if (width > 3 * out_width) | |
2216 | hf = 4; | |
2217 | else if (width > 2 * out_width) | |
2218 | hf = 3; | |
2219 | else if (width > out_width) | |
2220 | hf = 2; | |
2221 | else | |
2222 | hf = 1; | |
80c39712 TV |
2223 | if (height > out_height) |
2224 | vf = 2; | |
2225 | else | |
2226 | vf = 1; | |
2227 | ||
dcbe765b CM |
2228 | return pclk * vf * hf; |
2229 | } | |
2230 | ||
8702ee50 | 2231 | static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, |
8ba85306 | 2232 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
dcbe765b | 2233 | { |
8ba85306 AT |
2234 | /* |
2235 | * If the overlay/writeback is in mem to mem mode, there are no | |
2236 | * downscaling limitations with respect to pixel clock, return 1 as | |
2237 | * required core clock to represent that we have sufficient enough | |
2238 | * core clock to do maximum downscaling | |
2239 | */ | |
2240 | if (mem_to_mem) | |
2241 | return 1; | |
2242 | ||
dcbe765b CM |
2243 | if (width > out_width) |
2244 | return DIV_ROUND_UP(pclk, out_width) * width; | |
2245 | else | |
2246 | return pclk; | |
2247 | } | |
2248 | ||
0c6921de | 2249 | static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2250 | const struct omap_video_timings *mgr_timings, |
2251 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2252 | enum omap_color_mode color_mode, bool *five_taps, | |
2253 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2254 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2255 | { |
2256 | int error; | |
2257 | u16 in_width, in_height; | |
2258 | int min_factor = min(*decim_x, *decim_y); | |
2259 | const int maxsinglelinewidth = | |
2260 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
3e8a6ff2 | 2261 | |
dcbe765b CM |
2262 | *five_taps = false; |
2263 | ||
2264 | do { | |
eec77da2 TV |
2265 | in_height = height / *decim_y; |
2266 | in_width = width / *decim_x; | |
8702ee50 | 2267 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, |
8ba85306 | 2268 | in_height, out_width, out_height, mem_to_mem); |
dcbe765b CM |
2269 | error = (in_width > maxsinglelinewidth || !*core_clk || |
2270 | *core_clk > dispc_core_clk_rate()); | |
2271 | if (error) { | |
2272 | if (*decim_x == *decim_y) { | |
2273 | *decim_x = min_factor; | |
2274 | ++*decim_y; | |
2275 | } else { | |
2276 | swap(*decim_x, *decim_y); | |
2277 | if (*decim_x < *decim_y) | |
2278 | ++*decim_x; | |
2279 | } | |
2280 | } | |
2281 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | |
2282 | ||
3ce17b48 TV |
2283 | if (error) { |
2284 | DSSERR("failed to find scaling settings\n"); | |
2285 | return -EINVAL; | |
2286 | } | |
2287 | ||
dcbe765b CM |
2288 | if (in_width > maxsinglelinewidth) { |
2289 | DSSERR("Cannot scale max input width exceeded"); | |
2290 | return -EINVAL; | |
2291 | } | |
2292 | return 0; | |
2293 | } | |
2294 | ||
0c6921de | 2295 | static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2296 | const struct omap_video_timings *mgr_timings, |
2297 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2298 | enum omap_color_mode color_mode, bool *five_taps, | |
2299 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2300 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2301 | { |
2302 | int error; | |
2303 | u16 in_width, in_height; | |
dcbe765b CM |
2304 | const int maxsinglelinewidth = |
2305 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
2306 | ||
2307 | do { | |
eec77da2 TV |
2308 | in_height = height / *decim_y; |
2309 | in_width = width / *decim_x; | |
e4998634 | 2310 | *five_taps = in_height > out_height; |
dcbe765b CM |
2311 | |
2312 | if (in_width > maxsinglelinewidth) | |
2313 | if (in_height > out_height && | |
2314 | in_height < out_height * 2) | |
2315 | *five_taps = false; | |
e4998634 ID |
2316 | again: |
2317 | if (*five_taps) | |
2318 | *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, | |
2319 | in_width, in_height, out_width, | |
2320 | out_height, color_mode); | |
2321 | else | |
8702ee50 | 2322 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, |
8ba85306 AT |
2323 | in_height, out_width, out_height, |
2324 | mem_to_mem); | |
dcbe765b | 2325 | |
e4998634 ID |
2326 | error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, |
2327 | pos_x, in_width, in_height, out_width, | |
2328 | out_height, *five_taps); | |
2329 | if (error && *five_taps) { | |
2330 | *five_taps = false; | |
2331 | goto again; | |
2332 | } | |
2333 | ||
dcbe765b CM |
2334 | error = (error || in_width > maxsinglelinewidth * 2 || |
2335 | (in_width > maxsinglelinewidth && *five_taps) || | |
2336 | !*core_clk || *core_clk > dispc_core_clk_rate()); | |
ab6b2582 TV |
2337 | |
2338 | if (!error) { | |
2339 | /* verify that we're inside the limits of scaler */ | |
2340 | if (in_width / 4 > out_width) | |
2341 | error = 1; | |
2342 | ||
2343 | if (*five_taps) { | |
2344 | if (in_height / 4 > out_height) | |
2345 | error = 1; | |
dcbe765b | 2346 | } else { |
ab6b2582 TV |
2347 | if (in_height / 2 > out_height) |
2348 | error = 1; | |
dcbe765b CM |
2349 | } |
2350 | } | |
ab6b2582 | 2351 | |
7059e3d8 TV |
2352 | if (error) |
2353 | ++*decim_y; | |
dcbe765b CM |
2354 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); |
2355 | ||
3ce17b48 TV |
2356 | if (error) { |
2357 | DSSERR("failed to find scaling settings\n"); | |
2358 | return -EINVAL; | |
2359 | } | |
2360 | ||
f5a73482 TV |
2361 | if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, |
2362 | in_height, out_width, out_height, *five_taps)) { | |
dcbe765b CM |
2363 | DSSERR("horizontal timing too tight\n"); |
2364 | return -EINVAL; | |
7282f1b7 | 2365 | } |
dcbe765b CM |
2366 | |
2367 | if (in_width > (maxsinglelinewidth * 2)) { | |
2368 | DSSERR("Cannot setup scaling"); | |
2369 | DSSERR("width exceeds maximum width possible"); | |
2370 | return -EINVAL; | |
2371 | } | |
2372 | ||
2373 | if (in_width > maxsinglelinewidth && *five_taps) { | |
2374 | DSSERR("cannot setup scaling with five taps"); | |
2375 | return -EINVAL; | |
2376 | } | |
2377 | return 0; | |
2378 | } | |
2379 | ||
0c6921de | 2380 | static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2381 | const struct omap_video_timings *mgr_timings, |
2382 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2383 | enum omap_color_mode color_mode, bool *five_taps, | |
2384 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2385 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2386 | { |
2387 | u16 in_width, in_width_max; | |
2388 | int decim_x_min = *decim_x; | |
eec77da2 | 2389 | u16 in_height = height / *decim_y; |
dcbe765b CM |
2390 | const int maxsinglelinewidth = |
2391 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
8ba85306 | 2392 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
3e8a6ff2 | 2393 | |
5d501085 AT |
2394 | if (mem_to_mem) { |
2395 | in_width_max = out_width * maxdownscale; | |
2396 | } else { | |
8ba85306 AT |
2397 | in_width_max = dispc_core_clk_rate() / |
2398 | DIV_ROUND_UP(pclk, out_width); | |
5d501085 | 2399 | } |
dcbe765b | 2400 | |
dcbe765b CM |
2401 | *decim_x = DIV_ROUND_UP(width, in_width_max); |
2402 | ||
2403 | *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; | |
2404 | if (*decim_x > *x_predecim) | |
2405 | return -EINVAL; | |
2406 | ||
2407 | do { | |
eec77da2 | 2408 | in_width = width / *decim_x; |
dcbe765b CM |
2409 | } while (*decim_x <= *x_predecim && |
2410 | in_width > maxsinglelinewidth && ++*decim_x); | |
2411 | ||
2412 | if (in_width > maxsinglelinewidth) { | |
2413 | DSSERR("Cannot scale width exceeds max line width"); | |
2414 | return -EINVAL; | |
2415 | } | |
2416 | ||
8702ee50 | 2417 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, |
8ba85306 | 2418 | out_width, out_height, mem_to_mem); |
dcbe765b | 2419 | return 0; |
80c39712 TV |
2420 | } |
2421 | ||
e4c5ae7f TV |
2422 | #define DIV_FRAC(dividend, divisor) \ |
2423 | ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) | |
2424 | ||
74e16458 | 2425 | static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, |
3e8a6ff2 | 2426 | enum omap_overlay_caps caps, |
81ab95b7 AT |
2427 | const struct omap_video_timings *mgr_timings, |
2428 | u16 width, u16 height, u16 out_width, u16 out_height, | |
aed74b55 | 2429 | enum omap_color_mode color_mode, bool *five_taps, |
d557a9cf | 2430 | int *x_predecim, int *y_predecim, u16 pos_x, |
8ba85306 | 2431 | enum omap_dss_rotation_type rotation_type, bool mem_to_mem) |
79ad75f2 | 2432 | { |
0373cac6 | 2433 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
aed74b55 | 2434 | const int max_decim_limit = 16; |
8b53d991 | 2435 | unsigned long core_clk = 0; |
dcbe765b | 2436 | int decim_x, decim_y, ret; |
79ad75f2 | 2437 | |
f95cb5eb TV |
2438 | if (width == out_width && height == out_height) |
2439 | return 0; | |
2440 | ||
4e1d3ca0 TV |
2441 | if (pclk == 0 || mgr_timings->pixelclock == 0) { |
2442 | DSSERR("cannot calculate scaling settings: pclk is zero\n"); | |
2443 | return -EINVAL; | |
2444 | } | |
2445 | ||
5b54ed3e | 2446 | if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) |
f95cb5eb | 2447 | return -EINVAL; |
79ad75f2 | 2448 | |
74e16458 | 2449 | if (mem_to_mem) { |
1c031441 AT |
2450 | *x_predecim = *y_predecim = 1; |
2451 | } else { | |
2452 | *x_predecim = max_decim_limit; | |
2453 | *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && | |
2454 | dss_has_feature(FEAT_BURST_2D)) ? | |
2455 | 2 : max_decim_limit; | |
2456 | } | |
aed74b55 CM |
2457 | |
2458 | if (color_mode == OMAP_DSS_COLOR_CLUT1 || | |
2459 | color_mode == OMAP_DSS_COLOR_CLUT2 || | |
2460 | color_mode == OMAP_DSS_COLOR_CLUT4 || | |
2461 | color_mode == OMAP_DSS_COLOR_CLUT8) { | |
2462 | *x_predecim = 1; | |
2463 | *y_predecim = 1; | |
2464 | *five_taps = false; | |
2465 | return 0; | |
2466 | } | |
2467 | ||
2468 | decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); | |
2469 | decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); | |
2470 | ||
aed74b55 | 2471 | if (decim_x > *x_predecim || out_width > width * 8) |
79ad75f2 AT |
2472 | return -EINVAL; |
2473 | ||
aed74b55 | 2474 | if (decim_y > *y_predecim || out_height > height * 8) |
79ad75f2 AT |
2475 | return -EINVAL; |
2476 | ||
0c6921de | 2477 | ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, |
3e8a6ff2 | 2478 | out_width, out_height, color_mode, five_taps, |
8ba85306 AT |
2479 | x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, |
2480 | mem_to_mem); | |
dcbe765b CM |
2481 | if (ret) |
2482 | return ret; | |
79ad75f2 | 2483 | |
e4c5ae7f TV |
2484 | DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n", |
2485 | width, height, | |
2486 | out_width, out_height, | |
2487 | out_width / width, DIV_FRAC(out_width, width), | |
2488 | out_height / height, DIV_FRAC(out_height, height), | |
2489 | ||
2490 | decim_x, decim_y, | |
2491 | width / decim_x, height / decim_y, | |
2492 | out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), | |
2493 | out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), | |
2494 | ||
2495 | *five_taps ? 5 : 3, | |
2496 | core_clk, dispc_core_clk_rate()); | |
79ad75f2 | 2497 | |
8b53d991 | 2498 | if (!core_clk || core_clk > dispc_core_clk_rate()) { |
79ad75f2 | 2499 | DSSERR("failed to set up scaling, " |
8b53d991 CM |
2500 | "required core clk rate = %lu Hz, " |
2501 | "current core clk rate = %lu Hz\n", | |
2502 | core_clk, dispc_core_clk_rate()); | |
79ad75f2 AT |
2503 | return -EINVAL; |
2504 | } | |
2505 | ||
aed74b55 CM |
2506 | *x_predecim = decim_x; |
2507 | *y_predecim = decim_y; | |
79ad75f2 AT |
2508 | return 0; |
2509 | } | |
2510 | ||
f9b719b6 TV |
2511 | int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, |
2512 | const struct omap_overlay_info *oi, | |
2513 | const struct omap_video_timings *timings, | |
2514 | int *x_predecim, int *y_predecim) | |
2515 | { | |
2516 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); | |
2517 | bool five_taps = true; | |
62a83183 | 2518 | bool fieldmode = false; |
f9b719b6 TV |
2519 | u16 in_height = oi->height; |
2520 | u16 in_width = oi->width; | |
2521 | bool ilace = timings->interlace; | |
2522 | u16 out_width, out_height; | |
2523 | int pos_x = oi->pos_x; | |
2524 | unsigned long pclk = dispc_mgr_pclk_rate(channel); | |
2525 | unsigned long lclk = dispc_mgr_lclk_rate(channel); | |
2526 | ||
2527 | out_width = oi->out_width == 0 ? oi->width : oi->out_width; | |
2528 | out_height = oi->out_height == 0 ? oi->height : oi->out_height; | |
2529 | ||
2530 | if (ilace && oi->height == out_height) | |
62a83183 | 2531 | fieldmode = true; |
f9b719b6 TV |
2532 | |
2533 | if (ilace) { | |
2534 | if (fieldmode) | |
2535 | in_height /= 2; | |
2536 | out_height /= 2; | |
2537 | ||
2538 | DSSDBG("adjusting for ilace: height %d, out_height %d\n", | |
2539 | in_height, out_height); | |
2540 | } | |
2541 | ||
2542 | if (!dss_feat_color_mode_supported(plane, oi->color_mode)) | |
2543 | return -EINVAL; | |
2544 | ||
2545 | return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width, | |
2546 | in_height, out_width, out_height, oi->color_mode, | |
2547 | &five_taps, x_predecim, y_predecim, pos_x, | |
2548 | oi->rotation_type, false); | |
2549 | } | |
348be69d | 2550 | EXPORT_SYMBOL(dispc_ovl_check); |
f9b719b6 | 2551 | |
84a880fd | 2552 | static int dispc_ovl_setup_common(enum omap_plane plane, |
3e8a6ff2 AT |
2553 | enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, |
2554 | u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, | |
2555 | u16 out_width, u16 out_height, enum omap_color_mode color_mode, | |
2556 | u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, | |
2557 | u8 global_alpha, enum omap_dss_rotation_type rotation_type, | |
8ba85306 AT |
2558 | bool replication, const struct omap_video_timings *mgr_timings, |
2559 | bool mem_to_mem) | |
80c39712 | 2560 | { |
7282f1b7 | 2561 | bool five_taps = true; |
62a83183 | 2562 | bool fieldmode = false; |
79ad75f2 | 2563 | int r, cconv = 0; |
80c39712 TV |
2564 | unsigned offset0, offset1; |
2565 | s32 row_inc; | |
2566 | s32 pix_inc; | |
6be0d73e | 2567 | u16 frame_width, frame_height; |
80c39712 | 2568 | unsigned int field_offset = 0; |
84a880fd AT |
2569 | u16 in_height = height; |
2570 | u16 in_width = width; | |
aed74b55 | 2571 | int x_predecim = 1, y_predecim = 1; |
8050cbe4 | 2572 | bool ilace = mgr_timings->interlace; |
74e16458 TV |
2573 | unsigned long pclk = dispc_plane_pclk_rate(plane); |
2574 | unsigned long lclk = dispc_plane_lclk_rate(plane); | |
e6d80f95 | 2575 | |
e566658f | 2576 | if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) |
80c39712 TV |
2577 | return -EINVAL; |
2578 | ||
c4661b33 TV |
2579 | switch (color_mode) { |
2580 | case OMAP_DSS_COLOR_YUV2: | |
2581 | case OMAP_DSS_COLOR_UYVY: | |
2582 | case OMAP_DSS_COLOR_NV12: | |
2583 | if (in_width & 1) { | |
2584 | DSSERR("input width %d is not even for YUV format\n", | |
2585 | in_width); | |
2586 | return -EINVAL; | |
2587 | } | |
2588 | break; | |
2589 | ||
2590 | default: | |
2591 | break; | |
2592 | } | |
2593 | ||
84a880fd AT |
2594 | out_width = out_width == 0 ? width : out_width; |
2595 | out_height = out_height == 0 ? height : out_height; | |
cf073668 | 2596 | |
84a880fd | 2597 | if (ilace && height == out_height) |
62a83183 | 2598 | fieldmode = true; |
80c39712 TV |
2599 | |
2600 | if (ilace) { | |
2601 | if (fieldmode) | |
aed74b55 | 2602 | in_height /= 2; |
8eeb7019 | 2603 | pos_y /= 2; |
aed74b55 | 2604 | out_height /= 2; |
80c39712 TV |
2605 | |
2606 | DSSDBG("adjusting for ilace: height %d, pos_y %d, " | |
84a880fd AT |
2607 | "out_height %d\n", in_height, pos_y, |
2608 | out_height); | |
80c39712 TV |
2609 | } |
2610 | ||
84a880fd | 2611 | if (!dss_feat_color_mode_supported(plane, color_mode)) |
8dad2ab6 AT |
2612 | return -EINVAL; |
2613 | ||
74e16458 | 2614 | r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width, |
84a880fd AT |
2615 | in_height, out_width, out_height, color_mode, |
2616 | &five_taps, &x_predecim, &y_predecim, pos_x, | |
8ba85306 | 2617 | rotation_type, mem_to_mem); |
79ad75f2 AT |
2618 | if (r) |
2619 | return r; | |
80c39712 | 2620 | |
eec77da2 TV |
2621 | in_width = in_width / x_predecim; |
2622 | in_height = in_height / y_predecim; | |
aed74b55 | 2623 | |
c4661b33 TV |
2624 | if (x_predecim > 1 || y_predecim > 1) |
2625 | DSSDBG("predecimation %d x %x, new input size %d x %d\n", | |
2626 | x_predecim, y_predecim, in_width, in_height); | |
2627 | ||
2628 | switch (color_mode) { | |
2629 | case OMAP_DSS_COLOR_YUV2: | |
2630 | case OMAP_DSS_COLOR_UYVY: | |
2631 | case OMAP_DSS_COLOR_NV12: | |
2632 | if (in_width & 1) { | |
2633 | DSSDBG("predecimated input width is not even for YUV format\n"); | |
2634 | DSSDBG("adjusting input width %d -> %d\n", | |
2635 | in_width, in_width & ~1); | |
2636 | ||
2637 | in_width &= ~1; | |
2638 | } | |
2639 | break; | |
2640 | ||
2641 | default: | |
2642 | break; | |
2643 | } | |
2644 | ||
84a880fd AT |
2645 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2646 | color_mode == OMAP_DSS_COLOR_UYVY || | |
2647 | color_mode == OMAP_DSS_COLOR_NV12) | |
79ad75f2 | 2648 | cconv = 1; |
80c39712 TV |
2649 | |
2650 | if (ilace && !fieldmode) { | |
2651 | /* | |
2652 | * when downscaling the bottom field may have to start several | |
2653 | * source lines below the top field. Unfortunately ACCUI | |
2654 | * registers will only hold the fractional part of the offset | |
2655 | * so the integer part must be added to the base address of the | |
2656 | * bottom field. | |
2657 | */ | |
aed74b55 | 2658 | if (!in_height || in_height == out_height) |
80c39712 TV |
2659 | field_offset = 0; |
2660 | else | |
aed74b55 | 2661 | field_offset = in_height / out_height / 2; |
80c39712 TV |
2662 | } |
2663 | ||
2664 | /* Fields are independent but interleaved in memory. */ | |
2665 | if (fieldmode) | |
2666 | field_offset = 1; | |
2667 | ||
c6eee968 TV |
2668 | offset0 = 0; |
2669 | offset1 = 0; | |
2670 | row_inc = 0; | |
2671 | pix_inc = 0; | |
2672 | ||
6be0d73e AT |
2673 | if (plane == OMAP_DSS_WB) { |
2674 | frame_width = out_width; | |
2675 | frame_height = out_height; | |
2676 | } else { | |
2677 | frame_width = in_width; | |
2678 | frame_height = height; | |
2679 | } | |
2680 | ||
84a880fd | 2681 | if (rotation_type == OMAP_DSS_ROT_TILER) |
6be0d73e | 2682 | calc_tiler_rotation_offset(screen_width, frame_width, |
84a880fd | 2683 | color_mode, fieldmode, field_offset, |
65e006ff CM |
2684 | &offset0, &offset1, &row_inc, &pix_inc, |
2685 | x_predecim, y_predecim); | |
84a880fd | 2686 | else if (rotation_type == OMAP_DSS_ROT_DMA) |
6be0d73e AT |
2687 | calc_dma_rotation_offset(rotation, mirror, screen_width, |
2688 | frame_width, frame_height, | |
84a880fd | 2689 | color_mode, fieldmode, field_offset, |
aed74b55 CM |
2690 | &offset0, &offset1, &row_inc, &pix_inc, |
2691 | x_predecim, y_predecim); | |
80c39712 | 2692 | else |
84a880fd | 2693 | calc_vrfb_rotation_offset(rotation, mirror, |
6be0d73e | 2694 | screen_width, frame_width, frame_height, |
84a880fd | 2695 | color_mode, fieldmode, field_offset, |
aed74b55 CM |
2696 | &offset0, &offset1, &row_inc, &pix_inc, |
2697 | x_predecim, y_predecim); | |
80c39712 TV |
2698 | |
2699 | DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", | |
2700 | offset0, offset1, row_inc, pix_inc); | |
2701 | ||
84a880fd | 2702 | dispc_ovl_set_color_mode(plane, color_mode); |
80c39712 | 2703 | |
84a880fd | 2704 | dispc_ovl_configure_burst_type(plane, rotation_type); |
65e006ff | 2705 | |
84a880fd AT |
2706 | dispc_ovl_set_ba0(plane, paddr + offset0); |
2707 | dispc_ovl_set_ba1(plane, paddr + offset1); | |
80c39712 | 2708 | |
84a880fd AT |
2709 | if (OMAP_DSS_COLOR_NV12 == color_mode) { |
2710 | dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); | |
2711 | dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); | |
0d66cbb5 AJ |
2712 | } |
2713 | ||
f2aee319 TV |
2714 | if (dispc.feat->last_pixel_inc_missing) |
2715 | row_inc += pix_inc - 1; | |
2716 | ||
f0e5caab TV |
2717 | dispc_ovl_set_row_inc(plane, row_inc); |
2718 | dispc_ovl_set_pix_inc(plane, pix_inc); | |
80c39712 | 2719 | |
84a880fd | 2720 | DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, |
aed74b55 | 2721 | in_height, out_width, out_height); |
80c39712 | 2722 | |
84a880fd | 2723 | dispc_ovl_set_pos(plane, caps, pos_x, pos_y); |
80c39712 | 2724 | |
78b687fc | 2725 | dispc_ovl_set_input_size(plane, in_width, in_height); |
80c39712 | 2726 | |
5b54ed3e | 2727 | if (caps & OMAP_DSS_OVL_CAP_SCALE) { |
aed74b55 CM |
2728 | dispc_ovl_set_scaling(plane, in_width, in_height, out_width, |
2729 | out_height, ilace, five_taps, fieldmode, | |
84a880fd | 2730 | color_mode, rotation); |
78b687fc | 2731 | dispc_ovl_set_output_size(plane, out_width, out_height); |
f0e5caab | 2732 | dispc_ovl_set_vid_color_conv(plane, cconv); |
80c39712 TV |
2733 | } |
2734 | ||
c35eeb2e AT |
2735 | dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror, |
2736 | color_mode); | |
80c39712 | 2737 | |
84a880fd AT |
2738 | dispc_ovl_set_zorder(plane, caps, zorder); |
2739 | dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); | |
2740 | dispc_ovl_setup_global_alpha(plane, caps, global_alpha); | |
80c39712 | 2741 | |
d79db853 | 2742 | dispc_ovl_enable_replication(plane, caps, replication); |
c3d92529 | 2743 | |
80c39712 TV |
2744 | return 0; |
2745 | } | |
2746 | ||
84a880fd | 2747 | int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, |
8ba85306 AT |
2748 | bool replication, const struct omap_video_timings *mgr_timings, |
2749 | bool mem_to_mem) | |
84a880fd AT |
2750 | { |
2751 | int r; | |
16bf20c7 | 2752 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); |
84a880fd AT |
2753 | enum omap_channel channel; |
2754 | ||
2755 | channel = dispc_ovl_get_channel_out(plane); | |
2756 | ||
24f13a66 AB |
2757 | DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" |
2758 | " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", | |
2759 | plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, | |
84a880fd AT |
2760 | oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, |
2761 | oi->color_mode, oi->rotation, oi->mirror, channel, replication); | |
2762 | ||
16bf20c7 | 2763 | r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, |
3e8a6ff2 AT |
2764 | oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, |
2765 | oi->out_width, oi->out_height, oi->color_mode, oi->rotation, | |
2766 | oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, | |
8ba85306 | 2767 | oi->rotation_type, replication, mgr_timings, mem_to_mem); |
84a880fd AT |
2768 | |
2769 | return r; | |
2770 | } | |
348be69d | 2771 | EXPORT_SYMBOL(dispc_ovl_setup); |
84a880fd | 2772 | |
749feffa | 2773 | int dispc_wb_setup(const struct omap_dss_writeback_info *wi, |
9e4a0fc7 | 2774 | bool mem_to_mem, const struct omap_video_timings *mgr_timings) |
749feffa AT |
2775 | { |
2776 | int r; | |
9e4a0fc7 | 2777 | u32 l; |
749feffa AT |
2778 | enum omap_plane plane = OMAP_DSS_WB; |
2779 | const int pos_x = 0, pos_y = 0; | |
2780 | const u8 zorder = 0, global_alpha = 0; | |
2781 | const bool replication = false; | |
9e4a0fc7 | 2782 | bool truncation; |
749feffa AT |
2783 | int in_width = mgr_timings->x_res; |
2784 | int in_height = mgr_timings->y_res; | |
2785 | enum omap_overlay_caps caps = | |
2786 | OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; | |
2787 | ||
2788 | DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " | |
2789 | "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width, | |
2790 | in_height, wi->width, wi->height, wi->color_mode, wi->rotation, | |
2791 | wi->mirror); | |
2792 | ||
2793 | r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr, | |
2794 | wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, | |
2795 | wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder, | |
2796 | wi->pre_mult_alpha, global_alpha, wi->rotation_type, | |
9e4a0fc7 AT |
2797 | replication, mgr_timings, mem_to_mem); |
2798 | ||
2799 | switch (wi->color_mode) { | |
2800 | case OMAP_DSS_COLOR_RGB16: | |
2801 | case OMAP_DSS_COLOR_RGB24P: | |
2802 | case OMAP_DSS_COLOR_ARGB16: | |
2803 | case OMAP_DSS_COLOR_RGBA16: | |
2804 | case OMAP_DSS_COLOR_RGB12U: | |
2805 | case OMAP_DSS_COLOR_ARGB16_1555: | |
2806 | case OMAP_DSS_COLOR_XRGB16_1555: | |
2807 | case OMAP_DSS_COLOR_RGBX16: | |
2808 | truncation = true; | |
2809 | break; | |
2810 | default: | |
2811 | truncation = false; | |
2812 | break; | |
2813 | } | |
2814 | ||
2815 | /* setup extra DISPC_WB_ATTRIBUTES */ | |
2816 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
2817 | l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ | |
2818 | l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ | |
2819 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); | |
749feffa AT |
2820 | |
2821 | return r; | |
2822 | } | |
2823 | ||
f0e5caab | 2824 | int dispc_ovl_enable(enum omap_plane plane, bool enable) |
80c39712 | 2825 | { |
e6d80f95 TV |
2826 | DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); |
2827 | ||
9b372c2d | 2828 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); |
e6d80f95 TV |
2829 | |
2830 | return 0; | |
80c39712 | 2831 | } |
348be69d | 2832 | EXPORT_SYMBOL(dispc_ovl_enable); |
80c39712 | 2833 | |
04bd8ac1 TV |
2834 | bool dispc_ovl_enabled(enum omap_plane plane) |
2835 | { | |
2836 | return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); | |
2837 | } | |
348be69d | 2838 | EXPORT_SYMBOL(dispc_ovl_enabled); |
04bd8ac1 | 2839 | |
f1a813d3 | 2840 | void dispc_mgr_enable(enum omap_channel channel, bool enable) |
80c39712 | 2841 | { |
efa70b3b CM |
2842 | mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); |
2843 | /* flush posted write */ | |
2844 | mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); | |
80c39712 | 2845 | } |
348be69d | 2846 | EXPORT_SYMBOL(dispc_mgr_enable); |
80c39712 | 2847 | |
65398511 TV |
2848 | bool dispc_mgr_is_enabled(enum omap_channel channel) |
2849 | { | |
2850 | return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); | |
2851 | } | |
348be69d | 2852 | EXPORT_SYMBOL(dispc_mgr_is_enabled); |
65398511 | 2853 | |
0b23e5b8 AT |
2854 | void dispc_wb_enable(bool enable) |
2855 | { | |
916188a4 | 2856 | dispc_ovl_enable(OMAP_DSS_WB, enable); |
0b23e5b8 AT |
2857 | } |
2858 | ||
2859 | bool dispc_wb_is_enabled(void) | |
2860 | { | |
916188a4 | 2861 | return dispc_ovl_enabled(OMAP_DSS_WB); |
0b23e5b8 AT |
2862 | } |
2863 | ||
fb2cec1f | 2864 | static void dispc_lcd_enable_signal_polarity(bool act_high) |
80c39712 | 2865 | { |
6ced40bf AT |
2866 | if (!dss_has_feature(FEAT_LCDENABLEPOL)) |
2867 | return; | |
2868 | ||
80c39712 | 2869 | REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); |
80c39712 TV |
2870 | } |
2871 | ||
2872 | void dispc_lcd_enable_signal(bool enable) | |
2873 | { | |
6ced40bf AT |
2874 | if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) |
2875 | return; | |
2876 | ||
80c39712 | 2877 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); |
80c39712 TV |
2878 | } |
2879 | ||
2880 | void dispc_pck_free_enable(bool enable) | |
2881 | { | |
6ced40bf AT |
2882 | if (!dss_has_feature(FEAT_PCKFREEENABLE)) |
2883 | return; | |
2884 | ||
80c39712 | 2885 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); |
80c39712 TV |
2886 | } |
2887 | ||
fb2cec1f | 2888 | static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) |
80c39712 | 2889 | { |
efa70b3b | 2890 | mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); |
80c39712 TV |
2891 | } |
2892 | ||
2893 | ||
fb2cec1f | 2894 | static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) |
80c39712 | 2895 | { |
d21f43bc | 2896 | mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); |
80c39712 TV |
2897 | } |
2898 | ||
2899 | void dispc_set_loadmode(enum omap_dss_load_mode mode) | |
2900 | { | |
80c39712 | 2901 | REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); |
80c39712 TV |
2902 | } |
2903 | ||
2904 | ||
c64dca40 | 2905 | static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) |
80c39712 | 2906 | { |
8613b000 | 2907 | dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); |
80c39712 TV |
2908 | } |
2909 | ||
c64dca40 | 2910 | static void dispc_mgr_set_trans_key(enum omap_channel ch, |
80c39712 TV |
2911 | enum omap_dss_trans_key_type type, |
2912 | u32 trans_key) | |
2913 | { | |
efa70b3b | 2914 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); |
80c39712 | 2915 | |
8613b000 | 2916 | dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); |
80c39712 TV |
2917 | } |
2918 | ||
c64dca40 | 2919 | static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) |
80c39712 | 2920 | { |
efa70b3b | 2921 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); |
80c39712 | 2922 | } |
11354dd5 | 2923 | |
c64dca40 TV |
2924 | static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, |
2925 | bool enable) | |
80c39712 | 2926 | { |
11354dd5 | 2927 | if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) |
80c39712 TV |
2928 | return; |
2929 | ||
80c39712 TV |
2930 | if (ch == OMAP_DSS_CHANNEL_LCD) |
2931 | REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); | |
2a205f34 | 2932 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
80c39712 | 2933 | REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); |
80c39712 | 2934 | } |
11354dd5 | 2935 | |
c64dca40 | 2936 | void dispc_mgr_setup(enum omap_channel channel, |
a8f3fcd1 | 2937 | const struct omap_overlay_manager_info *info) |
c64dca40 TV |
2938 | { |
2939 | dispc_mgr_set_default_color(channel, info->default_color); | |
2940 | dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); | |
2941 | dispc_mgr_enable_trans_key(channel, info->trans_enabled); | |
2942 | dispc_mgr_enable_alpha_fixed_zorder(channel, | |
2943 | info->partial_alpha_enabled); | |
2944 | if (dss_has_feature(FEAT_CPR)) { | |
2945 | dispc_mgr_enable_cpr(channel, info->cpr_enable); | |
2946 | dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); | |
2947 | } | |
2948 | } | |
348be69d | 2949 | EXPORT_SYMBOL(dispc_mgr_setup); |
80c39712 | 2950 | |
fb2cec1f | 2951 | static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) |
80c39712 TV |
2952 | { |
2953 | int code; | |
2954 | ||
2955 | switch (data_lines) { | |
2956 | case 12: | |
2957 | code = 0; | |
2958 | break; | |
2959 | case 16: | |
2960 | code = 1; | |
2961 | break; | |
2962 | case 18: | |
2963 | code = 2; | |
2964 | break; | |
2965 | case 24: | |
2966 | code = 3; | |
2967 | break; | |
2968 | default: | |
2969 | BUG(); | |
2970 | return; | |
2971 | } | |
2972 | ||
efa70b3b | 2973 | mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); |
80c39712 TV |
2974 | } |
2975 | ||
fb2cec1f | 2976 | static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) |
80c39712 TV |
2977 | { |
2978 | u32 l; | |
569969d6 | 2979 | int gpout0, gpout1; |
80c39712 TV |
2980 | |
2981 | switch (mode) { | |
569969d6 AT |
2982 | case DSS_IO_PAD_MODE_RESET: |
2983 | gpout0 = 0; | |
2984 | gpout1 = 0; | |
80c39712 | 2985 | break; |
569969d6 AT |
2986 | case DSS_IO_PAD_MODE_RFBI: |
2987 | gpout0 = 1; | |
80c39712 TV |
2988 | gpout1 = 0; |
2989 | break; | |
569969d6 AT |
2990 | case DSS_IO_PAD_MODE_BYPASS: |
2991 | gpout0 = 1; | |
80c39712 TV |
2992 | gpout1 = 1; |
2993 | break; | |
80c39712 TV |
2994 | default: |
2995 | BUG(); | |
2996 | return; | |
2997 | } | |
2998 | ||
569969d6 AT |
2999 | l = dispc_read_reg(DISPC_CONTROL); |
3000 | l = FLD_MOD(l, gpout0, 15, 15); | |
3001 | l = FLD_MOD(l, gpout1, 16, 16); | |
3002 | dispc_write_reg(DISPC_CONTROL, l); | |
3003 | } | |
3004 | ||
fb2cec1f | 3005 | static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) |
569969d6 | 3006 | { |
efa70b3b | 3007 | mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); |
80c39712 TV |
3008 | } |
3009 | ||
fb2cec1f TV |
3010 | void dispc_mgr_set_lcd_config(enum omap_channel channel, |
3011 | const struct dss_lcd_mgr_config *config) | |
3012 | { | |
3013 | dispc_mgr_set_io_pad_mode(config->io_pad_mode); | |
3014 | ||
3015 | dispc_mgr_enable_stallmode(channel, config->stallmode); | |
3016 | dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); | |
3017 | ||
3018 | dispc_mgr_set_clock_div(channel, &config->clock_info); | |
3019 | ||
3020 | dispc_mgr_set_tft_data_lines(channel, config->video_port_width); | |
3021 | ||
3022 | dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); | |
3023 | ||
3024 | dispc_mgr_set_lcd_type_tft(channel); | |
3025 | } | |
348be69d | 3026 | EXPORT_SYMBOL(dispc_mgr_set_lcd_config); |
fb2cec1f | 3027 | |
8f366162 AT |
3028 | static bool _dispc_mgr_size_ok(u16 width, u16 height) |
3029 | { | |
33b89928 AT |
3030 | return width <= dispc.feat->mgr_width_max && |
3031 | height <= dispc.feat->mgr_height_max; | |
8f366162 AT |
3032 | } |
3033 | ||
80c39712 TV |
3034 | static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, |
3035 | int vsw, int vfp, int vbp) | |
3036 | { | |
dcbe765b CM |
3037 | if (hsw < 1 || hsw > dispc.feat->sw_max || |
3038 | hfp < 1 || hfp > dispc.feat->hp_max || | |
3039 | hbp < 1 || hbp > dispc.feat->hp_max || | |
3040 | vsw < 1 || vsw > dispc.feat->sw_max || | |
3041 | vfp < 0 || vfp > dispc.feat->vp_max || | |
3042 | vbp < 0 || vbp > dispc.feat->vp_max) | |
3043 | return false; | |
80c39712 TV |
3044 | return true; |
3045 | } | |
3046 | ||
ca5ca69c AT |
3047 | static bool _dispc_mgr_pclk_ok(enum omap_channel channel, |
3048 | unsigned long pclk) | |
3049 | { | |
3050 | if (dss_mgr_is_lcd(channel)) | |
3051 | return pclk <= dispc.feat->max_lcd_pclk ? true : false; | |
3052 | else | |
3053 | return pclk <= dispc.feat->max_tv_pclk ? true : false; | |
3054 | } | |
3055 | ||
8f366162 | 3056 | bool dispc_mgr_timings_ok(enum omap_channel channel, |
b917fa39 | 3057 | const struct omap_video_timings *timings) |
80c39712 | 3058 | { |
eadd33bb TV |
3059 | if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) |
3060 | return false; | |
8f366162 | 3061 | |
eadd33bb TV |
3062 | if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) |
3063 | return false; | |
ca5ca69c AT |
3064 | |
3065 | if (dss_mgr_is_lcd(channel)) { | |
beb8384d | 3066 | /* TODO: OMAP4+ supports interlace for LCD outputs */ |
eadd33bb TV |
3067 | if (timings->interlace) |
3068 | return false; | |
beb8384d | 3069 | |
eadd33bb | 3070 | if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, |
ca5ca69c | 3071 | timings->hbp, timings->vsw, timings->vfp, |
eadd33bb TV |
3072 | timings->vbp)) |
3073 | return false; | |
ca5ca69c | 3074 | } |
8f366162 | 3075 | |
eadd33bb | 3076 | return true; |
80c39712 TV |
3077 | } |
3078 | ||
26d9dd0d | 3079 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, |
655e2941 AT |
3080 | int hfp, int hbp, int vsw, int vfp, int vbp, |
3081 | enum omap_dss_signal_level vsync_level, | |
3082 | enum omap_dss_signal_level hsync_level, | |
3083 | enum omap_dss_signal_edge data_pclk_edge, | |
3084 | enum omap_dss_signal_level de_level, | |
3085 | enum omap_dss_signal_edge sync_pclk_edge) | |
3086 | ||
80c39712 | 3087 | { |
655e2941 | 3088 | u32 timing_h, timing_v, l; |
ed351881 | 3089 | bool onoff, rf, ipc, vs, hs, de; |
80c39712 | 3090 | |
dcbe765b CM |
3091 | timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | |
3092 | FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | | |
3093 | FLD_VAL(hbp-1, dispc.feat->bp_start, 20); | |
3094 | timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | | |
3095 | FLD_VAL(vfp, dispc.feat->fp_start, 8) | | |
3096 | FLD_VAL(vbp, dispc.feat->bp_start, 20); | |
80c39712 | 3097 | |
64ba4f74 SS |
3098 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); |
3099 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); | |
655e2941 | 3100 | |
ed351881 TV |
3101 | switch (vsync_level) { |
3102 | case OMAPDSS_SIG_ACTIVE_LOW: | |
3103 | vs = true; | |
3104 | break; | |
3105 | case OMAPDSS_SIG_ACTIVE_HIGH: | |
3106 | vs = false; | |
3107 | break; | |
3108 | default: | |
3109 | BUG(); | |
3110 | } | |
3111 | ||
3112 | switch (hsync_level) { | |
3113 | case OMAPDSS_SIG_ACTIVE_LOW: | |
3114 | hs = true; | |
3115 | break; | |
3116 | case OMAPDSS_SIG_ACTIVE_HIGH: | |
3117 | hs = false; | |
3118 | break; | |
3119 | default: | |
3120 | BUG(); | |
3121 | } | |
3122 | ||
3123 | switch (de_level) { | |
3124 | case OMAPDSS_SIG_ACTIVE_LOW: | |
3125 | de = true; | |
3126 | break; | |
3127 | case OMAPDSS_SIG_ACTIVE_HIGH: | |
3128 | de = false; | |
3129 | break; | |
3130 | default: | |
3131 | BUG(); | |
3132 | } | |
3133 | ||
655e2941 AT |
3134 | switch (data_pclk_edge) { |
3135 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
3136 | ipc = false; | |
3137 | break; | |
3138 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: | |
3139 | ipc = true; | |
3140 | break; | |
655e2941 AT |
3141 | default: |
3142 | BUG(); | |
3143 | } | |
3144 | ||
7a16360d TV |
3145 | /* always use the 'rf' setting */ |
3146 | onoff = true; | |
3147 | ||
655e2941 | 3148 | switch (sync_pclk_edge) { |
655e2941 | 3149 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: |
655e2941 AT |
3150 | rf = false; |
3151 | break; | |
3152 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
655e2941 AT |
3153 | rf = true; |
3154 | break; | |
3155 | default: | |
3156 | BUG(); | |
cf6ac4ce | 3157 | } |
655e2941 | 3158 | |
d80e02ef TV |
3159 | l = FLD_VAL(onoff, 17, 17) | |
3160 | FLD_VAL(rf, 16, 16) | | |
ed351881 | 3161 | FLD_VAL(de, 15, 15) | |
d80e02ef | 3162 | FLD_VAL(ipc, 14, 14) | |
ed351881 TV |
3163 | FLD_VAL(hs, 13, 13) | |
3164 | FLD_VAL(vs, 12, 12); | |
d80e02ef | 3165 | |
655e2941 | 3166 | dispc_write_reg(DISPC_POL_FREQ(channel), l); |
0006fd63 TV |
3167 | |
3168 | if (dispc.syscon_pol) { | |
3169 | const int shifts[] = { | |
3170 | [OMAP_DSS_CHANNEL_LCD] = 0, | |
3171 | [OMAP_DSS_CHANNEL_LCD2] = 1, | |
3172 | [OMAP_DSS_CHANNEL_LCD3] = 2, | |
3173 | }; | |
3174 | ||
3175 | u32 mask, val; | |
3176 | ||
3177 | mask = (1 << 0) | (1 << 3) | (1 << 6); | |
3178 | val = (rf << 0) | (ipc << 3) | (onoff << 6); | |
3179 | ||
3180 | mask <<= 16 + shifts[channel]; | |
3181 | val <<= 16 + shifts[channel]; | |
3182 | ||
3183 | regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, | |
3184 | mask, val); | |
3185 | } | |
80c39712 TV |
3186 | } |
3187 | ||
3188 | /* change name to mode? */ | |
c51d921a | 3189 | void dispc_mgr_set_timings(enum omap_channel channel, |
a8f3fcd1 | 3190 | const struct omap_video_timings *timings) |
80c39712 TV |
3191 | { |
3192 | unsigned xtot, ytot; | |
3193 | unsigned long ht, vt; | |
2aefad49 | 3194 | struct omap_video_timings t = *timings; |
80c39712 | 3195 | |
2aefad49 | 3196 | DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res); |
80c39712 | 3197 | |
2aefad49 | 3198 | if (!dispc_mgr_timings_ok(channel, &t)) { |
8f366162 | 3199 | BUG(); |
c6eee968 TV |
3200 | return; |
3201 | } | |
80c39712 | 3202 | |
dd88b7a6 | 3203 | if (dss_mgr_is_lcd(channel)) { |
2aefad49 | 3204 | _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, |
655e2941 AT |
3205 | t.vfp, t.vbp, t.vsync_level, t.hsync_level, |
3206 | t.data_pclk_edge, t.de_level, t.sync_pclk_edge); | |
80c39712 | 3207 | |
2aefad49 AT |
3208 | xtot = t.x_res + t.hfp + t.hsw + t.hbp; |
3209 | ytot = t.y_res + t.vfp + t.vsw + t.vbp; | |
80c39712 | 3210 | |
d8d78941 TV |
3211 | ht = timings->pixelclock / xtot; |
3212 | vt = timings->pixelclock / xtot / ytot; | |
c51d921a | 3213 | |
d8d78941 | 3214 | DSSDBG("pck %u\n", timings->pixelclock); |
c51d921a | 3215 | DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", |
2aefad49 | 3216 | t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); |
655e2941 AT |
3217 | DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", |
3218 | t.vsync_level, t.hsync_level, t.data_pclk_edge, | |
3219 | t.de_level, t.sync_pclk_edge); | |
80c39712 | 3220 | |
c51d921a | 3221 | DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); |
2aefad49 | 3222 | } else { |
23c8f88e | 3223 | if (t.interlace == true) |
2aefad49 | 3224 | t.y_res /= 2; |
c51d921a | 3225 | } |
8f366162 | 3226 | |
2aefad49 | 3227 | dispc_mgr_set_size(channel, t.x_res, t.y_res); |
80c39712 | 3228 | } |
348be69d | 3229 | EXPORT_SYMBOL(dispc_mgr_set_timings); |
80c39712 | 3230 | |
26d9dd0d | 3231 | static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, |
ff1b2cde | 3232 | u16 pck_div) |
80c39712 TV |
3233 | { |
3234 | BUG_ON(lck_div < 1); | |
9eaaf207 | 3235 | BUG_ON(pck_div < 1); |
80c39712 | 3236 | |
ce7fa5eb | 3237 | dispc_write_reg(DISPC_DIVISORo(channel), |
80c39712 | 3238 | FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); |
7b3926b3 TV |
3239 | |
3240 | if (dss_has_feature(FEAT_CORE_CLK_DIV) == false && | |
3241 | channel == OMAP_DSS_CHANNEL_LCD) | |
3242 | dispc.core_clk_rate = dispc_fclk_rate() / lck_div; | |
80c39712 TV |
3243 | } |
3244 | ||
26d9dd0d | 3245 | static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, |
2a205f34 | 3246 | int *pck_div) |
80c39712 TV |
3247 | { |
3248 | u32 l; | |
ce7fa5eb | 3249 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 TV |
3250 | *lck_div = FLD_GET(l, 23, 16); |
3251 | *pck_div = FLD_GET(l, 7, 0); | |
3252 | } | |
3253 | ||
3254 | unsigned long dispc_fclk_rate(void) | |
3255 | { | |
2daea7af | 3256 | struct dss_pll *pll; |
80c39712 TV |
3257 | unsigned long r = 0; |
3258 | ||
66534e8e | 3259 | switch (dss_get_dispc_clk_source()) { |
89a35e51 | 3260 | case OMAP_DSS_CLK_SRC_FCK: |
5aaee69d | 3261 | r = dss_get_dispc_clk_rate(); |
66534e8e | 3262 | break; |
89a35e51 | 3263 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
2daea7af | 3264 | pll = dss_pll_find("dsi0"); |
93550927 TV |
3265 | if (!pll) |
3266 | pll = dss_pll_find("video0"); | |
3267 | ||
2daea7af | 3268 | r = pll->cinfo.clkout[0]; |
66534e8e | 3269 | break; |
5a8b572d | 3270 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
2daea7af | 3271 | pll = dss_pll_find("dsi1"); |
93550927 TV |
3272 | if (!pll) |
3273 | pll = dss_pll_find("video1"); | |
3274 | ||
2daea7af | 3275 | r = pll->cinfo.clkout[0]; |
5a8b572d | 3276 | break; |
66534e8e TA |
3277 | default: |
3278 | BUG(); | |
c6eee968 | 3279 | return 0; |
66534e8e TA |
3280 | } |
3281 | ||
80c39712 TV |
3282 | return r; |
3283 | } | |
3284 | ||
26d9dd0d | 3285 | unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) |
80c39712 | 3286 | { |
2daea7af | 3287 | struct dss_pll *pll; |
80c39712 TV |
3288 | int lcd; |
3289 | unsigned long r; | |
3290 | u32 l; | |
3291 | ||
c31cba8a TV |
3292 | if (dss_mgr_is_lcd(channel)) { |
3293 | l = dispc_read_reg(DISPC_DIVISORo(channel)); | |
80c39712 | 3294 | |
c31cba8a | 3295 | lcd = FLD_GET(l, 23, 16); |
80c39712 | 3296 | |
c31cba8a TV |
3297 | switch (dss_get_lcd_clk_source(channel)) { |
3298 | case OMAP_DSS_CLK_SRC_FCK: | |
5aaee69d | 3299 | r = dss_get_dispc_clk_rate(); |
c31cba8a TV |
3300 | break; |
3301 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: | |
2daea7af | 3302 | pll = dss_pll_find("dsi0"); |
93550927 TV |
3303 | if (!pll) |
3304 | pll = dss_pll_find("video0"); | |
3305 | ||
2daea7af | 3306 | r = pll->cinfo.clkout[0]; |
c31cba8a TV |
3307 | break; |
3308 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: | |
2daea7af | 3309 | pll = dss_pll_find("dsi1"); |
93550927 TV |
3310 | if (!pll) |
3311 | pll = dss_pll_find("video1"); | |
3312 | ||
2daea7af | 3313 | r = pll->cinfo.clkout[0]; |
c31cba8a TV |
3314 | break; |
3315 | default: | |
3316 | BUG(); | |
3317 | return 0; | |
3318 | } | |
80c39712 | 3319 | |
c31cba8a TV |
3320 | return r / lcd; |
3321 | } else { | |
3322 | return dispc_fclk_rate(); | |
3323 | } | |
80c39712 TV |
3324 | } |
3325 | ||
26d9dd0d | 3326 | unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) |
80c39712 | 3327 | { |
80c39712 | 3328 | unsigned long r; |
80c39712 | 3329 | |
dd88b7a6 | 3330 | if (dss_mgr_is_lcd(channel)) { |
c3dc6a7a AT |
3331 | int pcd; |
3332 | u32 l; | |
80c39712 | 3333 | |
c3dc6a7a | 3334 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 | 3335 | |
c3dc6a7a | 3336 | pcd = FLD_GET(l, 7, 0); |
80c39712 | 3337 | |
c3dc6a7a AT |
3338 | r = dispc_mgr_lclk_rate(channel); |
3339 | ||
3340 | return r / pcd; | |
3341 | } else { | |
5391e87d | 3342 | return dispc.tv_pclk_rate; |
c3dc6a7a | 3343 | } |
80c39712 TV |
3344 | } |
3345 | ||
5391e87d TV |
3346 | void dispc_set_tv_pclk(unsigned long pclk) |
3347 | { | |
3348 | dispc.tv_pclk_rate = pclk; | |
3349 | } | |
3350 | ||
8b53d991 CM |
3351 | unsigned long dispc_core_clk_rate(void) |
3352 | { | |
7b3926b3 | 3353 | return dispc.core_clk_rate; |
8b53d991 CM |
3354 | } |
3355 | ||
3e8a6ff2 AT |
3356 | static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) |
3357 | { | |
251886d8 TV |
3358 | enum omap_channel channel; |
3359 | ||
3360 | if (plane == OMAP_DSS_WB) | |
3361 | return 0; | |
3362 | ||
3363 | channel = dispc_ovl_get_channel_out(plane); | |
3e8a6ff2 AT |
3364 | |
3365 | return dispc_mgr_pclk_rate(channel); | |
3366 | } | |
3367 | ||
3368 | static unsigned long dispc_plane_lclk_rate(enum omap_plane plane) | |
3369 | { | |
251886d8 TV |
3370 | enum omap_channel channel; |
3371 | ||
3372 | if (plane == OMAP_DSS_WB) | |
3373 | return 0; | |
3374 | ||
3375 | channel = dispc_ovl_get_channel_out(plane); | |
3e8a6ff2 | 3376 | |
c31cba8a | 3377 | return dispc_mgr_lclk_rate(channel); |
3e8a6ff2 | 3378 | } |
c31cba8a | 3379 | |
6f1891fc | 3380 | static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) |
80c39712 TV |
3381 | { |
3382 | int lcd, pcd; | |
6f1891fc CM |
3383 | enum omap_dss_clk_source lcd_clk_src; |
3384 | ||
3385 | seq_printf(s, "- %s -\n", mgr_desc[channel].name); | |
3386 | ||
3387 | lcd_clk_src = dss_get_lcd_clk_source(channel); | |
3388 | ||
3389 | seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name, | |
3390 | dss_get_generic_clk_source_name(lcd_clk_src), | |
3391 | dss_feat_get_clk_source_name(lcd_clk_src)); | |
3392 | ||
3393 | dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); | |
3394 | ||
3395 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
3396 | dispc_mgr_lclk_rate(channel), lcd); | |
3397 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", | |
3398 | dispc_mgr_pclk_rate(channel), pcd); | |
3399 | } | |
3400 | ||
3401 | void dispc_dump_clocks(struct seq_file *s) | |
3402 | { | |
3403 | int lcd; | |
0cf35df3 | 3404 | u32 l; |
89a35e51 | 3405 | enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); |
80c39712 | 3406 | |
4fbafaf3 TV |
3407 | if (dispc_runtime_get()) |
3408 | return; | |
80c39712 | 3409 | |
80c39712 TV |
3410 | seq_printf(s, "- DISPC -\n"); |
3411 | ||
067a57e4 AT |
3412 | seq_printf(s, "dispc fclk source = %s (%s)\n", |
3413 | dss_get_generic_clk_source_name(dispc_clk_src), | |
3414 | dss_feat_get_clk_source_name(dispc_clk_src)); | |
80c39712 TV |
3415 | |
3416 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); | |
2a205f34 | 3417 | |
0cf35df3 MR |
3418 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { |
3419 | seq_printf(s, "- DISPC-CORE-CLK -\n"); | |
3420 | l = dispc_read_reg(DISPC_DIVISOR); | |
3421 | lcd = FLD_GET(l, 23, 16); | |
3422 | ||
3423 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
3424 | (dispc_fclk_rate()/lcd), lcd); | |
3425 | } | |
2a205f34 | 3426 | |
6f1891fc | 3427 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); |
ea75159e | 3428 | |
6f1891fc CM |
3429 | if (dss_has_feature(FEAT_MGR_LCD2)) |
3430 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); | |
3431 | if (dss_has_feature(FEAT_MGR_LCD3)) | |
3432 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); | |
4fbafaf3 TV |
3433 | |
3434 | dispc_runtime_put(); | |
80c39712 TV |
3435 | } |
3436 | ||
e40402cf | 3437 | static void dispc_dump_regs(struct seq_file *s) |
80c39712 | 3438 | { |
4dd2da15 AT |
3439 | int i, j; |
3440 | const char *mgr_names[] = { | |
3441 | [OMAP_DSS_CHANNEL_LCD] = "LCD", | |
3442 | [OMAP_DSS_CHANNEL_DIGIT] = "TV", | |
3443 | [OMAP_DSS_CHANNEL_LCD2] = "LCD2", | |
6f1891fc | 3444 | [OMAP_DSS_CHANNEL_LCD3] = "LCD3", |
4dd2da15 AT |
3445 | }; |
3446 | const char *ovl_names[] = { | |
3447 | [OMAP_DSS_GFX] = "GFX", | |
3448 | [OMAP_DSS_VIDEO1] = "VID1", | |
3449 | [OMAP_DSS_VIDEO2] = "VID2", | |
b8c095b4 | 3450 | [OMAP_DSS_VIDEO3] = "VID3", |
4dd2da15 AT |
3451 | }; |
3452 | const char **p_names; | |
3453 | ||
9b372c2d | 3454 | #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) |
80c39712 | 3455 | |
4fbafaf3 TV |
3456 | if (dispc_runtime_get()) |
3457 | return; | |
80c39712 | 3458 | |
5010be80 | 3459 | /* DISPC common registers */ |
80c39712 TV |
3460 | DUMPREG(DISPC_REVISION); |
3461 | DUMPREG(DISPC_SYSCONFIG); | |
3462 | DUMPREG(DISPC_SYSSTATUS); | |
3463 | DUMPREG(DISPC_IRQSTATUS); | |
3464 | DUMPREG(DISPC_IRQENABLE); | |
3465 | DUMPREG(DISPC_CONTROL); | |
3466 | DUMPREG(DISPC_CONFIG); | |
3467 | DUMPREG(DISPC_CAPABLE); | |
80c39712 TV |
3468 | DUMPREG(DISPC_LINE_STATUS); |
3469 | DUMPREG(DISPC_LINE_NUMBER); | |
11354dd5 AT |
3470 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
3471 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 3472 | DUMPREG(DISPC_GLOBAL_ALPHA); |
2a205f34 SS |
3473 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
3474 | DUMPREG(DISPC_CONTROL2); | |
3475 | DUMPREG(DISPC_CONFIG2); | |
5010be80 | 3476 | } |
6f1891fc CM |
3477 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
3478 | DUMPREG(DISPC_CONTROL3); | |
3479 | DUMPREG(DISPC_CONFIG3); | |
3480 | } | |
29fceeeb TV |
3481 | if (dss_has_feature(FEAT_MFLAG)) |
3482 | DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); | |
5010be80 AT |
3483 | |
3484 | #undef DUMPREG | |
3485 | ||
3486 | #define DISPC_REG(i, name) name(i) | |
4dd2da15 | 3487 | #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ |
311d5ce8 | 3488 | (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ |
5010be80 AT |
3489 | dispc_read_reg(DISPC_REG(i, r))) |
3490 | ||
4dd2da15 | 3491 | p_names = mgr_names; |
5010be80 | 3492 | |
4dd2da15 AT |
3493 | /* DISPC channel specific registers */ |
3494 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { | |
3495 | DUMPREG(i, DISPC_DEFAULT_COLOR); | |
3496 | DUMPREG(i, DISPC_TRANS_COLOR); | |
3497 | DUMPREG(i, DISPC_SIZE_MGR); | |
80c39712 | 3498 | |
4dd2da15 AT |
3499 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
3500 | continue; | |
5010be80 | 3501 | |
4dd2da15 AT |
3502 | DUMPREG(i, DISPC_TIMING_H); |
3503 | DUMPREG(i, DISPC_TIMING_V); | |
3504 | DUMPREG(i, DISPC_POL_FREQ); | |
3505 | DUMPREG(i, DISPC_DIVISORo); | |
5010be80 | 3506 | |
4dd2da15 AT |
3507 | DUMPREG(i, DISPC_DATA_CYCLE1); |
3508 | DUMPREG(i, DISPC_DATA_CYCLE2); | |
3509 | DUMPREG(i, DISPC_DATA_CYCLE3); | |
2a205f34 | 3510 | |
332e9d70 | 3511 | if (dss_has_feature(FEAT_CPR)) { |
4dd2da15 AT |
3512 | DUMPREG(i, DISPC_CPR_COEF_R); |
3513 | DUMPREG(i, DISPC_CPR_COEF_G); | |
3514 | DUMPREG(i, DISPC_CPR_COEF_B); | |
332e9d70 | 3515 | } |
2a205f34 | 3516 | } |
80c39712 | 3517 | |
4dd2da15 AT |
3518 | p_names = ovl_names; |
3519 | ||
3520 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { | |
3521 | DUMPREG(i, DISPC_OVL_BA0); | |
3522 | DUMPREG(i, DISPC_OVL_BA1); | |
3523 | DUMPREG(i, DISPC_OVL_POSITION); | |
3524 | DUMPREG(i, DISPC_OVL_SIZE); | |
3525 | DUMPREG(i, DISPC_OVL_ATTRIBUTES); | |
3526 | DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); | |
3527 | DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); | |
3528 | DUMPREG(i, DISPC_OVL_ROW_INC); | |
3529 | DUMPREG(i, DISPC_OVL_PIXEL_INC); | |
aba837a2 | 3530 | |
4dd2da15 AT |
3531 | if (dss_has_feature(FEAT_PRELOAD)) |
3532 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
aba837a2 TV |
3533 | if (dss_has_feature(FEAT_MFLAG)) |
3534 | DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); | |
4dd2da15 AT |
3535 | |
3536 | if (i == OMAP_DSS_GFX) { | |
3537 | DUMPREG(i, DISPC_OVL_WINDOW_SKIP); | |
3538 | DUMPREG(i, DISPC_OVL_TABLE_BA); | |
3539 | continue; | |
3540 | } | |
3541 | ||
3542 | DUMPREG(i, DISPC_OVL_FIR); | |
3543 | DUMPREG(i, DISPC_OVL_PICTURE_SIZE); | |
3544 | DUMPREG(i, DISPC_OVL_ACCU0); | |
3545 | DUMPREG(i, DISPC_OVL_ACCU1); | |
3546 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3547 | DUMPREG(i, DISPC_OVL_BA0_UV); | |
3548 | DUMPREG(i, DISPC_OVL_BA1_UV); | |
3549 | DUMPREG(i, DISPC_OVL_FIR2); | |
3550 | DUMPREG(i, DISPC_OVL_ACCU2_0); | |
3551 | DUMPREG(i, DISPC_OVL_ACCU2_1); | |
3552 | } | |
3553 | if (dss_has_feature(FEAT_ATTR2)) | |
3554 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); | |
ab5ca071 | 3555 | } |
5010be80 AT |
3556 | |
3557 | #undef DISPC_REG | |
3558 | #undef DUMPREG | |
3559 | ||
3560 | #define DISPC_REG(plane, name, i) name(plane, i) | |
3561 | #define DUMPREG(plane, name, i) \ | |
4dd2da15 | 3562 | seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ |
311d5ce8 | 3563 | (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ |
5010be80 AT |
3564 | dispc_read_reg(DISPC_REG(plane, name, i))) |
3565 | ||
4dd2da15 | 3566 | /* Video pipeline coefficient registers */ |
332e9d70 | 3567 | |
4dd2da15 AT |
3568 | /* start from OMAP_DSS_VIDEO1 */ |
3569 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { | |
3570 | for (j = 0; j < 8; j++) | |
3571 | DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); | |
9b372c2d | 3572 | |
4dd2da15 AT |
3573 | for (j = 0; j < 8; j++) |
3574 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); | |
5010be80 | 3575 | |
4dd2da15 AT |
3576 | for (j = 0; j < 5; j++) |
3577 | DUMPREG(i, DISPC_OVL_CONV_COEF, j); | |
ab5ca071 | 3578 | |
4dd2da15 AT |
3579 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
3580 | for (j = 0; j < 8; j++) | |
3581 | DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); | |
3582 | } | |
3583 | ||
3584 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3585 | for (j = 0; j < 8; j++) | |
3586 | DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); | |
3587 | ||
3588 | for (j = 0; j < 8; j++) | |
3589 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); | |
3590 | ||
3591 | for (j = 0; j < 8; j++) | |
3592 | DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); | |
3593 | } | |
332e9d70 | 3594 | } |
80c39712 | 3595 | |
4fbafaf3 | 3596 | dispc_runtime_put(); |
5010be80 AT |
3597 | |
3598 | #undef DISPC_REG | |
80c39712 TV |
3599 | #undef DUMPREG |
3600 | } | |
3601 | ||
80c39712 TV |
3602 | /* calculate clock rates using dividers in cinfo */ |
3603 | int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, | |
80c39712 TV |
3604 | struct dispc_clock_info *cinfo) |
3605 | { | |
80c39712 TV |
3606 | if (cinfo->lck_div > 255 || cinfo->lck_div == 0) |
3607 | return -EINVAL; | |
9eaaf207 | 3608 | if (cinfo->pck_div < 1 || cinfo->pck_div > 255) |
80c39712 | 3609 | return -EINVAL; |
80c39712 | 3610 | |
80c39712 TV |
3611 | cinfo->lck = dispc_fclk_rate / cinfo->lck_div; |
3612 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
9eaaf207 | 3613 | |
80c39712 TV |
3614 | return 0; |
3615 | } | |
80c39712 | 3616 | |
7c284e6e TV |
3617 | bool dispc_div_calc(unsigned long dispc, |
3618 | unsigned long pck_min, unsigned long pck_max, | |
3619 | dispc_div_calc_func func, void *data) | |
3620 | { | |
3621 | int lckd, lckd_start, lckd_stop; | |
3622 | int pckd, pckd_start, pckd_stop; | |
3623 | unsigned long pck, lck; | |
3624 | unsigned long lck_max; | |
3625 | unsigned long pckd_hw_min, pckd_hw_max; | |
3626 | unsigned min_fck_per_pck; | |
3627 | unsigned long fck; | |
80c39712 | 3628 | |
7c284e6e TV |
3629 | #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK |
3630 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
3631 | #else | |
3632 | min_fck_per_pck = 0; | |
3633 | #endif | |
80c39712 | 3634 | |
7c284e6e TV |
3635 | pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); |
3636 | pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); | |
80c39712 | 3637 | |
7c284e6e | 3638 | lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
80c39712 | 3639 | |
7c284e6e TV |
3640 | pck_min = pck_min ? pck_min : 1; |
3641 | pck_max = pck_max ? pck_max : ULONG_MAX; | |
80c39712 | 3642 | |
7c284e6e TV |
3643 | lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); |
3644 | lckd_stop = min(dispc / pck_min, 255ul); | |
80c39712 | 3645 | |
7c284e6e TV |
3646 | for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { |
3647 | lck = dispc / lckd; | |
80c39712 | 3648 | |
7c284e6e TV |
3649 | pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); |
3650 | pckd_stop = min(lck / pck_min, pckd_hw_max); | |
80c39712 | 3651 | |
7c284e6e TV |
3652 | for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { |
3653 | pck = lck / pckd; | |
80c39712 | 3654 | |
7c284e6e TV |
3655 | /* |
3656 | * For OMAP2/3 the DISPC fclk is the same as LCD's logic | |
3657 | * clock, which means we're configuring DISPC fclk here | |
3658 | * also. Thus we need to use the calculated lck. For | |
3659 | * OMAP4+ the DISPC fclk is a separate clock. | |
3660 | */ | |
3661 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
3662 | fck = dispc_core_clk_rate(); | |
3663 | else | |
3664 | fck = lck; | |
3665 | ||
3666 | if (fck < pck * min_fck_per_pck) | |
3667 | continue; | |
3668 | ||
3669 | if (func(lckd, pckd, lck, pck, data)) | |
3670 | return true; | |
3671 | } | |
3672 | } | |
3673 | ||
3674 | return false; | |
80c39712 TV |
3675 | } |
3676 | ||
f0d08f89 | 3677 | void dispc_mgr_set_clock_div(enum omap_channel channel, |
a8f3fcd1 | 3678 | const struct dispc_clock_info *cinfo) |
80c39712 TV |
3679 | { |
3680 | DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); | |
3681 | DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); | |
3682 | ||
26d9dd0d | 3683 | dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); |
80c39712 TV |
3684 | } |
3685 | ||
26d9dd0d | 3686 | int dispc_mgr_get_clock_div(enum omap_channel channel, |
ff1b2cde | 3687 | struct dispc_clock_info *cinfo) |
80c39712 TV |
3688 | { |
3689 | unsigned long fck; | |
3690 | ||
3691 | fck = dispc_fclk_rate(); | |
3692 | ||
ce7fa5eb MR |
3693 | cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); |
3694 | cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); | |
80c39712 TV |
3695 | |
3696 | cinfo->lck = fck / cinfo->lck_div; | |
3697 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
3698 | ||
3699 | return 0; | |
3700 | } | |
3701 | ||
4e0397cf TV |
3702 | u32 dispc_read_irqstatus(void) |
3703 | { | |
3704 | return dispc_read_reg(DISPC_IRQSTATUS); | |
3705 | } | |
348be69d | 3706 | EXPORT_SYMBOL(dispc_read_irqstatus); |
4e0397cf TV |
3707 | |
3708 | void dispc_clear_irqstatus(u32 mask) | |
3709 | { | |
3710 | dispc_write_reg(DISPC_IRQSTATUS, mask); | |
3711 | } | |
348be69d | 3712 | EXPORT_SYMBOL(dispc_clear_irqstatus); |
4e0397cf TV |
3713 | |
3714 | u32 dispc_read_irqenable(void) | |
3715 | { | |
3716 | return dispc_read_reg(DISPC_IRQENABLE); | |
3717 | } | |
348be69d | 3718 | EXPORT_SYMBOL(dispc_read_irqenable); |
4e0397cf TV |
3719 | |
3720 | void dispc_write_irqenable(u32 mask) | |
3721 | { | |
3722 | u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); | |
3723 | ||
3724 | /* clear the irqstatus for newly enabled irqs */ | |
3725 | dispc_clear_irqstatus((mask ^ old_mask) & mask); | |
3726 | ||
3727 | dispc_write_reg(DISPC_IRQENABLE, mask); | |
3728 | } | |
348be69d | 3729 | EXPORT_SYMBOL(dispc_write_irqenable); |
4e0397cf | 3730 | |
80c39712 TV |
3731 | void dispc_enable_sidle(void) |
3732 | { | |
3733 | REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ | |
3734 | } | |
3735 | ||
3736 | void dispc_disable_sidle(void) | |
3737 | { | |
3738 | REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ | |
3739 | } | |
3740 | ||
3741 | static void _omap_dispc_initial_config(void) | |
3742 | { | |
3743 | u32 l; | |
3744 | ||
0cf35df3 MR |
3745 | /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ |
3746 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { | |
3747 | l = dispc_read_reg(DISPC_DIVISOR); | |
3748 | /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ | |
3749 | l = FLD_MOD(l, 1, 0, 0); | |
3750 | l = FLD_MOD(l, 1, 23, 16); | |
3751 | dispc_write_reg(DISPC_DIVISOR, l); | |
7b3926b3 TV |
3752 | |
3753 | dispc.core_clk_rate = dispc_fclk_rate(); | |
0cf35df3 MR |
3754 | } |
3755 | ||
80c39712 | 3756 | /* FUNCGATED */ |
6ced40bf AT |
3757 | if (dss_has_feature(FEAT_FUNCGATED)) |
3758 | REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); | |
80c39712 | 3759 | |
6e5264b0 | 3760 | dispc_setup_color_conv_coef(); |
80c39712 TV |
3761 | |
3762 | dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); | |
3763 | ||
42a6961c | 3764 | dispc_init_fifos(); |
5ed8cf5b TV |
3765 | |
3766 | dispc_configure_burst_sizes(); | |
54128701 AT |
3767 | |
3768 | dispc_ovl_enable_zorder_planes(); | |
d0df9a2c AT |
3769 | |
3770 | if (dispc.feat->mstandby_workaround) | |
3771 | REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); | |
c64aa3a6 TV |
3772 | |
3773 | if (dss_has_feature(FEAT_MFLAG)) | |
3774 | dispc_init_mflag(); | |
80c39712 TV |
3775 | } |
3776 | ||
ede92695 | 3777 | static const struct dispc_features omap24xx_dispc_feats = { |
dcbe765b CM |
3778 | .sw_start = 5, |
3779 | .fp_start = 15, | |
3780 | .bp_start = 27, | |
3781 | .sw_max = 64, | |
3782 | .vp_max = 255, | |
3783 | .hp_max = 256, | |
33b89928 AT |
3784 | .mgr_width_start = 10, |
3785 | .mgr_height_start = 26, | |
3786 | .mgr_width_max = 2048, | |
3787 | .mgr_height_max = 2048, | |
ca5ca69c | 3788 | .max_lcd_pclk = 66500000, |
dcbe765b CM |
3789 | .calc_scaling = dispc_ovl_calc_scaling_24xx, |
3790 | .calc_core_clk = calc_core_clk_24xx, | |
42a6961c | 3791 | .num_fifos = 3, |
cffa947d | 3792 | .no_framedone_tv = true, |
8bc65552 | 3793 | .set_max_preload = false, |
f2aee319 | 3794 | .last_pixel_inc_missing = true, |
dcbe765b CM |
3795 | }; |
3796 | ||
ede92695 | 3797 | static const struct dispc_features omap34xx_rev1_0_dispc_feats = { |
dcbe765b CM |
3798 | .sw_start = 5, |
3799 | .fp_start = 15, | |
3800 | .bp_start = 27, | |
3801 | .sw_max = 64, | |
3802 | .vp_max = 255, | |
3803 | .hp_max = 256, | |
33b89928 AT |
3804 | .mgr_width_start = 10, |
3805 | .mgr_height_start = 26, | |
3806 | .mgr_width_max = 2048, | |
3807 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3808 | .max_lcd_pclk = 173000000, |
3809 | .max_tv_pclk = 59000000, | |
dcbe765b CM |
3810 | .calc_scaling = dispc_ovl_calc_scaling_34xx, |
3811 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3812 | .num_fifos = 3, |
cffa947d | 3813 | .no_framedone_tv = true, |
8bc65552 | 3814 | .set_max_preload = false, |
f2aee319 | 3815 | .last_pixel_inc_missing = true, |
dcbe765b CM |
3816 | }; |
3817 | ||
ede92695 | 3818 | static const struct dispc_features omap34xx_rev3_0_dispc_feats = { |
dcbe765b CM |
3819 | .sw_start = 7, |
3820 | .fp_start = 19, | |
3821 | .bp_start = 31, | |
3822 | .sw_max = 256, | |
3823 | .vp_max = 4095, | |
3824 | .hp_max = 4096, | |
33b89928 AT |
3825 | .mgr_width_start = 10, |
3826 | .mgr_height_start = 26, | |
3827 | .mgr_width_max = 2048, | |
3828 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3829 | .max_lcd_pclk = 173000000, |
3830 | .max_tv_pclk = 59000000, | |
dcbe765b CM |
3831 | .calc_scaling = dispc_ovl_calc_scaling_34xx, |
3832 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3833 | .num_fifos = 3, |
cffa947d | 3834 | .no_framedone_tv = true, |
8bc65552 | 3835 | .set_max_preload = false, |
f2aee319 | 3836 | .last_pixel_inc_missing = true, |
dcbe765b CM |
3837 | }; |
3838 | ||
ede92695 | 3839 | static const struct dispc_features omap44xx_dispc_feats = { |
dcbe765b CM |
3840 | .sw_start = 7, |
3841 | .fp_start = 19, | |
3842 | .bp_start = 31, | |
3843 | .sw_max = 256, | |
3844 | .vp_max = 4095, | |
3845 | .hp_max = 4096, | |
33b89928 AT |
3846 | .mgr_width_start = 10, |
3847 | .mgr_height_start = 26, | |
3848 | .mgr_width_max = 2048, | |
3849 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3850 | .max_lcd_pclk = 170000000, |
3851 | .max_tv_pclk = 185625000, | |
dcbe765b CM |
3852 | .calc_scaling = dispc_ovl_calc_scaling_44xx, |
3853 | .calc_core_clk = calc_core_clk_44xx, | |
42a6961c | 3854 | .num_fifos = 5, |
66a0f9e4 | 3855 | .gfx_fifo_workaround = true, |
8bc65552 | 3856 | .set_max_preload = true, |
dcbe765b CM |
3857 | }; |
3858 | ||
ede92695 | 3859 | static const struct dispc_features omap54xx_dispc_feats = { |
264236f8 AT |
3860 | .sw_start = 7, |
3861 | .fp_start = 19, | |
3862 | .bp_start = 31, | |
3863 | .sw_max = 256, | |
3864 | .vp_max = 4095, | |
3865 | .hp_max = 4096, | |
3866 | .mgr_width_start = 11, | |
3867 | .mgr_height_start = 27, | |
3868 | .mgr_width_max = 4096, | |
3869 | .mgr_height_max = 4096, | |
ca5ca69c AT |
3870 | .max_lcd_pclk = 170000000, |
3871 | .max_tv_pclk = 186000000, | |
264236f8 AT |
3872 | .calc_scaling = dispc_ovl_calc_scaling_44xx, |
3873 | .calc_core_clk = calc_core_clk_44xx, | |
3874 | .num_fifos = 5, | |
3875 | .gfx_fifo_workaround = true, | |
d0df9a2c | 3876 | .mstandby_workaround = true, |
8bc65552 | 3877 | .set_max_preload = true, |
264236f8 AT |
3878 | }; |
3879 | ||
ede92695 | 3880 | static int dispc_init_features(struct platform_device *pdev) |
dcbe765b CM |
3881 | { |
3882 | const struct dispc_features *src; | |
3883 | struct dispc_features *dst; | |
3884 | ||
84b47623 | 3885 | dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); |
dcbe765b | 3886 | if (!dst) { |
84b47623 | 3887 | dev_err(&pdev->dev, "Failed to allocate DISPC Features\n"); |
dcbe765b CM |
3888 | return -ENOMEM; |
3889 | } | |
3890 | ||
b2c7d54f | 3891 | switch (omapdss_get_version()) { |
84b47623 | 3892 | case OMAPDSS_VER_OMAP24xx: |
dcbe765b | 3893 | src = &omap24xx_dispc_feats; |
84b47623 TV |
3894 | break; |
3895 | ||
3896 | case OMAPDSS_VER_OMAP34xx_ES1: | |
3897 | src = &omap34xx_rev1_0_dispc_feats; | |
3898 | break; | |
3899 | ||
3900 | case OMAPDSS_VER_OMAP34xx_ES3: | |
3901 | case OMAPDSS_VER_OMAP3630: | |
3902 | case OMAPDSS_VER_AM35xx: | |
d6279d4a | 3903 | case OMAPDSS_VER_AM43xx: |
84b47623 TV |
3904 | src = &omap34xx_rev3_0_dispc_feats; |
3905 | break; | |
3906 | ||
3907 | case OMAPDSS_VER_OMAP4430_ES1: | |
3908 | case OMAPDSS_VER_OMAP4430_ES2: | |
3909 | case OMAPDSS_VER_OMAP4: | |
dcbe765b | 3910 | src = &omap44xx_dispc_feats; |
84b47623 TV |
3911 | break; |
3912 | ||
3913 | case OMAPDSS_VER_OMAP5: | |
93550927 | 3914 | case OMAPDSS_VER_DRA7xx: |
264236f8 | 3915 | src = &omap54xx_dispc_feats; |
84b47623 TV |
3916 | break; |
3917 | ||
3918 | default: | |
dcbe765b CM |
3919 | return -ENODEV; |
3920 | } | |
3921 | ||
3922 | memcpy(dst, src, sizeof(*dst)); | |
3923 | dispc.feat = dst; | |
3924 | ||
3925 | return 0; | |
3926 | } | |
3927 | ||
0925afc9 TV |
3928 | static irqreturn_t dispc_irq_handler(int irq, void *arg) |
3929 | { | |
3930 | if (!dispc.is_enabled) | |
3931 | return IRQ_NONE; | |
3932 | ||
3933 | return dispc.user_handler(irq, dispc.user_data); | |
3934 | } | |
3935 | ||
96e2e637 TV |
3936 | int dispc_request_irq(irq_handler_t handler, void *dev_id) |
3937 | { | |
0925afc9 TV |
3938 | int r; |
3939 | ||
3940 | if (dispc.user_handler != NULL) | |
3941 | return -EBUSY; | |
3942 | ||
3943 | dispc.user_handler = handler; | |
3944 | dispc.user_data = dev_id; | |
3945 | ||
3946 | /* ensure the dispc_irq_handler sees the values above */ | |
3947 | smp_wmb(); | |
3948 | ||
3949 | r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, | |
3950 | IRQF_SHARED, "OMAP DISPC", &dispc); | |
3951 | if (r) { | |
3952 | dispc.user_handler = NULL; | |
3953 | dispc.user_data = NULL; | |
3954 | } | |
3955 | ||
3956 | return r; | |
96e2e637 | 3957 | } |
348be69d | 3958 | EXPORT_SYMBOL(dispc_request_irq); |
96e2e637 TV |
3959 | |
3960 | void dispc_free_irq(void *dev_id) | |
3961 | { | |
0925afc9 TV |
3962 | devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); |
3963 | ||
3964 | dispc.user_handler = NULL; | |
3965 | dispc.user_data = NULL; | |
96e2e637 | 3966 | } |
348be69d | 3967 | EXPORT_SYMBOL(dispc_free_irq); |
96e2e637 | 3968 | |
060b6d9c | 3969 | /* DISPC HW IP initialisation */ |
736e60dd | 3970 | static int dispc_bind(struct device *dev, struct device *master, void *data) |
060b6d9c | 3971 | { |
736e60dd | 3972 | struct platform_device *pdev = to_platform_device(dev); |
060b6d9c | 3973 | u32 rev; |
affe360d | 3974 | int r = 0; |
ea9da36a | 3975 | struct resource *dispc_mem; |
0006fd63 | 3976 | struct device_node *np = pdev->dev.of_node; |
ea9da36a | 3977 | |
060b6d9c SG |
3978 | dispc.pdev = pdev; |
3979 | ||
d49cd155 TV |
3980 | spin_lock_init(&dispc.control_lock); |
3981 | ||
84b47623 | 3982 | r = dispc_init_features(dispc.pdev); |
dcbe765b CM |
3983 | if (r) |
3984 | return r; | |
3985 | ||
ea9da36a SG |
3986 | dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); |
3987 | if (!dispc_mem) { | |
3988 | DSSERR("can't get IORESOURCE_MEM DISPC\n"); | |
cd3b3449 | 3989 | return -EINVAL; |
ea9da36a | 3990 | } |
cd3b3449 | 3991 | |
6e2a14d2 JL |
3992 | dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, |
3993 | resource_size(dispc_mem)); | |
060b6d9c SG |
3994 | if (!dispc.base) { |
3995 | DSSERR("can't ioremap DISPC\n"); | |
cd3b3449 | 3996 | return -ENOMEM; |
affe360d | 3997 | } |
cd3b3449 | 3998 | |
affe360d | 3999 | dispc.irq = platform_get_irq(dispc.pdev, 0); |
4000 | if (dispc.irq < 0) { | |
4001 | DSSERR("platform_get_irq failed\n"); | |
cd3b3449 | 4002 | return -ENODEV; |
affe360d | 4003 | } |
4004 | ||
0006fd63 TV |
4005 | if (np && of_property_read_bool(np, "syscon-pol")) { |
4006 | dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); | |
4007 | if (IS_ERR(dispc.syscon_pol)) { | |
4008 | dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); | |
4009 | return PTR_ERR(dispc.syscon_pol); | |
4010 | } | |
4011 | ||
4012 | if (of_property_read_u32_index(np, "syscon-pol", 1, | |
4013 | &dispc.syscon_pol_offset)) { | |
4014 | dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); | |
4015 | return -EINVAL; | |
4016 | } | |
4017 | } | |
4018 | ||
4fbafaf3 TV |
4019 | pm_runtime_enable(&pdev->dev); |
4020 | ||
4021 | r = dispc_runtime_get(); | |
4022 | if (r) | |
4023 | goto err_runtime_get; | |
060b6d9c SG |
4024 | |
4025 | _omap_dispc_initial_config(); | |
4026 | ||
060b6d9c | 4027 | rev = dispc_read_reg(DISPC_REVISION); |
a06b62f8 | 4028 | dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", |
060b6d9c SG |
4029 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
4030 | ||
4fbafaf3 | 4031 | dispc_runtime_put(); |
060b6d9c | 4032 | |
04b1fc02 TV |
4033 | dss_init_overlay_managers(); |
4034 | ||
e40402cf TV |
4035 | dss_debugfs_create_file("dispc", dispc_dump_regs); |
4036 | ||
060b6d9c | 4037 | return 0; |
4fbafaf3 TV |
4038 | |
4039 | err_runtime_get: | |
4040 | pm_runtime_disable(&pdev->dev); | |
affe360d | 4041 | return r; |
060b6d9c SG |
4042 | } |
4043 | ||
736e60dd TV |
4044 | static void dispc_unbind(struct device *dev, struct device *master, |
4045 | void *data) | |
060b6d9c | 4046 | { |
736e60dd | 4047 | pm_runtime_disable(dev); |
4fbafaf3 | 4048 | |
04b1fc02 | 4049 | dss_uninit_overlay_managers(); |
736e60dd TV |
4050 | } |
4051 | ||
4052 | static const struct component_ops dispc_component_ops = { | |
4053 | .bind = dispc_bind, | |
4054 | .unbind = dispc_unbind, | |
4055 | }; | |
04b1fc02 | 4056 | |
736e60dd TV |
4057 | static int dispc_probe(struct platform_device *pdev) |
4058 | { | |
4059 | return component_add(&pdev->dev, &dispc_component_ops); | |
4060 | } | |
4061 | ||
4062 | static int dispc_remove(struct platform_device *pdev) | |
4063 | { | |
4064 | component_del(&pdev->dev, &dispc_component_ops); | |
060b6d9c SG |
4065 | return 0; |
4066 | } | |
4067 | ||
4fbafaf3 TV |
4068 | static int dispc_runtime_suspend(struct device *dev) |
4069 | { | |
0925afc9 TV |
4070 | dispc.is_enabled = false; |
4071 | /* ensure the dispc_irq_handler sees the is_enabled value */ | |
4072 | smp_wmb(); | |
4073 | /* wait for current handler to finish before turning the DISPC off */ | |
4074 | synchronize_irq(dispc.irq); | |
4075 | ||
4fbafaf3 | 4076 | dispc_save_context(); |
4fbafaf3 TV |
4077 | |
4078 | return 0; | |
4079 | } | |
4080 | ||
4081 | static int dispc_runtime_resume(struct device *dev) | |
4082 | { | |
9229b516 TV |
4083 | /* |
4084 | * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) | |
4085 | * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in | |
4086 | * _omap_dispc_initial_config(). We can thus use it to detect if | |
4087 | * we have lost register context. | |
4088 | */ | |
0925afc9 TV |
4089 | if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { |
4090 | _omap_dispc_initial_config(); | |
9229b516 | 4091 | |
0925afc9 TV |
4092 | dispc_restore_context(); |
4093 | } | |
be07dcd7 | 4094 | |
0925afc9 TV |
4095 | dispc.is_enabled = true; |
4096 | /* ensure the dispc_irq_handler sees the is_enabled value */ | |
4097 | smp_wmb(); | |
4fbafaf3 TV |
4098 | |
4099 | return 0; | |
4100 | } | |
4101 | ||
4102 | static const struct dev_pm_ops dispc_pm_ops = { | |
4103 | .runtime_suspend = dispc_runtime_suspend, | |
4104 | .runtime_resume = dispc_runtime_resume, | |
4105 | }; | |
4106 | ||
d7977f88 TV |
4107 | static const struct of_device_id dispc_of_match[] = { |
4108 | { .compatible = "ti,omap2-dispc", }, | |
4109 | { .compatible = "ti,omap3-dispc", }, | |
4110 | { .compatible = "ti,omap4-dispc", }, | |
2e7e6b68 | 4111 | { .compatible = "ti,omap5-dispc", }, |
93550927 | 4112 | { .compatible = "ti,dra7-dispc", }, |
d7977f88 TV |
4113 | {}, |
4114 | }; | |
4115 | ||
060b6d9c | 4116 | static struct platform_driver omap_dispchw_driver = { |
736e60dd TV |
4117 | .probe = dispc_probe, |
4118 | .remove = dispc_remove, | |
060b6d9c SG |
4119 | .driver = { |
4120 | .name = "omapdss_dispc", | |
4fbafaf3 | 4121 | .pm = &dispc_pm_ops, |
d7977f88 | 4122 | .of_match_table = dispc_of_match, |
422ccbd5 | 4123 | .suppress_bind_attrs = true, |
060b6d9c SG |
4124 | }, |
4125 | }; | |
4126 | ||
6e7e8f06 | 4127 | int __init dispc_init_platform_driver(void) |
060b6d9c | 4128 | { |
736e60dd | 4129 | return platform_driver_register(&omap_dispchw_driver); |
060b6d9c SG |
4130 | } |
4131 | ||
ede92695 | 4132 | void dispc_uninit_platform_driver(void) |
060b6d9c | 4133 | { |
04c742c3 | 4134 | platform_driver_unregister(&omap_dispchw_driver); |
060b6d9c | 4135 | } |