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OMAPDSS: make a two dss feat funcs internal to omapdss
[deliverable/linux.git] / drivers / video / fbdev / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
736e60dd 42#include <linux/component.h>
80c39712 43
a0b38cc4 44#include <video/omapdss.h>
80c39712
TV		 45
46#include "dss.h"
a0acb557 47#include "dss_features.h"
9b372c2d 48#include "dispc.h"
80c39712
TV		 49
50/* DISPC */
8613b000 51#define DISPC_SZ_REGS SZ_4K
80c39712 52
5ed8cf5b
TV		 53enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57};
58
80c39712
TV		 59#define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
61
62#define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64
dcbe765b
CM		 65struct dispc_features {
66 u8 sw_start;
67 u8 fp_start;
68 u8 bp_start;
69 u16 sw_max;
70 u16 vp_max;
71 u16 hp_max;
33b89928
AT		 72 u8 mgr_width_start;
73 u8 mgr_height_start;
74 u16 mgr_width_max;
75 u16 mgr_height_max;
ca5ca69c
AT		 76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
0c6921de 78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 84 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 85 u16 width, u16 height, u16 out_width, u16 out_height,
86 bool mem_to_mem);
42a6961c 87 u8 num_fifos;
66a0f9e4
TV		 88
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
cffa947d
TV		 91
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
d0df9a2c
AT		 94
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
8bc65552
AT		 97
98 bool set_max_preload:1;
f2aee319
TV		 99
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
e5f80917
TV		 102
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
20efbc35
TV		 105
106 bool has_writeback:1;
dcbe765b
CM		 107};
108
42a6961c
TV		 109#define DISPC_MAX_NR_FIFOS 5
110
80c39712 111static struct {
060b6d9c 112 struct platform_device *pdev;
80c39712 113 void __iomem *base;
4fbafaf3 114
affe360d 115 int irq;
0925afc9
TV		 116 irq_handler_t user_handler;
117 void *user_data;
80c39712 118
7b3926b3 119 unsigned long core_clk_rate;
5391e87d 120 unsigned long tv_pclk_rate;
7b3926b3 121
42a6961c
TV		 122 u32 fifo_size[DISPC_MAX_NR_FIFOS];
123 /* maps which plane is using a fifo. fifo-id -> plane-id */
124 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 125
49ea86f3 126 bool ctx_valid;
80c39712 127 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 128
dcbe765b 129 const struct dispc_features *feat;
0925afc9
TV		 130
131 bool is_enabled;
0006fd63
TV		 132
133 struct regmap *syscon_pol;
134 u32 syscon_pol_offset;
d49cd155
TV		 135
136 /* DISPC_CONTROL & DISPC_CONFIG lock*/
137 spinlock_t control_lock;
80c39712
TV		 138} dispc;
139
0d66cbb5
AJ		 140enum omap_color_component {
141 /* used for all color formats for OMAP3 and earlier
142 * and for RGB and Y color component on OMAP4
143 */
144 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
145 /* used for UV component for
146 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
147 * color formats on OMAP4
148 */
149 DISPC_COLOR_COMPONENT_UV = 1 << 1,
150};
151
efa70b3b
CM		 152enum mgr_reg_fields {
153 DISPC_MGR_FLD_ENABLE,
154 DISPC_MGR_FLD_STNTFT,
155 DISPC_MGR_FLD_GO,
156 DISPC_MGR_FLD_TFTDATALINES,
157 DISPC_MGR_FLD_STALLMODE,
158 DISPC_MGR_FLD_TCKENABLE,
159 DISPC_MGR_FLD_TCKSELECTION,
160 DISPC_MGR_FLD_CPR,
161 DISPC_MGR_FLD_FIFOHANDCHECK,
162 /* used to maintain a count of the above fields */
163 DISPC_MGR_FLD_NUM,
164};
165
5c348ba9
JS		 166struct dispc_reg_field {
167 u16 reg;
168 u8 high;
169 u8 low;
170};
171
efa70b3b
CM		 172static const struct {
173 const char *name;
174 u32 vsync_irq;
175 u32 framedone_irq;
176 u32 sync_lost_irq;
5c348ba9 177 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 178} mgr_desc[] = {
179 [OMAP_DSS_CHANNEL_LCD] = {
180 .name = "LCD",
181 .vsync_irq = DISPC_IRQ_VSYNC,
182 .framedone_irq = DISPC_IRQ_FRAMEDONE,
183 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
184 .reg_desc = {
185 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
186 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
187 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
188 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
189 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
190 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
191 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
192 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
193 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
194 },
195 },
196 [OMAP_DSS_CHANNEL_DIGIT] = {
197 .name = "DIGIT",
198 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 199 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 200 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
201 .reg_desc = {
202 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
203 [DISPC_MGR_FLD_STNTFT] = { },
204 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
205 [DISPC_MGR_FLD_TFTDATALINES] = { },
206 [DISPC_MGR_FLD_STALLMODE] = { },
207 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
208 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
209 [DISPC_MGR_FLD_CPR] = { },
210 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
211 },
212 },
213 [OMAP_DSS_CHANNEL_LCD2] = {
214 .name = "LCD2",
215 .vsync_irq = DISPC_IRQ_VSYNC2,
216 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
217 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
218 .reg_desc = {
219 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
220 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
221 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
222 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
223 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
224 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
225 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
226 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
227 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
228 },
229 },
e86d456a
CM		 230 [OMAP_DSS_CHANNEL_LCD3] = {
231 .name = "LCD3",
232 .vsync_irq = DISPC_IRQ_VSYNC3,
233 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
234 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
235 .reg_desc = {
236 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
237 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
238 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
239 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
240 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
241 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
242 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
243 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
244 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
245 },
246 },
efa70b3b
CM		 247};
248
6e5264b0
AT		 249struct color_conv_coef {
250 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
251 int full_range;
252};
253
3e8a6ff2
AT		 254static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
255static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 256
55978cc2 257static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 258{
55978cc2 259 __raw_writel(val, dispc.base + idx);
80c39712
TV		 260}
261
55978cc2 262static inline u32 dispc_read_reg(const u16 idx)
80c39712 263{
55978cc2 264 return __raw_readl(dispc.base + idx);
80c39712
TV		 265}
266
efa70b3b
CM		 267static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
268{
5c348ba9 269 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 270 return REG_GET(rfld.reg, rfld.high, rfld.low);
271}
272
273static void mgr_fld_write(enum omap_channel channel,
274 enum mgr_reg_fields regfld, int val) {
5c348ba9 275 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
d49cd155
TV		 276 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
277 unsigned long flags;
278
279 if (need_lock)
280 spin_lock_irqsave(&dispc.control_lock, flags);
281
efa70b3b 282 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
d49cd155
TV		 283
284 if (need_lock)
285 spin_unlock_irqrestore(&dispc.control_lock, flags);
efa70b3b
CM		 286}
287
80c39712 288#define SR(reg) \
55978cc2 289 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 290#define RR(reg) \
55978cc2 291 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 292
4fbafaf3 293static void dispc_save_context(void)
80c39712 294{
c6104b8e 295 int i, j;
80c39712 296
4fbafaf3
TV		 297 DSSDBG("dispc_save_context\n");
298
80c39712
TV		 299 SR(IRQENABLE);
300 SR(CONTROL);
301 SR(CONFIG);
80c39712 302 SR(LINE_NUMBER);
11354dd5
AT		 303 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
304 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 305 SR(GLOBAL_ALPHA);
2a205f34
SS		 306 if (dss_has_feature(FEAT_MGR_LCD2)) {
307 SR(CONTROL2);
2a205f34
SS		 308 SR(CONFIG2);
309 }
e86d456a
CM		 310 if (dss_has_feature(FEAT_MGR_LCD3)) {
311 SR(CONTROL3);
312 SR(CONFIG3);
313 }
80c39712 314
c6104b8e
AT		 315 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
316 SR(DEFAULT_COLOR(i));
317 SR(TRANS_COLOR(i));
318 SR(SIZE_MGR(i));
319 if (i == OMAP_DSS_CHANNEL_DIGIT)
320 continue;
321 SR(TIMING_H(i));
322 SR(TIMING_V(i));
323 SR(POL_FREQ(i));
324 SR(DIVISORo(i));
325
326 SR(DATA_CYCLE1(i));
327 SR(DATA_CYCLE2(i));
328 SR(DATA_CYCLE3(i));
329
332e9d70 330 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 331 SR(CPR_COEF_R(i));
332 SR(CPR_COEF_G(i));
333 SR(CPR_COEF_B(i));
332e9d70 334 }
2a205f34 335 }
80c39712 336
c6104b8e
AT		 337 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
338 SR(OVL_BA0(i));
339 SR(OVL_BA1(i));
340 SR(OVL_POSITION(i));
341 SR(OVL_SIZE(i));
342 SR(OVL_ATTRIBUTES(i));
343 SR(OVL_FIFO_THRESHOLD(i));
344 SR(OVL_ROW_INC(i));
345 SR(OVL_PIXEL_INC(i));
346 if (dss_has_feature(FEAT_PRELOAD))
347 SR(OVL_PRELOAD(i));
348 if (i == OMAP_DSS_GFX) {
349 SR(OVL_WINDOW_SKIP(i));
350 SR(OVL_TABLE_BA(i));
351 continue;
352 }
353 SR(OVL_FIR(i));
354 SR(OVL_PICTURE_SIZE(i));
355 SR(OVL_ACCU0(i));
356 SR(OVL_ACCU1(i));
9b372c2d 357
c6104b8e
AT		 358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 360
c6104b8e
AT		 361 for (j = 0; j < 8; j++)
362 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 363
c6104b8e
AT		 364 for (j = 0; j < 5; j++)
365 SR(OVL_CONV_COEF(i, j));
ab5ca071 366
c6104b8e
AT		 367 if (dss_has_feature(FEAT_FIR_COEF_V)) {
368 for (j = 0; j < 8; j++)
369 SR(OVL_FIR_COEF_V(i, j));
370 }
9b372c2d 371
c6104b8e
AT		 372 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
373 SR(OVL_BA0_UV(i));
374 SR(OVL_BA1_UV(i));
375 SR(OVL_FIR2(i));
376 SR(OVL_ACCU2_0(i));
377 SR(OVL_ACCU2_1(i));
ab5ca071 378
c6104b8e
AT		 379 for (j = 0; j < 8; j++)
380 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 381
c6104b8e
AT		 382 for (j = 0; j < 8; j++)
383 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 384
c6104b8e
AT		 385 for (j = 0; j < 8; j++)
386 SR(OVL_FIR_COEF_V2(i, j));
387 }
388 if (dss_has_feature(FEAT_ATTR2))
389 SR(OVL_ATTRIBUTES2(i));
ab5ca071 390 }
0cf35df3
MR		 391
392 if (dss_has_feature(FEAT_CORE_CLK_DIV))
393 SR(DIVISOR);
49ea86f3 394
49ea86f3
TV		 395 dispc.ctx_valid = true;
396
9229b516 397 DSSDBG("context saved\n");
80c39712
TV		 398}
399
4fbafaf3 400static void dispc_restore_context(void)
80c39712 401{
9229b516 402 int i, j;
4fbafaf3
TV		 403
404 DSSDBG("dispc_restore_context\n");
405
49ea86f3
TV		 406 if (!dispc.ctx_valid)
407 return;
408
75c7d59d 409 /*RR(IRQENABLE);*/
80c39712
TV		 410 /*RR(CONTROL);*/
411 RR(CONFIG);
80c39712 412 RR(LINE_NUMBER);
11354dd5
AT		 413 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
414 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 415 RR(GLOBAL_ALPHA);
c6104b8e 416 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 417 RR(CONFIG2);
e86d456a
CM		 418 if (dss_has_feature(FEAT_MGR_LCD3))
419 RR(CONFIG3);
80c39712 420
c6104b8e
AT		 421 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
422 RR(DEFAULT_COLOR(i));
423 RR(TRANS_COLOR(i));
424 RR(SIZE_MGR(i));
425 if (i == OMAP_DSS_CHANNEL_DIGIT)
426 continue;
427 RR(TIMING_H(i));
428 RR(TIMING_V(i));
429 RR(POL_FREQ(i));
430 RR(DIVISORo(i));
431
432 RR(DATA_CYCLE1(i));
433 RR(DATA_CYCLE2(i));
434 RR(DATA_CYCLE3(i));
2a205f34 435
332e9d70 436 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 437 RR(CPR_COEF_R(i));
438 RR(CPR_COEF_G(i));
439 RR(CPR_COEF_B(i));
332e9d70 440 }
2a205f34 441 }
80c39712 442
c6104b8e
AT		 443 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
444 RR(OVL_BA0(i));
445 RR(OVL_BA1(i));
446 RR(OVL_POSITION(i));
447 RR(OVL_SIZE(i));
448 RR(OVL_ATTRIBUTES(i));
449 RR(OVL_FIFO_THRESHOLD(i));
450 RR(OVL_ROW_INC(i));
451 RR(OVL_PIXEL_INC(i));
452 if (dss_has_feature(FEAT_PRELOAD))
453 RR(OVL_PRELOAD(i));
454 if (i == OMAP_DSS_GFX) {
455 RR(OVL_WINDOW_SKIP(i));
456 RR(OVL_TABLE_BA(i));
457 continue;
458 }
459 RR(OVL_FIR(i));
460 RR(OVL_PICTURE_SIZE(i));
461 RR(OVL_ACCU0(i));
462 RR(OVL_ACCU1(i));
9b372c2d 463
c6104b8e
AT		 464 for (j = 0; j < 8; j++)
465 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 466
c6104b8e
AT		 467 for (j = 0; j < 8; j++)
468 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 469
c6104b8e
AT		 470 for (j = 0; j < 5; j++)
471 RR(OVL_CONV_COEF(i, j));
ab5ca071 472
c6104b8e
AT		 473 if (dss_has_feature(FEAT_FIR_COEF_V)) {
474 for (j = 0; j < 8; j++)
475 RR(OVL_FIR_COEF_V(i, j));
476 }
9b372c2d 477
c6104b8e
AT		 478 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
479 RR(OVL_BA0_UV(i));
480 RR(OVL_BA1_UV(i));
481 RR(OVL_FIR2(i));
482 RR(OVL_ACCU2_0(i));
483 RR(OVL_ACCU2_1(i));
ab5ca071 484
c6104b8e
AT		 485 for (j = 0; j < 8; j++)
486 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 487
c6104b8e
AT		 488 for (j = 0; j < 8; j++)
489 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 490
c6104b8e
AT		 491 for (j = 0; j < 8; j++)
492 RR(OVL_FIR_COEF_V2(i, j));
493 }
494 if (dss_has_feature(FEAT_ATTR2))
495 RR(OVL_ATTRIBUTES2(i));
ab5ca071 496 }
80c39712 497
0cf35df3
MR		 498 if (dss_has_feature(FEAT_CORE_CLK_DIV))
499 RR(DIVISOR);
500
80c39712
TV		 501 /* enable last, because LCD & DIGIT enable are here */
502 RR(CONTROL);
2a205f34
SS		 503 if (dss_has_feature(FEAT_MGR_LCD2))
504 RR(CONTROL2);
e86d456a
CM		 505 if (dss_has_feature(FEAT_MGR_LCD3))
506 RR(CONTROL3);
75c7d59d 507 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 508 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 509
510 /*
511 * enable last so IRQs won't trigger before
512 * the context is fully restored
513 */
514 RR(IRQENABLE);
49ea86f3
TV		 515
516 DSSDBG("context restored\n");
80c39712
TV		 517}
518
519#undef SR
520#undef RR
521
4fbafaf3
TV		 522int dispc_runtime_get(void)
523{
524 int r;
525
526 DSSDBG("dispc_runtime_get\n");
527
528 r = pm_runtime_get_sync(&dispc.pdev->dev);
529 WARN_ON(r < 0);
530 return r < 0 ? r : 0;
531}
348be69d 532EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 533
534void dispc_runtime_put(void)
535{
536 int r;
537
538 DSSDBG("dispc_runtime_put\n");
539
0eaf9f52 540 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 541 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 542}
348be69d 543EXPORT_SYMBOL(dispc_runtime_put);
80c39712 544
3dcec4d6
TV		 545u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
546{
efa70b3b 547 return mgr_desc[channel].vsync_irq;
3dcec4d6 548}
348be69d 549EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 550
7d1365c9
TV		 551u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
552{
cffa947d
TV		 553 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
554 return 0;
555
efa70b3b 556 return mgr_desc[channel].framedone_irq;
7d1365c9 557}
348be69d 558EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 559
cb699200
TV		 560u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
561{
562 return mgr_desc[channel].sync_lost_irq;
563}
348be69d 564EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 565
0b23e5b8
AT		 566u32 dispc_wb_get_framedone_irq(void)
567{
568 return DISPC_IRQ_FRAMEDONEWB;
569}
570
26d9dd0d 571bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 572{
efa70b3b 573 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 574}
348be69d 575EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 576
26d9dd0d 577void dispc_mgr_go(enum omap_channel channel)
80c39712 578{
3c91ee8c
TV		 579 WARN_ON(dispc_mgr_is_enabled(channel) == false);
580 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 581
efa70b3b 582 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 583
efa70b3b 584 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 585}
348be69d 586EXPORT_SYMBOL(dispc_mgr_go);
80c39712 587
0b23e5b8
AT		 588bool dispc_wb_go_busy(void)
589{
590 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
591}
592
593void dispc_wb_go(void)
594{
595 enum omap_plane plane = OMAP_DSS_WB;
596 bool enable, go;
597
598 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
599
600 if (!enable)
601 return;
602
603 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
604 if (go) {
605 DSSERR("GO bit not down for WB\n");
606 return;
607 }
608
609 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
610}
611
f0e5caab 612static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 613{
9b372c2d 614 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 615}
616
f0e5caab 617static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 618{
9b372c2d 619 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 620}
621
f0e5caab 622static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 623{
9b372c2d 624 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 625}
626
f0e5caab 627static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 628{
629 BUG_ON(plane == OMAP_DSS_GFX);
630
631 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
632}
633
f0e5caab
TV		 634static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
635 u32 value)
ab5ca071
AJ		 636{
637 BUG_ON(plane == OMAP_DSS_GFX);
638
639 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
640}
641
f0e5caab 642static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 643{
644 BUG_ON(plane == OMAP_DSS_GFX);
645
646 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
647}
648
debd9074
CM		 649static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
650 int fir_vinc, int five_taps,
651 enum omap_color_component color_comp)
80c39712 652{
debd9074 653 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 654 int i;
655
debd9074
CM		 656 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
657 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 658
659 for (i = 0; i < 8; i++) {
660 u32 h, hv;
661
debd9074
CM		 662 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
663 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
664 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
665 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
666 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
667 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
668 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
669 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 670
0d66cbb5 671 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 672 dispc_ovl_write_firh_reg(plane, i, h);
673 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 674 } else {
f0e5caab
TV		 675 dispc_ovl_write_firh2_reg(plane, i, h);
676 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 677 }
678
80c39712
TV		 679 }
680
66be8f6c
GI		 681 if (five_taps) {
682 for (i = 0; i < 8; i++) {
683 u32 v;
debd9074
CM		 684 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
685 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 686 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 687 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 688 else
f0e5caab 689 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 690 }
80c39712
TV		 691 }
692}
693
80c39712 694
6e5264b0
AT		 695static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
696 const struct color_conv_coef *ct)
697{
80c39712
TV		 698#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
699
6e5264b0
AT		 700 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
701 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
702 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
703 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
704 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 705
6e5264b0 706 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 707
708#undef CVAL
80c39712
TV		 709}
710
6e5264b0
AT		 711static void dispc_setup_color_conv_coef(void)
712{
713 int i;
714 int num_ovl = dss_feat_get_num_ovls();
6e5264b0 715 const struct color_conv_coef ctbl_bt601_5_ovl = {
7d18bbee 716 /* YUV -> RGB */
6e5264b0
AT		 717 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
718 };
719 const struct color_conv_coef ctbl_bt601_5_wb = {
7d18bbee
TV		 720 /* RGB -> YUV */
721 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
6e5264b0
AT		 722 };
723
724 for (i = 1; i < num_ovl; i++)
725 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
726
20efbc35
TV		 727 if (dispc.feat->has_writeback)
728 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
6e5264b0 729}
80c39712 730
f0e5caab 731static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 732{
9b372c2d 733 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 734}
735
f0e5caab 736static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 737{
9b372c2d 738 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 739}
740
f0e5caab 741static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 742{
743 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
744}
745
f0e5caab 746static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 747{
748 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
749}
750
d79db853
AT		 751static void dispc_ovl_set_pos(enum omap_plane plane,
752 enum omap_overlay_caps caps, int x, int y)
80c39712 753{
d79db853
AT		 754 u32 val;
755
756 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
757 return;
758
759 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 760
761 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 762}
763
78b687fc
AT		 764static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
765 int height)
80c39712 766{
80c39712 767 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 768
36d87d95 769 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 770 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
771 else
772 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 773}
774
78b687fc
AT		 775static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
776 int height)
80c39712
TV		 777{
778 u32 val;
80c39712
TV		 779
780 BUG_ON(plane == OMAP_DSS_GFX);
781
782 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 783
36d87d95
AT		 784 if (plane == OMAP_DSS_WB)
785 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
786 else
787 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 788}
789
5b54ed3e
AT		 790static void dispc_ovl_set_zorder(enum omap_plane plane,
791 enum omap_overlay_caps caps, u8 zorder)
54128701 792{
5b54ed3e 793 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 794 return;
795
796 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
797}
798
799static void dispc_ovl_enable_zorder_planes(void)
800{
801 int i;
802
803 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
804 return;
805
806 for (i = 0; i < dss_feat_get_num_ovls(); i++)
807 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
808}
809
5b54ed3e
AT		 810static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
811 enum omap_overlay_caps caps, bool enable)
fd28a390 812{
5b54ed3e 813 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 814 return;
815
9b372c2d 816 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 817}
818
5b54ed3e
AT		 819static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
820 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 821{
b8c095b4 822 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 823 int shift;
824
5b54ed3e 825 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 826 return;
a0acb557 827
fe3cc9d6
TV		 828 shift = shifts[plane];
829 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 830}
831
f0e5caab 832static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 833{
9b372c2d 834 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 835}
836
f0e5caab 837static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 838{
9b372c2d 839 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 840}
841
f0e5caab 842static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 843 enum omap_color_mode color_mode)
844{
845 u32 m = 0;
f20e4220
AJ		 846 if (plane != OMAP_DSS_GFX) {
847 switch (color_mode) {
848 case OMAP_DSS_COLOR_NV12:
849 m = 0x0; break;
08f3267e 850 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 851 m = 0x1; break;
852 case OMAP_DSS_COLOR_RGBA16:
853 m = 0x2; break;
08f3267e 854 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 855 m = 0x4; break;
856 case OMAP_DSS_COLOR_ARGB16:
857 m = 0x5; break;
858 case OMAP_DSS_COLOR_RGB16:
859 m = 0x6; break;
860 case OMAP_DSS_COLOR_ARGB16_1555:
861 m = 0x7; break;
862 case OMAP_DSS_COLOR_RGB24U:
863 m = 0x8; break;
864 case OMAP_DSS_COLOR_RGB24P:
865 m = 0x9; break;
866 case OMAP_DSS_COLOR_YUV2:
867 m = 0xa; break;
868 case OMAP_DSS_COLOR_UYVY:
869 m = 0xb; break;
870 case OMAP_DSS_COLOR_ARGB32:
871 m = 0xc; break;
872 case OMAP_DSS_COLOR_RGBA32:
873 m = 0xd; break;
874 case OMAP_DSS_COLOR_RGBX32:
875 m = 0xe; break;
876 case OMAP_DSS_COLOR_XRGB16_1555:
877 m = 0xf; break;
878 default:
c6eee968 879 BUG(); return;
f20e4220
AJ		 880 }
881 } else {
882 switch (color_mode) {
883 case OMAP_DSS_COLOR_CLUT1:
884 m = 0x0; break;
885 case OMAP_DSS_COLOR_CLUT2:
886 m = 0x1; break;
887 case OMAP_DSS_COLOR_CLUT4:
888 m = 0x2; break;
889 case OMAP_DSS_COLOR_CLUT8:
890 m = 0x3; break;
891 case OMAP_DSS_COLOR_RGB12U:
892 m = 0x4; break;
893 case OMAP_DSS_COLOR_ARGB16:
894 m = 0x5; break;
895 case OMAP_DSS_COLOR_RGB16:
896 m = 0x6; break;
897 case OMAP_DSS_COLOR_ARGB16_1555:
898 m = 0x7; break;
899 case OMAP_DSS_COLOR_RGB24U:
900 m = 0x8; break;
901 case OMAP_DSS_COLOR_RGB24P:
902 m = 0x9; break;
08f3267e 903 case OMAP_DSS_COLOR_RGBX16:
f20e4220 904 m = 0xa; break;
08f3267e 905 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 906 m = 0xb; break;
907 case OMAP_DSS_COLOR_ARGB32:
908 m = 0xc; break;
909 case OMAP_DSS_COLOR_RGBA32:
910 m = 0xd; break;
911 case OMAP_DSS_COLOR_RGBX32:
912 m = 0xe; break;
913 case OMAP_DSS_COLOR_XRGB16_1555:
914 m = 0xf; break;
915 default:
c6eee968 916 BUG(); return;
f20e4220 917 }
80c39712
TV		 918 }
919
9b372c2d 920 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 921}
922
65e006ff
CM		 923static void dispc_ovl_configure_burst_type(enum omap_plane plane,
924 enum omap_dss_rotation_type rotation_type)
925{
926 if (dss_has_feature(FEAT_BURST_2D) == 0)
927 return;
928
929 if (rotation_type == OMAP_DSS_ROT_TILER)
930 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
931 else
932 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
933}
934
f427984e 935void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 936{
937 int shift;
938 u32 val;
2a205f34 939 int chan = 0, chan2 = 0;
80c39712
TV		 940
941 switch (plane) {
942 case OMAP_DSS_GFX:
943 shift = 8;
944 break;
945 case OMAP_DSS_VIDEO1:
946 case OMAP_DSS_VIDEO2:
b8c095b4 947 case OMAP_DSS_VIDEO3:
80c39712
TV		 948 shift = 16;
949 break;
950 default:
951 BUG();
952 return;
953 }
954
9b372c2d 955 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 956 if (dss_has_feature(FEAT_MGR_LCD2)) {
957 switch (channel) {
958 case OMAP_DSS_CHANNEL_LCD:
959 chan = 0;
960 chan2 = 0;
961 break;
962 case OMAP_DSS_CHANNEL_DIGIT:
963 chan = 1;
964 chan2 = 0;
965 break;
966 case OMAP_DSS_CHANNEL_LCD2:
967 chan = 0;
968 chan2 = 1;
969 break;
e86d456a
CM		 970 case OMAP_DSS_CHANNEL_LCD3:
971 if (dss_has_feature(FEAT_MGR_LCD3)) {
972 chan = 0;
973 chan2 = 2;
974 } else {
975 BUG();
976 return;
977 }
978 break;
c2665c41
TV		 979 case OMAP_DSS_CHANNEL_WB:
980 chan = 0;
981 chan2 = 3;
982 break;
2a205f34
SS		 983 default:
984 BUG();
c6eee968 985 return;
2a205f34
SS		 986 }
987
988 val = FLD_MOD(val, chan, shift, shift);
989 val = FLD_MOD(val, chan2, 31, 30);
990 } else {
991 val = FLD_MOD(val, channel, shift, shift);
992 }
9b372c2d 993 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 994}
348be69d 995EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 996
2cc5d1af
TV		 997static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
998{
999 int shift;
1000 u32 val;
2cc5d1af
TV		 1001
1002 switch (plane) {
1003 case OMAP_DSS_GFX:
1004 shift = 8;
1005 break;
1006 case OMAP_DSS_VIDEO1:
1007 case OMAP_DSS_VIDEO2:
1008 case OMAP_DSS_VIDEO3:
1009 shift = 16;
1010 break;
1011 default:
1012 BUG();
c6eee968 1013 return 0;
2cc5d1af
TV		 1014 }
1015
1016 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1017
d7df5ad4
TV		 1018 if (FLD_GET(val, shift, shift) == 1)
1019 return OMAP_DSS_CHANNEL_DIGIT;
2cc5d1af 1020
d7df5ad4
TV		 1021 if (!dss_has_feature(FEAT_MGR_LCD2))
1022 return OMAP_DSS_CHANNEL_LCD;
1023
1024 switch (FLD_GET(val, 31, 30)) {
1025 case 0:
1026 default:
1027 return OMAP_DSS_CHANNEL_LCD;
1028 case 1:
1029 return OMAP_DSS_CHANNEL_LCD2;
1030 case 2:
1031 return OMAP_DSS_CHANNEL_LCD3;
c2665c41
TV		 1032 case 3:
1033 return OMAP_DSS_CHANNEL_WB;
d7df5ad4 1034 }
2cc5d1af
TV		 1035}
1036
d9ac773c
AT		 1037void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1038{
1039 enum omap_plane plane = OMAP_DSS_WB;
1040
1041 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1042}
1043
f0e5caab 1044static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1045 enum omap_burst_size burst_size)
1046{
8bbe09ee 1047 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1048 int shift;
80c39712 1049
fe3cc9d6 1050 shift = shifts[plane];
5ed8cf5b 1051 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1052}
1053
5ed8cf5b
TV		 1054static void dispc_configure_burst_sizes(void)
1055{
1056 int i;
1057 const int burst_size = BURST_SIZE_X8;
1058
1059 /* Configure burst size always to maximum size */
392faa0e 1060 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1061 dispc_ovl_set_burst_size(i, burst_size);
5b354af9
TV		 1062 if (dispc.feat->has_writeback)
1063 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
5ed8cf5b
TV		 1064}
1065
83fa2f2e 1066static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1067{
1068 unsigned unit = dss_feat_get_burst_size_unit();
1069 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1070 return unit * 8;
1071}
1072
d3862610
M		 1073void dispc_enable_gamma_table(bool enable)
1074{
1075 /*
1076 * This is partially implemented to support only disabling of
1077 * the gamma table.
1078 */
1079 if (enable) {
1080 DSSWARN("Gamma table enabling for TV not yet supported");
1081 return;
1082 }
1083
1084 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1085}
1086
c64dca40 1087static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1088{
efa70b3b 1089 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1090 return;
1091
efa70b3b 1092 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1093}
1094
c64dca40 1095static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1096 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1097{
1098 u32 coef_r, coef_g, coef_b;
1099
dd88b7a6 1100 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1101 return;
1102
1103 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1104 FLD_VAL(coefs->rb, 9, 0);
1105 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1106 FLD_VAL(coefs->gb, 9, 0);
1107 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1108 FLD_VAL(coefs->bb, 9, 0);
1109
1110 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1111 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1112 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1113}
1114
f0e5caab 1115static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1116{
1117 u32 val;
1118
1119 BUG_ON(plane == OMAP_DSS_GFX);
1120
9b372c2d 1121 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1122 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1123 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1124}
1125
d79db853
AT		 1126static void dispc_ovl_enable_replication(enum omap_plane plane,
1127 enum omap_overlay_caps caps, bool enable)
80c39712 1128{
b8c095b4 1129 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1130 int shift;
80c39712 1131
d79db853
AT		 1132 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1133 return;
1134
fe3cc9d6
TV		 1135 shift = shifts[plane];
1136 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1137}
1138
8f366162 1139static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1140 u16 height)
80c39712
TV		 1141{
1142 u32 val;
80c39712 1143
33b89928
AT		 1144 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1145 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1146
8f366162 1147 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1148}
1149
42a6961c 1150static void dispc_init_fifos(void)
80c39712 1151{
80c39712 1152 u32 size;
42a6961c 1153 int fifo;
a0acb557 1154 u8 start, end;
5ed8cf5b 1155 u32 unit;
47fc469b 1156 int i;
5ed8cf5b
TV		 1157
1158 unit = dss_feat_get_buffer_size_unit();
80c39712 1159
a0acb557 1160 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1161
42a6961c
TV		 1162 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1163 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1164 size *= unit;
42a6961c
TV		 1165 dispc.fifo_size[fifo] = size;
1166
1167 /*
1168 * By default fifos are mapped directly to overlays, fifo 0 to
1169 * ovl 0, fifo 1 to ovl 1, etc.
1170 */
1171 dispc.fifo_assignment[fifo] = fifo;
80c39712 1172 }
66a0f9e4
TV		 1173
1174 /*
1175 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1176 * causes problems with certain use cases, like using the tiler in 2D
1177 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1178 * giving GFX plane a larger fifo. WB but should work fine with a
1179 * smaller fifo.
1180 */
1181 if (dispc.feat->gfx_fifo_workaround) {
1182 u32 v;
1183
1184 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1185
1186 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1187 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1188 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1189 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1190
1191 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1192
1193 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1194 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1195 }
47fc469b
TV		 1196
1197 /*
1198 * Setup default fifo thresholds.
1199 */
1200 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1201 u32 low, high;
1202 const bool use_fifomerge = false;
1203 const bool manual_update = false;
1204
1205 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1206 use_fifomerge, manual_update);
1207
1208 dispc_ovl_set_fifo_threshold(i, low, high);
1209 }
65e116e1
TV		 1210
1211 if (dispc.feat->has_writeback) {
1212 u32 low, high;
1213 const bool use_fifomerge = false;
1214 const bool manual_update = false;
1215
1216 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1217 use_fifomerge, manual_update);
1218
1219 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1220 }
80c39712
TV		 1221}
1222
83fa2f2e 1223static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1224{
42a6961c
TV		 1225 int fifo;
1226 u32 size = 0;
1227
1228 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1229 if (dispc.fifo_assignment[fifo] == plane)
1230 size += dispc.fifo_size[fifo];
1231 }
1232
1233 return size;
80c39712
TV		 1234}
1235
6f04e1bf 1236void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1237{
a0acb557 1238 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1239 u32 unit;
1240
1241 unit = dss_feat_get_buffer_size_unit();
1242
1243 WARN_ON(low % unit != 0);
1244 WARN_ON(high % unit != 0);
1245
1246 low /= unit;
1247 high /= unit;
a0acb557 1248
9b372c2d
AT		 1249 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1250 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1251
3cb5d966 1252 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1253 plane,
9b372c2d 1254 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1255 lo_start, lo_end) * unit,
9b372c2d 1256 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1257 hi_start, hi_end) * unit,
1258 low * unit, high * unit);
80c39712 1259
9b372c2d 1260 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1261 FLD_VAL(high, hi_start, hi_end) |
1262 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1263
1264 /*
1265 * configure the preload to the pipeline's high threhold, if HT it's too
1266 * large for the preload field, set the threshold to the maximum value
1267 * that can be held by the preload register
1268 */
1269 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1270 plane != OMAP_DSS_WB)
1271 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712
TV		 1272}
1273
1274void dispc_enable_fifomerge(bool enable)
1275{
e6b0f884
TV		 1276 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1277 WARN_ON(enable);
1278 return;
1279 }
1280
80c39712
TV		 1281 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1282 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1283}
1284
83fa2f2e 1285void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1286 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1287 bool manual_update)
83fa2f2e
TV		 1288{
1289 /*
1290 * All sizes are in bytes. Both the buffer and burst are made of
1291 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1292 */
1293
1294 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1295 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1296 int i;
83fa2f2e
TV		 1297
1298 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1299 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1300
e0e405b9
TV		 1301 if (use_fifomerge) {
1302 total_fifo_size = 0;
392faa0e 1303 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1304 total_fifo_size += dispc_ovl_get_fifo_size(i);
1305 } else {
1306 total_fifo_size = ovl_fifo_size;
1307 }
1308
1309 /*
1310 * We use the same low threshold for both fifomerge and non-fifomerge
1311 * cases, but for fifomerge we calculate the high threshold using the
1312 * combined fifo size
1313 */
1314
3568f2a4 1315 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1316 *fifo_low = ovl_fifo_size - burst_size * 2;
1317 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1318 } else if (plane == OMAP_DSS_WB) {
1319 /*
1320 * Most optimal configuration for writeback is to push out data
1321 * to the interconnect the moment writeback pushes enough pixels
1322 * in the FIFO to form a burst
1323 */
1324 *fifo_low = 0;
1325 *fifo_high = burst_size;
e0e405b9
TV		 1326 } else {
1327 *fifo_low = ovl_fifo_size - burst_size;
1328 *fifo_high = total_fifo_size - buf_unit;
1329 }
83fa2f2e
TV		 1330}
1331
c64aa3a6
TV		 1332static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1333{
1334 int bit;
1335
1336 if (plane == OMAP_DSS_GFX)
1337 bit = 14;
1338 else
1339 bit = 23;
1340
1341 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1342}
1343
1344static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1345 int low, int high)
1346{
1347 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1348 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1349}
1350
1351static void dispc_init_mflag(void)
1352{
1353 int i;
1354
fe59e5cf
TV		 1355 /*
1356 * HACK: NV12 color format and MFLAG seem to have problems working
1357 * together: using two displays, and having an NV12 overlay on one of
1358 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1359 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1360 * remove the errors, but there doesn't seem to be a clear logic on
1361 * which values work and which not.
1362 *
1363 * As a work-around, set force MFLAG to always on.
1364 */
c64aa3a6 1365 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
fe59e5cf 1366 (1 << 0) | /* MFLAG_CTRL = force always on */
c64aa3a6
TV		 1367 (0 << 2)); /* MFLAG_START = disable */
1368
1369 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1370 u32 size = dispc_ovl_get_fifo_size(i);
1371 u32 unit = dss_feat_get_buffer_size_unit();
1372 u32 low, high;
1373
1374 dispc_ovl_set_mflag(i, true);
1375
1376 /*
1377 * Simulation team suggests below thesholds:
1378 * HT = fifosize * 5 / 8;
1379 * LT = fifosize * 4 / 8;
1380 */
1381
1382 low = size * 4 / 8 / unit;
1383 high = size * 5 / 8 / unit;
1384
1385 dispc_ovl_set_mflag_threshold(i, low, high);
1386 }
ecb0b366
TV		 1387
1388 if (dispc.feat->has_writeback) {
1389 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1390 u32 unit = dss_feat_get_buffer_size_unit();
1391 u32 low, high;
1392
1393 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1394
1395 /*
1396 * Simulation team suggests below thesholds:
1397 * HT = fifosize * 5 / 8;
1398 * LT = fifosize * 4 / 8;
1399 */
1400
1401 low = size * 4 / 8 / unit;
1402 high = size * 5 / 8 / unit;
1403
1404 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1405 }
c64aa3a6
TV		 1406}
1407
f0e5caab 1408static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1409 int hinc, int vinc,
1410 enum omap_color_component color_comp)
80c39712
TV		 1411{
1412 u32 val;
80c39712 1413
0d66cbb5
AJ		 1414 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1415 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1416
0d66cbb5
AJ		 1417 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1418 &hinc_start, &hinc_end);
1419 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1420 &vinc_start, &vinc_end);
1421 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1422 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1423
0d66cbb5
AJ		 1424 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1425 } else {
1426 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1427 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1428 }
80c39712
TV		 1429}
1430
f0e5caab 1431static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1432{
1433 u32 val;
87a7484b 1434 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1435
87a7484b
AT		 1436 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1437 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1438
1439 val = FLD_VAL(vaccu, vert_start, vert_end) |
1440 FLD_VAL(haccu, hor_start, hor_end);
1441
9b372c2d 1442 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1443}
1444
f0e5caab 1445static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1446{
1447 u32 val;
87a7484b 1448 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1449
87a7484b
AT		 1450 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1451 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1452
1453 val = FLD_VAL(vaccu, vert_start, vert_end) |
1454 FLD_VAL(haccu, hor_start, hor_end);
1455
9b372c2d 1456 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1457}
1458
f0e5caab
TV		 1459static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1460 int vaccu)
ab5ca071
AJ		 1461{
1462 u32 val;
1463
1464 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1465 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1466}
1467
f0e5caab
TV		 1468static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1469 int vaccu)
ab5ca071
AJ		 1470{
1471 u32 val;
1472
1473 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1474 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1475}
80c39712 1476
f0e5caab 1477static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1478 u16 orig_width, u16 orig_height,
1479 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1480 bool five_taps, u8 rotation,
1481 enum omap_color_component color_comp)
80c39712 1482{
0d66cbb5 1483 int fir_hinc, fir_vinc;
80c39712 1484
ed14a3ce
AJ		 1485 fir_hinc = 1024 * orig_width / out_width;
1486 fir_vinc = 1024 * orig_height / out_height;
80c39712 1487
debd9074
CM		 1488 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1489 color_comp);
f0e5caab 1490 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1491}
1492
05dd0f53
CM		 1493static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1494 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1495 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1496{
1497 int h_accu2_0, h_accu2_1;
1498 int v_accu2_0, v_accu2_1;
1499 int chroma_hinc, chroma_vinc;
1500 int idx;
1501
1502 struct accu {
1503 s8 h0_m, h0_n;
1504 s8 h1_m, h1_n;
1505 s8 v0_m, v0_n;
1506 s8 v1_m, v1_n;
1507 };
1508
1509 const struct accu *accu_table;
1510 const struct accu *accu_val;
1511
1512 static const struct accu accu_nv12[4] = {
1513 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1514 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1515 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1516 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1517 };
1518
1519 static const struct accu accu_nv12_ilace[4] = {
1520 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1521 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1522 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1523 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1524 };
1525
1526 static const struct accu accu_yuv[4] = {
1527 { 0, 1, 0, 1, 0, 1, 0, 1 },
1528 { 0, 1, 0, 1, 0, 1, 0, 1 },
1529 { -1, 1, 0, 1, 0, 1, 0, 1 },
1530 { 0, 1, 0, 1, -1, 1, 0, 1 },
1531 };
1532
1533 switch (rotation) {
1534 case OMAP_DSS_ROT_0:
1535 idx = 0;
1536 break;
1537 case OMAP_DSS_ROT_90:
1538 idx = 1;
1539 break;
1540 case OMAP_DSS_ROT_180:
1541 idx = 2;
1542 break;
1543 case OMAP_DSS_ROT_270:
1544 idx = 3;
1545 break;
1546 default:
1547 BUG();
c6eee968 1548 return;
05dd0f53
CM		 1549 }
1550
1551 switch (color_mode) {
1552 case OMAP_DSS_COLOR_NV12:
1553 if (ilace)
1554 accu_table = accu_nv12_ilace;
1555 else
1556 accu_table = accu_nv12;
1557 break;
1558 case OMAP_DSS_COLOR_YUV2:
1559 case OMAP_DSS_COLOR_UYVY:
1560 accu_table = accu_yuv;
1561 break;
1562 default:
1563 BUG();
c6eee968 1564 return;
05dd0f53
CM		 1565 }
1566
1567 accu_val = &accu_table[idx];
1568
1569 chroma_hinc = 1024 * orig_width / out_width;
1570 chroma_vinc = 1024 * orig_height / out_height;
1571
1572 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1573 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1574 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1575 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1576
1577 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1578 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1579}
1580
f0e5caab 1581static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1582 u16 orig_width, u16 orig_height,
1583 u16 out_width, u16 out_height,
1584 bool ilace, bool five_taps,
1585 bool fieldmode, enum omap_color_mode color_mode,
1586 u8 rotation)
1587{
1588 int accu0 = 0;
1589 int accu1 = 0;
1590 u32 l;
80c39712 1591
f0e5caab 1592 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1593 out_width, out_height, five_taps,
1594 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1595 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1596
87a7484b
AT		 1597 /* RESIZEENABLE and VERTICALTAPS */
1598 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1599 l |= (orig_width != out_width) ? (1 << 5) : 0;
1600 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1601 l |= five_taps ? (1 << 21) : 0;
80c39712 1602
87a7484b
AT		 1603 /* VRESIZECONF and HRESIZECONF */
1604 if (dss_has_feature(FEAT_RESIZECONF)) {
1605 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1606 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1607 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1608 }
80c39712 1609
87a7484b
AT		 1610 /* LINEBUFFERSPLIT */
1611 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1612 l &= ~(0x1 << 22);
1613 l |= five_taps ? (1 << 22) : 0;
1614 }
80c39712 1615
9b372c2d 1616 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1617
1618 /*
1619 * field 0 = even field = bottom field
1620 * field 1 = odd field = top field
1621 */
1622 if (ilace && !fieldmode) {
1623 accu1 = 0;
0d66cbb5 1624 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1625 if (accu0 >= 1024/2) {
1626 accu1 = 1024/2;
1627 accu0 -= accu1;
1628 }
1629 }
1630
f0e5caab
TV		 1631 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1632 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1633}
1634
f0e5caab 1635static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1636 u16 orig_width, u16 orig_height,
1637 u16 out_width, u16 out_height,
1638 bool ilace, bool five_taps,
1639 bool fieldmode, enum omap_color_mode color_mode,
1640 u8 rotation)
1641{
1642 int scale_x = out_width != orig_width;
1643 int scale_y = out_height != orig_height;
f92afae2 1644 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1645
1646 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1647 return;
1648 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1649 color_mode != OMAP_DSS_COLOR_UYVY &&
1650 color_mode != OMAP_DSS_COLOR_NV12)) {
1651 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1652 if (plane != OMAP_DSS_WB)
1653 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1654 return;
1655 }
36377357
TV		 1656
1657 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1658 out_height, ilace, color_mode, rotation);
1659
0d66cbb5
AJ		 1660 switch (color_mode) {
1661 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1662 if (chroma_upscale) {
1663 /* UV is subsampled by 2 horizontally and vertically */
1664 orig_height >>= 1;
1665 orig_width >>= 1;
1666 } else {
1667 /* UV is downsampled by 2 horizontally and vertically */
1668 orig_height <<= 1;
1669 orig_width <<= 1;
1670 }
1671
0d66cbb5
AJ		 1672 break;
1673 case OMAP_DSS_COLOR_YUV2:
1674 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1675 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1676 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1677 rotation == OMAP_DSS_ROT_180) {
1678 if (chroma_upscale)
1679 /* UV is subsampled by 2 horizontally */
1680 orig_width >>= 1;
1681 else
1682 /* UV is downsampled by 2 horizontally */
1683 orig_width <<= 1;
1684 }
1685
0d66cbb5
AJ		 1686 /* must use FIR for YUV422 if rotated */
1687 if (rotation != OMAP_DSS_ROT_0)
1688 scale_x = scale_y = true;
20fbb50b 1689
0d66cbb5
AJ		 1690 break;
1691 default:
1692 BUG();
c6eee968 1693 return;
0d66cbb5
AJ		 1694 }
1695
1696 if (out_width != orig_width)
1697 scale_x = true;
1698 if (out_height != orig_height)
1699 scale_y = true;
1700
f0e5caab 1701 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1702 out_width, out_height, five_taps,
1703 rotation, DISPC_COLOR_COMPONENT_UV);
1704
2a5561b1
AT		 1705 if (plane != OMAP_DSS_WB)
1706 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1707 (scale_x || scale_y) ? 1 : 0, 8, 8);
1708
0d66cbb5
AJ		 1709 /* set H scaling */
1710 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1711 /* set V scaling */
1712 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1713}
1714
f0e5caab 1715static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1716 u16 orig_width, u16 orig_height,
1717 u16 out_width, u16 out_height,
1718 bool ilace, bool five_taps,
1719 bool fieldmode, enum omap_color_mode color_mode,
1720 u8 rotation)
1721{
1722 BUG_ON(plane == OMAP_DSS_GFX);
1723
f0e5caab 1724 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1725 orig_width, orig_height,
1726 out_width, out_height,
1727 ilace, five_taps,
1728 fieldmode, color_mode,
1729 rotation);
1730
f0e5caab 1731 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1732 orig_width, orig_height,
1733 out_width, out_height,
1734 ilace, five_taps,
1735 fieldmode, color_mode,
1736 rotation);
1737}
1738
f0e5caab 1739static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1740 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1741 bool mirroring, enum omap_color_mode color_mode)
1742{
87a7484b
AT		 1743 bool row_repeat = false;
1744 int vidrot = 0;
1745
80c39712
TV		 1746 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1747 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1748
1749 if (mirroring) {
1750 switch (rotation) {
1751 case OMAP_DSS_ROT_0:
1752 vidrot = 2;
1753 break;
1754 case OMAP_DSS_ROT_90:
1755 vidrot = 1;
1756 break;
1757 case OMAP_DSS_ROT_180:
1758 vidrot = 0;
1759 break;
1760 case OMAP_DSS_ROT_270:
1761 vidrot = 3;
1762 break;
1763 }
1764 } else {
1765 switch (rotation) {
1766 case OMAP_DSS_ROT_0:
1767 vidrot = 0;
1768 break;
1769 case OMAP_DSS_ROT_90:
1770 vidrot = 1;
1771 break;
1772 case OMAP_DSS_ROT_180:
1773 vidrot = 2;
1774 break;
1775 case OMAP_DSS_ROT_270:
1776 vidrot = 3;
1777 break;
1778 }
1779 }
1780
80c39712 1781 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1782 row_repeat = true;
80c39712 1783 else
87a7484b 1784 row_repeat = false;
80c39712 1785 }
87a7484b 1786
3397cc6a
TV		 1787 /*
1788 * OMAP4/5 Errata i631:
1789 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1790 * rows beyond the framebuffer, which may cause OCP error.
1791 */
1792 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1793 rotation_type != OMAP_DSS_ROT_TILER)
1794 vidrot = 1;
1795
9b372c2d 1796 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1797 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1798 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1799 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1800
1801 if (color_mode == OMAP_DSS_COLOR_NV12) {
1802 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1803 (rotation == OMAP_DSS_ROT_0 ||
1804 rotation == OMAP_DSS_ROT_180);
1805 /* DOUBLESTRIDE */
1806 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1807 }
1808
80c39712
TV		 1809}
1810
1811static int color_mode_to_bpp(enum omap_color_mode color_mode)
1812{
1813 switch (color_mode) {
1814 case OMAP_DSS_COLOR_CLUT1:
1815 return 1;
1816 case OMAP_DSS_COLOR_CLUT2:
1817 return 2;
1818 case OMAP_DSS_COLOR_CLUT4:
1819 return 4;
1820 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1821 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1822 return 8;
1823 case OMAP_DSS_COLOR_RGB12U:
1824 case OMAP_DSS_COLOR_RGB16:
1825 case OMAP_DSS_COLOR_ARGB16:
1826 case OMAP_DSS_COLOR_YUV2:
1827 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1828 case OMAP_DSS_COLOR_RGBA16:
1829 case OMAP_DSS_COLOR_RGBX16:
1830 case OMAP_DSS_COLOR_ARGB16_1555:
1831 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1832 return 16;
1833 case OMAP_DSS_COLOR_RGB24P:
1834 return 24;
1835 case OMAP_DSS_COLOR_RGB24U:
1836 case OMAP_DSS_COLOR_ARGB32:
1837 case OMAP_DSS_COLOR_RGBA32:
1838 case OMAP_DSS_COLOR_RGBX32:
1839 return 32;
1840 default:
1841 BUG();
c6eee968 1842 return 0;
80c39712
TV		 1843 }
1844}
1845
1846static s32 pixinc(int pixels, u8 ps)
1847{
1848 if (pixels == 1)
1849 return 1;
1850 else if (pixels > 1)
1851 return 1 + (pixels - 1) * ps;
1852 else if (pixels < 0)
1853 return 1 - (-pixels + 1) * ps;
1854 else
1855 BUG();
c6eee968 1856 return 0;
80c39712
TV		 1857}
1858
1859static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1860 u16 screen_width,
1861 u16 width, u16 height,
1862 enum omap_color_mode color_mode, bool fieldmode,
1863 unsigned int field_offset,
1864 unsigned *offset0, unsigned *offset1,
aed74b55 1865 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1866{
1867 u8 ps;
1868
1869 /* FIXME CLUT formats */
1870 switch (color_mode) {
1871 case OMAP_DSS_COLOR_CLUT1:
1872 case OMAP_DSS_COLOR_CLUT2:
1873 case OMAP_DSS_COLOR_CLUT4:
1874 case OMAP_DSS_COLOR_CLUT8:
1875 BUG();
1876 return;
1877 case OMAP_DSS_COLOR_YUV2:
1878 case OMAP_DSS_COLOR_UYVY:
1879 ps = 4;
1880 break;
1881 default:
1882 ps = color_mode_to_bpp(color_mode) / 8;
1883 break;
1884 }
1885
1886 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1887 width, height);
1888
1889 /*
1890 * field 0 = even field = bottom field
1891 * field 1 = odd field = top field
1892 */
1893 switch (rotation + mirror * 4) {
1894 case OMAP_DSS_ROT_0:
1895 case OMAP_DSS_ROT_180:
1896 /*
1897 * If the pixel format is YUV or UYVY divide the width
1898 * of the image by 2 for 0 and 180 degree rotation.
1899 */
1900 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1901 color_mode == OMAP_DSS_COLOR_UYVY)
1902 width = width >> 1;
1903 case OMAP_DSS_ROT_90:
1904 case OMAP_DSS_ROT_270:
1905 *offset1 = 0;
1906 if (field_offset)
1907 *offset0 = field_offset * screen_width * ps;
1908 else
1909 *offset0 = 0;
1910
aed74b55
CM		 1911 *row_inc = pixinc(1 +
1912 (y_predecim * screen_width - x_predecim * width) +
1913 (fieldmode ? screen_width : 0), ps);
1914 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1915 break;
1916
1917 case OMAP_DSS_ROT_0 + 4:
1918 case OMAP_DSS_ROT_180 + 4:
1919 /* If the pixel format is YUV or UYVY divide the width
1920 * of the image by 2 for 0 degree and 180 degree
1921 */
1922 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1923 color_mode == OMAP_DSS_COLOR_UYVY)
1924 width = width >> 1;
1925 case OMAP_DSS_ROT_90 + 4:
1926 case OMAP_DSS_ROT_270 + 4:
1927 *offset1 = 0;
1928 if (field_offset)
1929 *offset0 = field_offset * screen_width * ps;
1930 else
1931 *offset0 = 0;
aed74b55
CM		 1932 *row_inc = pixinc(1 -
1933 (y_predecim * screen_width + x_predecim * width) -
1934 (fieldmode ? screen_width : 0), ps);
1935 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1936 break;
1937
1938 default:
1939 BUG();
c6eee968 1940 return;
80c39712
TV		 1941 }
1942}
1943
1944static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1945 u16 screen_width,
1946 u16 width, u16 height,
1947 enum omap_color_mode color_mode, bool fieldmode,
1948 unsigned int field_offset,
1949 unsigned *offset0, unsigned *offset1,
aed74b55 1950 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1951{
1952 u8 ps;
1953 u16 fbw, fbh;
1954
1955 /* FIXME CLUT formats */
1956 switch (color_mode) {
1957 case OMAP_DSS_COLOR_CLUT1:
1958 case OMAP_DSS_COLOR_CLUT2:
1959 case OMAP_DSS_COLOR_CLUT4:
1960 case OMAP_DSS_COLOR_CLUT8:
1961 BUG();
1962 return;
1963 default:
1964 ps = color_mode_to_bpp(color_mode) / 8;
1965 break;
1966 }
1967
1968 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1969 width, height);
1970
1971 /* width & height are overlay sizes, convert to fb sizes */
1972
1973 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1974 fbw = width;
1975 fbh = height;
1976 } else {
1977 fbw = height;
1978 fbh = width;
1979 }
1980
1981 /*
1982 * field 0 = even field = bottom field
1983 * field 1 = odd field = top field
1984 */
1985 switch (rotation + mirror * 4) {
1986 case OMAP_DSS_ROT_0:
1987 *offset1 = 0;
1988 if (field_offset)
1989 *offset0 = *offset1 + field_offset * screen_width * ps;
1990 else
1991 *offset0 = *offset1;
aed74b55
CM		 1992 *row_inc = pixinc(1 +
1993 (y_predecim * screen_width - fbw * x_predecim) +
1994 (fieldmode ? screen_width : 0), ps);
1995 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1996 color_mode == OMAP_DSS_COLOR_UYVY)
1997 *pix_inc = pixinc(x_predecim, 2 * ps);
1998 else
1999 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2000 break;
2001 case OMAP_DSS_ROT_90:
2002 *offset1 = screen_width * (fbh - 1) * ps;
2003 if (field_offset)
2004 *offset0 = *offset1 + field_offset * ps;
2005 else
2006 *offset0 = *offset1;
aed74b55
CM		 2007 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2008 y_predecim + (fieldmode ? 1 : 0), ps);
2009 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2010 break;
2011 case OMAP_DSS_ROT_180:
2012 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2013 if (field_offset)
2014 *offset0 = *offset1 - field_offset * screen_width * ps;
2015 else
2016 *offset0 = *offset1;
2017 *row_inc = pixinc(-1 -
aed74b55
CM		 2018 (y_predecim * screen_width - fbw * x_predecim) -
2019 (fieldmode ? screen_width : 0), ps);
2020 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2021 color_mode == OMAP_DSS_COLOR_UYVY)
2022 *pix_inc = pixinc(-x_predecim, 2 * ps);
2023 else
2024 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2025 break;
2026 case OMAP_DSS_ROT_270:
2027 *offset1 = (fbw - 1) * ps;
2028 if (field_offset)
2029 *offset0 = *offset1 - field_offset * ps;
2030 else
2031 *offset0 = *offset1;
aed74b55
CM		 2032 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2033 y_predecim - (fieldmode ? 1 : 0), ps);
2034 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2035 break;
2036
2037 /* mirroring */
2038 case OMAP_DSS_ROT_0 + 4:
2039 *offset1 = (fbw - 1) * ps;
2040 if (field_offset)
2041 *offset0 = *offset1 + field_offset * screen_width * ps;
2042 else
2043 *offset0 = *offset1;
aed74b55 2044 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 2045 (fieldmode ? screen_width : 0),
2046 ps);
aed74b55
CM		 2047 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2048 color_mode == OMAP_DSS_COLOR_UYVY)
2049 *pix_inc = pixinc(-x_predecim, 2 * ps);
2050 else
2051 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2052 break;
2053
2054 case OMAP_DSS_ROT_90 + 4:
2055 *offset1 = 0;
2056 if (field_offset)
2057 *offset0 = *offset1 + field_offset * ps;
2058 else
2059 *offset0 = *offset1;
aed74b55
CM		 2060 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2061 y_predecim + (fieldmode ? 1 : 0),
80c39712 2062 ps);
aed74b55 2063 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2064 break;
2065
2066 case OMAP_DSS_ROT_180 + 4:
2067 *offset1 = screen_width * (fbh - 1) * ps;
2068 if (field_offset)
2069 *offset0 = *offset1 - field_offset * screen_width * ps;
2070 else
2071 *offset0 = *offset1;
aed74b55 2072 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 2073 (fieldmode ? screen_width : 0),
2074 ps);
aed74b55
CM		 2075 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2076 color_mode == OMAP_DSS_COLOR_UYVY)
2077 *pix_inc = pixinc(x_predecim, 2 * ps);
2078 else
2079 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2080 break;
2081
2082 case OMAP_DSS_ROT_270 + 4:
2083 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2084 if (field_offset)
2085 *offset0 = *offset1 - field_offset * ps;
2086 else
2087 *offset0 = *offset1;
aed74b55
CM		 2088 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2089 y_predecim - (fieldmode ? 1 : 0),
80c39712 2090 ps);
aed74b55 2091 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2092 break;
2093
2094 default:
2095 BUG();
c6eee968 2096 return;
80c39712
TV		 2097 }
2098}
2099
65e006ff
CM		 2100static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2101 enum omap_color_mode color_mode, bool fieldmode,
2102 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2103 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2104{
2105 u8 ps;
2106
2107 switch (color_mode) {
2108 case OMAP_DSS_COLOR_CLUT1:
2109 case OMAP_DSS_COLOR_CLUT2:
2110 case OMAP_DSS_COLOR_CLUT4:
2111 case OMAP_DSS_COLOR_CLUT8:
2112 BUG();
2113 return;
2114 default:
2115 ps = color_mode_to_bpp(color_mode) / 8;
2116 break;
2117 }
2118
2119 DSSDBG("scrw %d, width %d\n", screen_width, width);
2120
2121 /*
2122 * field 0 = even field = bottom field
2123 * field 1 = odd field = top field
2124 */
2125 *offset1 = 0;
2126 if (field_offset)
2127 *offset0 = *offset1 + field_offset * screen_width * ps;
2128 else
2129 *offset0 = *offset1;
2130 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2131 (fieldmode ? screen_width : 0), ps);
2132 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2133 color_mode == OMAP_DSS_COLOR_UYVY)
2134 *pix_inc = pixinc(x_predecim, 2 * ps);
2135 else
2136 *pix_inc = pixinc(x_predecim, ps);
2137}
2138
7faa9233
CM		 2139/*
2140 * This function is used to avoid synclosts in OMAP3, because of some
2141 * undocumented horizontal position and timing related limitations.
2142 */
465ec13f 2143static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2144 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2145 u16 width, u16 height, u16 out_width, u16 out_height,
2146 bool five_taps)
7faa9233 2147{
230edc03 2148 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2149 unsigned long nonactive;
7faa9233
CM		 2150 static const u8 limits[3] = { 8, 10, 20 };
2151 u64 val, blank;
2152 int i;
2153
81ab95b7 2154 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2155
2156 i = 0;
2157 if (out_height < height)
2158 i++;
2159 if (out_width < width)
2160 i++;
81ab95b7 2161 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2162 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2163 if (blank <= limits[i])
2164 return -EINVAL;
2165
e4998634
ID		 2166 /* FIXME add checks for 3-tap filter once the limitations are known */
2167 if (!five_taps)
2168 return 0;
2169
7faa9233
CM		 2170 /*
2171 * Pixel data should be prepared before visible display point starts.
2172 * So, atleast DS-2 lines must have already been fetched by DISPC
2173 * during nonactive - pos_x period.
2174 */
2175 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2176 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2177 val, max(0, ds - 2) * width);
2178 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2179 return -EINVAL;
2180
2181 /*
2182 * All lines need to be refilled during the nonactive period of which
2183 * only one line can be loaded during the active period. So, atleast
2184 * DS - 1 lines should be loaded during nonactive period.
2185 */
2186 val = div_u64((u64)nonactive * lclk, pclk);
2187 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2188 val, max(0, ds - 1) * width);
2189 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2190 return -EINVAL;
2191
2192 return 0;
2193}
2194
8702ee50 2195static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2196 const struct omap_video_timings *mgr_timings, u16 width,
2197 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2198 enum omap_color_mode color_mode)
80c39712 2199{
8b53d991 2200 u32 core_clk = 0;
3e8a6ff2 2201 u64 tmp;
80c39712 2202
7282f1b7
CM		 2203 if (height <= out_height && width <= out_width)
2204 return (unsigned long) pclk;
2205
80c39712 2206 if (height > out_height) {
81ab95b7 2207 unsigned int ppl = mgr_timings->x_res;
80c39712 2208
c582935c 2209 tmp = (u64)pclk * height * out_width;
80c39712 2210 do_div(tmp, 2 * out_height * ppl);
8b53d991 2211 core_clk = tmp;
80c39712 2212
2d9c5597
VS		 2213 if (height > 2 * out_height) {
2214 if (ppl == out_width)
2215 return 0;
2216
c582935c 2217 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
80c39712 2218 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2219 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2220 }
2221 }
2222
2223 if (width > out_width) {
c582935c 2224 tmp = (u64)pclk * width;
80c39712 2225 do_div(tmp, out_width);
8b53d991 2226 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2227
2228 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2229 core_clk <<= 1;
80c39712
TV		 2230 }
2231
8b53d991 2232 return core_clk;
80c39712
TV		 2233}
2234
8702ee50 2235static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2236 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2237{
dcbe765b
CM		 2238 if (height > out_height && width > out_width)
2239 return pclk * 4;
2240 else
2241 return pclk * 2;
2242}
2243
8702ee50 2244static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2245 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2246{
2247 unsigned int hf, vf;
2248
2249 /*
2250 * FIXME how to determine the 'A' factor
2251 * for the no downscaling case ?
2252 */
2253
2254 if (width > 3 * out_width)
2255 hf = 4;
2256 else if (width > 2 * out_width)
2257 hf = 3;
2258 else if (width > out_width)
2259 hf = 2;
2260 else
2261 hf = 1;
80c39712
TV		 2262 if (height > out_height)
2263 vf = 2;
2264 else
2265 vf = 1;
2266
dcbe765b
CM		 2267 return pclk * vf * hf;
2268}
2269
8702ee50 2270static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2271 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2272{
8ba85306
AT		 2273 /*
2274 * If the overlay/writeback is in mem to mem mode, there are no
2275 * downscaling limitations with respect to pixel clock, return 1 as
2276 * required core clock to represent that we have sufficient enough
2277 * core clock to do maximum downscaling
2278 */
2279 if (mem_to_mem)
2280 return 1;
2281
dcbe765b
CM		 2282 if (width > out_width)
2283 return DIV_ROUND_UP(pclk, out_width) * width;
2284 else
2285 return pclk;
2286}
2287
0c6921de 2288static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2289 const struct omap_video_timings *mgr_timings,
2290 u16 width, u16 height, u16 out_width, u16 out_height,
2291 enum omap_color_mode color_mode, bool *five_taps,
2292 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2293 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2294{
2295 int error;
2296 u16 in_width, in_height;
2297 int min_factor = min(*decim_x, *decim_y);
2298 const int maxsinglelinewidth =
2299 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2300
dcbe765b
CM		 2301 *five_taps = false;
2302
2303 do {
eec77da2
TV		 2304 in_height = height / *decim_y;
2305 in_width = width / *decim_x;
8702ee50 2306 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2307 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2308 error = (in_width > maxsinglelinewidth || !*core_clk ||
2309 *core_clk > dispc_core_clk_rate());
2310 if (error) {
2311 if (*decim_x == *decim_y) {
2312 *decim_x = min_factor;
2313 ++*decim_y;
2314 } else {
2315 swap(*decim_x, *decim_y);
2316 if (*decim_x < *decim_y)
2317 ++*decim_x;
2318 }
2319 }
2320 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2321
3ce17b48
TV		 2322 if (error) {
2323 DSSERR("failed to find scaling settings\n");
2324 return -EINVAL;
2325 }
2326
dcbe765b
CM		 2327 if (in_width > maxsinglelinewidth) {
2328 DSSERR("Cannot scale max input width exceeded");
2329 return -EINVAL;
2330 }
2331 return 0;
2332}
2333
0c6921de 2334static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2335 const struct omap_video_timings *mgr_timings,
2336 u16 width, u16 height, u16 out_width, u16 out_height,
2337 enum omap_color_mode color_mode, bool *five_taps,
2338 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2339 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2340{
2341 int error;
2342 u16 in_width, in_height;
dcbe765b
CM		 2343 const int maxsinglelinewidth =
2344 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2345
2346 do {
eec77da2
TV		 2347 in_height = height / *decim_y;
2348 in_width = width / *decim_x;
e4998634 2349 *five_taps = in_height > out_height;
dcbe765b
CM		 2350
2351 if (in_width > maxsinglelinewidth)
2352 if (in_height > out_height &&
2353 in_height < out_height * 2)
2354 *five_taps = false;
e4998634
ID		 2355again:
2356 if (*five_taps)
2357 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2358 in_width, in_height, out_width,
2359 out_height, color_mode);
2360 else
8702ee50 2361 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2362 in_height, out_width, out_height,
2363 mem_to_mem);
dcbe765b 2364
e4998634
ID		 2365 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2366 pos_x, in_width, in_height, out_width,
2367 out_height, *five_taps);
2368 if (error && *five_taps) {
2369 *five_taps = false;
2370 goto again;
2371 }
2372
dcbe765b
CM		 2373 error = (error || in_width > maxsinglelinewidth * 2 ||
2374 (in_width > maxsinglelinewidth && *five_taps) ||
2375 !*core_clk || *core_clk > dispc_core_clk_rate());
ab6b2582
TV		 2376
2377 if (!error) {
2378 /* verify that we're inside the limits of scaler */
2379 if (in_width / 4 > out_width)
2380 error = 1;
2381
2382 if (*five_taps) {
2383 if (in_height / 4 > out_height)
2384 error = 1;
dcbe765b 2385 } else {
ab6b2582
TV		 2386 if (in_height / 2 > out_height)
2387 error = 1;
dcbe765b
CM		 2388 }
2389 }
ab6b2582 2390
7059e3d8
TV		 2391 if (error)
2392 ++*decim_y;
dcbe765b
CM		 2393 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2394
3ce17b48
TV		 2395 if (error) {
2396 DSSERR("failed to find scaling settings\n");
2397 return -EINVAL;
2398 }
2399
f5a73482
TV		 2400 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2401 in_height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2402 DSSERR("horizontal timing too tight\n");
2403 return -EINVAL;
7282f1b7 2404 }
dcbe765b
CM		 2405
2406 if (in_width > (maxsinglelinewidth * 2)) {
2407 DSSERR("Cannot setup scaling");
2408 DSSERR("width exceeds maximum width possible");
2409 return -EINVAL;
2410 }
2411
2412 if (in_width > maxsinglelinewidth && *five_taps) {
2413 DSSERR("cannot setup scaling with five taps");
2414 return -EINVAL;
2415 }
2416 return 0;
2417}
2418
0c6921de 2419static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2420 const struct omap_video_timings *mgr_timings,
2421 u16 width, u16 height, u16 out_width, u16 out_height,
2422 enum omap_color_mode color_mode, bool *five_taps,
2423 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2424 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2425{
2426 u16 in_width, in_width_max;
2427 int decim_x_min = *decim_x;
eec77da2 2428 u16 in_height = height / *decim_y;
dcbe765b
CM		 2429 const int maxsinglelinewidth =
2430 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2431 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2432
5d501085
AT		 2433 if (mem_to_mem) {
2434 in_width_max = out_width * maxdownscale;
2435 } else {
8ba85306
AT		 2436 in_width_max = dispc_core_clk_rate() /
2437 DIV_ROUND_UP(pclk, out_width);
5d501085 2438 }
dcbe765b 2439
dcbe765b
CM		 2440 *decim_x = DIV_ROUND_UP(width, in_width_max);
2441
2442 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2443 if (*decim_x > *x_predecim)
2444 return -EINVAL;
2445
2446 do {
eec77da2 2447 in_width = width / *decim_x;
dcbe765b
CM		 2448 } while (*decim_x <= *x_predecim &&
2449 in_width > maxsinglelinewidth && ++*decim_x);
2450
2451 if (in_width > maxsinglelinewidth) {
2452 DSSERR("Cannot scale width exceeds max line width");
2453 return -EINVAL;
2454 }
2455
8702ee50 2456 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2457 out_width, out_height, mem_to_mem);
dcbe765b 2458 return 0;
80c39712
TV		 2459}
2460
e4c5ae7f
TV		 2461#define DIV_FRAC(dividend, divisor) \
2462 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2463
74e16458 2464static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2465 enum omap_overlay_caps caps,
81ab95b7
AT		 2466 const struct omap_video_timings *mgr_timings,
2467 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2468 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2469 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2470 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2471{
0373cac6 2472 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2473 const int max_decim_limit = 16;
8b53d991 2474 unsigned long core_clk = 0;
dcbe765b 2475 int decim_x, decim_y, ret;
79ad75f2 2476
f95cb5eb
TV		 2477 if (width == out_width && height == out_height)
2478 return 0;
2479
fd2eac5a 2480 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
4e1d3ca0
TV		 2481 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2482 return -EINVAL;
2483 }
2484
5b54ed3e 2485 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2486 return -EINVAL;
79ad75f2 2487
74e16458 2488 if (mem_to_mem) {
1c031441
AT		 2489 *x_predecim = *y_predecim = 1;
2490 } else {
2491 *x_predecim = max_decim_limit;
2492 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2493 dss_has_feature(FEAT_BURST_2D)) ?
2494 2 : max_decim_limit;
2495 }
aed74b55
CM		 2496
2497 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2498 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2499 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2500 color_mode == OMAP_DSS_COLOR_CLUT8) {
2501 *x_predecim = 1;
2502 *y_predecim = 1;
2503 *five_taps = false;
2504 return 0;
2505 }
2506
2507 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2508 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2509
aed74b55 2510 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2511 return -EINVAL;
2512
aed74b55 2513 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2514 return -EINVAL;
2515
0c6921de 2516 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2517 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2518 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2519 mem_to_mem);
dcbe765b
CM		 2520 if (ret)
2521 return ret;
79ad75f2 2522
e4c5ae7f
TV		 2523 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2524 width, height,
2525 out_width, out_height,
2526 out_width / width, DIV_FRAC(out_width, width),
2527 out_height / height, DIV_FRAC(out_height, height),
2528
2529 decim_x, decim_y,
2530 width / decim_x, height / decim_y,
2531 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2532 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2533
2534 *five_taps ? 5 : 3,
2535 core_clk, dispc_core_clk_rate());
79ad75f2 2536
8b53d991 2537 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2538 DSSERR("failed to set up scaling, "
8b53d991
CM		 2539 "required core clk rate = %lu Hz, "
2540 "current core clk rate = %lu Hz\n",
2541 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2542 return -EINVAL;
2543 }
2544
aed74b55
CM		 2545 *x_predecim = decim_x;
2546 *y_predecim = decim_y;
79ad75f2
AT		 2547 return 0;
2548}
2549
f9b719b6
TV		 2550int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2551 const struct omap_overlay_info *oi,
2552 const struct omap_video_timings *timings,
2553 int *x_predecim, int *y_predecim)
2554{
2555 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2556 bool five_taps = true;
62a83183 2557 bool fieldmode = false;
f9b719b6
TV		 2558 u16 in_height = oi->height;
2559 u16 in_width = oi->width;
2560 bool ilace = timings->interlace;
2561 u16 out_width, out_height;
2562 int pos_x = oi->pos_x;
2563 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2564 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2565
2566 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2567 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2568
2569 if (ilace && oi->height == out_height)
62a83183 2570 fieldmode = true;
f9b719b6
TV		 2571
2572 if (ilace) {
2573 if (fieldmode)
2574 in_height /= 2;
2575 out_height /= 2;
2576
2577 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2578 in_height, out_height);
2579 }
2580
2581 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2582 return -EINVAL;
2583
2584 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2585 in_height, out_width, out_height, oi->color_mode,
2586 &five_taps, x_predecim, y_predecim, pos_x,
2587 oi->rotation_type, false);
2588}
348be69d 2589EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2590
84a880fd 2591static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2592 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2593 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2594 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2595 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2596 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2597 bool replication, const struct omap_video_timings *mgr_timings,
2598 bool mem_to_mem)
80c39712 2599{
7282f1b7 2600 bool five_taps = true;
62a83183 2601 bool fieldmode = false;
79ad75f2 2602 int r, cconv = 0;
80c39712
TV		 2603 unsigned offset0, offset1;
2604 s32 row_inc;
2605 s32 pix_inc;
6be0d73e 2606 u16 frame_width, frame_height;
80c39712 2607 unsigned int field_offset = 0;
84a880fd
AT		 2608 u16 in_height = height;
2609 u16 in_width = width;
aed74b55 2610 int x_predecim = 1, y_predecim = 1;
8050cbe4 2611 bool ilace = mgr_timings->interlace;
74e16458
TV		 2612 unsigned long pclk = dispc_plane_pclk_rate(plane);
2613 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2614
e566658f 2615 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2616 return -EINVAL;
2617
c4661b33
TV		 2618 switch (color_mode) {
2619 case OMAP_DSS_COLOR_YUV2:
2620 case OMAP_DSS_COLOR_UYVY:
2621 case OMAP_DSS_COLOR_NV12:
2622 if (in_width & 1) {
2623 DSSERR("input width %d is not even for YUV format\n",
2624 in_width);
2625 return -EINVAL;
2626 }
2627 break;
2628
2629 default:
2630 break;
2631 }
2632
84a880fd
AT		 2633 out_width = out_width == 0 ? width : out_width;
2634 out_height = out_height == 0 ? height : out_height;
cf073668 2635
84a880fd 2636 if (ilace && height == out_height)
62a83183 2637 fieldmode = true;
80c39712
TV		 2638
2639 if (ilace) {
2640 if (fieldmode)
aed74b55 2641 in_height /= 2;
8eeb7019 2642 pos_y /= 2;
aed74b55 2643 out_height /= 2;
80c39712
TV		 2644
2645 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2646 "out_height %d\n", in_height, pos_y,
2647 out_height);
80c39712
TV		 2648 }
2649
84a880fd 2650 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2651 return -EINVAL;
2652
74e16458 2653 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2654 in_height, out_width, out_height, color_mode,
2655 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2656 rotation_type, mem_to_mem);
79ad75f2
AT		 2657 if (r)
2658 return r;
80c39712 2659
eec77da2
TV		 2660 in_width = in_width / x_predecim;
2661 in_height = in_height / y_predecim;
aed74b55 2662
c4661b33
TV		 2663 if (x_predecim > 1 || y_predecim > 1)
2664 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2665 x_predecim, y_predecim, in_width, in_height);
2666
2667 switch (color_mode) {
2668 case OMAP_DSS_COLOR_YUV2:
2669 case OMAP_DSS_COLOR_UYVY:
2670 case OMAP_DSS_COLOR_NV12:
2671 if (in_width & 1) {
2672 DSSDBG("predecimated input width is not even for YUV format\n");
2673 DSSDBG("adjusting input width %d -> %d\n",
2674 in_width, in_width & ~1);
2675
2676 in_width &= ~1;
2677 }
2678 break;
2679
2680 default:
2681 break;
2682 }
2683
84a880fd
AT		 2684 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2685 color_mode == OMAP_DSS_COLOR_UYVY ||
2686 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2687 cconv = 1;
80c39712
TV		 2688
2689 if (ilace && !fieldmode) {
2690 /*
2691 * when downscaling the bottom field may have to start several
2692 * source lines below the top field. Unfortunately ACCUI
2693 * registers will only hold the fractional part of the offset
2694 * so the integer part must be added to the base address of the
2695 * bottom field.
2696 */
aed74b55 2697 if (!in_height || in_height == out_height)
80c39712
TV		 2698 field_offset = 0;
2699 else
aed74b55 2700 field_offset = in_height / out_height / 2;
80c39712
TV		 2701 }
2702
2703 /* Fields are independent but interleaved in memory. */
2704 if (fieldmode)
2705 field_offset = 1;
2706
c6eee968
TV		 2707 offset0 = 0;
2708 offset1 = 0;
2709 row_inc = 0;
2710 pix_inc = 0;
2711
6be0d73e
AT		 2712 if (plane == OMAP_DSS_WB) {
2713 frame_width = out_width;
2714 frame_height = out_height;
2715 } else {
2716 frame_width = in_width;
2717 frame_height = height;
2718 }
2719
84a880fd 2720 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2721 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2722 color_mode, fieldmode, field_offset,
65e006ff
CM		 2723 &offset0, &offset1, &row_inc, &pix_inc,
2724 x_predecim, y_predecim);
84a880fd 2725 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2726 calc_dma_rotation_offset(rotation, mirror, screen_width,
2727 frame_width, frame_height,
84a880fd 2728 color_mode, fieldmode, field_offset,
aed74b55
CM		 2729 &offset0, &offset1, &row_inc, &pix_inc,
2730 x_predecim, y_predecim);
80c39712 2731 else
84a880fd 2732 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2733 screen_width, frame_width, frame_height,
84a880fd 2734 color_mode, fieldmode, field_offset,
aed74b55
CM		 2735 &offset0, &offset1, &row_inc, &pix_inc,
2736 x_predecim, y_predecim);
80c39712
TV		 2737
2738 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2739 offset0, offset1, row_inc, pix_inc);
2740
84a880fd 2741 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2742
84a880fd 2743 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2744
84a880fd
AT		 2745 dispc_ovl_set_ba0(plane, paddr + offset0);
2746 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2747
84a880fd
AT		 2748 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2749 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2750 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2751 }
2752
f2aee319
TV		 2753 if (dispc.feat->last_pixel_inc_missing)
2754 row_inc += pix_inc - 1;
2755
f0e5caab
TV		 2756 dispc_ovl_set_row_inc(plane, row_inc);
2757 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2758
84a880fd 2759 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2760 in_height, out_width, out_height);
80c39712 2761
84a880fd 2762 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2763
78b687fc 2764 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2765
5b54ed3e 2766 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2767 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2768 out_height, ilace, five_taps, fieldmode,
84a880fd 2769 color_mode, rotation);
78b687fc 2770 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2771 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2772 }
2773
c35eeb2e
AT		 2774 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2775 color_mode);
80c39712 2776
84a880fd
AT		 2777 dispc_ovl_set_zorder(plane, caps, zorder);
2778 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2779 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2780
d79db853 2781 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2782
80c39712
TV		 2783 return 0;
2784}
2785
84a880fd 2786int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2787 bool replication, const struct omap_video_timings *mgr_timings,
2788 bool mem_to_mem)
84a880fd
AT		 2789{
2790 int r;
16bf20c7 2791 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2792 enum omap_channel channel;
2793
2794 channel = dispc_ovl_get_channel_out(plane);
2795
24f13a66
AB		 2796 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2797 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2798 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd
AT		 2799 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2800 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2801
16bf20c7 2802 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2803 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2804 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2805 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2806 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2807
2808 return r;
2809}
348be69d 2810EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2811
749feffa 2812int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2813 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2814{
2815 int r;
9e4a0fc7 2816 u32 l;
749feffa
AT		 2817 enum omap_plane plane = OMAP_DSS_WB;
2818 const int pos_x = 0, pos_y = 0;
2819 const u8 zorder = 0, global_alpha = 0;
2820 const bool replication = false;
9e4a0fc7 2821 bool truncation;
749feffa
AT		 2822 int in_width = mgr_timings->x_res;
2823 int in_height = mgr_timings->y_res;
2824 enum omap_overlay_caps caps =
2825 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2826
2827 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2828 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2829 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2830 wi->mirror);
2831
2832 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2833 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2834 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2835 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2836 replication, mgr_timings, mem_to_mem);
2837
2838 switch (wi->color_mode) {
2839 case OMAP_DSS_COLOR_RGB16:
2840 case OMAP_DSS_COLOR_RGB24P:
2841 case OMAP_DSS_COLOR_ARGB16:
2842 case OMAP_DSS_COLOR_RGBA16:
2843 case OMAP_DSS_COLOR_RGB12U:
2844 case OMAP_DSS_COLOR_ARGB16_1555:
2845 case OMAP_DSS_COLOR_XRGB16_1555:
2846 case OMAP_DSS_COLOR_RGBX16:
2847 truncation = true;
2848 break;
2849 default:
2850 truncation = false;
2851 break;
2852 }
2853
2854 /* setup extra DISPC_WB_ATTRIBUTES */
2855 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2856 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2857 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
4c055ce0
TV		 2858 if (mem_to_mem)
2859 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
98cd5796
TV		 2860 else
2861 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
9e4a0fc7 2862 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa 2863
98cd5796
TV		 2864 if (mem_to_mem) {
2865 /* WBDELAYCOUNT */
2866 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2867 } else {
2868 int wbdelay;
2869
2870 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2871 mgr_timings->vbp, 255);
2872
2873 /* WBDELAYCOUNT */
2874 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2875 }
2876
749feffa
AT		 2877 return r;
2878}
2879
f0e5caab 2880int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2881{
e6d80f95
TV		 2882 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2883
9b372c2d 2884 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2885
2886 return 0;
80c39712 2887}
348be69d 2888EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2889
04bd8ac1
TV		 2890bool dispc_ovl_enabled(enum omap_plane plane)
2891{
2892 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2893}
348be69d 2894EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2895
f1a813d3 2896void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2897{
efa70b3b
CM		 2898 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2899 /* flush posted write */
2900 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2901}
348be69d 2902EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2903
65398511
TV		 2904bool dispc_mgr_is_enabled(enum omap_channel channel)
2905{
2906 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2907}
348be69d 2908EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2909
0b23e5b8
AT		 2910void dispc_wb_enable(bool enable)
2911{
916188a4 2912 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2913}
2914
2915bool dispc_wb_is_enabled(void)
2916{
916188a4 2917 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2918}
2919
fb2cec1f 2920static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2921{
6ced40bf
AT		 2922 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2923 return;
2924
80c39712 2925 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2926}
2927
2928void dispc_lcd_enable_signal(bool enable)
2929{
6ced40bf
AT		 2930 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2931 return;
2932
80c39712 2933 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2934}
2935
2936void dispc_pck_free_enable(bool enable)
2937{
6ced40bf
AT		 2938 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2939 return;
2940
80c39712 2941 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2942}
2943
fb2cec1f 2944static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2945{
efa70b3b 2946 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2947}
2948
2949
fb2cec1f 2950static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2951{
d21f43bc 2952 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2953}
2954
2955void dispc_set_loadmode(enum omap_dss_load_mode mode)
2956{
80c39712 2957 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2958}
2959
2960
c64dca40 2961static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2962{
8613b000 2963 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2964}
2965
c64dca40 2966static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2967 enum omap_dss_trans_key_type type,
2968 u32 trans_key)
2969{
efa70b3b 2970 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2971
8613b000 2972 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2973}
2974
c64dca40 2975static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2976{
efa70b3b 2977 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2978}
11354dd5 2979
c64dca40
TV		 2980static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2981 bool enable)
80c39712 2982{
11354dd5 2983 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2984 return;
2985
80c39712
TV		 2986 if (ch == OMAP_DSS_CHANNEL_LCD)
2987 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2988 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2989 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2990}
11354dd5 2991
c64dca40 2992void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2993 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2994{
2995 dispc_mgr_set_default_color(channel, info->default_color);
2996 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2997 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2998 dispc_mgr_enable_alpha_fixed_zorder(channel,
2999 info->partial_alpha_enabled);
3000 if (dss_has_feature(FEAT_CPR)) {
3001 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3002 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3003 }
3004}
348be69d 3005EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 3006
fb2cec1f 3007static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 3008{
3009 int code;
3010
3011 switch (data_lines) {
3012 case 12:
3013 code = 0;
3014 break;
3015 case 16:
3016 code = 1;
3017 break;
3018 case 18:
3019 code = 2;
3020 break;
3021 case 24:
3022 code = 3;
3023 break;
3024 default:
3025 BUG();
3026 return;
3027 }
3028
efa70b3b 3029 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 3030}
3031
fb2cec1f 3032static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 3033{
3034 u32 l;
569969d6 3035 int gpout0, gpout1;
80c39712
TV		 3036
3037 switch (mode) {
569969d6
AT		 3038 case DSS_IO_PAD_MODE_RESET:
3039 gpout0 = 0;
3040 gpout1 = 0;
80c39712 3041 break;
569969d6
AT		 3042 case DSS_IO_PAD_MODE_RFBI:
3043 gpout0 = 1;
80c39712
TV		 3044 gpout1 = 0;
3045 break;
569969d6
AT		 3046 case DSS_IO_PAD_MODE_BYPASS:
3047 gpout0 = 1;
80c39712
TV		 3048 gpout1 = 1;
3049 break;
80c39712
TV		 3050 default:
3051 BUG();
3052 return;
3053 }
3054
569969d6
AT		 3055 l = dispc_read_reg(DISPC_CONTROL);
3056 l = FLD_MOD(l, gpout0, 15, 15);
3057 l = FLD_MOD(l, gpout1, 16, 16);
3058 dispc_write_reg(DISPC_CONTROL, l);
3059}
3060
fb2cec1f 3061static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 3062{
efa70b3b 3063 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 3064}
3065
fb2cec1f
TV		 3066void dispc_mgr_set_lcd_config(enum omap_channel channel,
3067 const struct dss_lcd_mgr_config *config)
3068{
3069 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3070
3071 dispc_mgr_enable_stallmode(channel, config->stallmode);
3072 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3073
3074 dispc_mgr_set_clock_div(channel, &config->clock_info);
3075
3076 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3077
3078 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3079
3080 dispc_mgr_set_lcd_type_tft(channel);
3081}
348be69d 3082EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 3083
8f366162
AT		 3084static bool _dispc_mgr_size_ok(u16 width, u16 height)
3085{
33b89928
AT		 3086 return width <= dispc.feat->mgr_width_max &&
3087 height <= dispc.feat->mgr_height_max;
8f366162
AT		 3088}
3089
80c39712
TV		 3090static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3091 int vsw, int vfp, int vbp)
3092{
dcbe765b
CM		 3093 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3094 hfp < 1 || hfp > dispc.feat->hp_max ||
3095 hbp < 1 || hbp > dispc.feat->hp_max ||
3096 vsw < 1 || vsw > dispc.feat->sw_max ||
3097 vfp < 0 || vfp > dispc.feat->vp_max ||
3098 vbp < 0 || vbp > dispc.feat->vp_max)
3099 return false;
80c39712
TV		 3100 return true;
3101}
3102
ca5ca69c
AT		 3103static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3104 unsigned long pclk)
3105{
3106 if (dss_mgr_is_lcd(channel))
3107 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3108 else
3109 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3110}
3111
8f366162 3112bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 3113 const struct omap_video_timings *timings)
80c39712 3114{
eadd33bb
TV		 3115 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3116 return false;
8f366162 3117
eadd33bb
TV		 3118 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3119 return false;
ca5ca69c
AT		 3120
3121 if (dss_mgr_is_lcd(channel)) {
beb8384d 3122 /* TODO: OMAP4+ supports interlace for LCD outputs */
eadd33bb
TV		 3123 if (timings->interlace)
3124 return false;
beb8384d 3125
eadd33bb 3126 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
ca5ca69c 3127 timings->hbp, timings->vsw, timings->vfp,
eadd33bb
TV		 3128 timings->vbp))
3129 return false;
ca5ca69c 3130 }
8f366162 3131
eadd33bb 3132 return true;
80c39712
TV		 3133}
3134
26d9dd0d 3135static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3136 int hfp, int hbp, int vsw, int vfp, int vbp,
3137 enum omap_dss_signal_level vsync_level,
3138 enum omap_dss_signal_level hsync_level,
3139 enum omap_dss_signal_edge data_pclk_edge,
3140 enum omap_dss_signal_level de_level,
3141 enum omap_dss_signal_edge sync_pclk_edge)
3142
80c39712 3143{
655e2941 3144 u32 timing_h, timing_v, l;
ed351881 3145 bool onoff, rf, ipc, vs, hs, de;
80c39712 3146
dcbe765b
CM		 3147 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3148 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3149 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3150 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3151 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3152 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3153
64ba4f74
SS		 3154 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3155 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 3156
ed351881
TV		 3157 switch (vsync_level) {
3158 case OMAPDSS_SIG_ACTIVE_LOW:
3159 vs = true;
3160 break;
3161 case OMAPDSS_SIG_ACTIVE_HIGH:
3162 vs = false;
3163 break;
3164 default:
3165 BUG();
3166 }
3167
3168 switch (hsync_level) {
3169 case OMAPDSS_SIG_ACTIVE_LOW:
3170 hs = true;
3171 break;
3172 case OMAPDSS_SIG_ACTIVE_HIGH:
3173 hs = false;
3174 break;
3175 default:
3176 BUG();
3177 }
3178
3179 switch (de_level) {
3180 case OMAPDSS_SIG_ACTIVE_LOW:
3181 de = true;
3182 break;
3183 case OMAPDSS_SIG_ACTIVE_HIGH:
3184 de = false;
3185 break;
3186 default:
3187 BUG();
3188 }
3189
655e2941
AT		 3190 switch (data_pclk_edge) {
3191 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3192 ipc = false;
3193 break;
3194 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3195 ipc = true;
3196 break;
655e2941
AT		 3197 default:
3198 BUG();
3199 }
3200
7a16360d
TV		 3201 /* always use the 'rf' setting */
3202 onoff = true;
3203
655e2941 3204 switch (sync_pclk_edge) {
655e2941 3205 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
655e2941
AT		 3206 rf = false;
3207 break;
3208 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
655e2941
AT		 3209 rf = true;
3210 break;
3211 default:
3212 BUG();
cf6ac4ce 3213 }
655e2941 3214
d80e02ef
TV		 3215 l = FLD_VAL(onoff, 17, 17) |
3216 FLD_VAL(rf, 16, 16) |
ed351881 3217 FLD_VAL(de, 15, 15) |
d80e02ef 3218 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 3219 FLD_VAL(hs, 13, 13) |
3220 FLD_VAL(vs, 12, 12);
d80e02ef 3221
e5f80917
TV		 3222 /* always set ALIGN bit when available */
3223 if (dispc.feat->supports_sync_align)
3224 l |= (1 << 18);
3225
655e2941 3226 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 3227
3228 if (dispc.syscon_pol) {
3229 const int shifts[] = {
3230 [OMAP_DSS_CHANNEL_LCD] = 0,
3231 [OMAP_DSS_CHANNEL_LCD2] = 1,
3232 [OMAP_DSS_CHANNEL_LCD3] = 2,
3233 };
3234
3235 u32 mask, val;
3236
3237 mask = (1 << 0) | (1 << 3) | (1 << 6);
3238 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3239
3240 mask <<= 16 + shifts[channel];
3241 val <<= 16 + shifts[channel];
3242
3243 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3244 mask, val);
3245 }
80c39712
TV		 3246}
3247
3248/* change name to mode? */
c51d921a 3249void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3250 const struct omap_video_timings *timings)
80c39712
TV		 3251{
3252 unsigned xtot, ytot;
3253 unsigned long ht, vt;
2aefad49 3254 struct omap_video_timings t = *timings;
80c39712 3255
2aefad49 3256 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3257
2aefad49 3258 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3259 BUG();
c6eee968
TV		 3260 return;
3261 }
80c39712 3262
dd88b7a6 3263 if (dss_mgr_is_lcd(channel)) {
2aefad49 3264 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3265 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3266 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3267
2aefad49
AT		 3268 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3269 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3270
d8d78941
TV		 3271 ht = timings->pixelclock / xtot;
3272 vt = timings->pixelclock / xtot / ytot;
c51d921a 3273
d8d78941 3274 DSSDBG("pck %u\n", timings->pixelclock);
c51d921a 3275 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3276 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3277 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3278 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3279 t.de_level, t.sync_pclk_edge);
80c39712 3280
c51d921a 3281 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3282 } else {
23c8f88e 3283 if (t.interlace == true)
2aefad49 3284 t.y_res /= 2;
c51d921a 3285 }
8f366162 3286
2aefad49 3287 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 3288}
348be69d 3289EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3290
26d9dd0d 3291static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3292 u16 pck_div)
80c39712
TV		 3293{
3294 BUG_ON(lck_div < 1);
9eaaf207 3295 BUG_ON(pck_div < 1);
80c39712 3296
ce7fa5eb 3297 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3298 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 3299
3300 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3301 channel == OMAP_DSS_CHANNEL_LCD)
3302 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3303}
3304
26d9dd0d 3305static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3306 int *pck_div)
80c39712
TV		 3307{
3308 u32 l;
ce7fa5eb 3309 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3310 *lck_div = FLD_GET(l, 23, 16);
3311 *pck_div = FLD_GET(l, 7, 0);
3312}
3313
3314unsigned long dispc_fclk_rate(void)
3315{
2daea7af 3316 struct dss_pll *pll;
80c39712
TV		 3317 unsigned long r = 0;
3318
66534e8e 3319 switch (dss_get_dispc_clk_source()) {
89a35e51 3320 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3321 r = dss_get_dispc_clk_rate();
66534e8e 3322 break;
89a35e51 3323 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3324 pll = dss_pll_find("dsi0");
93550927
TV		 3325 if (!pll)
3326 pll = dss_pll_find("video0");
3327
2daea7af 3328 r = pll->cinfo.clkout[0];
66534e8e 3329 break;
5a8b572d 3330 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3331 pll = dss_pll_find("dsi1");
93550927
TV		 3332 if (!pll)
3333 pll = dss_pll_find("video1");
3334
2daea7af 3335 r = pll->cinfo.clkout[0];
5a8b572d 3336 break;
66534e8e
TA		 3337 default:
3338 BUG();
c6eee968 3339 return 0;
66534e8e
TA		 3340 }
3341
80c39712
TV		 3342 return r;
3343}
3344
26d9dd0d 3345unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3346{
2daea7af 3347 struct dss_pll *pll;
80c39712
TV		 3348 int lcd;
3349 unsigned long r;
3350 u32 l;
3351
c31cba8a
TV		 3352 if (dss_mgr_is_lcd(channel)) {
3353 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3354
c31cba8a 3355 lcd = FLD_GET(l, 23, 16);
80c39712 3356
c31cba8a
TV		 3357 switch (dss_get_lcd_clk_source(channel)) {
3358 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3359 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3360 break;
3361 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3362 pll = dss_pll_find("dsi0");
93550927
TV		 3363 if (!pll)
3364 pll = dss_pll_find("video0");
3365
2daea7af 3366 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3367 break;
3368 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3369 pll = dss_pll_find("dsi1");
93550927
TV		 3370 if (!pll)
3371 pll = dss_pll_find("video1");
3372
2daea7af 3373 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3374 break;
3375 default:
3376 BUG();
3377 return 0;
3378 }
80c39712 3379
c31cba8a
TV		 3380 return r / lcd;
3381 } else {
3382 return dispc_fclk_rate();
3383 }
80c39712
TV		 3384}
3385
26d9dd0d 3386unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3387{
80c39712 3388 unsigned long r;
80c39712 3389
dd88b7a6 3390 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3391 int pcd;
3392 u32 l;
80c39712 3393
c3dc6a7a 3394 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3395
c3dc6a7a 3396 pcd = FLD_GET(l, 7, 0);
80c39712 3397
c3dc6a7a
AT		 3398 r = dispc_mgr_lclk_rate(channel);
3399
3400 return r / pcd;
3401 } else {
5391e87d 3402 return dispc.tv_pclk_rate;
c3dc6a7a 3403 }
80c39712
TV		 3404}
3405
5391e87d
TV		 3406void dispc_set_tv_pclk(unsigned long pclk)
3407{
3408 dispc.tv_pclk_rate = pclk;
3409}
3410
8b53d991
CM		 3411unsigned long dispc_core_clk_rate(void)
3412{
7b3926b3 3413 return dispc.core_clk_rate;
8b53d991
CM		 3414}
3415
3e8a6ff2
AT		 3416static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3417{
251886d8
TV		 3418 enum omap_channel channel;
3419
3420 if (plane == OMAP_DSS_WB)
3421 return 0;
3422
3423 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3424
3425 return dispc_mgr_pclk_rate(channel);
3426}
3427
3428static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3429{
251886d8
TV		 3430 enum omap_channel channel;
3431
3432 if (plane == OMAP_DSS_WB)
3433 return 0;
3434
3435 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3436
c31cba8a 3437 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3438}
c31cba8a 3439
6f1891fc 3440static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3441{
3442 int lcd, pcd;
6f1891fc
CM		 3443 enum omap_dss_clk_source lcd_clk_src;
3444
3445 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3446
3447 lcd_clk_src = dss_get_lcd_clk_source(channel);
3448
3449 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3450 dss_get_generic_clk_source_name(lcd_clk_src),
3451 dss_feat_get_clk_source_name(lcd_clk_src));
3452
3453 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3454
3455 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3456 dispc_mgr_lclk_rate(channel), lcd);
3457 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3458 dispc_mgr_pclk_rate(channel), pcd);
3459}
3460
3461void dispc_dump_clocks(struct seq_file *s)
3462{
3463 int lcd;
0cf35df3 3464 u32 l;
89a35e51 3465 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3466
4fbafaf3
TV		 3467 if (dispc_runtime_get())
3468 return;
80c39712 3469
80c39712
TV		 3470 seq_printf(s, "- DISPC -\n");
3471
067a57e4
AT		 3472 seq_printf(s, "dispc fclk source = %s (%s)\n",
3473 dss_get_generic_clk_source_name(dispc_clk_src),
3474 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3475
3476 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3477
0cf35df3
MR		 3478 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3479 seq_printf(s, "- DISPC-CORE-CLK -\n");
3480 l = dispc_read_reg(DISPC_DIVISOR);
3481 lcd = FLD_GET(l, 23, 16);
3482
3483 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3484 (dispc_fclk_rate()/lcd), lcd);
3485 }
2a205f34 3486
6f1891fc 3487 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3488
6f1891fc
CM		 3489 if (dss_has_feature(FEAT_MGR_LCD2))
3490 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3491 if (dss_has_feature(FEAT_MGR_LCD3))
3492 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3493
3494 dispc_runtime_put();
80c39712
TV		 3495}
3496
e40402cf 3497static void dispc_dump_regs(struct seq_file *s)
80c39712 3498{
4dd2da15
AT		 3499 int i, j;
3500 const char *mgr_names[] = {
3501 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3502 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3503 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3504 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3505 };
3506 const char *ovl_names[] = {
3507 [OMAP_DSS_GFX] = "GFX",
3508 [OMAP_DSS_VIDEO1] = "VID1",
3509 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3510 [OMAP_DSS_VIDEO3] = "VID3",
06c525fe 3511 [OMAP_DSS_WB] = "WB",
4dd2da15
AT		 3512 };
3513 const char **p_names;
3514
9b372c2d 3515#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3516
4fbafaf3
TV		 3517 if (dispc_runtime_get())
3518 return;
80c39712 3519
5010be80 3520 /* DISPC common registers */
80c39712
TV		 3521 DUMPREG(DISPC_REVISION);
3522 DUMPREG(DISPC_SYSCONFIG);
3523 DUMPREG(DISPC_SYSSTATUS);
3524 DUMPREG(DISPC_IRQSTATUS);
3525 DUMPREG(DISPC_IRQENABLE);
3526 DUMPREG(DISPC_CONTROL);
3527 DUMPREG(DISPC_CONFIG);
3528 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3529 DUMPREG(DISPC_LINE_STATUS);
3530 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3531 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3532 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3533 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3534 if (dss_has_feature(FEAT_MGR_LCD2)) {
3535 DUMPREG(DISPC_CONTROL2);
3536 DUMPREG(DISPC_CONFIG2);
5010be80 3537 }
6f1891fc
CM		 3538 if (dss_has_feature(FEAT_MGR_LCD3)) {
3539 DUMPREG(DISPC_CONTROL3);
3540 DUMPREG(DISPC_CONFIG3);
3541 }
29fceeeb
TV		 3542 if (dss_has_feature(FEAT_MFLAG))
3543 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3544
3545#undef DUMPREG
3546
3547#define DISPC_REG(i, name) name(i)
4dd2da15 3548#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3549 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3550 dispc_read_reg(DISPC_REG(i, r)))
3551
4dd2da15 3552 p_names = mgr_names;
5010be80 3553
4dd2da15
AT		 3554 /* DISPC channel specific registers */
3555 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3556 DUMPREG(i, DISPC_DEFAULT_COLOR);
3557 DUMPREG(i, DISPC_TRANS_COLOR);
3558 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3559
4dd2da15
AT		 3560 if (i == OMAP_DSS_CHANNEL_DIGIT)
3561 continue;
5010be80 3562
4dd2da15
AT		 3563 DUMPREG(i, DISPC_TIMING_H);
3564 DUMPREG(i, DISPC_TIMING_V);
3565 DUMPREG(i, DISPC_POL_FREQ);
3566 DUMPREG(i, DISPC_DIVISORo);
5010be80 3567
4dd2da15
AT		 3568 DUMPREG(i, DISPC_DATA_CYCLE1);
3569 DUMPREG(i, DISPC_DATA_CYCLE2);
3570 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3571
332e9d70 3572 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3573 DUMPREG(i, DISPC_CPR_COEF_R);
3574 DUMPREG(i, DISPC_CPR_COEF_G);
3575 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3576 }
2a205f34 3577 }
80c39712 3578
4dd2da15
AT		 3579 p_names = ovl_names;
3580
3581 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3582 DUMPREG(i, DISPC_OVL_BA0);
3583 DUMPREG(i, DISPC_OVL_BA1);
3584 DUMPREG(i, DISPC_OVL_POSITION);
3585 DUMPREG(i, DISPC_OVL_SIZE);
3586 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3587 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3588 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3589 DUMPREG(i, DISPC_OVL_ROW_INC);
3590 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3591
4dd2da15
AT		 3592 if (dss_has_feature(FEAT_PRELOAD))
3593 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3594 if (dss_has_feature(FEAT_MFLAG))
3595 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3596
3597 if (i == OMAP_DSS_GFX) {
3598 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3599 DUMPREG(i, DISPC_OVL_TABLE_BA);
3600 continue;
3601 }
3602
3603 DUMPREG(i, DISPC_OVL_FIR);
3604 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3605 DUMPREG(i, DISPC_OVL_ACCU0);
3606 DUMPREG(i, DISPC_OVL_ACCU1);
3607 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3608 DUMPREG(i, DISPC_OVL_BA0_UV);
3609 DUMPREG(i, DISPC_OVL_BA1_UV);
3610 DUMPREG(i, DISPC_OVL_FIR2);
3611 DUMPREG(i, DISPC_OVL_ACCU2_0);
3612 DUMPREG(i, DISPC_OVL_ACCU2_1);
3613 }
3614 if (dss_has_feature(FEAT_ATTR2))
3615 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3616 }
5010be80 3617
20efbc35 3618 if (dispc.feat->has_writeback) {
06c525fe
TV		 3619 i = OMAP_DSS_WB;
3620 DUMPREG(i, DISPC_OVL_BA0);
3621 DUMPREG(i, DISPC_OVL_BA1);
3622 DUMPREG(i, DISPC_OVL_SIZE);
3623 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3624 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3625 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3626 DUMPREG(i, DISPC_OVL_ROW_INC);
3627 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3628
3629 if (dss_has_feature(FEAT_MFLAG))
3630 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3631
3632 DUMPREG(i, DISPC_OVL_FIR);
3633 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3634 DUMPREG(i, DISPC_OVL_ACCU0);
3635 DUMPREG(i, DISPC_OVL_ACCU1);
3636 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3637 DUMPREG(i, DISPC_OVL_BA0_UV);
3638 DUMPREG(i, DISPC_OVL_BA1_UV);
3639 DUMPREG(i, DISPC_OVL_FIR2);
3640 DUMPREG(i, DISPC_OVL_ACCU2_0);
3641 DUMPREG(i, DISPC_OVL_ACCU2_1);
3642 }
3643 if (dss_has_feature(FEAT_ATTR2))
3644 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3645 }
3646
5010be80
AT		 3647#undef DISPC_REG
3648#undef DUMPREG
3649
3650#define DISPC_REG(plane, name, i) name(plane, i)
3651#define DUMPREG(plane, name, i) \
4dd2da15 3652 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3653 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3654 dispc_read_reg(DISPC_REG(plane, name, i)))
3655
4dd2da15 3656 /* Video pipeline coefficient registers */
332e9d70 3657
4dd2da15
AT		 3658 /* start from OMAP_DSS_VIDEO1 */
3659 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3660 for (j = 0; j < 8; j++)
3661 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3662
4dd2da15
AT		 3663 for (j = 0; j < 8; j++)
3664 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3665
4dd2da15
AT		 3666 for (j = 0; j < 5; j++)
3667 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3668
4dd2da15
AT		 3669 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3670 for (j = 0; j < 8; j++)
3671 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3672 }
3673
3674 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3675 for (j = 0; j < 8; j++)
3676 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3677
3678 for (j = 0; j < 8; j++)
3679 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3680
3681 for (j = 0; j < 8; j++)
3682 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3683 }
332e9d70 3684 }
80c39712 3685
4fbafaf3 3686 dispc_runtime_put();
5010be80
AT		 3687
3688#undef DISPC_REG
80c39712
TV		 3689#undef DUMPREG
3690}
3691
80c39712
TV		 3692/* calculate clock rates using dividers in cinfo */
3693int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3694 struct dispc_clock_info *cinfo)
3695{
80c39712
TV		 3696 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3697 return -EINVAL;
9eaaf207 3698 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3699 return -EINVAL;
80c39712 3700
80c39712
TV		 3701 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3702 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3703
80c39712
TV		 3704 return 0;
3705}
80c39712 3706
7c284e6e
TV		 3707bool dispc_div_calc(unsigned long dispc,
3708 unsigned long pck_min, unsigned long pck_max,
3709 dispc_div_calc_func func, void *data)
3710{
3711 int lckd, lckd_start, lckd_stop;
3712 int pckd, pckd_start, pckd_stop;
3713 unsigned long pck, lck;
3714 unsigned long lck_max;
3715 unsigned long pckd_hw_min, pckd_hw_max;
3716 unsigned min_fck_per_pck;
3717 unsigned long fck;
80c39712 3718
7c284e6e
TV		 3719#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3720 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3721#else
3722 min_fck_per_pck = 0;
3723#endif
80c39712 3724
7c284e6e
TV		 3725 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3726 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3727
7c284e6e 3728 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3729
7c284e6e
TV		 3730 pck_min = pck_min ? pck_min : 1;
3731 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3732
7c284e6e
TV		 3733 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3734 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3735
7c284e6e
TV		 3736 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3737 lck = dispc / lckd;
80c39712 3738
7c284e6e
TV		 3739 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3740 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3741
7c284e6e
TV		 3742 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3743 pck = lck / pckd;
80c39712 3744
7c284e6e
TV		 3745 /*
3746 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3747 * clock, which means we're configuring DISPC fclk here
3748 * also. Thus we need to use the calculated lck. For
3749 * OMAP4+ the DISPC fclk is a separate clock.
3750 */
3751 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3752 fck = dispc_core_clk_rate();
3753 else
3754 fck = lck;
3755
3756 if (fck < pck * min_fck_per_pck)
3757 continue;
3758
3759 if (func(lckd, pckd, lck, pck, data))
3760 return true;
3761 }
3762 }
3763
3764 return false;
80c39712
TV		 3765}
3766
f0d08f89 3767void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3768 const struct dispc_clock_info *cinfo)
80c39712
TV		 3769{
3770 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3771 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3772
26d9dd0d 3773 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3774}
3775
26d9dd0d 3776int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3777 struct dispc_clock_info *cinfo)
80c39712
TV		 3778{
3779 unsigned long fck;
3780
3781 fck = dispc_fclk_rate();
3782
ce7fa5eb
MR		 3783 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3784 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3785
3786 cinfo->lck = fck / cinfo->lck_div;
3787 cinfo->pck = cinfo->lck / cinfo->pck_div;
3788
3789 return 0;
3790}
3791
4e0397cf
TV		 3792u32 dispc_read_irqstatus(void)
3793{
3794 return dispc_read_reg(DISPC_IRQSTATUS);
3795}
348be69d 3796EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3797
3798void dispc_clear_irqstatus(u32 mask)
3799{
3800 dispc_write_reg(DISPC_IRQSTATUS, mask);
3801}
348be69d 3802EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3803
3804u32 dispc_read_irqenable(void)
3805{
3806 return dispc_read_reg(DISPC_IRQENABLE);
3807}
348be69d 3808EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3809
3810void dispc_write_irqenable(u32 mask)
3811{
3812 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3813
3814 /* clear the irqstatus for newly enabled irqs */
3815 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3816
3817 dispc_write_reg(DISPC_IRQENABLE, mask);
3818}
348be69d 3819EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3820
80c39712
TV		 3821void dispc_enable_sidle(void)
3822{
3823 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3824}
3825
3826void dispc_disable_sidle(void)
3827{
3828 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3829}
3830
3831static void _omap_dispc_initial_config(void)
3832{
3833 u32 l;
3834
0cf35df3
MR		 3835 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3836 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3837 l = dispc_read_reg(DISPC_DIVISOR);
3838 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3839 l = FLD_MOD(l, 1, 0, 0);
3840 l = FLD_MOD(l, 1, 23, 16);
3841 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3842
3843 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3844 }
3845
80c39712 3846 /* FUNCGATED */
6ced40bf
AT		 3847 if (dss_has_feature(FEAT_FUNCGATED))
3848 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3849
6e5264b0 3850 dispc_setup_color_conv_coef();
80c39712
TV		 3851
3852 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3853
42a6961c 3854 dispc_init_fifos();
5ed8cf5b
TV		 3855
3856 dispc_configure_burst_sizes();
54128701
AT		 3857
3858 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3859
3860 if (dispc.feat->mstandby_workaround)
3861 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
c64aa3a6
TV		 3862
3863 if (dss_has_feature(FEAT_MFLAG))
3864 dispc_init_mflag();
80c39712
TV		 3865}
3866
ede92695 3867static const struct dispc_features omap24xx_dispc_feats = {
dcbe765b
CM		 3868 .sw_start = 5,
3869 .fp_start = 15,
3870 .bp_start = 27,
3871 .sw_max = 64,
3872 .vp_max = 255,
3873 .hp_max = 256,
33b89928
AT		 3874 .mgr_width_start = 10,
3875 .mgr_height_start = 26,
3876 .mgr_width_max = 2048,
3877 .mgr_height_max = 2048,
ca5ca69c 3878 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3879 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3880 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3881 .num_fifos = 3,
cffa947d 3882 .no_framedone_tv = true,
8bc65552 3883 .set_max_preload = false,
f2aee319 3884 .last_pixel_inc_missing = true,
dcbe765b
CM		 3885};
3886
ede92695 3887static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
dcbe765b
CM		 3888 .sw_start = 5,
3889 .fp_start = 15,
3890 .bp_start = 27,
3891 .sw_max = 64,
3892 .vp_max = 255,
3893 .hp_max = 256,
33b89928
AT		 3894 .mgr_width_start = 10,
3895 .mgr_height_start = 26,
3896 .mgr_width_max = 2048,
3897 .mgr_height_max = 2048,
ca5ca69c
AT		 3898 .max_lcd_pclk = 173000000,
3899 .max_tv_pclk = 59000000,
dcbe765b
CM		 3900 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3901 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3902 .num_fifos = 3,
cffa947d 3903 .no_framedone_tv = true,
8bc65552 3904 .set_max_preload = false,
f2aee319 3905 .last_pixel_inc_missing = true,
dcbe765b
CM		 3906};
3907
ede92695 3908static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
dcbe765b
CM		 3909 .sw_start = 7,
3910 .fp_start = 19,
3911 .bp_start = 31,
3912 .sw_max = 256,
3913 .vp_max = 4095,
3914 .hp_max = 4096,
33b89928
AT		 3915 .mgr_width_start = 10,
3916 .mgr_height_start = 26,
3917 .mgr_width_max = 2048,
3918 .mgr_height_max = 2048,
ca5ca69c
AT		 3919 .max_lcd_pclk = 173000000,
3920 .max_tv_pclk = 59000000,
dcbe765b
CM		 3921 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3922 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3923 .num_fifos = 3,
cffa947d 3924 .no_framedone_tv = true,
8bc65552 3925 .set_max_preload = false,
f2aee319 3926 .last_pixel_inc_missing = true,
dcbe765b
CM		 3927};
3928
ede92695 3929static const struct dispc_features omap44xx_dispc_feats = {
dcbe765b
CM		 3930 .sw_start = 7,
3931 .fp_start = 19,
3932 .bp_start = 31,
3933 .sw_max = 256,
3934 .vp_max = 4095,
3935 .hp_max = 4096,
33b89928
AT		 3936 .mgr_width_start = 10,
3937 .mgr_height_start = 26,
3938 .mgr_width_max = 2048,
3939 .mgr_height_max = 2048,
ca5ca69c
AT		 3940 .max_lcd_pclk = 170000000,
3941 .max_tv_pclk = 185625000,
dcbe765b
CM		 3942 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3943 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3944 .num_fifos = 5,
66a0f9e4 3945 .gfx_fifo_workaround = true,
8bc65552 3946 .set_max_preload = true,
e5f80917 3947 .supports_sync_align = true,
20efbc35 3948 .has_writeback = true,
dcbe765b
CM		 3949};
3950
ede92695 3951static const struct dispc_features omap54xx_dispc_feats = {
264236f8
AT		 3952 .sw_start = 7,
3953 .fp_start = 19,
3954 .bp_start = 31,
3955 .sw_max = 256,
3956 .vp_max = 4095,
3957 .hp_max = 4096,
3958 .mgr_width_start = 11,
3959 .mgr_height_start = 27,
3960 .mgr_width_max = 4096,
3961 .mgr_height_max = 4096,
ca5ca69c
AT		 3962 .max_lcd_pclk = 170000000,
3963 .max_tv_pclk = 186000000,
264236f8
AT		 3964 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3965 .calc_core_clk = calc_core_clk_44xx,
3966 .num_fifos = 5,
3967 .gfx_fifo_workaround = true,
d0df9a2c 3968 .mstandby_workaround = true,
8bc65552 3969 .set_max_preload = true,
e5f80917 3970 .supports_sync_align = true,
20efbc35 3971 .has_writeback = true,
264236f8
AT		 3972};
3973
ede92695 3974static int dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3975{
3976 const struct dispc_features *src;
3977 struct dispc_features *dst;
3978
84b47623 3979 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3980 if (!dst) {
84b47623 3981 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3982 return -ENOMEM;
3983 }
3984
b2c7d54f 3985 switch (omapdss_get_version()) {
84b47623 3986 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3987 src = &omap24xx_dispc_feats;
84b47623
TV		 3988 break;
3989
3990 case OMAPDSS_VER_OMAP34xx_ES1:
3991 src = &omap34xx_rev1_0_dispc_feats;
3992 break;
3993
3994 case OMAPDSS_VER_OMAP34xx_ES3:
3995 case OMAPDSS_VER_OMAP3630:
3996 case OMAPDSS_VER_AM35xx:
d6279d4a 3997 case OMAPDSS_VER_AM43xx:
84b47623
TV		 3998 src = &omap34xx_rev3_0_dispc_feats;
3999 break;
4000
4001 case OMAPDSS_VER_OMAP4430_ES1:
4002 case OMAPDSS_VER_OMAP4430_ES2:
4003 case OMAPDSS_VER_OMAP4:
dcbe765b 4004 src = &omap44xx_dispc_feats;
84b47623
TV		 4005 break;
4006
4007 case OMAPDSS_VER_OMAP5:
93550927 4008 case OMAPDSS_VER_DRA7xx:
264236f8 4009 src = &omap54xx_dispc_feats;
84b47623
TV		 4010 break;
4011
4012 default:
dcbe765b
CM		 4013 return -ENODEV;
4014 }
4015
4016 memcpy(dst, src, sizeof(*dst));
4017 dispc.feat = dst;
4018
4019 return 0;
4020}
4021
0925afc9
TV		 4022static irqreturn_t dispc_irq_handler(int irq, void *arg)
4023{
4024 if (!dispc.is_enabled)
4025 return IRQ_NONE;
4026
4027 return dispc.user_handler(irq, dispc.user_data);
4028}
4029
96e2e637
TV		 4030int dispc_request_irq(irq_handler_t handler, void *dev_id)
4031{
0925afc9
TV		 4032 int r;
4033
4034 if (dispc.user_handler != NULL)
4035 return -EBUSY;
4036
4037 dispc.user_handler = handler;
4038 dispc.user_data = dev_id;
4039
4040 /* ensure the dispc_irq_handler sees the values above */
4041 smp_wmb();
4042
4043 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4044 IRQF_SHARED, "OMAP DISPC", &dispc);
4045 if (r) {
4046 dispc.user_handler = NULL;
4047 dispc.user_data = NULL;
4048 }
4049
4050 return r;
96e2e637 4051}
348be69d 4052EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 4053
4054void dispc_free_irq(void *dev_id)
4055{
0925afc9
TV		 4056 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4057
4058 dispc.user_handler = NULL;
4059 dispc.user_data = NULL;
96e2e637 4060}
348be69d 4061EXPORT_SYMBOL(dispc_free_irq);
96e2e637 4062
060b6d9c 4063/* DISPC HW IP initialisation */
736e60dd 4064static int dispc_bind(struct device *dev, struct device *master, void *data)
060b6d9c 4065{
736e60dd 4066 struct platform_device *pdev = to_platform_device(dev);
060b6d9c 4067 u32 rev;
affe360d 4068 int r = 0;
ea9da36a 4069 struct resource *dispc_mem;
0006fd63 4070 struct device_node *np = pdev->dev.of_node;
ea9da36a 4071
060b6d9c
SG		 4072 dispc.pdev = pdev;
4073
d49cd155
TV		 4074 spin_lock_init(&dispc.control_lock);
4075
84b47623 4076 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4077 if (r)
4078 return r;
4079
ea9da36a
SG		 4080 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4081 if (!dispc_mem) {
4082 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4083 return -EINVAL;
ea9da36a 4084 }
cd3b3449 4085
6e2a14d2
JL		 4086 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4087 resource_size(dispc_mem));
060b6d9c
SG		 4088 if (!dispc.base) {
4089 DSSERR("can't ioremap DISPC\n");
cd3b3449 4090 return -ENOMEM;
affe360d 4091 }
cd3b3449 4092
affe360d 4093 dispc.irq = platform_get_irq(dispc.pdev, 0);
4094 if (dispc.irq < 0) {
4095 DSSERR("platform_get_irq failed\n");
cd3b3449 4096 return -ENODEV;
affe360d 4097 }
4098
0006fd63
TV		 4099 if (np && of_property_read_bool(np, "syscon-pol")) {
4100 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4101 if (IS_ERR(dispc.syscon_pol)) {
4102 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4103 return PTR_ERR(dispc.syscon_pol);
4104 }
4105
4106 if (of_property_read_u32_index(np, "syscon-pol", 1,
4107 &dispc.syscon_pol_offset)) {
4108 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4109 return -EINVAL;
4110 }
4111 }
4112
4fbafaf3
TV		 4113 pm_runtime_enable(&pdev->dev);
4114
4115 r = dispc_runtime_get();
4116 if (r)
4117 goto err_runtime_get;
060b6d9c
SG		 4118
4119 _omap_dispc_initial_config();
4120
060b6d9c 4121 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4122 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4123 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4124
4fbafaf3 4125 dispc_runtime_put();
060b6d9c 4126
04b1fc02
TV		 4127 dss_init_overlay_managers();
4128
e40402cf
TV		 4129 dss_debugfs_create_file("dispc", dispc_dump_regs);
4130
060b6d9c 4131 return 0;
4fbafaf3
TV		 4132
4133err_runtime_get:
4134 pm_runtime_disable(&pdev->dev);
affe360d 4135 return r;
060b6d9c
SG		 4136}
4137
736e60dd
TV		 4138static void dispc_unbind(struct device *dev, struct device *master,
4139 void *data)
060b6d9c 4140{
736e60dd 4141 pm_runtime_disable(dev);
4fbafaf3 4142
04b1fc02 4143 dss_uninit_overlay_managers();
736e60dd
TV		 4144}
4145
4146static const struct component_ops dispc_component_ops = {
4147 .bind = dispc_bind,
4148 .unbind = dispc_unbind,
4149};
04b1fc02 4150
736e60dd
TV		 4151static int dispc_probe(struct platform_device *pdev)
4152{
4153 return component_add(&pdev->dev, &dispc_component_ops);
4154}
4155
4156static int dispc_remove(struct platform_device *pdev)
4157{
4158 component_del(&pdev->dev, &dispc_component_ops);
060b6d9c
SG		 4159 return 0;
4160}
4161
4fbafaf3
TV		 4162static int dispc_runtime_suspend(struct device *dev)
4163{
0925afc9
TV		 4164 dispc.is_enabled = false;
4165 /* ensure the dispc_irq_handler sees the is_enabled value */
4166 smp_wmb();
4167 /* wait for current handler to finish before turning the DISPC off */
4168 synchronize_irq(dispc.irq);
4169
4fbafaf3 4170 dispc_save_context();
4fbafaf3
TV		 4171
4172 return 0;
4173}
4174
4175static int dispc_runtime_resume(struct device *dev)
4176{
9229b516
TV		 4177 /*
4178 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4179 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4180 * _omap_dispc_initial_config(). We can thus use it to detect if
4181 * we have lost register context.
4182 */
0925afc9
TV		 4183 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4184 _omap_dispc_initial_config();
9229b516 4185
0925afc9
TV		 4186 dispc_restore_context();
4187 }
be07dcd7 4188
0925afc9
TV		 4189 dispc.is_enabled = true;
4190 /* ensure the dispc_irq_handler sees the is_enabled value */
4191 smp_wmb();
4fbafaf3
TV		 4192
4193 return 0;
4194}
4195
4196static const struct dev_pm_ops dispc_pm_ops = {
4197 .runtime_suspend = dispc_runtime_suspend,
4198 .runtime_resume = dispc_runtime_resume,
4199};
4200
d7977f88
TV		 4201static const struct of_device_id dispc_of_match[] = {
4202 { .compatible = "ti,omap2-dispc", },
4203 { .compatible = "ti,omap3-dispc", },
4204 { .compatible = "ti,omap4-dispc", },
2e7e6b68 4205 { .compatible = "ti,omap5-dispc", },
93550927 4206 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 4207 {},
4208};
4209
060b6d9c 4210static struct platform_driver omap_dispchw_driver = {
736e60dd
TV		 4211 .probe = dispc_probe,
4212 .remove = dispc_remove,
060b6d9c
SG		 4213 .driver = {
4214 .name = "omapdss_dispc",
4fbafaf3 4215 .pm = &dispc_pm_ops,
d7977f88 4216 .of_match_table = dispc_of_match,
422ccbd5 4217 .suppress_bind_attrs = true,
060b6d9c
SG		 4218 },
4219};
4220
6e7e8f06 4221int __init dispc_init_platform_driver(void)
060b6d9c 4222{
736e60dd 4223 return platform_driver_register(&omap_dispchw_driver);
060b6d9c
SG		 4224}
4225
ede92695 4226void dispc_uninit_platform_driver(void)
060b6d9c 4227{
04c742c3 4228 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4229}
Linux kernel - Deliverables
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