projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAPDSS: DISPC: add check for scaling limits
[deliverable/linux.git] / drivers / video / fbdev / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
80c39712 42
a0b38cc4 43#include <video/omapdss.h>
80c39712
TV		 44
45#include "dss.h"
a0acb557 46#include "dss_features.h"
9b372c2d 47#include "dispc.h"
80c39712
TV		 48
49/* DISPC */
8613b000 50#define DISPC_SZ_REGS SZ_4K
80c39712 51
5ed8cf5b
TV		 52enum omap_burst_size {
53 BURST_SIZE_X2 = 0,
54 BURST_SIZE_X4 = 1,
55 BURST_SIZE_X8 = 2,
56};
57
80c39712
TV		 58#define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
60
61#define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
63
dcbe765b
CM		 64struct dispc_features {
65 u8 sw_start;
66 u8 fp_start;
67 u8 bp_start;
68 u16 sw_max;
69 u16 vp_max;
70 u16 hp_max;
33b89928
AT		 71 u8 mgr_width_start;
72 u8 mgr_height_start;
73 u16 mgr_width_max;
74 u16 mgr_height_max;
ca5ca69c
AT		 75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk;
0c6921de 77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 78 const struct omap_video_timings *mgr_timings,
79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 82 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 83 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 84 u16 width, u16 height, u16 out_width, u16 out_height,
85 bool mem_to_mem);
42a6961c 86 u8 num_fifos;
66a0f9e4
TV		 87
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround:1;
cffa947d
TV		 90
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv:1;
d0df9a2c
AT		 93
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround:1;
8bc65552
AT		 96
97 bool set_max_preload:1;
dcbe765b
CM		 98};
99
42a6961c
TV		 100#define DISPC_MAX_NR_FIFOS 5
101
80c39712 102static struct {
060b6d9c 103 struct platform_device *pdev;
80c39712 104 void __iomem *base;
4fbafaf3 105
affe360d 106 int irq;
0925afc9
TV		 107 irq_handler_t user_handler;
108 void *user_data;
80c39712 109
7b3926b3 110 unsigned long core_clk_rate;
5391e87d 111 unsigned long tv_pclk_rate;
7b3926b3 112
42a6961c
TV		 113 u32 fifo_size[DISPC_MAX_NR_FIFOS];
114 /* maps which plane is using a fifo. fifo-id -> plane-id */
115 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 116
49ea86f3 117 bool ctx_valid;
80c39712 118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 119
dcbe765b 120 const struct dispc_features *feat;
0925afc9
TV		 121
122 bool is_enabled;
0006fd63
TV		 123
124 struct regmap *syscon_pol;
125 u32 syscon_pol_offset;
d49cd155
TV		 126
127 /* DISPC_CONTROL & DISPC_CONFIG lock*/
128 spinlock_t control_lock;
80c39712
TV		 129} dispc;
130
0d66cbb5
AJ		 131enum omap_color_component {
132 /* used for all color formats for OMAP3 and earlier
133 * and for RGB and Y color component on OMAP4
134 */
135 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
136 /* used for UV component for
137 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
138 * color formats on OMAP4
139 */
140 DISPC_COLOR_COMPONENT_UV = 1 << 1,
141};
142
efa70b3b
CM		 143enum mgr_reg_fields {
144 DISPC_MGR_FLD_ENABLE,
145 DISPC_MGR_FLD_STNTFT,
146 DISPC_MGR_FLD_GO,
147 DISPC_MGR_FLD_TFTDATALINES,
148 DISPC_MGR_FLD_STALLMODE,
149 DISPC_MGR_FLD_TCKENABLE,
150 DISPC_MGR_FLD_TCKSELECTION,
151 DISPC_MGR_FLD_CPR,
152 DISPC_MGR_FLD_FIFOHANDCHECK,
153 /* used to maintain a count of the above fields */
154 DISPC_MGR_FLD_NUM,
155};
156
5c348ba9
JS		 157struct dispc_reg_field {
158 u16 reg;
159 u8 high;
160 u8 low;
161};
162
efa70b3b
CM		 163static const struct {
164 const char *name;
165 u32 vsync_irq;
166 u32 framedone_irq;
167 u32 sync_lost_irq;
5c348ba9 168 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 169} mgr_desc[] = {
170 [OMAP_DSS_CHANNEL_LCD] = {
171 .name = "LCD",
172 .vsync_irq = DISPC_IRQ_VSYNC,
173 .framedone_irq = DISPC_IRQ_FRAMEDONE,
174 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
175 .reg_desc = {
176 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
177 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
178 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
179 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
180 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
181 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
182 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
183 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
184 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
185 },
186 },
187 [OMAP_DSS_CHANNEL_DIGIT] = {
188 .name = "DIGIT",
189 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 190 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 191 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
192 .reg_desc = {
193 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
194 [DISPC_MGR_FLD_STNTFT] = { },
195 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
196 [DISPC_MGR_FLD_TFTDATALINES] = { },
197 [DISPC_MGR_FLD_STALLMODE] = { },
198 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
199 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
200 [DISPC_MGR_FLD_CPR] = { },
201 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
202 },
203 },
204 [OMAP_DSS_CHANNEL_LCD2] = {
205 .name = "LCD2",
206 .vsync_irq = DISPC_IRQ_VSYNC2,
207 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
208 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
209 .reg_desc = {
210 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
211 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
212 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
213 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
214 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
215 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
216 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
217 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
218 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
219 },
220 },
e86d456a
CM		 221 [OMAP_DSS_CHANNEL_LCD3] = {
222 .name = "LCD3",
223 .vsync_irq = DISPC_IRQ_VSYNC3,
224 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
225 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
226 .reg_desc = {
227 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
228 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
229 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
230 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
231 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
232 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
233 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
234 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
235 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
236 },
237 },
efa70b3b
CM		 238};
239
6e5264b0
AT		 240struct color_conv_coef {
241 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
242 int full_range;
243};
244
3e8a6ff2
AT		 245static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
246static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 247
55978cc2 248static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 249{
55978cc2 250 __raw_writel(val, dispc.base + idx);
80c39712
TV		 251}
252
55978cc2 253static inline u32 dispc_read_reg(const u16 idx)
80c39712 254{
55978cc2 255 return __raw_readl(dispc.base + idx);
80c39712
TV		 256}
257
efa70b3b
CM		 258static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
259{
5c348ba9 260 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 261 return REG_GET(rfld.reg, rfld.high, rfld.low);
262}
263
264static void mgr_fld_write(enum omap_channel channel,
265 enum mgr_reg_fields regfld, int val) {
5c348ba9 266 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
d49cd155
TV		 267 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
268 unsigned long flags;
269
270 if (need_lock)
271 spin_lock_irqsave(&dispc.control_lock, flags);
272
efa70b3b 273 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
d49cd155
TV		 274
275 if (need_lock)
276 spin_unlock_irqrestore(&dispc.control_lock, flags);
efa70b3b
CM		 277}
278
80c39712 279#define SR(reg) \
55978cc2 280 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 281#define RR(reg) \
55978cc2 282 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 283
4fbafaf3 284static void dispc_save_context(void)
80c39712 285{
c6104b8e 286 int i, j;
80c39712 287
4fbafaf3
TV		 288 DSSDBG("dispc_save_context\n");
289
80c39712
TV		 290 SR(IRQENABLE);
291 SR(CONTROL);
292 SR(CONFIG);
80c39712 293 SR(LINE_NUMBER);
11354dd5
AT		 294 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
295 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 296 SR(GLOBAL_ALPHA);
2a205f34
SS		 297 if (dss_has_feature(FEAT_MGR_LCD2)) {
298 SR(CONTROL2);
2a205f34
SS		 299 SR(CONFIG2);
300 }
e86d456a
CM		 301 if (dss_has_feature(FEAT_MGR_LCD3)) {
302 SR(CONTROL3);
303 SR(CONFIG3);
304 }
80c39712 305
c6104b8e
AT		 306 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
307 SR(DEFAULT_COLOR(i));
308 SR(TRANS_COLOR(i));
309 SR(SIZE_MGR(i));
310 if (i == OMAP_DSS_CHANNEL_DIGIT)
311 continue;
312 SR(TIMING_H(i));
313 SR(TIMING_V(i));
314 SR(POL_FREQ(i));
315 SR(DIVISORo(i));
316
317 SR(DATA_CYCLE1(i));
318 SR(DATA_CYCLE2(i));
319 SR(DATA_CYCLE3(i));
320
332e9d70 321 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 322 SR(CPR_COEF_R(i));
323 SR(CPR_COEF_G(i));
324 SR(CPR_COEF_B(i));
332e9d70 325 }
2a205f34 326 }
80c39712 327
c6104b8e
AT		 328 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
329 SR(OVL_BA0(i));
330 SR(OVL_BA1(i));
331 SR(OVL_POSITION(i));
332 SR(OVL_SIZE(i));
333 SR(OVL_ATTRIBUTES(i));
334 SR(OVL_FIFO_THRESHOLD(i));
335 SR(OVL_ROW_INC(i));
336 SR(OVL_PIXEL_INC(i));
337 if (dss_has_feature(FEAT_PRELOAD))
338 SR(OVL_PRELOAD(i));
339 if (i == OMAP_DSS_GFX) {
340 SR(OVL_WINDOW_SKIP(i));
341 SR(OVL_TABLE_BA(i));
342 continue;
343 }
344 SR(OVL_FIR(i));
345 SR(OVL_PICTURE_SIZE(i));
346 SR(OVL_ACCU0(i));
347 SR(OVL_ACCU1(i));
9b372c2d 348
c6104b8e
AT		 349 for (j = 0; j < 8; j++)
350 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 351
c6104b8e
AT		 352 for (j = 0; j < 8; j++)
353 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 354
c6104b8e
AT		 355 for (j = 0; j < 5; j++)
356 SR(OVL_CONV_COEF(i, j));
ab5ca071 357
c6104b8e
AT		 358 if (dss_has_feature(FEAT_FIR_COEF_V)) {
359 for (j = 0; j < 8; j++)
360 SR(OVL_FIR_COEF_V(i, j));
361 }
9b372c2d 362
c6104b8e
AT		 363 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
364 SR(OVL_BA0_UV(i));
365 SR(OVL_BA1_UV(i));
366 SR(OVL_FIR2(i));
367 SR(OVL_ACCU2_0(i));
368 SR(OVL_ACCU2_1(i));
ab5ca071 369
c6104b8e
AT		 370 for (j = 0; j < 8; j++)
371 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 372
c6104b8e
AT		 373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 375
c6104b8e
AT		 376 for (j = 0; j < 8; j++)
377 SR(OVL_FIR_COEF_V2(i, j));
378 }
379 if (dss_has_feature(FEAT_ATTR2))
380 SR(OVL_ATTRIBUTES2(i));
ab5ca071 381 }
0cf35df3
MR		 382
383 if (dss_has_feature(FEAT_CORE_CLK_DIV))
384 SR(DIVISOR);
49ea86f3 385
49ea86f3
TV		 386 dispc.ctx_valid = true;
387
9229b516 388 DSSDBG("context saved\n");
80c39712
TV		 389}
390
4fbafaf3 391static void dispc_restore_context(void)
80c39712 392{
9229b516 393 int i, j;
4fbafaf3
TV		 394
395 DSSDBG("dispc_restore_context\n");
396
49ea86f3
TV		 397 if (!dispc.ctx_valid)
398 return;
399
75c7d59d 400 /*RR(IRQENABLE);*/
80c39712
TV		 401 /*RR(CONTROL);*/
402 RR(CONFIG);
80c39712 403 RR(LINE_NUMBER);
11354dd5
AT		 404 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
405 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 406 RR(GLOBAL_ALPHA);
c6104b8e 407 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 408 RR(CONFIG2);
e86d456a
CM		 409 if (dss_has_feature(FEAT_MGR_LCD3))
410 RR(CONFIG3);
80c39712 411
c6104b8e
AT		 412 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
413 RR(DEFAULT_COLOR(i));
414 RR(TRANS_COLOR(i));
415 RR(SIZE_MGR(i));
416 if (i == OMAP_DSS_CHANNEL_DIGIT)
417 continue;
418 RR(TIMING_H(i));
419 RR(TIMING_V(i));
420 RR(POL_FREQ(i));
421 RR(DIVISORo(i));
422
423 RR(DATA_CYCLE1(i));
424 RR(DATA_CYCLE2(i));
425 RR(DATA_CYCLE3(i));
2a205f34 426
332e9d70 427 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 428 RR(CPR_COEF_R(i));
429 RR(CPR_COEF_G(i));
430 RR(CPR_COEF_B(i));
332e9d70 431 }
2a205f34 432 }
80c39712 433
c6104b8e
AT		 434 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
435 RR(OVL_BA0(i));
436 RR(OVL_BA1(i));
437 RR(OVL_POSITION(i));
438 RR(OVL_SIZE(i));
439 RR(OVL_ATTRIBUTES(i));
440 RR(OVL_FIFO_THRESHOLD(i));
441 RR(OVL_ROW_INC(i));
442 RR(OVL_PIXEL_INC(i));
443 if (dss_has_feature(FEAT_PRELOAD))
444 RR(OVL_PRELOAD(i));
445 if (i == OMAP_DSS_GFX) {
446 RR(OVL_WINDOW_SKIP(i));
447 RR(OVL_TABLE_BA(i));
448 continue;
449 }
450 RR(OVL_FIR(i));
451 RR(OVL_PICTURE_SIZE(i));
452 RR(OVL_ACCU0(i));
453 RR(OVL_ACCU1(i));
9b372c2d 454
c6104b8e
AT		 455 for (j = 0; j < 8; j++)
456 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 457
c6104b8e
AT		 458 for (j = 0; j < 8; j++)
459 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 460
c6104b8e
AT		 461 for (j = 0; j < 5; j++)
462 RR(OVL_CONV_COEF(i, j));
ab5ca071 463
c6104b8e
AT		 464 if (dss_has_feature(FEAT_FIR_COEF_V)) {
465 for (j = 0; j < 8; j++)
466 RR(OVL_FIR_COEF_V(i, j));
467 }
9b372c2d 468
c6104b8e
AT		 469 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
470 RR(OVL_BA0_UV(i));
471 RR(OVL_BA1_UV(i));
472 RR(OVL_FIR2(i));
473 RR(OVL_ACCU2_0(i));
474 RR(OVL_ACCU2_1(i));
ab5ca071 475
c6104b8e
AT		 476 for (j = 0; j < 8; j++)
477 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 478
c6104b8e
AT		 479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 481
c6104b8e
AT		 482 for (j = 0; j < 8; j++)
483 RR(OVL_FIR_COEF_V2(i, j));
484 }
485 if (dss_has_feature(FEAT_ATTR2))
486 RR(OVL_ATTRIBUTES2(i));
ab5ca071 487 }
80c39712 488
0cf35df3
MR		 489 if (dss_has_feature(FEAT_CORE_CLK_DIV))
490 RR(DIVISOR);
491
80c39712
TV		 492 /* enable last, because LCD & DIGIT enable are here */
493 RR(CONTROL);
2a205f34
SS		 494 if (dss_has_feature(FEAT_MGR_LCD2))
495 RR(CONTROL2);
e86d456a
CM		 496 if (dss_has_feature(FEAT_MGR_LCD3))
497 RR(CONTROL3);
75c7d59d 498 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 499 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 500
501 /*
502 * enable last so IRQs won't trigger before
503 * the context is fully restored
504 */
505 RR(IRQENABLE);
49ea86f3
TV		 506
507 DSSDBG("context restored\n");
80c39712
TV		 508}
509
510#undef SR
511#undef RR
512
4fbafaf3
TV		 513int dispc_runtime_get(void)
514{
515 int r;
516
517 DSSDBG("dispc_runtime_get\n");
518
519 r = pm_runtime_get_sync(&dispc.pdev->dev);
520 WARN_ON(r < 0);
521 return r < 0 ? r : 0;
522}
348be69d 523EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 524
525void dispc_runtime_put(void)
526{
527 int r;
528
529 DSSDBG("dispc_runtime_put\n");
530
0eaf9f52 531 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 532 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 533}
348be69d 534EXPORT_SYMBOL(dispc_runtime_put);
80c39712 535
3dcec4d6
TV		 536u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
537{
efa70b3b 538 return mgr_desc[channel].vsync_irq;
3dcec4d6 539}
348be69d 540EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 541
7d1365c9
TV		 542u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
543{
cffa947d
TV		 544 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
545 return 0;
546
efa70b3b 547 return mgr_desc[channel].framedone_irq;
7d1365c9 548}
348be69d 549EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 550
cb699200
TV		 551u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
552{
553 return mgr_desc[channel].sync_lost_irq;
554}
348be69d 555EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 556
0b23e5b8
AT		 557u32 dispc_wb_get_framedone_irq(void)
558{
559 return DISPC_IRQ_FRAMEDONEWB;
560}
561
26d9dd0d 562bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 563{
efa70b3b 564 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 565}
348be69d 566EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 567
26d9dd0d 568void dispc_mgr_go(enum omap_channel channel)
80c39712 569{
3c91ee8c
TV		 570 WARN_ON(dispc_mgr_is_enabled(channel) == false);
571 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 572
efa70b3b 573 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 574
efa70b3b 575 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 576}
348be69d 577EXPORT_SYMBOL(dispc_mgr_go);
80c39712 578
0b23e5b8
AT		 579bool dispc_wb_go_busy(void)
580{
581 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
582}
583
584void dispc_wb_go(void)
585{
586 enum omap_plane plane = OMAP_DSS_WB;
587 bool enable, go;
588
589 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
590
591 if (!enable)
592 return;
593
594 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
595 if (go) {
596 DSSERR("GO bit not down for WB\n");
597 return;
598 }
599
600 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
601}
602
f0e5caab 603static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 604{
9b372c2d 605 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 606}
607
f0e5caab 608static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 609{
9b372c2d 610 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 611}
612
f0e5caab 613static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 614{
9b372c2d 615 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 616}
617
f0e5caab 618static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 619{
620 BUG_ON(plane == OMAP_DSS_GFX);
621
622 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
623}
624
f0e5caab
TV		 625static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
626 u32 value)
ab5ca071
AJ		 627{
628 BUG_ON(plane == OMAP_DSS_GFX);
629
630 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
631}
632
f0e5caab 633static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 634{
635 BUG_ON(plane == OMAP_DSS_GFX);
636
637 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
638}
639
debd9074
CM		 640static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
641 int fir_vinc, int five_taps,
642 enum omap_color_component color_comp)
80c39712 643{
debd9074 644 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 645 int i;
646
debd9074
CM		 647 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
648 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 649
650 for (i = 0; i < 8; i++) {
651 u32 h, hv;
652
debd9074
CM		 653 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
654 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
655 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
656 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
657 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
658 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
659 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
660 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 661
0d66cbb5 662 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 663 dispc_ovl_write_firh_reg(plane, i, h);
664 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 665 } else {
f0e5caab
TV		 666 dispc_ovl_write_firh2_reg(plane, i, h);
667 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 668 }
669
80c39712
TV		 670 }
671
66be8f6c
GI		 672 if (five_taps) {
673 for (i = 0; i < 8; i++) {
674 u32 v;
debd9074
CM		 675 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
676 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 677 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 678 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 679 else
f0e5caab 680 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 681 }
80c39712
TV		 682 }
683}
684
80c39712 685
6e5264b0
AT		 686static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
687 const struct color_conv_coef *ct)
688{
80c39712
TV		 689#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
690
6e5264b0
AT		 691 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
692 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
694 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 696
6e5264b0 697 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 698
699#undef CVAL
80c39712
TV		 700}
701
6e5264b0
AT		 702static void dispc_setup_color_conv_coef(void)
703{
704 int i;
705 int num_ovl = dss_feat_get_num_ovls();
706 int num_wb = dss_feat_get_num_wbs();
707 const struct color_conv_coef ctbl_bt601_5_ovl = {
708 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
709 };
710 const struct color_conv_coef ctbl_bt601_5_wb = {
711 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
712 };
713
714 for (i = 1; i < num_ovl; i++)
715 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
716
717 for (; i < num_wb; i++)
718 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
719}
80c39712 720
f0e5caab 721static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 722{
9b372c2d 723 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 724}
725
f0e5caab 726static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 727{
9b372c2d 728 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 729}
730
f0e5caab 731static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 732{
733 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
734}
735
f0e5caab 736static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 737{
738 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
739}
740
d79db853
AT		 741static void dispc_ovl_set_pos(enum omap_plane plane,
742 enum omap_overlay_caps caps, int x, int y)
80c39712 743{
d79db853
AT		 744 u32 val;
745
746 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
747 return;
748
749 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 750
751 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 752}
753
78b687fc
AT		 754static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
755 int height)
80c39712 756{
80c39712 757 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 758
36d87d95 759 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 760 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
761 else
762 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 763}
764
78b687fc
AT		 765static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
766 int height)
80c39712
TV		 767{
768 u32 val;
80c39712
TV		 769
770 BUG_ON(plane == OMAP_DSS_GFX);
771
772 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 773
36d87d95
AT		 774 if (plane == OMAP_DSS_WB)
775 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
776 else
777 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 778}
779
5b54ed3e
AT		 780static void dispc_ovl_set_zorder(enum omap_plane plane,
781 enum omap_overlay_caps caps, u8 zorder)
54128701 782{
5b54ed3e 783 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 784 return;
785
786 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
787}
788
789static void dispc_ovl_enable_zorder_planes(void)
790{
791 int i;
792
793 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
794 return;
795
796 for (i = 0; i < dss_feat_get_num_ovls(); i++)
797 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
798}
799
5b54ed3e
AT		 800static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
801 enum omap_overlay_caps caps, bool enable)
fd28a390 802{
5b54ed3e 803 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 804 return;
805
9b372c2d 806 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 807}
808
5b54ed3e
AT		 809static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
810 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 811{
b8c095b4 812 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 813 int shift;
814
5b54ed3e 815 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 816 return;
a0acb557 817
fe3cc9d6
TV		 818 shift = shifts[plane];
819 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 820}
821
f0e5caab 822static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 823{
9b372c2d 824 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 825}
826
f0e5caab 827static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 828{
9b372c2d 829 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 830}
831
f0e5caab 832static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 833 enum omap_color_mode color_mode)
834{
835 u32 m = 0;
f20e4220
AJ		 836 if (plane != OMAP_DSS_GFX) {
837 switch (color_mode) {
838 case OMAP_DSS_COLOR_NV12:
839 m = 0x0; break;
08f3267e 840 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 841 m = 0x1; break;
842 case OMAP_DSS_COLOR_RGBA16:
843 m = 0x2; break;
08f3267e 844 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 845 m = 0x4; break;
846 case OMAP_DSS_COLOR_ARGB16:
847 m = 0x5; break;
848 case OMAP_DSS_COLOR_RGB16:
849 m = 0x6; break;
850 case OMAP_DSS_COLOR_ARGB16_1555:
851 m = 0x7; break;
852 case OMAP_DSS_COLOR_RGB24U:
853 m = 0x8; break;
854 case OMAP_DSS_COLOR_RGB24P:
855 m = 0x9; break;
856 case OMAP_DSS_COLOR_YUV2:
857 m = 0xa; break;
858 case OMAP_DSS_COLOR_UYVY:
859 m = 0xb; break;
860 case OMAP_DSS_COLOR_ARGB32:
861 m = 0xc; break;
862 case OMAP_DSS_COLOR_RGBA32:
863 m = 0xd; break;
864 case OMAP_DSS_COLOR_RGBX32:
865 m = 0xe; break;
866 case OMAP_DSS_COLOR_XRGB16_1555:
867 m = 0xf; break;
868 default:
c6eee968 869 BUG(); return;
f20e4220
AJ		 870 }
871 } else {
872 switch (color_mode) {
873 case OMAP_DSS_COLOR_CLUT1:
874 m = 0x0; break;
875 case OMAP_DSS_COLOR_CLUT2:
876 m = 0x1; break;
877 case OMAP_DSS_COLOR_CLUT4:
878 m = 0x2; break;
879 case OMAP_DSS_COLOR_CLUT8:
880 m = 0x3; break;
881 case OMAP_DSS_COLOR_RGB12U:
882 m = 0x4; break;
883 case OMAP_DSS_COLOR_ARGB16:
884 m = 0x5; break;
885 case OMAP_DSS_COLOR_RGB16:
886 m = 0x6; break;
887 case OMAP_DSS_COLOR_ARGB16_1555:
888 m = 0x7; break;
889 case OMAP_DSS_COLOR_RGB24U:
890 m = 0x8; break;
891 case OMAP_DSS_COLOR_RGB24P:
892 m = 0x9; break;
08f3267e 893 case OMAP_DSS_COLOR_RGBX16:
f20e4220 894 m = 0xa; break;
08f3267e 895 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 896 m = 0xb; break;
897 case OMAP_DSS_COLOR_ARGB32:
898 m = 0xc; break;
899 case OMAP_DSS_COLOR_RGBA32:
900 m = 0xd; break;
901 case OMAP_DSS_COLOR_RGBX32:
902 m = 0xe; break;
903 case OMAP_DSS_COLOR_XRGB16_1555:
904 m = 0xf; break;
905 default:
c6eee968 906 BUG(); return;
f20e4220 907 }
80c39712
TV		 908 }
909
9b372c2d 910 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 911}
912
65e006ff
CM		 913static void dispc_ovl_configure_burst_type(enum omap_plane plane,
914 enum omap_dss_rotation_type rotation_type)
915{
916 if (dss_has_feature(FEAT_BURST_2D) == 0)
917 return;
918
919 if (rotation_type == OMAP_DSS_ROT_TILER)
920 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
921 else
922 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
923}
924
f427984e 925void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 926{
927 int shift;
928 u32 val;
2a205f34 929 int chan = 0, chan2 = 0;
80c39712
TV		 930
931 switch (plane) {
932 case OMAP_DSS_GFX:
933 shift = 8;
934 break;
935 case OMAP_DSS_VIDEO1:
936 case OMAP_DSS_VIDEO2:
b8c095b4 937 case OMAP_DSS_VIDEO3:
80c39712
TV		 938 shift = 16;
939 break;
940 default:
941 BUG();
942 return;
943 }
944
9b372c2d 945 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 946 if (dss_has_feature(FEAT_MGR_LCD2)) {
947 switch (channel) {
948 case OMAP_DSS_CHANNEL_LCD:
949 chan = 0;
950 chan2 = 0;
951 break;
952 case OMAP_DSS_CHANNEL_DIGIT:
953 chan = 1;
954 chan2 = 0;
955 break;
956 case OMAP_DSS_CHANNEL_LCD2:
957 chan = 0;
958 chan2 = 1;
959 break;
e86d456a
CM		 960 case OMAP_DSS_CHANNEL_LCD3:
961 if (dss_has_feature(FEAT_MGR_LCD3)) {
962 chan = 0;
963 chan2 = 2;
964 } else {
965 BUG();
966 return;
967 }
968 break;
2a205f34
SS		 969 default:
970 BUG();
c6eee968 971 return;
2a205f34
SS		 972 }
973
974 val = FLD_MOD(val, chan, shift, shift);
975 val = FLD_MOD(val, chan2, 31, 30);
976 } else {
977 val = FLD_MOD(val, channel, shift, shift);
978 }
9b372c2d 979 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 980}
348be69d 981EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 982
2cc5d1af
TV		 983static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
984{
985 int shift;
986 u32 val;
987 enum omap_channel channel;
988
989 switch (plane) {
990 case OMAP_DSS_GFX:
991 shift = 8;
992 break;
993 case OMAP_DSS_VIDEO1:
994 case OMAP_DSS_VIDEO2:
995 case OMAP_DSS_VIDEO3:
996 shift = 16;
997 break;
998 default:
999 BUG();
c6eee968 1000 return 0;
2cc5d1af
TV		 1001 }
1002
1003 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1004
e86d456a
CM		 1005 if (dss_has_feature(FEAT_MGR_LCD3)) {
1006 if (FLD_GET(val, 31, 30) == 0)
1007 channel = FLD_GET(val, shift, shift);
1008 else if (FLD_GET(val, 31, 30) == 1)
1009 channel = OMAP_DSS_CHANNEL_LCD2;
1010 else
1011 channel = OMAP_DSS_CHANNEL_LCD3;
1012 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1013 if (FLD_GET(val, 31, 30) == 0)
1014 channel = FLD_GET(val, shift, shift);
1015 else
1016 channel = OMAP_DSS_CHANNEL_LCD2;
1017 } else {
1018 channel = FLD_GET(val, shift, shift);
1019 }
1020
1021 return channel;
1022}
1023
d9ac773c
AT		 1024void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1025{
1026 enum omap_plane plane = OMAP_DSS_WB;
1027
1028 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029}
1030
f0e5caab 1031static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1032 enum omap_burst_size burst_size)
1033{
8bbe09ee 1034 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1035 int shift;
80c39712 1036
fe3cc9d6 1037 shift = shifts[plane];
5ed8cf5b 1038 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1039}
1040
5ed8cf5b
TV		 1041static void dispc_configure_burst_sizes(void)
1042{
1043 int i;
1044 const int burst_size = BURST_SIZE_X8;
1045
1046 /* Configure burst size always to maximum size */
392faa0e 1047 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1048 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1049}
1050
83fa2f2e 1051static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1052{
1053 unsigned unit = dss_feat_get_burst_size_unit();
1054 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1055 return unit * 8;
1056}
1057
d3862610
M		 1058void dispc_enable_gamma_table(bool enable)
1059{
1060 /*
1061 * This is partially implemented to support only disabling of
1062 * the gamma table.
1063 */
1064 if (enable) {
1065 DSSWARN("Gamma table enabling for TV not yet supported");
1066 return;
1067 }
1068
1069 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070}
1071
c64dca40 1072static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1073{
efa70b3b 1074 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1075 return;
1076
efa70b3b 1077 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1078}
1079
c64dca40 1080static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1081 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1082{
1083 u32 coef_r, coef_g, coef_b;
1084
dd88b7a6 1085 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1086 return;
1087
1088 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1089 FLD_VAL(coefs->rb, 9, 0);
1090 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1091 FLD_VAL(coefs->gb, 9, 0);
1092 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1093 FLD_VAL(coefs->bb, 9, 0);
1094
1095 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1096 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1097 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098}
1099
f0e5caab 1100static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1101{
1102 u32 val;
1103
1104 BUG_ON(plane == OMAP_DSS_GFX);
1105
9b372c2d 1106 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1107 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1108 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1109}
1110
d79db853
AT		 1111static void dispc_ovl_enable_replication(enum omap_plane plane,
1112 enum omap_overlay_caps caps, bool enable)
80c39712 1113{
b8c095b4 1114 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1115 int shift;
80c39712 1116
d79db853
AT		 1117 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118 return;
1119
fe3cc9d6
TV		 1120 shift = shifts[plane];
1121 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1122}
1123
8f366162 1124static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1125 u16 height)
80c39712
TV		 1126{
1127 u32 val;
80c39712 1128
33b89928
AT		 1129 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1130 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1131
8f366162 1132 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1133}
1134
42a6961c 1135static void dispc_init_fifos(void)
80c39712 1136{
80c39712 1137 u32 size;
42a6961c 1138 int fifo;
a0acb557 1139 u8 start, end;
5ed8cf5b 1140 u32 unit;
47fc469b 1141 int i;
5ed8cf5b
TV		 1142
1143 unit = dss_feat_get_buffer_size_unit();
80c39712 1144
a0acb557 1145 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1146
42a6961c
TV		 1147 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1148 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1149 size *= unit;
42a6961c
TV		 1150 dispc.fifo_size[fifo] = size;
1151
1152 /*
1153 * By default fifos are mapped directly to overlays, fifo 0 to
1154 * ovl 0, fifo 1 to ovl 1, etc.
1155 */
1156 dispc.fifo_assignment[fifo] = fifo;
80c39712 1157 }
66a0f9e4
TV		 1158
1159 /*
1160 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1161 * causes problems with certain use cases, like using the tiler in 2D
1162 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1163 * giving GFX plane a larger fifo. WB but should work fine with a
1164 * smaller fifo.
1165 */
1166 if (dispc.feat->gfx_fifo_workaround) {
1167 u32 v;
1168
1169 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1170
1171 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1172 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1173 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1174 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1175
1176 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1177
1178 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1179 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1180 }
47fc469b
TV		 1181
1182 /*
1183 * Setup default fifo thresholds.
1184 */
1185 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1186 u32 low, high;
1187 const bool use_fifomerge = false;
1188 const bool manual_update = false;
1189
1190 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1191 use_fifomerge, manual_update);
1192
1193 dispc_ovl_set_fifo_threshold(i, low, high);
1194 }
80c39712
TV		 1195}
1196
83fa2f2e 1197static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1198{
42a6961c
TV		 1199 int fifo;
1200 u32 size = 0;
1201
1202 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1203 if (dispc.fifo_assignment[fifo] == plane)
1204 size += dispc.fifo_size[fifo];
1205 }
1206
1207 return size;
80c39712
TV		 1208}
1209
6f04e1bf 1210void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1211{
a0acb557 1212 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1213 u32 unit;
1214
1215 unit = dss_feat_get_buffer_size_unit();
1216
1217 WARN_ON(low % unit != 0);
1218 WARN_ON(high % unit != 0);
1219
1220 low /= unit;
1221 high /= unit;
a0acb557 1222
9b372c2d
AT		 1223 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1224 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1225
3cb5d966 1226 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1227 plane,
9b372c2d 1228 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1229 lo_start, lo_end) * unit,
9b372c2d 1230 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1231 hi_start, hi_end) * unit,
1232 low * unit, high * unit);
80c39712 1233
9b372c2d 1234 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1235 FLD_VAL(high, hi_start, hi_end) |
1236 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1237
1238 /*
1239 * configure the preload to the pipeline's high threhold, if HT it's too
1240 * large for the preload field, set the threshold to the maximum value
1241 * that can be held by the preload register
1242 */
1243 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1244 plane != OMAP_DSS_WB)
1245 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712 1246}
8ee5c842 1247EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
80c39712
TV		 1248
1249void dispc_enable_fifomerge(bool enable)
1250{
e6b0f884
TV		 1251 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1252 WARN_ON(enable);
1253 return;
1254 }
1255
80c39712
TV		 1256 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1257 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1258}
1259
83fa2f2e 1260void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1261 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1262 bool manual_update)
83fa2f2e
TV		 1263{
1264 /*
1265 * All sizes are in bytes. Both the buffer and burst are made of
1266 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1267 */
1268
1269 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1270 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1271 int i;
83fa2f2e
TV		 1272
1273 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1274 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1275
e0e405b9
TV		 1276 if (use_fifomerge) {
1277 total_fifo_size = 0;
392faa0e 1278 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1279 total_fifo_size += dispc_ovl_get_fifo_size(i);
1280 } else {
1281 total_fifo_size = ovl_fifo_size;
1282 }
1283
1284 /*
1285 * We use the same low threshold for both fifomerge and non-fifomerge
1286 * cases, but for fifomerge we calculate the high threshold using the
1287 * combined fifo size
1288 */
1289
3568f2a4 1290 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1291 *fifo_low = ovl_fifo_size - burst_size * 2;
1292 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1293 } else if (plane == OMAP_DSS_WB) {
1294 /*
1295 * Most optimal configuration for writeback is to push out data
1296 * to the interconnect the moment writeback pushes enough pixels
1297 * in the FIFO to form a burst
1298 */
1299 *fifo_low = 0;
1300 *fifo_high = burst_size;
e0e405b9
TV		 1301 } else {
1302 *fifo_low = ovl_fifo_size - burst_size;
1303 *fifo_high = total_fifo_size - buf_unit;
1304 }
83fa2f2e 1305}
8ee5c842 1306EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
83fa2f2e 1307
c64aa3a6
TV		 1308static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1309{
1310 int bit;
1311
1312 if (plane == OMAP_DSS_GFX)
1313 bit = 14;
1314 else
1315 bit = 23;
1316
1317 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1318}
1319
1320static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1321 int low, int high)
1322{
1323 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1324 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1325}
1326
1327static void dispc_init_mflag(void)
1328{
1329 int i;
1330
fe59e5cf
TV		 1331 /*
1332 * HACK: NV12 color format and MFLAG seem to have problems working
1333 * together: using two displays, and having an NV12 overlay on one of
1334 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1335 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1336 * remove the errors, but there doesn't seem to be a clear logic on
1337 * which values work and which not.
1338 *
1339 * As a work-around, set force MFLAG to always on.
1340 */
c64aa3a6 1341 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
fe59e5cf 1342 (1 << 0) | /* MFLAG_CTRL = force always on */
c64aa3a6
TV		 1343 (0 << 2)); /* MFLAG_START = disable */
1344
1345 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1346 u32 size = dispc_ovl_get_fifo_size(i);
1347 u32 unit = dss_feat_get_buffer_size_unit();
1348 u32 low, high;
1349
1350 dispc_ovl_set_mflag(i, true);
1351
1352 /*
1353 * Simulation team suggests below thesholds:
1354 * HT = fifosize * 5 / 8;
1355 * LT = fifosize * 4 / 8;
1356 */
1357
1358 low = size * 4 / 8 / unit;
1359 high = size * 5 / 8 / unit;
1360
1361 dispc_ovl_set_mflag_threshold(i, low, high);
1362 }
1363}
1364
f0e5caab 1365static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1366 int hinc, int vinc,
1367 enum omap_color_component color_comp)
80c39712
TV		 1368{
1369 u32 val;
80c39712 1370
0d66cbb5
AJ		 1371 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1372 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1373
0d66cbb5
AJ		 1374 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1375 &hinc_start, &hinc_end);
1376 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1377 &vinc_start, &vinc_end);
1378 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1379 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1380
0d66cbb5
AJ		 1381 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1382 } else {
1383 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1384 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1385 }
80c39712
TV		 1386}
1387
f0e5caab 1388static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1389{
1390 u32 val;
87a7484b 1391 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1392
87a7484b
AT		 1393 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1394 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1395
1396 val = FLD_VAL(vaccu, vert_start, vert_end) |
1397 FLD_VAL(haccu, hor_start, hor_end);
1398
9b372c2d 1399 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1400}
1401
f0e5caab 1402static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1403{
1404 u32 val;
87a7484b 1405 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1406
87a7484b
AT		 1407 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1408 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1409
1410 val = FLD_VAL(vaccu, vert_start, vert_end) |
1411 FLD_VAL(haccu, hor_start, hor_end);
1412
9b372c2d 1413 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1414}
1415
f0e5caab
TV		 1416static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1417 int vaccu)
ab5ca071
AJ		 1418{
1419 u32 val;
1420
1421 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1422 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1423}
1424
f0e5caab
TV		 1425static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1426 int vaccu)
ab5ca071
AJ		 1427{
1428 u32 val;
1429
1430 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1431 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1432}
80c39712 1433
f0e5caab 1434static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1435 u16 orig_width, u16 orig_height,
1436 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1437 bool five_taps, u8 rotation,
1438 enum omap_color_component color_comp)
80c39712 1439{
0d66cbb5 1440 int fir_hinc, fir_vinc;
80c39712 1441
ed14a3ce
AJ		 1442 fir_hinc = 1024 * orig_width / out_width;
1443 fir_vinc = 1024 * orig_height / out_height;
80c39712 1444
debd9074
CM		 1445 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1446 color_comp);
f0e5caab 1447 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1448}
1449
05dd0f53
CM		 1450static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1451 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1452 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1453{
1454 int h_accu2_0, h_accu2_1;
1455 int v_accu2_0, v_accu2_1;
1456 int chroma_hinc, chroma_vinc;
1457 int idx;
1458
1459 struct accu {
1460 s8 h0_m, h0_n;
1461 s8 h1_m, h1_n;
1462 s8 v0_m, v0_n;
1463 s8 v1_m, v1_n;
1464 };
1465
1466 const struct accu *accu_table;
1467 const struct accu *accu_val;
1468
1469 static const struct accu accu_nv12[4] = {
1470 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1471 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1472 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1473 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1474 };
1475
1476 static const struct accu accu_nv12_ilace[4] = {
1477 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1478 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1479 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1480 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1481 };
1482
1483 static const struct accu accu_yuv[4] = {
1484 { 0, 1, 0, 1, 0, 1, 0, 1 },
1485 { 0, 1, 0, 1, 0, 1, 0, 1 },
1486 { -1, 1, 0, 1, 0, 1, 0, 1 },
1487 { 0, 1, 0, 1, -1, 1, 0, 1 },
1488 };
1489
1490 switch (rotation) {
1491 case OMAP_DSS_ROT_0:
1492 idx = 0;
1493 break;
1494 case OMAP_DSS_ROT_90:
1495 idx = 1;
1496 break;
1497 case OMAP_DSS_ROT_180:
1498 idx = 2;
1499 break;
1500 case OMAP_DSS_ROT_270:
1501 idx = 3;
1502 break;
1503 default:
1504 BUG();
c6eee968 1505 return;
05dd0f53
CM		 1506 }
1507
1508 switch (color_mode) {
1509 case OMAP_DSS_COLOR_NV12:
1510 if (ilace)
1511 accu_table = accu_nv12_ilace;
1512 else
1513 accu_table = accu_nv12;
1514 break;
1515 case OMAP_DSS_COLOR_YUV2:
1516 case OMAP_DSS_COLOR_UYVY:
1517 accu_table = accu_yuv;
1518 break;
1519 default:
1520 BUG();
c6eee968 1521 return;
05dd0f53
CM		 1522 }
1523
1524 accu_val = &accu_table[idx];
1525
1526 chroma_hinc = 1024 * orig_width / out_width;
1527 chroma_vinc = 1024 * orig_height / out_height;
1528
1529 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1530 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1531 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1532 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1533
1534 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1535 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1536}
1537
f0e5caab 1538static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1539 u16 orig_width, u16 orig_height,
1540 u16 out_width, u16 out_height,
1541 bool ilace, bool five_taps,
1542 bool fieldmode, enum omap_color_mode color_mode,
1543 u8 rotation)
1544{
1545 int accu0 = 0;
1546 int accu1 = 0;
1547 u32 l;
80c39712 1548
f0e5caab 1549 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1550 out_width, out_height, five_taps,
1551 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1552 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1553
87a7484b
AT		 1554 /* RESIZEENABLE and VERTICALTAPS */
1555 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1556 l |= (orig_width != out_width) ? (1 << 5) : 0;
1557 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1558 l |= five_taps ? (1 << 21) : 0;
80c39712 1559
87a7484b
AT		 1560 /* VRESIZECONF and HRESIZECONF */
1561 if (dss_has_feature(FEAT_RESIZECONF)) {
1562 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1563 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1564 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1565 }
80c39712 1566
87a7484b
AT		 1567 /* LINEBUFFERSPLIT */
1568 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1569 l &= ~(0x1 << 22);
1570 l |= five_taps ? (1 << 22) : 0;
1571 }
80c39712 1572
9b372c2d 1573 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1574
1575 /*
1576 * field 0 = even field = bottom field
1577 * field 1 = odd field = top field
1578 */
1579 if (ilace && !fieldmode) {
1580 accu1 = 0;
0d66cbb5 1581 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1582 if (accu0 >= 1024/2) {
1583 accu1 = 1024/2;
1584 accu0 -= accu1;
1585 }
1586 }
1587
f0e5caab
TV		 1588 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1589 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1590}
1591
f0e5caab 1592static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1593 u16 orig_width, u16 orig_height,
1594 u16 out_width, u16 out_height,
1595 bool ilace, bool five_taps,
1596 bool fieldmode, enum omap_color_mode color_mode,
1597 u8 rotation)
1598{
1599 int scale_x = out_width != orig_width;
1600 int scale_y = out_height != orig_height;
f92afae2 1601 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1602
1603 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1604 return;
1605 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1606 color_mode != OMAP_DSS_COLOR_UYVY &&
1607 color_mode != OMAP_DSS_COLOR_NV12)) {
1608 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1609 if (plane != OMAP_DSS_WB)
1610 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1611 return;
1612 }
36377357
TV		 1613
1614 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1615 out_height, ilace, color_mode, rotation);
1616
0d66cbb5
AJ		 1617 switch (color_mode) {
1618 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1619 if (chroma_upscale) {
1620 /* UV is subsampled by 2 horizontally and vertically */
1621 orig_height >>= 1;
1622 orig_width >>= 1;
1623 } else {
1624 /* UV is downsampled by 2 horizontally and vertically */
1625 orig_height <<= 1;
1626 orig_width <<= 1;
1627 }
1628
0d66cbb5
AJ		 1629 break;
1630 case OMAP_DSS_COLOR_YUV2:
1631 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1632 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1633 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1634 rotation == OMAP_DSS_ROT_180) {
1635 if (chroma_upscale)
1636 /* UV is subsampled by 2 horizontally */
1637 orig_width >>= 1;
1638 else
1639 /* UV is downsampled by 2 horizontally */
1640 orig_width <<= 1;
1641 }
1642
0d66cbb5
AJ		 1643 /* must use FIR for YUV422 if rotated */
1644 if (rotation != OMAP_DSS_ROT_0)
1645 scale_x = scale_y = true;
20fbb50b 1646
0d66cbb5
AJ		 1647 break;
1648 default:
1649 BUG();
c6eee968 1650 return;
0d66cbb5
AJ		 1651 }
1652
1653 if (out_width != orig_width)
1654 scale_x = true;
1655 if (out_height != orig_height)
1656 scale_y = true;
1657
f0e5caab 1658 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1659 out_width, out_height, five_taps,
1660 rotation, DISPC_COLOR_COMPONENT_UV);
1661
2a5561b1
AT		 1662 if (plane != OMAP_DSS_WB)
1663 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1664 (scale_x || scale_y) ? 1 : 0, 8, 8);
1665
0d66cbb5
AJ		 1666 /* set H scaling */
1667 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1668 /* set V scaling */
1669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1670}
1671
f0e5caab 1672static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1673 u16 orig_width, u16 orig_height,
1674 u16 out_width, u16 out_height,
1675 bool ilace, bool five_taps,
1676 bool fieldmode, enum omap_color_mode color_mode,
1677 u8 rotation)
1678{
1679 BUG_ON(plane == OMAP_DSS_GFX);
1680
f0e5caab 1681 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1682 orig_width, orig_height,
1683 out_width, out_height,
1684 ilace, five_taps,
1685 fieldmode, color_mode,
1686 rotation);
1687
f0e5caab 1688 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1689 orig_width, orig_height,
1690 out_width, out_height,
1691 ilace, five_taps,
1692 fieldmode, color_mode,
1693 rotation);
1694}
1695
f0e5caab 1696static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1697 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1698 bool mirroring, enum omap_color_mode color_mode)
1699{
87a7484b
AT		 1700 bool row_repeat = false;
1701 int vidrot = 0;
1702
80c39712
TV		 1703 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1704 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1705
1706 if (mirroring) {
1707 switch (rotation) {
1708 case OMAP_DSS_ROT_0:
1709 vidrot = 2;
1710 break;
1711 case OMAP_DSS_ROT_90:
1712 vidrot = 1;
1713 break;
1714 case OMAP_DSS_ROT_180:
1715 vidrot = 0;
1716 break;
1717 case OMAP_DSS_ROT_270:
1718 vidrot = 3;
1719 break;
1720 }
1721 } else {
1722 switch (rotation) {
1723 case OMAP_DSS_ROT_0:
1724 vidrot = 0;
1725 break;
1726 case OMAP_DSS_ROT_90:
1727 vidrot = 1;
1728 break;
1729 case OMAP_DSS_ROT_180:
1730 vidrot = 2;
1731 break;
1732 case OMAP_DSS_ROT_270:
1733 vidrot = 3;
1734 break;
1735 }
1736 }
1737
80c39712 1738 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1739 row_repeat = true;
80c39712 1740 else
87a7484b 1741 row_repeat = false;
80c39712 1742 }
87a7484b 1743
3397cc6a
TV		 1744 /*
1745 * OMAP4/5 Errata i631:
1746 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1747 * rows beyond the framebuffer, which may cause OCP error.
1748 */
1749 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1750 rotation_type != OMAP_DSS_ROT_TILER)
1751 vidrot = 1;
1752
9b372c2d 1753 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1754 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1755 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1756 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1757
1758 if (color_mode == OMAP_DSS_COLOR_NV12) {
1759 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1760 (rotation == OMAP_DSS_ROT_0 ||
1761 rotation == OMAP_DSS_ROT_180);
1762 /* DOUBLESTRIDE */
1763 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1764 }
1765
80c39712
TV		 1766}
1767
1768static int color_mode_to_bpp(enum omap_color_mode color_mode)
1769{
1770 switch (color_mode) {
1771 case OMAP_DSS_COLOR_CLUT1:
1772 return 1;
1773 case OMAP_DSS_COLOR_CLUT2:
1774 return 2;
1775 case OMAP_DSS_COLOR_CLUT4:
1776 return 4;
1777 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1778 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1779 return 8;
1780 case OMAP_DSS_COLOR_RGB12U:
1781 case OMAP_DSS_COLOR_RGB16:
1782 case OMAP_DSS_COLOR_ARGB16:
1783 case OMAP_DSS_COLOR_YUV2:
1784 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1785 case OMAP_DSS_COLOR_RGBA16:
1786 case OMAP_DSS_COLOR_RGBX16:
1787 case OMAP_DSS_COLOR_ARGB16_1555:
1788 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1789 return 16;
1790 case OMAP_DSS_COLOR_RGB24P:
1791 return 24;
1792 case OMAP_DSS_COLOR_RGB24U:
1793 case OMAP_DSS_COLOR_ARGB32:
1794 case OMAP_DSS_COLOR_RGBA32:
1795 case OMAP_DSS_COLOR_RGBX32:
1796 return 32;
1797 default:
1798 BUG();
c6eee968 1799 return 0;
80c39712
TV		 1800 }
1801}
1802
1803static s32 pixinc(int pixels, u8 ps)
1804{
1805 if (pixels == 1)
1806 return 1;
1807 else if (pixels > 1)
1808 return 1 + (pixels - 1) * ps;
1809 else if (pixels < 0)
1810 return 1 - (-pixels + 1) * ps;
1811 else
1812 BUG();
c6eee968 1813 return 0;
80c39712
TV		 1814}
1815
1816static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1817 u16 screen_width,
1818 u16 width, u16 height,
1819 enum omap_color_mode color_mode, bool fieldmode,
1820 unsigned int field_offset,
1821 unsigned *offset0, unsigned *offset1,
aed74b55 1822 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1823{
1824 u8 ps;
1825
1826 /* FIXME CLUT formats */
1827 switch (color_mode) {
1828 case OMAP_DSS_COLOR_CLUT1:
1829 case OMAP_DSS_COLOR_CLUT2:
1830 case OMAP_DSS_COLOR_CLUT4:
1831 case OMAP_DSS_COLOR_CLUT8:
1832 BUG();
1833 return;
1834 case OMAP_DSS_COLOR_YUV2:
1835 case OMAP_DSS_COLOR_UYVY:
1836 ps = 4;
1837 break;
1838 default:
1839 ps = color_mode_to_bpp(color_mode) / 8;
1840 break;
1841 }
1842
1843 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1844 width, height);
1845
1846 /*
1847 * field 0 = even field = bottom field
1848 * field 1 = odd field = top field
1849 */
1850 switch (rotation + mirror * 4) {
1851 case OMAP_DSS_ROT_0:
1852 case OMAP_DSS_ROT_180:
1853 /*
1854 * If the pixel format is YUV or UYVY divide the width
1855 * of the image by 2 for 0 and 180 degree rotation.
1856 */
1857 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1858 color_mode == OMAP_DSS_COLOR_UYVY)
1859 width = width >> 1;
1860 case OMAP_DSS_ROT_90:
1861 case OMAP_DSS_ROT_270:
1862 *offset1 = 0;
1863 if (field_offset)
1864 *offset0 = field_offset * screen_width * ps;
1865 else
1866 *offset0 = 0;
1867
aed74b55
CM		 1868 *row_inc = pixinc(1 +
1869 (y_predecim * screen_width - x_predecim * width) +
1870 (fieldmode ? screen_width : 0), ps);
1871 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1872 break;
1873
1874 case OMAP_DSS_ROT_0 + 4:
1875 case OMAP_DSS_ROT_180 + 4:
1876 /* If the pixel format is YUV or UYVY divide the width
1877 * of the image by 2 for 0 degree and 180 degree
1878 */
1879 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1880 color_mode == OMAP_DSS_COLOR_UYVY)
1881 width = width >> 1;
1882 case OMAP_DSS_ROT_90 + 4:
1883 case OMAP_DSS_ROT_270 + 4:
1884 *offset1 = 0;
1885 if (field_offset)
1886 *offset0 = field_offset * screen_width * ps;
1887 else
1888 *offset0 = 0;
aed74b55
CM		 1889 *row_inc = pixinc(1 -
1890 (y_predecim * screen_width + x_predecim * width) -
1891 (fieldmode ? screen_width : 0), ps);
1892 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1893 break;
1894
1895 default:
1896 BUG();
c6eee968 1897 return;
80c39712
TV		 1898 }
1899}
1900
1901static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1902 u16 screen_width,
1903 u16 width, u16 height,
1904 enum omap_color_mode color_mode, bool fieldmode,
1905 unsigned int field_offset,
1906 unsigned *offset0, unsigned *offset1,
aed74b55 1907 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1908{
1909 u8 ps;
1910 u16 fbw, fbh;
1911
1912 /* FIXME CLUT formats */
1913 switch (color_mode) {
1914 case OMAP_DSS_COLOR_CLUT1:
1915 case OMAP_DSS_COLOR_CLUT2:
1916 case OMAP_DSS_COLOR_CLUT4:
1917 case OMAP_DSS_COLOR_CLUT8:
1918 BUG();
1919 return;
1920 default:
1921 ps = color_mode_to_bpp(color_mode) / 8;
1922 break;
1923 }
1924
1925 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1926 width, height);
1927
1928 /* width & height are overlay sizes, convert to fb sizes */
1929
1930 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1931 fbw = width;
1932 fbh = height;
1933 } else {
1934 fbw = height;
1935 fbh = width;
1936 }
1937
1938 /*
1939 * field 0 = even field = bottom field
1940 * field 1 = odd field = top field
1941 */
1942 switch (rotation + mirror * 4) {
1943 case OMAP_DSS_ROT_0:
1944 *offset1 = 0;
1945 if (field_offset)
1946 *offset0 = *offset1 + field_offset * screen_width * ps;
1947 else
1948 *offset0 = *offset1;
aed74b55
CM		 1949 *row_inc = pixinc(1 +
1950 (y_predecim * screen_width - fbw * x_predecim) +
1951 (fieldmode ? screen_width : 0), ps);
1952 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1953 color_mode == OMAP_DSS_COLOR_UYVY)
1954 *pix_inc = pixinc(x_predecim, 2 * ps);
1955 else
1956 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1957 break;
1958 case OMAP_DSS_ROT_90:
1959 *offset1 = screen_width * (fbh - 1) * ps;
1960 if (field_offset)
1961 *offset0 = *offset1 + field_offset * ps;
1962 else
1963 *offset0 = *offset1;
aed74b55
CM		 1964 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1965 y_predecim + (fieldmode ? 1 : 0), ps);
1966 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1967 break;
1968 case OMAP_DSS_ROT_180:
1969 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1970 if (field_offset)
1971 *offset0 = *offset1 - field_offset * screen_width * ps;
1972 else
1973 *offset0 = *offset1;
1974 *row_inc = pixinc(-1 -
aed74b55
CM		 1975 (y_predecim * screen_width - fbw * x_predecim) -
1976 (fieldmode ? screen_width : 0), ps);
1977 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1978 color_mode == OMAP_DSS_COLOR_UYVY)
1979 *pix_inc = pixinc(-x_predecim, 2 * ps);
1980 else
1981 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1982 break;
1983 case OMAP_DSS_ROT_270:
1984 *offset1 = (fbw - 1) * ps;
1985 if (field_offset)
1986 *offset0 = *offset1 - field_offset * ps;
1987 else
1988 *offset0 = *offset1;
aed74b55
CM		 1989 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1990 y_predecim - (fieldmode ? 1 : 0), ps);
1991 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1992 break;
1993
1994 /* mirroring */
1995 case OMAP_DSS_ROT_0 + 4:
1996 *offset1 = (fbw - 1) * ps;
1997 if (field_offset)
1998 *offset0 = *offset1 + field_offset * screen_width * ps;
1999 else
2000 *offset0 = *offset1;
aed74b55 2001 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 2002 (fieldmode ? screen_width : 0),
2003 ps);
aed74b55
CM		 2004 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2005 color_mode == OMAP_DSS_COLOR_UYVY)
2006 *pix_inc = pixinc(-x_predecim, 2 * ps);
2007 else
2008 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2009 break;
2010
2011 case OMAP_DSS_ROT_90 + 4:
2012 *offset1 = 0;
2013 if (field_offset)
2014 *offset0 = *offset1 + field_offset * ps;
2015 else
2016 *offset0 = *offset1;
aed74b55
CM		 2017 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2018 y_predecim + (fieldmode ? 1 : 0),
80c39712 2019 ps);
aed74b55 2020 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2021 break;
2022
2023 case OMAP_DSS_ROT_180 + 4:
2024 *offset1 = screen_width * (fbh - 1) * ps;
2025 if (field_offset)
2026 *offset0 = *offset1 - field_offset * screen_width * ps;
2027 else
2028 *offset0 = *offset1;
aed74b55 2029 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 2030 (fieldmode ? screen_width : 0),
2031 ps);
aed74b55
CM		 2032 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2033 color_mode == OMAP_DSS_COLOR_UYVY)
2034 *pix_inc = pixinc(x_predecim, 2 * ps);
2035 else
2036 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2037 break;
2038
2039 case OMAP_DSS_ROT_270 + 4:
2040 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2041 if (field_offset)
2042 *offset0 = *offset1 - field_offset * ps;
2043 else
2044 *offset0 = *offset1;
aed74b55
CM		 2045 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2046 y_predecim - (fieldmode ? 1 : 0),
80c39712 2047 ps);
aed74b55 2048 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2049 break;
2050
2051 default:
2052 BUG();
c6eee968 2053 return;
80c39712
TV		 2054 }
2055}
2056
65e006ff
CM		 2057static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2058 enum omap_color_mode color_mode, bool fieldmode,
2059 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2060 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2061{
2062 u8 ps;
2063
2064 switch (color_mode) {
2065 case OMAP_DSS_COLOR_CLUT1:
2066 case OMAP_DSS_COLOR_CLUT2:
2067 case OMAP_DSS_COLOR_CLUT4:
2068 case OMAP_DSS_COLOR_CLUT8:
2069 BUG();
2070 return;
2071 default:
2072 ps = color_mode_to_bpp(color_mode) / 8;
2073 break;
2074 }
2075
2076 DSSDBG("scrw %d, width %d\n", screen_width, width);
2077
2078 /*
2079 * field 0 = even field = bottom field
2080 * field 1 = odd field = top field
2081 */
2082 *offset1 = 0;
2083 if (field_offset)
2084 *offset0 = *offset1 + field_offset * screen_width * ps;
2085 else
2086 *offset0 = *offset1;
2087 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2088 (fieldmode ? screen_width : 0), ps);
2089 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2090 color_mode == OMAP_DSS_COLOR_UYVY)
2091 *pix_inc = pixinc(x_predecim, 2 * ps);
2092 else
2093 *pix_inc = pixinc(x_predecim, ps);
2094}
2095
7faa9233
CM		 2096/*
2097 * This function is used to avoid synclosts in OMAP3, because of some
2098 * undocumented horizontal position and timing related limitations.
2099 */
465ec13f 2100static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2101 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2102 u16 width, u16 height, u16 out_width, u16 out_height,
2103 bool five_taps)
7faa9233 2104{
230edc03 2105 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2106 unsigned long nonactive;
7faa9233
CM		 2107 static const u8 limits[3] = { 8, 10, 20 };
2108 u64 val, blank;
2109 int i;
2110
81ab95b7 2111 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2112
2113 i = 0;
2114 if (out_height < height)
2115 i++;
2116 if (out_width < width)
2117 i++;
81ab95b7 2118 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2119 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2120 if (blank <= limits[i])
2121 return -EINVAL;
2122
e4998634
ID		 2123 /* FIXME add checks for 3-tap filter once the limitations are known */
2124 if (!five_taps)
2125 return 0;
2126
7faa9233
CM		 2127 /*
2128 * Pixel data should be prepared before visible display point starts.
2129 * So, atleast DS-2 lines must have already been fetched by DISPC
2130 * during nonactive - pos_x period.
2131 */
2132 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2133 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2134 val, max(0, ds - 2) * width);
2135 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2136 return -EINVAL;
2137
2138 /*
2139 * All lines need to be refilled during the nonactive period of which
2140 * only one line can be loaded during the active period. So, atleast
2141 * DS - 1 lines should be loaded during nonactive period.
2142 */
2143 val = div_u64((u64)nonactive * lclk, pclk);
2144 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2145 val, max(0, ds - 1) * width);
2146 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2147 return -EINVAL;
2148
2149 return 0;
2150}
2151
8702ee50 2152static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2153 const struct omap_video_timings *mgr_timings, u16 width,
2154 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2155 enum omap_color_mode color_mode)
80c39712 2156{
8b53d991 2157 u32 core_clk = 0;
3e8a6ff2 2158 u64 tmp;
80c39712 2159
7282f1b7
CM		 2160 if (height <= out_height && width <= out_width)
2161 return (unsigned long) pclk;
2162
80c39712 2163 if (height > out_height) {
81ab95b7 2164 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2165
2166 tmp = pclk * height * out_width;
2167 do_div(tmp, 2 * out_height * ppl);
8b53d991 2168 core_clk = tmp;
80c39712 2169
2d9c5597
VS		 2170 if (height > 2 * out_height) {
2171 if (ppl == out_width)
2172 return 0;
2173
80c39712
TV		 2174 tmp = pclk * (height - 2 * out_height) * out_width;
2175 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2176 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2177 }
2178 }
2179
2180 if (width > out_width) {
2181 tmp = pclk * width;
2182 do_div(tmp, out_width);
8b53d991 2183 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2184
2185 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2186 core_clk <<= 1;
80c39712
TV		 2187 }
2188
8b53d991 2189 return core_clk;
80c39712
TV		 2190}
2191
8702ee50 2192static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2193 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2194{
dcbe765b
CM		 2195 if (height > out_height && width > out_width)
2196 return pclk * 4;
2197 else
2198 return pclk * 2;
2199}
2200
8702ee50 2201static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2202 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2203{
2204 unsigned int hf, vf;
2205
2206 /*
2207 * FIXME how to determine the 'A' factor
2208 * for the no downscaling case ?
2209 */
2210
2211 if (width > 3 * out_width)
2212 hf = 4;
2213 else if (width > 2 * out_width)
2214 hf = 3;
2215 else if (width > out_width)
2216 hf = 2;
2217 else
2218 hf = 1;
80c39712
TV		 2219 if (height > out_height)
2220 vf = 2;
2221 else
2222 vf = 1;
2223
dcbe765b
CM		 2224 return pclk * vf * hf;
2225}
2226
8702ee50 2227static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2228 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2229{
8ba85306
AT		 2230 /*
2231 * If the overlay/writeback is in mem to mem mode, there are no
2232 * downscaling limitations with respect to pixel clock, return 1 as
2233 * required core clock to represent that we have sufficient enough
2234 * core clock to do maximum downscaling
2235 */
2236 if (mem_to_mem)
2237 return 1;
2238
dcbe765b
CM		 2239 if (width > out_width)
2240 return DIV_ROUND_UP(pclk, out_width) * width;
2241 else
2242 return pclk;
2243}
2244
0c6921de 2245static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2246 const struct omap_video_timings *mgr_timings,
2247 u16 width, u16 height, u16 out_width, u16 out_height,
2248 enum omap_color_mode color_mode, bool *five_taps,
2249 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2250 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2251{
2252 int error;
2253 u16 in_width, in_height;
2254 int min_factor = min(*decim_x, *decim_y);
2255 const int maxsinglelinewidth =
2256 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2257
dcbe765b
CM		 2258 *five_taps = false;
2259
2260 do {
eec77da2
TV		 2261 in_height = height / *decim_y;
2262 in_width = width / *decim_x;
8702ee50 2263 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2264 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2265 error = (in_width > maxsinglelinewidth || !*core_clk ||
2266 *core_clk > dispc_core_clk_rate());
2267 if (error) {
2268 if (*decim_x == *decim_y) {
2269 *decim_x = min_factor;
2270 ++*decim_y;
2271 } else {
2272 swap(*decim_x, *decim_y);
2273 if (*decim_x < *decim_y)
2274 ++*decim_x;
2275 }
2276 }
2277 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2278
2279 if (in_width > maxsinglelinewidth) {
2280 DSSERR("Cannot scale max input width exceeded");
2281 return -EINVAL;
2282 }
2283 return 0;
2284}
2285
0c6921de 2286static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2287 const struct omap_video_timings *mgr_timings,
2288 u16 width, u16 height, u16 out_width, u16 out_height,
2289 enum omap_color_mode color_mode, bool *five_taps,
2290 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2291 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2292{
2293 int error;
2294 u16 in_width, in_height;
2295 int min_factor = min(*decim_x, *decim_y);
2296 const int maxsinglelinewidth =
2297 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2298
2299 do {
eec77da2
TV		 2300 in_height = height / *decim_y;
2301 in_width = width / *decim_x;
e4998634 2302 *five_taps = in_height > out_height;
dcbe765b
CM		 2303
2304 if (in_width > maxsinglelinewidth)
2305 if (in_height > out_height &&
2306 in_height < out_height * 2)
2307 *five_taps = false;
e4998634
ID		 2308again:
2309 if (*five_taps)
2310 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2311 in_width, in_height, out_width,
2312 out_height, color_mode);
2313 else
8702ee50 2314 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2315 in_height, out_width, out_height,
2316 mem_to_mem);
dcbe765b 2317
e4998634
ID		 2318 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2319 pos_x, in_width, in_height, out_width,
2320 out_height, *five_taps);
2321 if (error && *five_taps) {
2322 *five_taps = false;
2323 goto again;
2324 }
2325
dcbe765b
CM		 2326 error = (error || in_width > maxsinglelinewidth * 2 ||
2327 (in_width > maxsinglelinewidth && *five_taps) ||
2328 !*core_clk || *core_clk > dispc_core_clk_rate());
ab6b2582
TV		 2329
2330 if (!error) {
2331 /* verify that we're inside the limits of scaler */
2332 if (in_width / 4 > out_width)
2333 error = 1;
2334
2335 if (*five_taps) {
2336 if (in_height / 4 > out_height)
2337 error = 1;
2338 } else {
2339 if (in_height / 2 > out_height)
2340 error = 1;
2341 }
2342 }
2343
dcbe765b
CM		 2344 if (error) {
2345 if (*decim_x == *decim_y) {
2346 *decim_x = min_factor;
2347 ++*decim_y;
2348 } else {
2349 swap(*decim_x, *decim_y);
2350 if (*decim_x < *decim_y)
2351 ++*decim_x;
2352 }
2353 }
2354 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2355
f5a73482
TV		 2356 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2357 in_height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2358 DSSERR("horizontal timing too tight\n");
2359 return -EINVAL;
7282f1b7 2360 }
dcbe765b
CM		 2361
2362 if (in_width > (maxsinglelinewidth * 2)) {
2363 DSSERR("Cannot setup scaling");
2364 DSSERR("width exceeds maximum width possible");
2365 return -EINVAL;
2366 }
2367
2368 if (in_width > maxsinglelinewidth && *five_taps) {
2369 DSSERR("cannot setup scaling with five taps");
2370 return -EINVAL;
2371 }
2372 return 0;
2373}
2374
0c6921de 2375static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2376 const struct omap_video_timings *mgr_timings,
2377 u16 width, u16 height, u16 out_width, u16 out_height,
2378 enum omap_color_mode color_mode, bool *five_taps,
2379 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2380 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2381{
2382 u16 in_width, in_width_max;
2383 int decim_x_min = *decim_x;
eec77da2 2384 u16 in_height = height / *decim_y;
dcbe765b
CM		 2385 const int maxsinglelinewidth =
2386 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2387 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2388
5d501085
AT		 2389 if (mem_to_mem) {
2390 in_width_max = out_width * maxdownscale;
2391 } else {
8ba85306
AT		 2392 in_width_max = dispc_core_clk_rate() /
2393 DIV_ROUND_UP(pclk, out_width);
5d501085 2394 }
dcbe765b 2395
dcbe765b
CM		 2396 *decim_x = DIV_ROUND_UP(width, in_width_max);
2397
2398 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2399 if (*decim_x > *x_predecim)
2400 return -EINVAL;
2401
2402 do {
eec77da2 2403 in_width = width / *decim_x;
dcbe765b
CM		 2404 } while (*decim_x <= *x_predecim &&
2405 in_width > maxsinglelinewidth && ++*decim_x);
2406
2407 if (in_width > maxsinglelinewidth) {
2408 DSSERR("Cannot scale width exceeds max line width");
2409 return -EINVAL;
2410 }
2411
8702ee50 2412 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2413 out_width, out_height, mem_to_mem);
dcbe765b 2414 return 0;
80c39712
TV		 2415}
2416
74e16458 2417static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2418 enum omap_overlay_caps caps,
81ab95b7
AT		 2419 const struct omap_video_timings *mgr_timings,
2420 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2421 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2422 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2423 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2424{
0373cac6 2425 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2426 const int max_decim_limit = 16;
8b53d991 2427 unsigned long core_clk = 0;
dcbe765b 2428 int decim_x, decim_y, ret;
79ad75f2 2429
f95cb5eb
TV		 2430 if (width == out_width && height == out_height)
2431 return 0;
2432
4e1d3ca0
TV		 2433 if (pclk == 0 || mgr_timings->pixelclock == 0) {
2434 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2435 return -EINVAL;
2436 }
2437
5b54ed3e 2438 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2439 return -EINVAL;
79ad75f2 2440
74e16458 2441 if (mem_to_mem) {
1c031441
AT		 2442 *x_predecim = *y_predecim = 1;
2443 } else {
2444 *x_predecim = max_decim_limit;
2445 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2446 dss_has_feature(FEAT_BURST_2D)) ?
2447 2 : max_decim_limit;
2448 }
aed74b55
CM		 2449
2450 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2451 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2452 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2453 color_mode == OMAP_DSS_COLOR_CLUT8) {
2454 *x_predecim = 1;
2455 *y_predecim = 1;
2456 *five_taps = false;
2457 return 0;
2458 }
2459
2460 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2461 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2462
aed74b55 2463 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2464 return -EINVAL;
2465
aed74b55 2466 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2467 return -EINVAL;
2468
0c6921de 2469 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2470 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2471 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2472 mem_to_mem);
dcbe765b
CM		 2473 if (ret)
2474 return ret;
79ad75f2 2475
8b53d991
CM		 2476 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2477 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2478
8b53d991 2479 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2480 DSSERR("failed to set up scaling, "
8b53d991
CM		 2481 "required core clk rate = %lu Hz, "
2482 "current core clk rate = %lu Hz\n",
2483 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2484 return -EINVAL;
2485 }
2486
aed74b55
CM		 2487 *x_predecim = decim_x;
2488 *y_predecim = decim_y;
79ad75f2
AT		 2489 return 0;
2490}
2491
f9b719b6
TV		 2492int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2493 const struct omap_overlay_info *oi,
2494 const struct omap_video_timings *timings,
2495 int *x_predecim, int *y_predecim)
2496{
2497 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2498 bool five_taps = true;
62a83183 2499 bool fieldmode = false;
f9b719b6
TV		 2500 u16 in_height = oi->height;
2501 u16 in_width = oi->width;
2502 bool ilace = timings->interlace;
2503 u16 out_width, out_height;
2504 int pos_x = oi->pos_x;
2505 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2506 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2507
2508 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2509 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2510
2511 if (ilace && oi->height == out_height)
62a83183 2512 fieldmode = true;
f9b719b6
TV		 2513
2514 if (ilace) {
2515 if (fieldmode)
2516 in_height /= 2;
2517 out_height /= 2;
2518
2519 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2520 in_height, out_height);
2521 }
2522
2523 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2524 return -EINVAL;
2525
2526 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2527 in_height, out_width, out_height, oi->color_mode,
2528 &five_taps, x_predecim, y_predecim, pos_x,
2529 oi->rotation_type, false);
2530}
348be69d 2531EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2532
84a880fd 2533static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2534 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2535 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2536 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2537 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2538 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2539 bool replication, const struct omap_video_timings *mgr_timings,
2540 bool mem_to_mem)
80c39712 2541{
7282f1b7 2542 bool five_taps = true;
62a83183 2543 bool fieldmode = false;
79ad75f2 2544 int r, cconv = 0;
80c39712
TV		 2545 unsigned offset0, offset1;
2546 s32 row_inc;
2547 s32 pix_inc;
6be0d73e 2548 u16 frame_width, frame_height;
80c39712 2549 unsigned int field_offset = 0;
84a880fd
AT		 2550 u16 in_height = height;
2551 u16 in_width = width;
aed74b55 2552 int x_predecim = 1, y_predecim = 1;
8050cbe4 2553 bool ilace = mgr_timings->interlace;
74e16458
TV		 2554 unsigned long pclk = dispc_plane_pclk_rate(plane);
2555 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2556
e566658f 2557 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2558 return -EINVAL;
2559
c4661b33
TV		 2560 switch (color_mode) {
2561 case OMAP_DSS_COLOR_YUV2:
2562 case OMAP_DSS_COLOR_UYVY:
2563 case OMAP_DSS_COLOR_NV12:
2564 if (in_width & 1) {
2565 DSSERR("input width %d is not even for YUV format\n",
2566 in_width);
2567 return -EINVAL;
2568 }
2569 break;
2570
2571 default:
2572 break;
2573 }
2574
84a880fd
AT		 2575 out_width = out_width == 0 ? width : out_width;
2576 out_height = out_height == 0 ? height : out_height;
cf073668 2577
84a880fd 2578 if (ilace && height == out_height)
62a83183 2579 fieldmode = true;
80c39712
TV		 2580
2581 if (ilace) {
2582 if (fieldmode)
aed74b55 2583 in_height /= 2;
8eeb7019 2584 pos_y /= 2;
aed74b55 2585 out_height /= 2;
80c39712
TV		 2586
2587 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2588 "out_height %d\n", in_height, pos_y,
2589 out_height);
80c39712
TV		 2590 }
2591
84a880fd 2592 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2593 return -EINVAL;
2594
74e16458 2595 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2596 in_height, out_width, out_height, color_mode,
2597 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2598 rotation_type, mem_to_mem);
79ad75f2
AT		 2599 if (r)
2600 return r;
80c39712 2601
eec77da2
TV		 2602 in_width = in_width / x_predecim;
2603 in_height = in_height / y_predecim;
aed74b55 2604
c4661b33
TV		 2605 if (x_predecim > 1 || y_predecim > 1)
2606 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2607 x_predecim, y_predecim, in_width, in_height);
2608
2609 switch (color_mode) {
2610 case OMAP_DSS_COLOR_YUV2:
2611 case OMAP_DSS_COLOR_UYVY:
2612 case OMAP_DSS_COLOR_NV12:
2613 if (in_width & 1) {
2614 DSSDBG("predecimated input width is not even for YUV format\n");
2615 DSSDBG("adjusting input width %d -> %d\n",
2616 in_width, in_width & ~1);
2617
2618 in_width &= ~1;
2619 }
2620 break;
2621
2622 default:
2623 break;
2624 }
2625
84a880fd
AT		 2626 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2627 color_mode == OMAP_DSS_COLOR_UYVY ||
2628 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2629 cconv = 1;
80c39712
TV		 2630
2631 if (ilace && !fieldmode) {
2632 /*
2633 * when downscaling the bottom field may have to start several
2634 * source lines below the top field. Unfortunately ACCUI
2635 * registers will only hold the fractional part of the offset
2636 * so the integer part must be added to the base address of the
2637 * bottom field.
2638 */
aed74b55 2639 if (!in_height || in_height == out_height)
80c39712
TV		 2640 field_offset = 0;
2641 else
aed74b55 2642 field_offset = in_height / out_height / 2;
80c39712
TV		 2643 }
2644
2645 /* Fields are independent but interleaved in memory. */
2646 if (fieldmode)
2647 field_offset = 1;
2648
c6eee968
TV		 2649 offset0 = 0;
2650 offset1 = 0;
2651 row_inc = 0;
2652 pix_inc = 0;
2653
6be0d73e
AT		 2654 if (plane == OMAP_DSS_WB) {
2655 frame_width = out_width;
2656 frame_height = out_height;
2657 } else {
2658 frame_width = in_width;
2659 frame_height = height;
2660 }
2661
84a880fd 2662 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2663 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2664 color_mode, fieldmode, field_offset,
65e006ff
CM		 2665 &offset0, &offset1, &row_inc, &pix_inc,
2666 x_predecim, y_predecim);
84a880fd 2667 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2668 calc_dma_rotation_offset(rotation, mirror, screen_width,
2669 frame_width, frame_height,
84a880fd 2670 color_mode, fieldmode, field_offset,
aed74b55
CM		 2671 &offset0, &offset1, &row_inc, &pix_inc,
2672 x_predecim, y_predecim);
80c39712 2673 else
84a880fd 2674 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2675 screen_width, frame_width, frame_height,
84a880fd 2676 color_mode, fieldmode, field_offset,
aed74b55
CM		 2677 &offset0, &offset1, &row_inc, &pix_inc,
2678 x_predecim, y_predecim);
80c39712
TV		 2679
2680 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2681 offset0, offset1, row_inc, pix_inc);
2682
84a880fd 2683 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2684
84a880fd 2685 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2686
84a880fd
AT		 2687 dispc_ovl_set_ba0(plane, paddr + offset0);
2688 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2689
84a880fd
AT		 2690 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2691 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2692 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2693 }
2694
f0e5caab
TV		 2695 dispc_ovl_set_row_inc(plane, row_inc);
2696 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2697
84a880fd 2698 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2699 in_height, out_width, out_height);
80c39712 2700
84a880fd 2701 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2702
78b687fc 2703 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2704
5b54ed3e 2705 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2706 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2707 out_height, ilace, five_taps, fieldmode,
84a880fd 2708 color_mode, rotation);
78b687fc 2709 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2710 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2711 }
2712
c35eeb2e
AT		 2713 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2714 color_mode);
80c39712 2715
84a880fd
AT		 2716 dispc_ovl_set_zorder(plane, caps, zorder);
2717 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2718 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2719
d79db853 2720 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2721
80c39712
TV		 2722 return 0;
2723}
2724
84a880fd 2725int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2726 bool replication, const struct omap_video_timings *mgr_timings,
2727 bool mem_to_mem)
84a880fd
AT		 2728{
2729 int r;
16bf20c7 2730 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2731 enum omap_channel channel;
2732
2733 channel = dispc_ovl_get_channel_out(plane);
2734
24f13a66
AB		 2735 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2736 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2737 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd
AT		 2738 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2739 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2740
16bf20c7 2741 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2742 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2743 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2744 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2745 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2746
2747 return r;
2748}
348be69d 2749EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2750
749feffa 2751int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2752 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2753{
2754 int r;
9e4a0fc7 2755 u32 l;
749feffa
AT		 2756 enum omap_plane plane = OMAP_DSS_WB;
2757 const int pos_x = 0, pos_y = 0;
2758 const u8 zorder = 0, global_alpha = 0;
2759 const bool replication = false;
9e4a0fc7 2760 bool truncation;
749feffa
AT		 2761 int in_width = mgr_timings->x_res;
2762 int in_height = mgr_timings->y_res;
2763 enum omap_overlay_caps caps =
2764 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2765
2766 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2767 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2768 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2769 wi->mirror);
2770
2771 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2772 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2773 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2774 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2775 replication, mgr_timings, mem_to_mem);
2776
2777 switch (wi->color_mode) {
2778 case OMAP_DSS_COLOR_RGB16:
2779 case OMAP_DSS_COLOR_RGB24P:
2780 case OMAP_DSS_COLOR_ARGB16:
2781 case OMAP_DSS_COLOR_RGBA16:
2782 case OMAP_DSS_COLOR_RGB12U:
2783 case OMAP_DSS_COLOR_ARGB16_1555:
2784 case OMAP_DSS_COLOR_XRGB16_1555:
2785 case OMAP_DSS_COLOR_RGBX16:
2786 truncation = true;
2787 break;
2788 default:
2789 truncation = false;
2790 break;
2791 }
2792
2793 /* setup extra DISPC_WB_ATTRIBUTES */
2794 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2795 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2796 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2797 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2798
2799 return r;
2800}
2801
f0e5caab 2802int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2803{
e6d80f95
TV		 2804 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2805
9b372c2d 2806 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2807
2808 return 0;
80c39712 2809}
348be69d 2810EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2811
04bd8ac1
TV		 2812bool dispc_ovl_enabled(enum omap_plane plane)
2813{
2814 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2815}
348be69d 2816EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2817
f1a813d3 2818void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2819{
efa70b3b
CM		 2820 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2821 /* flush posted write */
2822 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2823}
348be69d 2824EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2825
65398511
TV		 2826bool dispc_mgr_is_enabled(enum omap_channel channel)
2827{
2828 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2829}
348be69d 2830EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2831
0b23e5b8
AT		 2832void dispc_wb_enable(bool enable)
2833{
916188a4 2834 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2835}
2836
2837bool dispc_wb_is_enabled(void)
2838{
916188a4 2839 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2840}
2841
fb2cec1f 2842static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2843{
6ced40bf
AT		 2844 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2845 return;
2846
80c39712 2847 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2848}
2849
2850void dispc_lcd_enable_signal(bool enable)
2851{
6ced40bf
AT		 2852 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2853 return;
2854
80c39712 2855 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2856}
2857
2858void dispc_pck_free_enable(bool enable)
2859{
6ced40bf
AT		 2860 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2861 return;
2862
80c39712 2863 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2864}
2865
fb2cec1f 2866static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2867{
efa70b3b 2868 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2869}
2870
2871
fb2cec1f 2872static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2873{
d21f43bc 2874 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2875}
2876
2877void dispc_set_loadmode(enum omap_dss_load_mode mode)
2878{
80c39712 2879 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2880}
2881
2882
c64dca40 2883static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2884{
8613b000 2885 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2886}
2887
c64dca40 2888static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2889 enum omap_dss_trans_key_type type,
2890 u32 trans_key)
2891{
efa70b3b 2892 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2893
8613b000 2894 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2895}
2896
c64dca40 2897static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2898{
efa70b3b 2899 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2900}
11354dd5 2901
c64dca40
TV		 2902static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2903 bool enable)
80c39712 2904{
11354dd5 2905 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2906 return;
2907
80c39712
TV		 2908 if (ch == OMAP_DSS_CHANNEL_LCD)
2909 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2910 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2911 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2912}
11354dd5 2913
c64dca40 2914void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2915 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2916{
2917 dispc_mgr_set_default_color(channel, info->default_color);
2918 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2919 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2920 dispc_mgr_enable_alpha_fixed_zorder(channel,
2921 info->partial_alpha_enabled);
2922 if (dss_has_feature(FEAT_CPR)) {
2923 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2924 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2925 }
2926}
348be69d 2927EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2928
fb2cec1f 2929static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2930{
2931 int code;
2932
2933 switch (data_lines) {
2934 case 12:
2935 code = 0;
2936 break;
2937 case 16:
2938 code = 1;
2939 break;
2940 case 18:
2941 code = 2;
2942 break;
2943 case 24:
2944 code = 3;
2945 break;
2946 default:
2947 BUG();
2948 return;
2949 }
2950
efa70b3b 2951 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2952}
2953
fb2cec1f 2954static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2955{
2956 u32 l;
569969d6 2957 int gpout0, gpout1;
80c39712
TV		 2958
2959 switch (mode) {
569969d6
AT		 2960 case DSS_IO_PAD_MODE_RESET:
2961 gpout0 = 0;
2962 gpout1 = 0;
80c39712 2963 break;
569969d6
AT		 2964 case DSS_IO_PAD_MODE_RFBI:
2965 gpout0 = 1;
80c39712
TV		 2966 gpout1 = 0;
2967 break;
569969d6
AT		 2968 case DSS_IO_PAD_MODE_BYPASS:
2969 gpout0 = 1;
80c39712
TV		 2970 gpout1 = 1;
2971 break;
80c39712
TV		 2972 default:
2973 BUG();
2974 return;
2975 }
2976
569969d6
AT		 2977 l = dispc_read_reg(DISPC_CONTROL);
2978 l = FLD_MOD(l, gpout0, 15, 15);
2979 l = FLD_MOD(l, gpout1, 16, 16);
2980 dispc_write_reg(DISPC_CONTROL, l);
2981}
2982
fb2cec1f 2983static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2984{
efa70b3b 2985 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2986}
2987
fb2cec1f
TV		 2988void dispc_mgr_set_lcd_config(enum omap_channel channel,
2989 const struct dss_lcd_mgr_config *config)
2990{
2991 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2992
2993 dispc_mgr_enable_stallmode(channel, config->stallmode);
2994 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2995
2996 dispc_mgr_set_clock_div(channel, &config->clock_info);
2997
2998 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2999
3000 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3001
3002 dispc_mgr_set_lcd_type_tft(channel);
3003}
348be69d 3004EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 3005
8f366162
AT		 3006static bool _dispc_mgr_size_ok(u16 width, u16 height)
3007{
33b89928
AT		 3008 return width <= dispc.feat->mgr_width_max &&
3009 height <= dispc.feat->mgr_height_max;
8f366162
AT		 3010}
3011
80c39712
TV		 3012static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3013 int vsw, int vfp, int vbp)
3014{
dcbe765b
CM		 3015 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3016 hfp < 1 || hfp > dispc.feat->hp_max ||
3017 hbp < 1 || hbp > dispc.feat->hp_max ||
3018 vsw < 1 || vsw > dispc.feat->sw_max ||
3019 vfp < 0 || vfp > dispc.feat->vp_max ||
3020 vbp < 0 || vbp > dispc.feat->vp_max)
3021 return false;
80c39712
TV		 3022 return true;
3023}
3024
ca5ca69c
AT		 3025static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3026 unsigned long pclk)
3027{
3028 if (dss_mgr_is_lcd(channel))
3029 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3030 else
3031 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3032}
3033
8f366162 3034bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 3035 const struct omap_video_timings *timings)
80c39712 3036{
eadd33bb
TV		 3037 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3038 return false;
8f366162 3039
eadd33bb
TV		 3040 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3041 return false;
ca5ca69c
AT		 3042
3043 if (dss_mgr_is_lcd(channel)) {
beb8384d 3044 /* TODO: OMAP4+ supports interlace for LCD outputs */
eadd33bb
TV		 3045 if (timings->interlace)
3046 return false;
beb8384d 3047
eadd33bb 3048 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
ca5ca69c 3049 timings->hbp, timings->vsw, timings->vfp,
eadd33bb
TV		 3050 timings->vbp))
3051 return false;
ca5ca69c 3052 }
8f366162 3053
eadd33bb 3054 return true;
80c39712
TV		 3055}
3056
26d9dd0d 3057static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3058 int hfp, int hbp, int vsw, int vfp, int vbp,
3059 enum omap_dss_signal_level vsync_level,
3060 enum omap_dss_signal_level hsync_level,
3061 enum omap_dss_signal_edge data_pclk_edge,
3062 enum omap_dss_signal_level de_level,
3063 enum omap_dss_signal_edge sync_pclk_edge)
3064
80c39712 3065{
655e2941 3066 u32 timing_h, timing_v, l;
ed351881 3067 bool onoff, rf, ipc, vs, hs, de;
80c39712 3068
dcbe765b
CM		 3069 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3070 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3071 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3072 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3073 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3074 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3075
64ba4f74
SS		 3076 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3077 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 3078
ed351881
TV		 3079 switch (vsync_level) {
3080 case OMAPDSS_SIG_ACTIVE_LOW:
3081 vs = true;
3082 break;
3083 case OMAPDSS_SIG_ACTIVE_HIGH:
3084 vs = false;
3085 break;
3086 default:
3087 BUG();
3088 }
3089
3090 switch (hsync_level) {
3091 case OMAPDSS_SIG_ACTIVE_LOW:
3092 hs = true;
3093 break;
3094 case OMAPDSS_SIG_ACTIVE_HIGH:
3095 hs = false;
3096 break;
3097 default:
3098 BUG();
3099 }
3100
3101 switch (de_level) {
3102 case OMAPDSS_SIG_ACTIVE_LOW:
3103 de = true;
3104 break;
3105 case OMAPDSS_SIG_ACTIVE_HIGH:
3106 de = false;
3107 break;
3108 default:
3109 BUG();
3110 }
3111
655e2941
AT		 3112 switch (data_pclk_edge) {
3113 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3114 ipc = false;
3115 break;
3116 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3117 ipc = true;
3118 break;
655e2941
AT		 3119 default:
3120 BUG();
3121 }
3122
7a16360d
TV		 3123 /* always use the 'rf' setting */
3124 onoff = true;
3125
655e2941 3126 switch (sync_pclk_edge) {
655e2941 3127 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
655e2941
AT		 3128 rf = false;
3129 break;
3130 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
655e2941
AT		 3131 rf = true;
3132 break;
3133 default:
3134 BUG();
cf6ac4ce 3135 }
655e2941 3136
d80e02ef
TV		 3137 l = FLD_VAL(onoff, 17, 17) |
3138 FLD_VAL(rf, 16, 16) |
ed351881 3139 FLD_VAL(de, 15, 15) |
d80e02ef 3140 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 3141 FLD_VAL(hs, 13, 13) |
3142 FLD_VAL(vs, 12, 12);
d80e02ef 3143
655e2941 3144 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 3145
3146 if (dispc.syscon_pol) {
3147 const int shifts[] = {
3148 [OMAP_DSS_CHANNEL_LCD] = 0,
3149 [OMAP_DSS_CHANNEL_LCD2] = 1,
3150 [OMAP_DSS_CHANNEL_LCD3] = 2,
3151 };
3152
3153 u32 mask, val;
3154
3155 mask = (1 << 0) | (1 << 3) | (1 << 6);
3156 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3157
3158 mask <<= 16 + shifts[channel];
3159 val <<= 16 + shifts[channel];
3160
3161 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3162 mask, val);
3163 }
80c39712
TV		 3164}
3165
3166/* change name to mode? */
c51d921a 3167void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3168 const struct omap_video_timings *timings)
80c39712
TV		 3169{
3170 unsigned xtot, ytot;
3171 unsigned long ht, vt;
2aefad49 3172 struct omap_video_timings t = *timings;
80c39712 3173
2aefad49 3174 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3175
2aefad49 3176 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3177 BUG();
c6eee968
TV		 3178 return;
3179 }
80c39712 3180
dd88b7a6 3181 if (dss_mgr_is_lcd(channel)) {
2aefad49 3182 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3183 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3184 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3185
2aefad49
AT		 3186 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3187 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3188
d8d78941
TV		 3189 ht = timings->pixelclock / xtot;
3190 vt = timings->pixelclock / xtot / ytot;
c51d921a 3191
d8d78941 3192 DSSDBG("pck %u\n", timings->pixelclock);
c51d921a 3193 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3194 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3195 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3196 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3197 t.de_level, t.sync_pclk_edge);
80c39712 3198
c51d921a 3199 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3200 } else {
23c8f88e 3201 if (t.interlace == true)
2aefad49 3202 t.y_res /= 2;
c51d921a 3203 }
8f366162 3204
2aefad49 3205 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 3206}
348be69d 3207EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3208
26d9dd0d 3209static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3210 u16 pck_div)
80c39712
TV		 3211{
3212 BUG_ON(lck_div < 1);
9eaaf207 3213 BUG_ON(pck_div < 1);
80c39712 3214
ce7fa5eb 3215 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3216 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 3217
3218 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3219 channel == OMAP_DSS_CHANNEL_LCD)
3220 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3221}
3222
26d9dd0d 3223static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3224 int *pck_div)
80c39712
TV		 3225{
3226 u32 l;
ce7fa5eb 3227 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3228 *lck_div = FLD_GET(l, 23, 16);
3229 *pck_div = FLD_GET(l, 7, 0);
3230}
3231
3232unsigned long dispc_fclk_rate(void)
3233{
2daea7af 3234 struct dss_pll *pll;
80c39712
TV		 3235 unsigned long r = 0;
3236
66534e8e 3237 switch (dss_get_dispc_clk_source()) {
89a35e51 3238 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3239 r = dss_get_dispc_clk_rate();
66534e8e 3240 break;
89a35e51 3241 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3242 pll = dss_pll_find("dsi0");
93550927
TV		 3243 if (!pll)
3244 pll = dss_pll_find("video0");
3245
2daea7af 3246 r = pll->cinfo.clkout[0];
66534e8e 3247 break;
5a8b572d 3248 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3249 pll = dss_pll_find("dsi1");
93550927
TV		 3250 if (!pll)
3251 pll = dss_pll_find("video1");
3252
2daea7af 3253 r = pll->cinfo.clkout[0];
5a8b572d 3254 break;
66534e8e
TA		 3255 default:
3256 BUG();
c6eee968 3257 return 0;
66534e8e
TA		 3258 }
3259
80c39712
TV		 3260 return r;
3261}
3262
26d9dd0d 3263unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3264{
2daea7af 3265 struct dss_pll *pll;
80c39712
TV		 3266 int lcd;
3267 unsigned long r;
3268 u32 l;
3269
c31cba8a
TV		 3270 if (dss_mgr_is_lcd(channel)) {
3271 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3272
c31cba8a 3273 lcd = FLD_GET(l, 23, 16);
80c39712 3274
c31cba8a
TV		 3275 switch (dss_get_lcd_clk_source(channel)) {
3276 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3277 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3278 break;
3279 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3280 pll = dss_pll_find("dsi0");
93550927
TV		 3281 if (!pll)
3282 pll = dss_pll_find("video0");
3283
2daea7af 3284 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3285 break;
3286 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3287 pll = dss_pll_find("dsi1");
93550927
TV		 3288 if (!pll)
3289 pll = dss_pll_find("video1");
3290
2daea7af 3291 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3292 break;
3293 default:
3294 BUG();
3295 return 0;
3296 }
80c39712 3297
c31cba8a
TV		 3298 return r / lcd;
3299 } else {
3300 return dispc_fclk_rate();
3301 }
80c39712
TV		 3302}
3303
26d9dd0d 3304unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3305{
80c39712 3306 unsigned long r;
80c39712 3307
dd88b7a6 3308 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3309 int pcd;
3310 u32 l;
80c39712 3311
c3dc6a7a 3312 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3313
c3dc6a7a 3314 pcd = FLD_GET(l, 7, 0);
80c39712 3315
c3dc6a7a
AT		 3316 r = dispc_mgr_lclk_rate(channel);
3317
3318 return r / pcd;
3319 } else {
5391e87d 3320 return dispc.tv_pclk_rate;
c3dc6a7a 3321 }
80c39712
TV		 3322}
3323
5391e87d
TV		 3324void dispc_set_tv_pclk(unsigned long pclk)
3325{
3326 dispc.tv_pclk_rate = pclk;
3327}
3328
8b53d991
CM		 3329unsigned long dispc_core_clk_rate(void)
3330{
7b3926b3 3331 return dispc.core_clk_rate;
8b53d991
CM		 3332}
3333
3e8a6ff2
AT		 3334static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3335{
251886d8
TV		 3336 enum omap_channel channel;
3337
3338 if (plane == OMAP_DSS_WB)
3339 return 0;
3340
3341 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3342
3343 return dispc_mgr_pclk_rate(channel);
3344}
3345
3346static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3347{
251886d8
TV		 3348 enum omap_channel channel;
3349
3350 if (plane == OMAP_DSS_WB)
3351 return 0;
3352
3353 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3354
c31cba8a 3355 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3356}
c31cba8a 3357
6f1891fc 3358static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3359{
3360 int lcd, pcd;
6f1891fc
CM		 3361 enum omap_dss_clk_source lcd_clk_src;
3362
3363 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3364
3365 lcd_clk_src = dss_get_lcd_clk_source(channel);
3366
3367 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3368 dss_get_generic_clk_source_name(lcd_clk_src),
3369 dss_feat_get_clk_source_name(lcd_clk_src));
3370
3371 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3372
3373 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3374 dispc_mgr_lclk_rate(channel), lcd);
3375 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3376 dispc_mgr_pclk_rate(channel), pcd);
3377}
3378
3379void dispc_dump_clocks(struct seq_file *s)
3380{
3381 int lcd;
0cf35df3 3382 u32 l;
89a35e51 3383 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3384
4fbafaf3
TV		 3385 if (dispc_runtime_get())
3386 return;
80c39712 3387
80c39712
TV		 3388 seq_printf(s, "- DISPC -\n");
3389
067a57e4
AT		 3390 seq_printf(s, "dispc fclk source = %s (%s)\n",
3391 dss_get_generic_clk_source_name(dispc_clk_src),
3392 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3393
3394 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3395
0cf35df3
MR		 3396 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3397 seq_printf(s, "- DISPC-CORE-CLK -\n");
3398 l = dispc_read_reg(DISPC_DIVISOR);
3399 lcd = FLD_GET(l, 23, 16);
3400
3401 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3402 (dispc_fclk_rate()/lcd), lcd);
3403 }
2a205f34 3404
6f1891fc 3405 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3406
6f1891fc
CM		 3407 if (dss_has_feature(FEAT_MGR_LCD2))
3408 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3409 if (dss_has_feature(FEAT_MGR_LCD3))
3410 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3411
3412 dispc_runtime_put();
80c39712
TV		 3413}
3414
e40402cf 3415static void dispc_dump_regs(struct seq_file *s)
80c39712 3416{
4dd2da15
AT		 3417 int i, j;
3418 const char *mgr_names[] = {
3419 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3420 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3421 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3422 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3423 };
3424 const char *ovl_names[] = {
3425 [OMAP_DSS_GFX] = "GFX",
3426 [OMAP_DSS_VIDEO1] = "VID1",
3427 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3428 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3429 };
3430 const char **p_names;
3431
9b372c2d 3432#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3433
4fbafaf3
TV		 3434 if (dispc_runtime_get())
3435 return;
80c39712 3436
5010be80 3437 /* DISPC common registers */
80c39712
TV		 3438 DUMPREG(DISPC_REVISION);
3439 DUMPREG(DISPC_SYSCONFIG);
3440 DUMPREG(DISPC_SYSSTATUS);
3441 DUMPREG(DISPC_IRQSTATUS);
3442 DUMPREG(DISPC_IRQENABLE);
3443 DUMPREG(DISPC_CONTROL);
3444 DUMPREG(DISPC_CONFIG);
3445 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3446 DUMPREG(DISPC_LINE_STATUS);
3447 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3448 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3449 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3450 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3451 if (dss_has_feature(FEAT_MGR_LCD2)) {
3452 DUMPREG(DISPC_CONTROL2);
3453 DUMPREG(DISPC_CONFIG2);
5010be80 3454 }
6f1891fc
CM		 3455 if (dss_has_feature(FEAT_MGR_LCD3)) {
3456 DUMPREG(DISPC_CONTROL3);
3457 DUMPREG(DISPC_CONFIG3);
3458 }
29fceeeb
TV		 3459 if (dss_has_feature(FEAT_MFLAG))
3460 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3461
3462#undef DUMPREG
3463
3464#define DISPC_REG(i, name) name(i)
4dd2da15 3465#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3466 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3467 dispc_read_reg(DISPC_REG(i, r)))
3468
4dd2da15 3469 p_names = mgr_names;
5010be80 3470
4dd2da15
AT		 3471 /* DISPC channel specific registers */
3472 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3473 DUMPREG(i, DISPC_DEFAULT_COLOR);
3474 DUMPREG(i, DISPC_TRANS_COLOR);
3475 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3476
4dd2da15
AT		 3477 if (i == OMAP_DSS_CHANNEL_DIGIT)
3478 continue;
5010be80 3479
4dd2da15
AT		 3480 DUMPREG(i, DISPC_TIMING_H);
3481 DUMPREG(i, DISPC_TIMING_V);
3482 DUMPREG(i, DISPC_POL_FREQ);
3483 DUMPREG(i, DISPC_DIVISORo);
5010be80 3484
4dd2da15
AT		 3485 DUMPREG(i, DISPC_DATA_CYCLE1);
3486 DUMPREG(i, DISPC_DATA_CYCLE2);
3487 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3488
332e9d70 3489 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3490 DUMPREG(i, DISPC_CPR_COEF_R);
3491 DUMPREG(i, DISPC_CPR_COEF_G);
3492 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3493 }
2a205f34 3494 }
80c39712 3495
4dd2da15
AT		 3496 p_names = ovl_names;
3497
3498 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3499 DUMPREG(i, DISPC_OVL_BA0);
3500 DUMPREG(i, DISPC_OVL_BA1);
3501 DUMPREG(i, DISPC_OVL_POSITION);
3502 DUMPREG(i, DISPC_OVL_SIZE);
3503 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3504 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3505 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3506 DUMPREG(i, DISPC_OVL_ROW_INC);
3507 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3508
4dd2da15
AT		 3509 if (dss_has_feature(FEAT_PRELOAD))
3510 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3511 if (dss_has_feature(FEAT_MFLAG))
3512 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3513
3514 if (i == OMAP_DSS_GFX) {
3515 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3516 DUMPREG(i, DISPC_OVL_TABLE_BA);
3517 continue;
3518 }
3519
3520 DUMPREG(i, DISPC_OVL_FIR);
3521 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3522 DUMPREG(i, DISPC_OVL_ACCU0);
3523 DUMPREG(i, DISPC_OVL_ACCU1);
3524 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3525 DUMPREG(i, DISPC_OVL_BA0_UV);
3526 DUMPREG(i, DISPC_OVL_BA1_UV);
3527 DUMPREG(i, DISPC_OVL_FIR2);
3528 DUMPREG(i, DISPC_OVL_ACCU2_0);
3529 DUMPREG(i, DISPC_OVL_ACCU2_1);
3530 }
3531 if (dss_has_feature(FEAT_ATTR2))
3532 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3533 }
5010be80
AT		 3534
3535#undef DISPC_REG
3536#undef DUMPREG
3537
3538#define DISPC_REG(plane, name, i) name(plane, i)
3539#define DUMPREG(plane, name, i) \
4dd2da15 3540 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3541 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3542 dispc_read_reg(DISPC_REG(plane, name, i)))
3543
4dd2da15 3544 /* Video pipeline coefficient registers */
332e9d70 3545
4dd2da15
AT		 3546 /* start from OMAP_DSS_VIDEO1 */
3547 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3548 for (j = 0; j < 8; j++)
3549 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3550
4dd2da15
AT		 3551 for (j = 0; j < 8; j++)
3552 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3553
4dd2da15
AT		 3554 for (j = 0; j < 5; j++)
3555 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3556
4dd2da15
AT		 3557 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3558 for (j = 0; j < 8; j++)
3559 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3560 }
3561
3562 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3563 for (j = 0; j < 8; j++)
3564 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3565
3566 for (j = 0; j < 8; j++)
3567 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3568
3569 for (j = 0; j < 8; j++)
3570 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3571 }
332e9d70 3572 }
80c39712 3573
4fbafaf3 3574 dispc_runtime_put();
5010be80
AT		 3575
3576#undef DISPC_REG
80c39712
TV		 3577#undef DUMPREG
3578}
3579
80c39712
TV		 3580/* calculate clock rates using dividers in cinfo */
3581int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3582 struct dispc_clock_info *cinfo)
3583{
80c39712
TV		 3584 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3585 return -EINVAL;
9eaaf207 3586 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3587 return -EINVAL;
80c39712 3588
80c39712
TV		 3589 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3590 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3591
80c39712
TV		 3592 return 0;
3593}
80c39712 3594
7c284e6e
TV		 3595bool dispc_div_calc(unsigned long dispc,
3596 unsigned long pck_min, unsigned long pck_max,
3597 dispc_div_calc_func func, void *data)
3598{
3599 int lckd, lckd_start, lckd_stop;
3600 int pckd, pckd_start, pckd_stop;
3601 unsigned long pck, lck;
3602 unsigned long lck_max;
3603 unsigned long pckd_hw_min, pckd_hw_max;
3604 unsigned min_fck_per_pck;
3605 unsigned long fck;
80c39712 3606
7c284e6e
TV		 3607#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3608 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3609#else
3610 min_fck_per_pck = 0;
3611#endif
80c39712 3612
7c284e6e
TV		 3613 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3614 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3615
7c284e6e 3616 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3617
7c284e6e
TV		 3618 pck_min = pck_min ? pck_min : 1;
3619 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3620
7c284e6e
TV		 3621 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3622 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3623
7c284e6e
TV		 3624 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3625 lck = dispc / lckd;
80c39712 3626
7c284e6e
TV		 3627 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3628 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3629
7c284e6e
TV		 3630 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3631 pck = lck / pckd;
80c39712 3632
7c284e6e
TV		 3633 /*
3634 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3635 * clock, which means we're configuring DISPC fclk here
3636 * also. Thus we need to use the calculated lck. For
3637 * OMAP4+ the DISPC fclk is a separate clock.
3638 */
3639 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3640 fck = dispc_core_clk_rate();
3641 else
3642 fck = lck;
3643
3644 if (fck < pck * min_fck_per_pck)
3645 continue;
3646
3647 if (func(lckd, pckd, lck, pck, data))
3648 return true;
3649 }
3650 }
3651
3652 return false;
80c39712
TV		 3653}
3654
f0d08f89 3655void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3656 const struct dispc_clock_info *cinfo)
80c39712
TV		 3657{
3658 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3659 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3660
26d9dd0d 3661 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3662}
3663
26d9dd0d 3664int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3665 struct dispc_clock_info *cinfo)
80c39712
TV		 3666{
3667 unsigned long fck;
3668
3669 fck = dispc_fclk_rate();
3670
ce7fa5eb
MR		 3671 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3672 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3673
3674 cinfo->lck = fck / cinfo->lck_div;
3675 cinfo->pck = cinfo->lck / cinfo->pck_div;
3676
3677 return 0;
3678}
3679
4e0397cf
TV		 3680u32 dispc_read_irqstatus(void)
3681{
3682 return dispc_read_reg(DISPC_IRQSTATUS);
3683}
348be69d 3684EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3685
3686void dispc_clear_irqstatus(u32 mask)
3687{
3688 dispc_write_reg(DISPC_IRQSTATUS, mask);
3689}
348be69d 3690EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3691
3692u32 dispc_read_irqenable(void)
3693{
3694 return dispc_read_reg(DISPC_IRQENABLE);
3695}
348be69d 3696EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3697
3698void dispc_write_irqenable(u32 mask)
3699{
3700 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3701
3702 /* clear the irqstatus for newly enabled irqs */
3703 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3704
3705 dispc_write_reg(DISPC_IRQENABLE, mask);
3706}
348be69d 3707EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3708
80c39712
TV		 3709void dispc_enable_sidle(void)
3710{
3711 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3712}
3713
3714void dispc_disable_sidle(void)
3715{
3716 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3717}
3718
3719static void _omap_dispc_initial_config(void)
3720{
3721 u32 l;
3722
0cf35df3
MR		 3723 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3724 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3725 l = dispc_read_reg(DISPC_DIVISOR);
3726 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3727 l = FLD_MOD(l, 1, 0, 0);
3728 l = FLD_MOD(l, 1, 23, 16);
3729 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3730
3731 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3732 }
3733
80c39712 3734 /* FUNCGATED */
6ced40bf
AT		 3735 if (dss_has_feature(FEAT_FUNCGATED))
3736 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3737
6e5264b0 3738 dispc_setup_color_conv_coef();
80c39712
TV		 3739
3740 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3741
42a6961c 3742 dispc_init_fifos();
5ed8cf5b
TV		 3743
3744 dispc_configure_burst_sizes();
54128701
AT		 3745
3746 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3747
3748 if (dispc.feat->mstandby_workaround)
3749 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
c64aa3a6
TV		 3750
3751 if (dss_has_feature(FEAT_MFLAG))
3752 dispc_init_mflag();
80c39712
TV		 3753}
3754
dcbe765b
CM		 3755static const struct dispc_features omap24xx_dispc_feats __initconst = {
3756 .sw_start = 5,
3757 .fp_start = 15,
3758 .bp_start = 27,
3759 .sw_max = 64,
3760 .vp_max = 255,
3761 .hp_max = 256,
33b89928
AT		 3762 .mgr_width_start = 10,
3763 .mgr_height_start = 26,
3764 .mgr_width_max = 2048,
3765 .mgr_height_max = 2048,
ca5ca69c 3766 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3767 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3768 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3769 .num_fifos = 3,
cffa947d 3770 .no_framedone_tv = true,
8bc65552 3771 .set_max_preload = false,
dcbe765b
CM		 3772};
3773
3774static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3775 .sw_start = 5,
3776 .fp_start = 15,
3777 .bp_start = 27,
3778 .sw_max = 64,
3779 .vp_max = 255,
3780 .hp_max = 256,
33b89928
AT		 3781 .mgr_width_start = 10,
3782 .mgr_height_start = 26,
3783 .mgr_width_max = 2048,
3784 .mgr_height_max = 2048,
ca5ca69c
AT		 3785 .max_lcd_pclk = 173000000,
3786 .max_tv_pclk = 59000000,
dcbe765b
CM		 3787 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3788 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3789 .num_fifos = 3,
cffa947d 3790 .no_framedone_tv = true,
8bc65552 3791 .set_max_preload = false,
dcbe765b
CM		 3792};
3793
3794static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3795 .sw_start = 7,
3796 .fp_start = 19,
3797 .bp_start = 31,
3798 .sw_max = 256,
3799 .vp_max = 4095,
3800 .hp_max = 4096,
33b89928
AT		 3801 .mgr_width_start = 10,
3802 .mgr_height_start = 26,
3803 .mgr_width_max = 2048,
3804 .mgr_height_max = 2048,
ca5ca69c
AT		 3805 .max_lcd_pclk = 173000000,
3806 .max_tv_pclk = 59000000,
dcbe765b
CM		 3807 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3808 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3809 .num_fifos = 3,
cffa947d 3810 .no_framedone_tv = true,
8bc65552 3811 .set_max_preload = false,
dcbe765b
CM		 3812};
3813
3814static const struct dispc_features omap44xx_dispc_feats __initconst = {
3815 .sw_start = 7,
3816 .fp_start = 19,
3817 .bp_start = 31,
3818 .sw_max = 256,
3819 .vp_max = 4095,
3820 .hp_max = 4096,
33b89928
AT		 3821 .mgr_width_start = 10,
3822 .mgr_height_start = 26,
3823 .mgr_width_max = 2048,
3824 .mgr_height_max = 2048,
ca5ca69c
AT		 3825 .max_lcd_pclk = 170000000,
3826 .max_tv_pclk = 185625000,
dcbe765b
CM		 3827 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3828 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3829 .num_fifos = 5,
66a0f9e4 3830 .gfx_fifo_workaround = true,
8bc65552 3831 .set_max_preload = true,
dcbe765b
CM		 3832};
3833
264236f8
AT		 3834static const struct dispc_features omap54xx_dispc_feats __initconst = {
3835 .sw_start = 7,
3836 .fp_start = 19,
3837 .bp_start = 31,
3838 .sw_max = 256,
3839 .vp_max = 4095,
3840 .hp_max = 4096,
3841 .mgr_width_start = 11,
3842 .mgr_height_start = 27,
3843 .mgr_width_max = 4096,
3844 .mgr_height_max = 4096,
ca5ca69c
AT		 3845 .max_lcd_pclk = 170000000,
3846 .max_tv_pclk = 186000000,
264236f8
AT		 3847 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3848 .calc_core_clk = calc_core_clk_44xx,
3849 .num_fifos = 5,
3850 .gfx_fifo_workaround = true,
d0df9a2c 3851 .mstandby_workaround = true,
8bc65552 3852 .set_max_preload = true,
264236f8
AT		 3853};
3854
84b47623 3855static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3856{
3857 const struct dispc_features *src;
3858 struct dispc_features *dst;
3859
84b47623 3860 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3861 if (!dst) {
84b47623 3862 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3863 return -ENOMEM;
3864 }
3865
b2c7d54f 3866 switch (omapdss_get_version()) {
84b47623 3867 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3868 src = &omap24xx_dispc_feats;
84b47623
TV		 3869 break;
3870
3871 case OMAPDSS_VER_OMAP34xx_ES1:
3872 src = &omap34xx_rev1_0_dispc_feats;
3873 break;
3874
3875 case OMAPDSS_VER_OMAP34xx_ES3:
3876 case OMAPDSS_VER_OMAP3630:
3877 case OMAPDSS_VER_AM35xx:
d6279d4a 3878 case OMAPDSS_VER_AM43xx:
84b47623
TV		 3879 src = &omap34xx_rev3_0_dispc_feats;
3880 break;
3881
3882 case OMAPDSS_VER_OMAP4430_ES1:
3883 case OMAPDSS_VER_OMAP4430_ES2:
3884 case OMAPDSS_VER_OMAP4:
dcbe765b 3885 src = &omap44xx_dispc_feats;
84b47623
TV		 3886 break;
3887
3888 case OMAPDSS_VER_OMAP5:
93550927 3889 case OMAPDSS_VER_DRA7xx:
264236f8 3890 src = &omap54xx_dispc_feats;
84b47623
TV		 3891 break;
3892
3893 default:
dcbe765b
CM		 3894 return -ENODEV;
3895 }
3896
3897 memcpy(dst, src, sizeof(*dst));
3898 dispc.feat = dst;
3899
3900 return 0;
3901}
3902
0925afc9
TV		 3903static irqreturn_t dispc_irq_handler(int irq, void *arg)
3904{
3905 if (!dispc.is_enabled)
3906 return IRQ_NONE;
3907
3908 return dispc.user_handler(irq, dispc.user_data);
3909}
3910
96e2e637
TV		 3911int dispc_request_irq(irq_handler_t handler, void *dev_id)
3912{
0925afc9
TV		 3913 int r;
3914
3915 if (dispc.user_handler != NULL)
3916 return -EBUSY;
3917
3918 dispc.user_handler = handler;
3919 dispc.user_data = dev_id;
3920
3921 /* ensure the dispc_irq_handler sees the values above */
3922 smp_wmb();
3923
3924 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3925 IRQF_SHARED, "OMAP DISPC", &dispc);
3926 if (r) {
3927 dispc.user_handler = NULL;
3928 dispc.user_data = NULL;
3929 }
3930
3931 return r;
96e2e637 3932}
348be69d 3933EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 3934
3935void dispc_free_irq(void *dev_id)
3936{
0925afc9
TV		 3937 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3938
3939 dispc.user_handler = NULL;
3940 dispc.user_data = NULL;
96e2e637 3941}
348be69d 3942EXPORT_SYMBOL(dispc_free_irq);
96e2e637 3943
060b6d9c 3944/* DISPC HW IP initialisation */
6e7e8f06 3945static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3946{
3947 u32 rev;
affe360d 3948 int r = 0;
ea9da36a 3949 struct resource *dispc_mem;
0006fd63 3950 struct device_node *np = pdev->dev.of_node;
ea9da36a 3951
060b6d9c
SG		 3952 dispc.pdev = pdev;
3953
d49cd155
TV		 3954 spin_lock_init(&dispc.control_lock);
3955
84b47623 3956 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 3957 if (r)
3958 return r;
3959
ea9da36a
SG		 3960 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3961 if (!dispc_mem) {
3962 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3963 return -EINVAL;
ea9da36a 3964 }
cd3b3449 3965
6e2a14d2
JL		 3966 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3967 resource_size(dispc_mem));
060b6d9c
SG		 3968 if (!dispc.base) {
3969 DSSERR("can't ioremap DISPC\n");
cd3b3449 3970 return -ENOMEM;
affe360d 3971 }
cd3b3449 3972
affe360d 3973 dispc.irq = platform_get_irq(dispc.pdev, 0);
3974 if (dispc.irq < 0) {
3975 DSSERR("platform_get_irq failed\n");
cd3b3449 3976 return -ENODEV;
affe360d 3977 }
3978
0006fd63
TV		 3979 if (np && of_property_read_bool(np, "syscon-pol")) {
3980 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3981 if (IS_ERR(dispc.syscon_pol)) {
3982 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3983 return PTR_ERR(dispc.syscon_pol);
3984 }
3985
3986 if (of_property_read_u32_index(np, "syscon-pol", 1,
3987 &dispc.syscon_pol_offset)) {
3988 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3989 return -EINVAL;
3990 }
3991 }
3992
4fbafaf3
TV		 3993 pm_runtime_enable(&pdev->dev);
3994
3995 r = dispc_runtime_get();
3996 if (r)
3997 goto err_runtime_get;
060b6d9c
SG		 3998
3999 _omap_dispc_initial_config();
4000
060b6d9c 4001 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4002 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4003 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4004
4fbafaf3 4005 dispc_runtime_put();
060b6d9c 4006
04b1fc02
TV		 4007 dss_init_overlay_managers();
4008
e40402cf
TV		 4009 dss_debugfs_create_file("dispc", dispc_dump_regs);
4010
060b6d9c 4011 return 0;
4fbafaf3
TV		 4012
4013err_runtime_get:
4014 pm_runtime_disable(&pdev->dev);
affe360d 4015 return r;
060b6d9c
SG		 4016}
4017
6e7e8f06 4018static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 4019{
4fbafaf3
TV		 4020 pm_runtime_disable(&pdev->dev);
4021
04b1fc02
TV		 4022 dss_uninit_overlay_managers();
4023
060b6d9c
SG		 4024 return 0;
4025}
4026
4fbafaf3
TV		 4027static int dispc_runtime_suspend(struct device *dev)
4028{
0925afc9
TV		 4029 dispc.is_enabled = false;
4030 /* ensure the dispc_irq_handler sees the is_enabled value */
4031 smp_wmb();
4032 /* wait for current handler to finish before turning the DISPC off */
4033 synchronize_irq(dispc.irq);
4034
4fbafaf3 4035 dispc_save_context();
4fbafaf3
TV		 4036
4037 return 0;
4038}
4039
4040static int dispc_runtime_resume(struct device *dev)
4041{
9229b516
TV		 4042 /*
4043 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4044 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4045 * _omap_dispc_initial_config(). We can thus use it to detect if
4046 * we have lost register context.
4047 */
0925afc9
TV		 4048 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4049 _omap_dispc_initial_config();
9229b516 4050
0925afc9
TV		 4051 dispc_restore_context();
4052 }
be07dcd7 4053
0925afc9
TV		 4054 dispc.is_enabled = true;
4055 /* ensure the dispc_irq_handler sees the is_enabled value */
4056 smp_wmb();
4fbafaf3
TV		 4057
4058 return 0;
4059}
4060
4061static const struct dev_pm_ops dispc_pm_ops = {
4062 .runtime_suspend = dispc_runtime_suspend,
4063 .runtime_resume = dispc_runtime_resume,
4064};
4065
d7977f88
TV		 4066static const struct of_device_id dispc_of_match[] = {
4067 { .compatible = "ti,omap2-dispc", },
4068 { .compatible = "ti,omap3-dispc", },
4069 { .compatible = "ti,omap4-dispc", },
2e7e6b68 4070 { .compatible = "ti,omap5-dispc", },
93550927 4071 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 4072 {},
4073};
4074
060b6d9c 4075static struct platform_driver omap_dispchw_driver = {
6e7e8f06 4076 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 4077 .driver = {
4078 .name = "omapdss_dispc",
4fbafaf3 4079 .pm = &dispc_pm_ops,
d7977f88 4080 .of_match_table = dispc_of_match,
422ccbd5 4081 .suppress_bind_attrs = true,
060b6d9c
SG		 4082 },
4083};
4084
6e7e8f06 4085int __init dispc_init_platform_driver(void)
060b6d9c 4086{
11436e1d 4087 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 4088}
4089
6e7e8f06 4090void __exit dispc_uninit_platform_driver(void)
060b6d9c 4091{
04c742c3 4092 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4093}
Linux kernel - Deliverables
This page took 0.648518 seconds and 5 git commands to generate.