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OMAPDSS: add num_wbs=1 to omap5 dss features
[deliverable/linux.git] / drivers / video / fbdev / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
736e60dd 42#include <linux/component.h>
80c39712 43
a0b38cc4 44#include <video/omapdss.h>
80c39712
TV		 45
46#include "dss.h"
a0acb557 47#include "dss_features.h"
9b372c2d 48#include "dispc.h"
80c39712
TV		 49
50/* DISPC */
8613b000 51#define DISPC_SZ_REGS SZ_4K
80c39712 52
5ed8cf5b
TV		 53enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57};
58
80c39712
TV		 59#define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
61
62#define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64
dcbe765b
CM		 65struct dispc_features {
66 u8 sw_start;
67 u8 fp_start;
68 u8 bp_start;
69 u16 sw_max;
70 u16 vp_max;
71 u16 hp_max;
33b89928
AT		 72 u8 mgr_width_start;
73 u8 mgr_height_start;
74 u16 mgr_width_max;
75 u16 mgr_height_max;
ca5ca69c
AT		 76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
0c6921de 78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 84 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 85 u16 width, u16 height, u16 out_width, u16 out_height,
86 bool mem_to_mem);
42a6961c 87 u8 num_fifos;
66a0f9e4
TV		 88
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
cffa947d
TV		 91
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
d0df9a2c
AT		 94
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
8bc65552
AT		 97
98 bool set_max_preload:1;
f2aee319
TV		 99
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
e5f80917
TV		 102
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
dcbe765b
CM		 105};
106
42a6961c
TV		 107#define DISPC_MAX_NR_FIFOS 5
108
80c39712 109static struct {
060b6d9c 110 struct platform_device *pdev;
80c39712 111 void __iomem *base;
4fbafaf3 112
affe360d 113 int irq;
0925afc9
TV		 114 irq_handler_t user_handler;
115 void *user_data;
80c39712 116
7b3926b3 117 unsigned long core_clk_rate;
5391e87d 118 unsigned long tv_pclk_rate;
7b3926b3 119
42a6961c
TV		 120 u32 fifo_size[DISPC_MAX_NR_FIFOS];
121 /* maps which plane is using a fifo. fifo-id -> plane-id */
122 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 123
49ea86f3 124 bool ctx_valid;
80c39712 125 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 126
dcbe765b 127 const struct dispc_features *feat;
0925afc9
TV		 128
129 bool is_enabled;
0006fd63
TV		 130
131 struct regmap *syscon_pol;
132 u32 syscon_pol_offset;
d49cd155
TV		 133
134 /* DISPC_CONTROL & DISPC_CONFIG lock*/
135 spinlock_t control_lock;
80c39712
TV		 136} dispc;
137
0d66cbb5
AJ		 138enum omap_color_component {
139 /* used for all color formats for OMAP3 and earlier
140 * and for RGB and Y color component on OMAP4
141 */
142 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
143 /* used for UV component for
144 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
145 * color formats on OMAP4
146 */
147 DISPC_COLOR_COMPONENT_UV = 1 << 1,
148};
149
efa70b3b
CM		 150enum mgr_reg_fields {
151 DISPC_MGR_FLD_ENABLE,
152 DISPC_MGR_FLD_STNTFT,
153 DISPC_MGR_FLD_GO,
154 DISPC_MGR_FLD_TFTDATALINES,
155 DISPC_MGR_FLD_STALLMODE,
156 DISPC_MGR_FLD_TCKENABLE,
157 DISPC_MGR_FLD_TCKSELECTION,
158 DISPC_MGR_FLD_CPR,
159 DISPC_MGR_FLD_FIFOHANDCHECK,
160 /* used to maintain a count of the above fields */
161 DISPC_MGR_FLD_NUM,
162};
163
5c348ba9
JS		 164struct dispc_reg_field {
165 u16 reg;
166 u8 high;
167 u8 low;
168};
169
efa70b3b
CM		 170static const struct {
171 const char *name;
172 u32 vsync_irq;
173 u32 framedone_irq;
174 u32 sync_lost_irq;
5c348ba9 175 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 176} mgr_desc[] = {
177 [OMAP_DSS_CHANNEL_LCD] = {
178 .name = "LCD",
179 .vsync_irq = DISPC_IRQ_VSYNC,
180 .framedone_irq = DISPC_IRQ_FRAMEDONE,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
184 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
187 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
190 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
192 },
193 },
194 [OMAP_DSS_CHANNEL_DIGIT] = {
195 .name = "DIGIT",
196 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 197 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 198 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
199 .reg_desc = {
200 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
201 [DISPC_MGR_FLD_STNTFT] = { },
202 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
203 [DISPC_MGR_FLD_TFTDATALINES] = { },
204 [DISPC_MGR_FLD_STALLMODE] = { },
205 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
206 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
207 [DISPC_MGR_FLD_CPR] = { },
208 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
209 },
210 },
211 [OMAP_DSS_CHANNEL_LCD2] = {
212 .name = "LCD2",
213 .vsync_irq = DISPC_IRQ_VSYNC2,
214 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
215 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
216 .reg_desc = {
217 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
218 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
219 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
220 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
221 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
222 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
223 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
224 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
225 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
226 },
227 },
e86d456a
CM		 228 [OMAP_DSS_CHANNEL_LCD3] = {
229 .name = "LCD3",
230 .vsync_irq = DISPC_IRQ_VSYNC3,
231 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
232 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
233 .reg_desc = {
234 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
235 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
236 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
237 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
238 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
239 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
240 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
241 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
242 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
243 },
244 },
efa70b3b
CM		 245};
246
6e5264b0
AT		 247struct color_conv_coef {
248 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
249 int full_range;
250};
251
3e8a6ff2
AT		 252static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
253static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 254
55978cc2 255static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 256{
55978cc2 257 __raw_writel(val, dispc.base + idx);
80c39712
TV		 258}
259
55978cc2 260static inline u32 dispc_read_reg(const u16 idx)
80c39712 261{
55978cc2 262 return __raw_readl(dispc.base + idx);
80c39712
TV		 263}
264
efa70b3b
CM		 265static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
266{
5c348ba9 267 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 268 return REG_GET(rfld.reg, rfld.high, rfld.low);
269}
270
271static void mgr_fld_write(enum omap_channel channel,
272 enum mgr_reg_fields regfld, int val) {
5c348ba9 273 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
d49cd155
TV		 274 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
275 unsigned long flags;
276
277 if (need_lock)
278 spin_lock_irqsave(&dispc.control_lock, flags);
279
efa70b3b 280 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
d49cd155
TV		 281
282 if (need_lock)
283 spin_unlock_irqrestore(&dispc.control_lock, flags);
efa70b3b
CM		 284}
285
80c39712 286#define SR(reg) \
55978cc2 287 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 288#define RR(reg) \
55978cc2 289 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 290
4fbafaf3 291static void dispc_save_context(void)
80c39712 292{
c6104b8e 293 int i, j;
80c39712 294
4fbafaf3
TV		 295 DSSDBG("dispc_save_context\n");
296
80c39712
TV		 297 SR(IRQENABLE);
298 SR(CONTROL);
299 SR(CONFIG);
80c39712 300 SR(LINE_NUMBER);
11354dd5
AT		 301 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
302 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 303 SR(GLOBAL_ALPHA);
2a205f34
SS		 304 if (dss_has_feature(FEAT_MGR_LCD2)) {
305 SR(CONTROL2);
2a205f34
SS		 306 SR(CONFIG2);
307 }
e86d456a
CM		 308 if (dss_has_feature(FEAT_MGR_LCD3)) {
309 SR(CONTROL3);
310 SR(CONFIG3);
311 }
80c39712 312
c6104b8e
AT		 313 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
314 SR(DEFAULT_COLOR(i));
315 SR(TRANS_COLOR(i));
316 SR(SIZE_MGR(i));
317 if (i == OMAP_DSS_CHANNEL_DIGIT)
318 continue;
319 SR(TIMING_H(i));
320 SR(TIMING_V(i));
321 SR(POL_FREQ(i));
322 SR(DIVISORo(i));
323
324 SR(DATA_CYCLE1(i));
325 SR(DATA_CYCLE2(i));
326 SR(DATA_CYCLE3(i));
327
332e9d70 328 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 329 SR(CPR_COEF_R(i));
330 SR(CPR_COEF_G(i));
331 SR(CPR_COEF_B(i));
332e9d70 332 }
2a205f34 333 }
80c39712 334
c6104b8e
AT		 335 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
336 SR(OVL_BA0(i));
337 SR(OVL_BA1(i));
338 SR(OVL_POSITION(i));
339 SR(OVL_SIZE(i));
340 SR(OVL_ATTRIBUTES(i));
341 SR(OVL_FIFO_THRESHOLD(i));
342 SR(OVL_ROW_INC(i));
343 SR(OVL_PIXEL_INC(i));
344 if (dss_has_feature(FEAT_PRELOAD))
345 SR(OVL_PRELOAD(i));
346 if (i == OMAP_DSS_GFX) {
347 SR(OVL_WINDOW_SKIP(i));
348 SR(OVL_TABLE_BA(i));
349 continue;
350 }
351 SR(OVL_FIR(i));
352 SR(OVL_PICTURE_SIZE(i));
353 SR(OVL_ACCU0(i));
354 SR(OVL_ACCU1(i));
9b372c2d 355
c6104b8e
AT		 356 for (j = 0; j < 8; j++)
357 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 358
c6104b8e
AT		 359 for (j = 0; j < 8; j++)
360 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 361
c6104b8e
AT		 362 for (j = 0; j < 5; j++)
363 SR(OVL_CONV_COEF(i, j));
ab5ca071 364
c6104b8e
AT		 365 if (dss_has_feature(FEAT_FIR_COEF_V)) {
366 for (j = 0; j < 8; j++)
367 SR(OVL_FIR_COEF_V(i, j));
368 }
9b372c2d 369
c6104b8e
AT		 370 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
371 SR(OVL_BA0_UV(i));
372 SR(OVL_BA1_UV(i));
373 SR(OVL_FIR2(i));
374 SR(OVL_ACCU2_0(i));
375 SR(OVL_ACCU2_1(i));
ab5ca071 376
c6104b8e
AT		 377 for (j = 0; j < 8; j++)
378 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 379
c6104b8e
AT		 380 for (j = 0; j < 8; j++)
381 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 382
c6104b8e
AT		 383 for (j = 0; j < 8; j++)
384 SR(OVL_FIR_COEF_V2(i, j));
385 }
386 if (dss_has_feature(FEAT_ATTR2))
387 SR(OVL_ATTRIBUTES2(i));
ab5ca071 388 }
0cf35df3
MR		 389
390 if (dss_has_feature(FEAT_CORE_CLK_DIV))
391 SR(DIVISOR);
49ea86f3 392
49ea86f3
TV		 393 dispc.ctx_valid = true;
394
9229b516 395 DSSDBG("context saved\n");
80c39712
TV		 396}
397
4fbafaf3 398static void dispc_restore_context(void)
80c39712 399{
9229b516 400 int i, j;
4fbafaf3
TV		 401
402 DSSDBG("dispc_restore_context\n");
403
49ea86f3
TV		 404 if (!dispc.ctx_valid)
405 return;
406
75c7d59d 407 /*RR(IRQENABLE);*/
80c39712
TV		 408 /*RR(CONTROL);*/
409 RR(CONFIG);
80c39712 410 RR(LINE_NUMBER);
11354dd5
AT		 411 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
412 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 413 RR(GLOBAL_ALPHA);
c6104b8e 414 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 415 RR(CONFIG2);
e86d456a
CM		 416 if (dss_has_feature(FEAT_MGR_LCD3))
417 RR(CONFIG3);
80c39712 418
c6104b8e
AT		 419 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
420 RR(DEFAULT_COLOR(i));
421 RR(TRANS_COLOR(i));
422 RR(SIZE_MGR(i));
423 if (i == OMAP_DSS_CHANNEL_DIGIT)
424 continue;
425 RR(TIMING_H(i));
426 RR(TIMING_V(i));
427 RR(POL_FREQ(i));
428 RR(DIVISORo(i));
429
430 RR(DATA_CYCLE1(i));
431 RR(DATA_CYCLE2(i));
432 RR(DATA_CYCLE3(i));
2a205f34 433
332e9d70 434 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 435 RR(CPR_COEF_R(i));
436 RR(CPR_COEF_G(i));
437 RR(CPR_COEF_B(i));
332e9d70 438 }
2a205f34 439 }
80c39712 440
c6104b8e
AT		 441 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
442 RR(OVL_BA0(i));
443 RR(OVL_BA1(i));
444 RR(OVL_POSITION(i));
445 RR(OVL_SIZE(i));
446 RR(OVL_ATTRIBUTES(i));
447 RR(OVL_FIFO_THRESHOLD(i));
448 RR(OVL_ROW_INC(i));
449 RR(OVL_PIXEL_INC(i));
450 if (dss_has_feature(FEAT_PRELOAD))
451 RR(OVL_PRELOAD(i));
452 if (i == OMAP_DSS_GFX) {
453 RR(OVL_WINDOW_SKIP(i));
454 RR(OVL_TABLE_BA(i));
455 continue;
456 }
457 RR(OVL_FIR(i));
458 RR(OVL_PICTURE_SIZE(i));
459 RR(OVL_ACCU0(i));
460 RR(OVL_ACCU1(i));
9b372c2d 461
c6104b8e
AT		 462 for (j = 0; j < 8; j++)
463 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 464
c6104b8e
AT		 465 for (j = 0; j < 8; j++)
466 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 467
c6104b8e
AT		 468 for (j = 0; j < 5; j++)
469 RR(OVL_CONV_COEF(i, j));
ab5ca071 470
c6104b8e
AT		 471 if (dss_has_feature(FEAT_FIR_COEF_V)) {
472 for (j = 0; j < 8; j++)
473 RR(OVL_FIR_COEF_V(i, j));
474 }
9b372c2d 475
c6104b8e
AT		 476 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
477 RR(OVL_BA0_UV(i));
478 RR(OVL_BA1_UV(i));
479 RR(OVL_FIR2(i));
480 RR(OVL_ACCU2_0(i));
481 RR(OVL_ACCU2_1(i));
ab5ca071 482
c6104b8e
AT		 483 for (j = 0; j < 8; j++)
484 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 485
c6104b8e
AT		 486 for (j = 0; j < 8; j++)
487 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 488
c6104b8e
AT		 489 for (j = 0; j < 8; j++)
490 RR(OVL_FIR_COEF_V2(i, j));
491 }
492 if (dss_has_feature(FEAT_ATTR2))
493 RR(OVL_ATTRIBUTES2(i));
ab5ca071 494 }
80c39712 495
0cf35df3
MR		 496 if (dss_has_feature(FEAT_CORE_CLK_DIV))
497 RR(DIVISOR);
498
80c39712
TV		 499 /* enable last, because LCD & DIGIT enable are here */
500 RR(CONTROL);
2a205f34
SS		 501 if (dss_has_feature(FEAT_MGR_LCD2))
502 RR(CONTROL2);
e86d456a
CM		 503 if (dss_has_feature(FEAT_MGR_LCD3))
504 RR(CONTROL3);
75c7d59d 505 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 506 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 507
508 /*
509 * enable last so IRQs won't trigger before
510 * the context is fully restored
511 */
512 RR(IRQENABLE);
49ea86f3
TV		 513
514 DSSDBG("context restored\n");
80c39712
TV		 515}
516
517#undef SR
518#undef RR
519
4fbafaf3
TV		 520int dispc_runtime_get(void)
521{
522 int r;
523
524 DSSDBG("dispc_runtime_get\n");
525
526 r = pm_runtime_get_sync(&dispc.pdev->dev);
527 WARN_ON(r < 0);
528 return r < 0 ? r : 0;
529}
348be69d 530EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 531
532void dispc_runtime_put(void)
533{
534 int r;
535
536 DSSDBG("dispc_runtime_put\n");
537
0eaf9f52 538 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 539 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 540}
348be69d 541EXPORT_SYMBOL(dispc_runtime_put);
80c39712 542
3dcec4d6
TV		 543u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
544{
efa70b3b 545 return mgr_desc[channel].vsync_irq;
3dcec4d6 546}
348be69d 547EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 548
7d1365c9
TV		 549u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
550{
cffa947d
TV		 551 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
552 return 0;
553
efa70b3b 554 return mgr_desc[channel].framedone_irq;
7d1365c9 555}
348be69d 556EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 557
cb699200
TV		 558u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
559{
560 return mgr_desc[channel].sync_lost_irq;
561}
348be69d 562EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 563
0b23e5b8
AT		 564u32 dispc_wb_get_framedone_irq(void)
565{
566 return DISPC_IRQ_FRAMEDONEWB;
567}
568
26d9dd0d 569bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 570{
efa70b3b 571 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 572}
348be69d 573EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 574
26d9dd0d 575void dispc_mgr_go(enum omap_channel channel)
80c39712 576{
3c91ee8c
TV		 577 WARN_ON(dispc_mgr_is_enabled(channel) == false);
578 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 579
efa70b3b 580 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 581
efa70b3b 582 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 583}
348be69d 584EXPORT_SYMBOL(dispc_mgr_go);
80c39712 585
0b23e5b8
AT		 586bool dispc_wb_go_busy(void)
587{
588 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
589}
590
591void dispc_wb_go(void)
592{
593 enum omap_plane plane = OMAP_DSS_WB;
594 bool enable, go;
595
596 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
597
598 if (!enable)
599 return;
600
601 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
602 if (go) {
603 DSSERR("GO bit not down for WB\n");
604 return;
605 }
606
607 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
608}
609
f0e5caab 610static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 611{
9b372c2d 612 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 613}
614
f0e5caab 615static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 616{
9b372c2d 617 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 618}
619
f0e5caab 620static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 621{
9b372c2d 622 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 623}
624
f0e5caab 625static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 626{
627 BUG_ON(plane == OMAP_DSS_GFX);
628
629 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
630}
631
f0e5caab
TV		 632static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
633 u32 value)
ab5ca071
AJ		 634{
635 BUG_ON(plane == OMAP_DSS_GFX);
636
637 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
638}
639
f0e5caab 640static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 641{
642 BUG_ON(plane == OMAP_DSS_GFX);
643
644 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
645}
646
debd9074
CM		 647static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
648 int fir_vinc, int five_taps,
649 enum omap_color_component color_comp)
80c39712 650{
debd9074 651 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 652 int i;
653
debd9074
CM		 654 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
655 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 656
657 for (i = 0; i < 8; i++) {
658 u32 h, hv;
659
debd9074
CM		 660 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
661 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
662 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
663 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
664 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
665 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
666 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
667 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 668
0d66cbb5 669 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 670 dispc_ovl_write_firh_reg(plane, i, h);
671 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 672 } else {
f0e5caab
TV		 673 dispc_ovl_write_firh2_reg(plane, i, h);
674 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 675 }
676
80c39712
TV		 677 }
678
66be8f6c
GI		 679 if (five_taps) {
680 for (i = 0; i < 8; i++) {
681 u32 v;
debd9074
CM		 682 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
683 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 684 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 685 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 686 else
f0e5caab 687 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 688 }
80c39712
TV		 689 }
690}
691
80c39712 692
6e5264b0
AT		 693static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
694 const struct color_conv_coef *ct)
695{
80c39712
TV		 696#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
697
6e5264b0
AT		 698 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
699 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
700 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
701 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
702 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 703
6e5264b0 704 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 705
706#undef CVAL
80c39712
TV		 707}
708
6e5264b0
AT		 709static void dispc_setup_color_conv_coef(void)
710{
711 int i;
712 int num_ovl = dss_feat_get_num_ovls();
713 int num_wb = dss_feat_get_num_wbs();
714 const struct color_conv_coef ctbl_bt601_5_ovl = {
715 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
716 };
717 const struct color_conv_coef ctbl_bt601_5_wb = {
718 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
719 };
720
721 for (i = 1; i < num_ovl; i++)
722 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
723
724 for (; i < num_wb; i++)
725 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
726}
80c39712 727
f0e5caab 728static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 729{
9b372c2d 730 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 731}
732
f0e5caab 733static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 734{
9b372c2d 735 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 736}
737
f0e5caab 738static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 739{
740 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
741}
742
f0e5caab 743static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 744{
745 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
746}
747
d79db853
AT		 748static void dispc_ovl_set_pos(enum omap_plane plane,
749 enum omap_overlay_caps caps, int x, int y)
80c39712 750{
d79db853
AT		 751 u32 val;
752
753 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
754 return;
755
756 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 757
758 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 759}
760
78b687fc
AT		 761static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
762 int height)
80c39712 763{
80c39712 764 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 765
36d87d95 766 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 767 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
768 else
769 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 770}
771
78b687fc
AT		 772static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
773 int height)
80c39712
TV		 774{
775 u32 val;
80c39712
TV		 776
777 BUG_ON(plane == OMAP_DSS_GFX);
778
779 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 780
36d87d95
AT		 781 if (plane == OMAP_DSS_WB)
782 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
783 else
784 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 785}
786
5b54ed3e
AT		 787static void dispc_ovl_set_zorder(enum omap_plane plane,
788 enum omap_overlay_caps caps, u8 zorder)
54128701 789{
5b54ed3e 790 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 791 return;
792
793 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
794}
795
796static void dispc_ovl_enable_zorder_planes(void)
797{
798 int i;
799
800 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
801 return;
802
803 for (i = 0; i < dss_feat_get_num_ovls(); i++)
804 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
805}
806
5b54ed3e
AT		 807static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
808 enum omap_overlay_caps caps, bool enable)
fd28a390 809{
5b54ed3e 810 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 811 return;
812
9b372c2d 813 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 814}
815
5b54ed3e
AT		 816static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
817 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 818{
b8c095b4 819 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 820 int shift;
821
5b54ed3e 822 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 823 return;
a0acb557 824
fe3cc9d6
TV		 825 shift = shifts[plane];
826 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 827}
828
f0e5caab 829static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 830{
9b372c2d 831 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 832}
833
f0e5caab 834static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 835{
9b372c2d 836 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 837}
838
f0e5caab 839static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 840 enum omap_color_mode color_mode)
841{
842 u32 m = 0;
f20e4220
AJ		 843 if (plane != OMAP_DSS_GFX) {
844 switch (color_mode) {
845 case OMAP_DSS_COLOR_NV12:
846 m = 0x0; break;
08f3267e 847 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 848 m = 0x1; break;
849 case OMAP_DSS_COLOR_RGBA16:
850 m = 0x2; break;
08f3267e 851 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 852 m = 0x4; break;
853 case OMAP_DSS_COLOR_ARGB16:
854 m = 0x5; break;
855 case OMAP_DSS_COLOR_RGB16:
856 m = 0x6; break;
857 case OMAP_DSS_COLOR_ARGB16_1555:
858 m = 0x7; break;
859 case OMAP_DSS_COLOR_RGB24U:
860 m = 0x8; break;
861 case OMAP_DSS_COLOR_RGB24P:
862 m = 0x9; break;
863 case OMAP_DSS_COLOR_YUV2:
864 m = 0xa; break;
865 case OMAP_DSS_COLOR_UYVY:
866 m = 0xb; break;
867 case OMAP_DSS_COLOR_ARGB32:
868 m = 0xc; break;
869 case OMAP_DSS_COLOR_RGBA32:
870 m = 0xd; break;
871 case OMAP_DSS_COLOR_RGBX32:
872 m = 0xe; break;
873 case OMAP_DSS_COLOR_XRGB16_1555:
874 m = 0xf; break;
875 default:
c6eee968 876 BUG(); return;
f20e4220
AJ		 877 }
878 } else {
879 switch (color_mode) {
880 case OMAP_DSS_COLOR_CLUT1:
881 m = 0x0; break;
882 case OMAP_DSS_COLOR_CLUT2:
883 m = 0x1; break;
884 case OMAP_DSS_COLOR_CLUT4:
885 m = 0x2; break;
886 case OMAP_DSS_COLOR_CLUT8:
887 m = 0x3; break;
888 case OMAP_DSS_COLOR_RGB12U:
889 m = 0x4; break;
890 case OMAP_DSS_COLOR_ARGB16:
891 m = 0x5; break;
892 case OMAP_DSS_COLOR_RGB16:
893 m = 0x6; break;
894 case OMAP_DSS_COLOR_ARGB16_1555:
895 m = 0x7; break;
896 case OMAP_DSS_COLOR_RGB24U:
897 m = 0x8; break;
898 case OMAP_DSS_COLOR_RGB24P:
899 m = 0x9; break;
08f3267e 900 case OMAP_DSS_COLOR_RGBX16:
f20e4220 901 m = 0xa; break;
08f3267e 902 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 903 m = 0xb; break;
904 case OMAP_DSS_COLOR_ARGB32:
905 m = 0xc; break;
906 case OMAP_DSS_COLOR_RGBA32:
907 m = 0xd; break;
908 case OMAP_DSS_COLOR_RGBX32:
909 m = 0xe; break;
910 case OMAP_DSS_COLOR_XRGB16_1555:
911 m = 0xf; break;
912 default:
c6eee968 913 BUG(); return;
f20e4220 914 }
80c39712
TV		 915 }
916
9b372c2d 917 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 918}
919
65e006ff
CM		 920static void dispc_ovl_configure_burst_type(enum omap_plane plane,
921 enum omap_dss_rotation_type rotation_type)
922{
923 if (dss_has_feature(FEAT_BURST_2D) == 0)
924 return;
925
926 if (rotation_type == OMAP_DSS_ROT_TILER)
927 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
928 else
929 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
930}
931
f427984e 932void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 933{
934 int shift;
935 u32 val;
2a205f34 936 int chan = 0, chan2 = 0;
80c39712
TV		 937
938 switch (plane) {
939 case OMAP_DSS_GFX:
940 shift = 8;
941 break;
942 case OMAP_DSS_VIDEO1:
943 case OMAP_DSS_VIDEO2:
b8c095b4 944 case OMAP_DSS_VIDEO3:
80c39712
TV		 945 shift = 16;
946 break;
947 default:
948 BUG();
949 return;
950 }
951
9b372c2d 952 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 953 if (dss_has_feature(FEAT_MGR_LCD2)) {
954 switch (channel) {
955 case OMAP_DSS_CHANNEL_LCD:
956 chan = 0;
957 chan2 = 0;
958 break;
959 case OMAP_DSS_CHANNEL_DIGIT:
960 chan = 1;
961 chan2 = 0;
962 break;
963 case OMAP_DSS_CHANNEL_LCD2:
964 chan = 0;
965 chan2 = 1;
966 break;
e86d456a
CM		 967 case OMAP_DSS_CHANNEL_LCD3:
968 if (dss_has_feature(FEAT_MGR_LCD3)) {
969 chan = 0;
970 chan2 = 2;
971 } else {
972 BUG();
973 return;
974 }
975 break;
2a205f34
SS		 976 default:
977 BUG();
c6eee968 978 return;
2a205f34
SS		 979 }
980
981 val = FLD_MOD(val, chan, shift, shift);
982 val = FLD_MOD(val, chan2, 31, 30);
983 } else {
984 val = FLD_MOD(val, channel, shift, shift);
985 }
9b372c2d 986 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 987}
348be69d 988EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 989
2cc5d1af
TV		 990static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
991{
992 int shift;
993 u32 val;
994 enum omap_channel channel;
995
996 switch (plane) {
997 case OMAP_DSS_GFX:
998 shift = 8;
999 break;
1000 case OMAP_DSS_VIDEO1:
1001 case OMAP_DSS_VIDEO2:
1002 case OMAP_DSS_VIDEO3:
1003 shift = 16;
1004 break;
1005 default:
1006 BUG();
c6eee968 1007 return 0;
2cc5d1af
TV		 1008 }
1009
1010 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1011
e86d456a
CM		 1012 if (dss_has_feature(FEAT_MGR_LCD3)) {
1013 if (FLD_GET(val, 31, 30) == 0)
1014 channel = FLD_GET(val, shift, shift);
1015 else if (FLD_GET(val, 31, 30) == 1)
1016 channel = OMAP_DSS_CHANNEL_LCD2;
1017 else
1018 channel = OMAP_DSS_CHANNEL_LCD3;
1019 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1020 if (FLD_GET(val, 31, 30) == 0)
1021 channel = FLD_GET(val, shift, shift);
1022 else
1023 channel = OMAP_DSS_CHANNEL_LCD2;
1024 } else {
1025 channel = FLD_GET(val, shift, shift);
1026 }
1027
1028 return channel;
1029}
1030
d9ac773c
AT		 1031void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1032{
1033 enum omap_plane plane = OMAP_DSS_WB;
1034
1035 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1036}
1037
f0e5caab 1038static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1039 enum omap_burst_size burst_size)
1040{
8bbe09ee 1041 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1042 int shift;
80c39712 1043
fe3cc9d6 1044 shift = shifts[plane];
5ed8cf5b 1045 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1046}
1047
5ed8cf5b
TV		 1048static void dispc_configure_burst_sizes(void)
1049{
1050 int i;
1051 const int burst_size = BURST_SIZE_X8;
1052
1053 /* Configure burst size always to maximum size */
392faa0e 1054 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1055 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1056}
1057
83fa2f2e 1058static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1059{
1060 unsigned unit = dss_feat_get_burst_size_unit();
1061 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1062 return unit * 8;
1063}
1064
d3862610
M		 1065void dispc_enable_gamma_table(bool enable)
1066{
1067 /*
1068 * This is partially implemented to support only disabling of
1069 * the gamma table.
1070 */
1071 if (enable) {
1072 DSSWARN("Gamma table enabling for TV not yet supported");
1073 return;
1074 }
1075
1076 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1077}
1078
c64dca40 1079static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1080{
efa70b3b 1081 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1082 return;
1083
efa70b3b 1084 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1085}
1086
c64dca40 1087static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1088 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1089{
1090 u32 coef_r, coef_g, coef_b;
1091
dd88b7a6 1092 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1093 return;
1094
1095 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1096 FLD_VAL(coefs->rb, 9, 0);
1097 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1098 FLD_VAL(coefs->gb, 9, 0);
1099 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1100 FLD_VAL(coefs->bb, 9, 0);
1101
1102 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1103 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1104 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1105}
1106
f0e5caab 1107static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1108{
1109 u32 val;
1110
1111 BUG_ON(plane == OMAP_DSS_GFX);
1112
9b372c2d 1113 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1114 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1115 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1116}
1117
d79db853
AT		 1118static void dispc_ovl_enable_replication(enum omap_plane plane,
1119 enum omap_overlay_caps caps, bool enable)
80c39712 1120{
b8c095b4 1121 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1122 int shift;
80c39712 1123
d79db853
AT		 1124 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1125 return;
1126
fe3cc9d6
TV		 1127 shift = shifts[plane];
1128 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1129}
1130
8f366162 1131static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1132 u16 height)
80c39712
TV		 1133{
1134 u32 val;
80c39712 1135
33b89928
AT		 1136 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1137 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1138
8f366162 1139 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1140}
1141
42a6961c 1142static void dispc_init_fifos(void)
80c39712 1143{
80c39712 1144 u32 size;
42a6961c 1145 int fifo;
a0acb557 1146 u8 start, end;
5ed8cf5b 1147 u32 unit;
47fc469b 1148 int i;
5ed8cf5b
TV		 1149
1150 unit = dss_feat_get_buffer_size_unit();
80c39712 1151
a0acb557 1152 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1153
42a6961c
TV		 1154 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1155 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1156 size *= unit;
42a6961c
TV		 1157 dispc.fifo_size[fifo] = size;
1158
1159 /*
1160 * By default fifos are mapped directly to overlays, fifo 0 to
1161 * ovl 0, fifo 1 to ovl 1, etc.
1162 */
1163 dispc.fifo_assignment[fifo] = fifo;
80c39712 1164 }
66a0f9e4
TV		 1165
1166 /*
1167 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1168 * causes problems with certain use cases, like using the tiler in 2D
1169 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1170 * giving GFX plane a larger fifo. WB but should work fine with a
1171 * smaller fifo.
1172 */
1173 if (dispc.feat->gfx_fifo_workaround) {
1174 u32 v;
1175
1176 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1177
1178 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1179 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1180 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1181 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1182
1183 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1184
1185 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1186 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1187 }
47fc469b
TV		 1188
1189 /*
1190 * Setup default fifo thresholds.
1191 */
1192 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1193 u32 low, high;
1194 const bool use_fifomerge = false;
1195 const bool manual_update = false;
1196
1197 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1198 use_fifomerge, manual_update);
1199
1200 dispc_ovl_set_fifo_threshold(i, low, high);
1201 }
80c39712
TV		 1202}
1203
83fa2f2e 1204static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1205{
42a6961c
TV		 1206 int fifo;
1207 u32 size = 0;
1208
1209 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1210 if (dispc.fifo_assignment[fifo] == plane)
1211 size += dispc.fifo_size[fifo];
1212 }
1213
1214 return size;
80c39712
TV		 1215}
1216
6f04e1bf 1217void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1218{
a0acb557 1219 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1220 u32 unit;
1221
1222 unit = dss_feat_get_buffer_size_unit();
1223
1224 WARN_ON(low % unit != 0);
1225 WARN_ON(high % unit != 0);
1226
1227 low /= unit;
1228 high /= unit;
a0acb557 1229
9b372c2d
AT		 1230 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1231 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1232
3cb5d966 1233 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1234 plane,
9b372c2d 1235 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1236 lo_start, lo_end) * unit,
9b372c2d 1237 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1238 hi_start, hi_end) * unit,
1239 low * unit, high * unit);
80c39712 1240
9b372c2d 1241 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1242 FLD_VAL(high, hi_start, hi_end) |
1243 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1244
1245 /*
1246 * configure the preload to the pipeline's high threhold, if HT it's too
1247 * large for the preload field, set the threshold to the maximum value
1248 * that can be held by the preload register
1249 */
1250 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1251 plane != OMAP_DSS_WB)
1252 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712 1253}
8ee5c842 1254EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
80c39712
TV		 1255
1256void dispc_enable_fifomerge(bool enable)
1257{
e6b0f884
TV		 1258 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1259 WARN_ON(enable);
1260 return;
1261 }
1262
80c39712
TV		 1263 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1264 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1265}
1266
83fa2f2e 1267void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1268 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1269 bool manual_update)
83fa2f2e
TV		 1270{
1271 /*
1272 * All sizes are in bytes. Both the buffer and burst are made of
1273 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1274 */
1275
1276 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1277 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1278 int i;
83fa2f2e
TV		 1279
1280 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1281 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1282
e0e405b9
TV		 1283 if (use_fifomerge) {
1284 total_fifo_size = 0;
392faa0e 1285 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1286 total_fifo_size += dispc_ovl_get_fifo_size(i);
1287 } else {
1288 total_fifo_size = ovl_fifo_size;
1289 }
1290
1291 /*
1292 * We use the same low threshold for both fifomerge and non-fifomerge
1293 * cases, but for fifomerge we calculate the high threshold using the
1294 * combined fifo size
1295 */
1296
3568f2a4 1297 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1298 *fifo_low = ovl_fifo_size - burst_size * 2;
1299 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1300 } else if (plane == OMAP_DSS_WB) {
1301 /*
1302 * Most optimal configuration for writeback is to push out data
1303 * to the interconnect the moment writeback pushes enough pixels
1304 * in the FIFO to form a burst
1305 */
1306 *fifo_low = 0;
1307 *fifo_high = burst_size;
e0e405b9
TV		 1308 } else {
1309 *fifo_low = ovl_fifo_size - burst_size;
1310 *fifo_high = total_fifo_size - buf_unit;
1311 }
83fa2f2e 1312}
8ee5c842 1313EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
83fa2f2e 1314
c64aa3a6
TV		 1315static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1316{
1317 int bit;
1318
1319 if (plane == OMAP_DSS_GFX)
1320 bit = 14;
1321 else
1322 bit = 23;
1323
1324 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1325}
1326
1327static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1328 int low, int high)
1329{
1330 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1331 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1332}
1333
1334static void dispc_init_mflag(void)
1335{
1336 int i;
1337
fe59e5cf
TV		 1338 /*
1339 * HACK: NV12 color format and MFLAG seem to have problems working
1340 * together: using two displays, and having an NV12 overlay on one of
1341 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1342 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1343 * remove the errors, but there doesn't seem to be a clear logic on
1344 * which values work and which not.
1345 *
1346 * As a work-around, set force MFLAG to always on.
1347 */
c64aa3a6 1348 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
fe59e5cf 1349 (1 << 0) | /* MFLAG_CTRL = force always on */
c64aa3a6
TV		 1350 (0 << 2)); /* MFLAG_START = disable */
1351
1352 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1353 u32 size = dispc_ovl_get_fifo_size(i);
1354 u32 unit = dss_feat_get_buffer_size_unit();
1355 u32 low, high;
1356
1357 dispc_ovl_set_mflag(i, true);
1358
1359 /*
1360 * Simulation team suggests below thesholds:
1361 * HT = fifosize * 5 / 8;
1362 * LT = fifosize * 4 / 8;
1363 */
1364
1365 low = size * 4 / 8 / unit;
1366 high = size * 5 / 8 / unit;
1367
1368 dispc_ovl_set_mflag_threshold(i, low, high);
1369 }
1370}
1371
f0e5caab 1372static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1373 int hinc, int vinc,
1374 enum omap_color_component color_comp)
80c39712
TV		 1375{
1376 u32 val;
80c39712 1377
0d66cbb5
AJ		 1378 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1379 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1380
0d66cbb5
AJ		 1381 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1382 &hinc_start, &hinc_end);
1383 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1384 &vinc_start, &vinc_end);
1385 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1386 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1387
0d66cbb5
AJ		 1388 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1389 } else {
1390 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1391 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1392 }
80c39712
TV		 1393}
1394
f0e5caab 1395static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1396{
1397 u32 val;
87a7484b 1398 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1399
87a7484b
AT		 1400 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1401 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1402
1403 val = FLD_VAL(vaccu, vert_start, vert_end) |
1404 FLD_VAL(haccu, hor_start, hor_end);
1405
9b372c2d 1406 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1407}
1408
f0e5caab 1409static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1410{
1411 u32 val;
87a7484b 1412 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1413
87a7484b
AT		 1414 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1415 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1416
1417 val = FLD_VAL(vaccu, vert_start, vert_end) |
1418 FLD_VAL(haccu, hor_start, hor_end);
1419
9b372c2d 1420 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1421}
1422
f0e5caab
TV		 1423static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1424 int vaccu)
ab5ca071
AJ		 1425{
1426 u32 val;
1427
1428 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1429 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1430}
1431
f0e5caab
TV		 1432static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1433 int vaccu)
ab5ca071
AJ		 1434{
1435 u32 val;
1436
1437 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1438 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1439}
80c39712 1440
f0e5caab 1441static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1442 u16 orig_width, u16 orig_height,
1443 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1444 bool five_taps, u8 rotation,
1445 enum omap_color_component color_comp)
80c39712 1446{
0d66cbb5 1447 int fir_hinc, fir_vinc;
80c39712 1448
ed14a3ce
AJ		 1449 fir_hinc = 1024 * orig_width / out_width;
1450 fir_vinc = 1024 * orig_height / out_height;
80c39712 1451
debd9074
CM		 1452 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1453 color_comp);
f0e5caab 1454 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1455}
1456
05dd0f53
CM		 1457static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1458 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1459 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1460{
1461 int h_accu2_0, h_accu2_1;
1462 int v_accu2_0, v_accu2_1;
1463 int chroma_hinc, chroma_vinc;
1464 int idx;
1465
1466 struct accu {
1467 s8 h0_m, h0_n;
1468 s8 h1_m, h1_n;
1469 s8 v0_m, v0_n;
1470 s8 v1_m, v1_n;
1471 };
1472
1473 const struct accu *accu_table;
1474 const struct accu *accu_val;
1475
1476 static const struct accu accu_nv12[4] = {
1477 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1478 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1479 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1480 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1481 };
1482
1483 static const struct accu accu_nv12_ilace[4] = {
1484 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1485 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1486 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1487 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1488 };
1489
1490 static const struct accu accu_yuv[4] = {
1491 { 0, 1, 0, 1, 0, 1, 0, 1 },
1492 { 0, 1, 0, 1, 0, 1, 0, 1 },
1493 { -1, 1, 0, 1, 0, 1, 0, 1 },
1494 { 0, 1, 0, 1, -1, 1, 0, 1 },
1495 };
1496
1497 switch (rotation) {
1498 case OMAP_DSS_ROT_0:
1499 idx = 0;
1500 break;
1501 case OMAP_DSS_ROT_90:
1502 idx = 1;
1503 break;
1504 case OMAP_DSS_ROT_180:
1505 idx = 2;
1506 break;
1507 case OMAP_DSS_ROT_270:
1508 idx = 3;
1509 break;
1510 default:
1511 BUG();
c6eee968 1512 return;
05dd0f53
CM		 1513 }
1514
1515 switch (color_mode) {
1516 case OMAP_DSS_COLOR_NV12:
1517 if (ilace)
1518 accu_table = accu_nv12_ilace;
1519 else
1520 accu_table = accu_nv12;
1521 break;
1522 case OMAP_DSS_COLOR_YUV2:
1523 case OMAP_DSS_COLOR_UYVY:
1524 accu_table = accu_yuv;
1525 break;
1526 default:
1527 BUG();
c6eee968 1528 return;
05dd0f53
CM		 1529 }
1530
1531 accu_val = &accu_table[idx];
1532
1533 chroma_hinc = 1024 * orig_width / out_width;
1534 chroma_vinc = 1024 * orig_height / out_height;
1535
1536 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1537 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1538 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1539 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1540
1541 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1542 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1543}
1544
f0e5caab 1545static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1546 u16 orig_width, u16 orig_height,
1547 u16 out_width, u16 out_height,
1548 bool ilace, bool five_taps,
1549 bool fieldmode, enum omap_color_mode color_mode,
1550 u8 rotation)
1551{
1552 int accu0 = 0;
1553 int accu1 = 0;
1554 u32 l;
80c39712 1555
f0e5caab 1556 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1557 out_width, out_height, five_taps,
1558 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1559 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1560
87a7484b
AT		 1561 /* RESIZEENABLE and VERTICALTAPS */
1562 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1563 l |= (orig_width != out_width) ? (1 << 5) : 0;
1564 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1565 l |= five_taps ? (1 << 21) : 0;
80c39712 1566
87a7484b
AT		 1567 /* VRESIZECONF and HRESIZECONF */
1568 if (dss_has_feature(FEAT_RESIZECONF)) {
1569 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1570 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1571 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1572 }
80c39712 1573
87a7484b
AT		 1574 /* LINEBUFFERSPLIT */
1575 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1576 l &= ~(0x1 << 22);
1577 l |= five_taps ? (1 << 22) : 0;
1578 }
80c39712 1579
9b372c2d 1580 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1581
1582 /*
1583 * field 0 = even field = bottom field
1584 * field 1 = odd field = top field
1585 */
1586 if (ilace && !fieldmode) {
1587 accu1 = 0;
0d66cbb5 1588 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1589 if (accu0 >= 1024/2) {
1590 accu1 = 1024/2;
1591 accu0 -= accu1;
1592 }
1593 }
1594
f0e5caab
TV		 1595 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1596 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1597}
1598
f0e5caab 1599static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1600 u16 orig_width, u16 orig_height,
1601 u16 out_width, u16 out_height,
1602 bool ilace, bool five_taps,
1603 bool fieldmode, enum omap_color_mode color_mode,
1604 u8 rotation)
1605{
1606 int scale_x = out_width != orig_width;
1607 int scale_y = out_height != orig_height;
f92afae2 1608 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1609
1610 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1611 return;
1612 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1613 color_mode != OMAP_DSS_COLOR_UYVY &&
1614 color_mode != OMAP_DSS_COLOR_NV12)) {
1615 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1616 if (plane != OMAP_DSS_WB)
1617 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1618 return;
1619 }
36377357
TV		 1620
1621 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1622 out_height, ilace, color_mode, rotation);
1623
0d66cbb5
AJ		 1624 switch (color_mode) {
1625 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1626 if (chroma_upscale) {
1627 /* UV is subsampled by 2 horizontally and vertically */
1628 orig_height >>= 1;
1629 orig_width >>= 1;
1630 } else {
1631 /* UV is downsampled by 2 horizontally and vertically */
1632 orig_height <<= 1;
1633 orig_width <<= 1;
1634 }
1635
0d66cbb5
AJ		 1636 break;
1637 case OMAP_DSS_COLOR_YUV2:
1638 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1639 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1640 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1641 rotation == OMAP_DSS_ROT_180) {
1642 if (chroma_upscale)
1643 /* UV is subsampled by 2 horizontally */
1644 orig_width >>= 1;
1645 else
1646 /* UV is downsampled by 2 horizontally */
1647 orig_width <<= 1;
1648 }
1649
0d66cbb5
AJ		 1650 /* must use FIR for YUV422 if rotated */
1651 if (rotation != OMAP_DSS_ROT_0)
1652 scale_x = scale_y = true;
20fbb50b 1653
0d66cbb5
AJ		 1654 break;
1655 default:
1656 BUG();
c6eee968 1657 return;
0d66cbb5
AJ		 1658 }
1659
1660 if (out_width != orig_width)
1661 scale_x = true;
1662 if (out_height != orig_height)
1663 scale_y = true;
1664
f0e5caab 1665 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1666 out_width, out_height, five_taps,
1667 rotation, DISPC_COLOR_COMPONENT_UV);
1668
2a5561b1
AT		 1669 if (plane != OMAP_DSS_WB)
1670 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1671 (scale_x || scale_y) ? 1 : 0, 8, 8);
1672
0d66cbb5
AJ		 1673 /* set H scaling */
1674 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1675 /* set V scaling */
1676 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1677}
1678
f0e5caab 1679static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1680 u16 orig_width, u16 orig_height,
1681 u16 out_width, u16 out_height,
1682 bool ilace, bool five_taps,
1683 bool fieldmode, enum omap_color_mode color_mode,
1684 u8 rotation)
1685{
1686 BUG_ON(plane == OMAP_DSS_GFX);
1687
f0e5caab 1688 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1689 orig_width, orig_height,
1690 out_width, out_height,
1691 ilace, five_taps,
1692 fieldmode, color_mode,
1693 rotation);
1694
f0e5caab 1695 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1696 orig_width, orig_height,
1697 out_width, out_height,
1698 ilace, five_taps,
1699 fieldmode, color_mode,
1700 rotation);
1701}
1702
f0e5caab 1703static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1704 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1705 bool mirroring, enum omap_color_mode color_mode)
1706{
87a7484b
AT		 1707 bool row_repeat = false;
1708 int vidrot = 0;
1709
80c39712
TV		 1710 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1711 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1712
1713 if (mirroring) {
1714 switch (rotation) {
1715 case OMAP_DSS_ROT_0:
1716 vidrot = 2;
1717 break;
1718 case OMAP_DSS_ROT_90:
1719 vidrot = 1;
1720 break;
1721 case OMAP_DSS_ROT_180:
1722 vidrot = 0;
1723 break;
1724 case OMAP_DSS_ROT_270:
1725 vidrot = 3;
1726 break;
1727 }
1728 } else {
1729 switch (rotation) {
1730 case OMAP_DSS_ROT_0:
1731 vidrot = 0;
1732 break;
1733 case OMAP_DSS_ROT_90:
1734 vidrot = 1;
1735 break;
1736 case OMAP_DSS_ROT_180:
1737 vidrot = 2;
1738 break;
1739 case OMAP_DSS_ROT_270:
1740 vidrot = 3;
1741 break;
1742 }
1743 }
1744
80c39712 1745 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1746 row_repeat = true;
80c39712 1747 else
87a7484b 1748 row_repeat = false;
80c39712 1749 }
87a7484b 1750
3397cc6a
TV		 1751 /*
1752 * OMAP4/5 Errata i631:
1753 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1754 * rows beyond the framebuffer, which may cause OCP error.
1755 */
1756 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1757 rotation_type != OMAP_DSS_ROT_TILER)
1758 vidrot = 1;
1759
9b372c2d 1760 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1761 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1762 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1763 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1764
1765 if (color_mode == OMAP_DSS_COLOR_NV12) {
1766 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1767 (rotation == OMAP_DSS_ROT_0 ||
1768 rotation == OMAP_DSS_ROT_180);
1769 /* DOUBLESTRIDE */
1770 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1771 }
1772
80c39712
TV		 1773}
1774
1775static int color_mode_to_bpp(enum omap_color_mode color_mode)
1776{
1777 switch (color_mode) {
1778 case OMAP_DSS_COLOR_CLUT1:
1779 return 1;
1780 case OMAP_DSS_COLOR_CLUT2:
1781 return 2;
1782 case OMAP_DSS_COLOR_CLUT4:
1783 return 4;
1784 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1785 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1786 return 8;
1787 case OMAP_DSS_COLOR_RGB12U:
1788 case OMAP_DSS_COLOR_RGB16:
1789 case OMAP_DSS_COLOR_ARGB16:
1790 case OMAP_DSS_COLOR_YUV2:
1791 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1792 case OMAP_DSS_COLOR_RGBA16:
1793 case OMAP_DSS_COLOR_RGBX16:
1794 case OMAP_DSS_COLOR_ARGB16_1555:
1795 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1796 return 16;
1797 case OMAP_DSS_COLOR_RGB24P:
1798 return 24;
1799 case OMAP_DSS_COLOR_RGB24U:
1800 case OMAP_DSS_COLOR_ARGB32:
1801 case OMAP_DSS_COLOR_RGBA32:
1802 case OMAP_DSS_COLOR_RGBX32:
1803 return 32;
1804 default:
1805 BUG();
c6eee968 1806 return 0;
80c39712
TV		 1807 }
1808}
1809
1810static s32 pixinc(int pixels, u8 ps)
1811{
1812 if (pixels == 1)
1813 return 1;
1814 else if (pixels > 1)
1815 return 1 + (pixels - 1) * ps;
1816 else if (pixels < 0)
1817 return 1 - (-pixels + 1) * ps;
1818 else
1819 BUG();
c6eee968 1820 return 0;
80c39712
TV		 1821}
1822
1823static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1824 u16 screen_width,
1825 u16 width, u16 height,
1826 enum omap_color_mode color_mode, bool fieldmode,
1827 unsigned int field_offset,
1828 unsigned *offset0, unsigned *offset1,
aed74b55 1829 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1830{
1831 u8 ps;
1832
1833 /* FIXME CLUT formats */
1834 switch (color_mode) {
1835 case OMAP_DSS_COLOR_CLUT1:
1836 case OMAP_DSS_COLOR_CLUT2:
1837 case OMAP_DSS_COLOR_CLUT4:
1838 case OMAP_DSS_COLOR_CLUT8:
1839 BUG();
1840 return;
1841 case OMAP_DSS_COLOR_YUV2:
1842 case OMAP_DSS_COLOR_UYVY:
1843 ps = 4;
1844 break;
1845 default:
1846 ps = color_mode_to_bpp(color_mode) / 8;
1847 break;
1848 }
1849
1850 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1851 width, height);
1852
1853 /*
1854 * field 0 = even field = bottom field
1855 * field 1 = odd field = top field
1856 */
1857 switch (rotation + mirror * 4) {
1858 case OMAP_DSS_ROT_0:
1859 case OMAP_DSS_ROT_180:
1860 /*
1861 * If the pixel format is YUV or UYVY divide the width
1862 * of the image by 2 for 0 and 180 degree rotation.
1863 */
1864 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1865 color_mode == OMAP_DSS_COLOR_UYVY)
1866 width = width >> 1;
1867 case OMAP_DSS_ROT_90:
1868 case OMAP_DSS_ROT_270:
1869 *offset1 = 0;
1870 if (field_offset)
1871 *offset0 = field_offset * screen_width * ps;
1872 else
1873 *offset0 = 0;
1874
aed74b55
CM		 1875 *row_inc = pixinc(1 +
1876 (y_predecim * screen_width - x_predecim * width) +
1877 (fieldmode ? screen_width : 0), ps);
1878 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1879 break;
1880
1881 case OMAP_DSS_ROT_0 + 4:
1882 case OMAP_DSS_ROT_180 + 4:
1883 /* If the pixel format is YUV or UYVY divide the width
1884 * of the image by 2 for 0 degree and 180 degree
1885 */
1886 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1887 color_mode == OMAP_DSS_COLOR_UYVY)
1888 width = width >> 1;
1889 case OMAP_DSS_ROT_90 + 4:
1890 case OMAP_DSS_ROT_270 + 4:
1891 *offset1 = 0;
1892 if (field_offset)
1893 *offset0 = field_offset * screen_width * ps;
1894 else
1895 *offset0 = 0;
aed74b55
CM		 1896 *row_inc = pixinc(1 -
1897 (y_predecim * screen_width + x_predecim * width) -
1898 (fieldmode ? screen_width : 0), ps);
1899 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1900 break;
1901
1902 default:
1903 BUG();
c6eee968 1904 return;
80c39712
TV		 1905 }
1906}
1907
1908static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1909 u16 screen_width,
1910 u16 width, u16 height,
1911 enum omap_color_mode color_mode, bool fieldmode,
1912 unsigned int field_offset,
1913 unsigned *offset0, unsigned *offset1,
aed74b55 1914 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1915{
1916 u8 ps;
1917 u16 fbw, fbh;
1918
1919 /* FIXME CLUT formats */
1920 switch (color_mode) {
1921 case OMAP_DSS_COLOR_CLUT1:
1922 case OMAP_DSS_COLOR_CLUT2:
1923 case OMAP_DSS_COLOR_CLUT4:
1924 case OMAP_DSS_COLOR_CLUT8:
1925 BUG();
1926 return;
1927 default:
1928 ps = color_mode_to_bpp(color_mode) / 8;
1929 break;
1930 }
1931
1932 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1933 width, height);
1934
1935 /* width & height are overlay sizes, convert to fb sizes */
1936
1937 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1938 fbw = width;
1939 fbh = height;
1940 } else {
1941 fbw = height;
1942 fbh = width;
1943 }
1944
1945 /*
1946 * field 0 = even field = bottom field
1947 * field 1 = odd field = top field
1948 */
1949 switch (rotation + mirror * 4) {
1950 case OMAP_DSS_ROT_0:
1951 *offset1 = 0;
1952 if (field_offset)
1953 *offset0 = *offset1 + field_offset * screen_width * ps;
1954 else
1955 *offset0 = *offset1;
aed74b55
CM		 1956 *row_inc = pixinc(1 +
1957 (y_predecim * screen_width - fbw * x_predecim) +
1958 (fieldmode ? screen_width : 0), ps);
1959 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1960 color_mode == OMAP_DSS_COLOR_UYVY)
1961 *pix_inc = pixinc(x_predecim, 2 * ps);
1962 else
1963 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1964 break;
1965 case OMAP_DSS_ROT_90:
1966 *offset1 = screen_width * (fbh - 1) * ps;
1967 if (field_offset)
1968 *offset0 = *offset1 + field_offset * ps;
1969 else
1970 *offset0 = *offset1;
aed74b55
CM		 1971 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1972 y_predecim + (fieldmode ? 1 : 0), ps);
1973 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1974 break;
1975 case OMAP_DSS_ROT_180:
1976 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1977 if (field_offset)
1978 *offset0 = *offset1 - field_offset * screen_width * ps;
1979 else
1980 *offset0 = *offset1;
1981 *row_inc = pixinc(-1 -
aed74b55
CM		 1982 (y_predecim * screen_width - fbw * x_predecim) -
1983 (fieldmode ? screen_width : 0), ps);
1984 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1985 color_mode == OMAP_DSS_COLOR_UYVY)
1986 *pix_inc = pixinc(-x_predecim, 2 * ps);
1987 else
1988 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1989 break;
1990 case OMAP_DSS_ROT_270:
1991 *offset1 = (fbw - 1) * ps;
1992 if (field_offset)
1993 *offset0 = *offset1 - field_offset * ps;
1994 else
1995 *offset0 = *offset1;
aed74b55
CM		 1996 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1997 y_predecim - (fieldmode ? 1 : 0), ps);
1998 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1999 break;
2000
2001 /* mirroring */
2002 case OMAP_DSS_ROT_0 + 4:
2003 *offset1 = (fbw - 1) * ps;
2004 if (field_offset)
2005 *offset0 = *offset1 + field_offset * screen_width * ps;
2006 else
2007 *offset0 = *offset1;
aed74b55 2008 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 2009 (fieldmode ? screen_width : 0),
2010 ps);
aed74b55
CM		 2011 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2012 color_mode == OMAP_DSS_COLOR_UYVY)
2013 *pix_inc = pixinc(-x_predecim, 2 * ps);
2014 else
2015 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2016 break;
2017
2018 case OMAP_DSS_ROT_90 + 4:
2019 *offset1 = 0;
2020 if (field_offset)
2021 *offset0 = *offset1 + field_offset * ps;
2022 else
2023 *offset0 = *offset1;
aed74b55
CM		 2024 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2025 y_predecim + (fieldmode ? 1 : 0),
80c39712 2026 ps);
aed74b55 2027 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2028 break;
2029
2030 case OMAP_DSS_ROT_180 + 4:
2031 *offset1 = screen_width * (fbh - 1) * ps;
2032 if (field_offset)
2033 *offset0 = *offset1 - field_offset * screen_width * ps;
2034 else
2035 *offset0 = *offset1;
aed74b55 2036 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 2037 (fieldmode ? screen_width : 0),
2038 ps);
aed74b55
CM		 2039 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2040 color_mode == OMAP_DSS_COLOR_UYVY)
2041 *pix_inc = pixinc(x_predecim, 2 * ps);
2042 else
2043 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2044 break;
2045
2046 case OMAP_DSS_ROT_270 + 4:
2047 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2048 if (field_offset)
2049 *offset0 = *offset1 - field_offset * ps;
2050 else
2051 *offset0 = *offset1;
aed74b55
CM		 2052 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2053 y_predecim - (fieldmode ? 1 : 0),
80c39712 2054 ps);
aed74b55 2055 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2056 break;
2057
2058 default:
2059 BUG();
c6eee968 2060 return;
80c39712
TV		 2061 }
2062}
2063
65e006ff
CM		 2064static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2065 enum omap_color_mode color_mode, bool fieldmode,
2066 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2067 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2068{
2069 u8 ps;
2070
2071 switch (color_mode) {
2072 case OMAP_DSS_COLOR_CLUT1:
2073 case OMAP_DSS_COLOR_CLUT2:
2074 case OMAP_DSS_COLOR_CLUT4:
2075 case OMAP_DSS_COLOR_CLUT8:
2076 BUG();
2077 return;
2078 default:
2079 ps = color_mode_to_bpp(color_mode) / 8;
2080 break;
2081 }
2082
2083 DSSDBG("scrw %d, width %d\n", screen_width, width);
2084
2085 /*
2086 * field 0 = even field = bottom field
2087 * field 1 = odd field = top field
2088 */
2089 *offset1 = 0;
2090 if (field_offset)
2091 *offset0 = *offset1 + field_offset * screen_width * ps;
2092 else
2093 *offset0 = *offset1;
2094 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2095 (fieldmode ? screen_width : 0), ps);
2096 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2097 color_mode == OMAP_DSS_COLOR_UYVY)
2098 *pix_inc = pixinc(x_predecim, 2 * ps);
2099 else
2100 *pix_inc = pixinc(x_predecim, ps);
2101}
2102
7faa9233
CM		 2103/*
2104 * This function is used to avoid synclosts in OMAP3, because of some
2105 * undocumented horizontal position and timing related limitations.
2106 */
465ec13f 2107static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2108 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2109 u16 width, u16 height, u16 out_width, u16 out_height,
2110 bool five_taps)
7faa9233 2111{
230edc03 2112 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2113 unsigned long nonactive;
7faa9233
CM		 2114 static const u8 limits[3] = { 8, 10, 20 };
2115 u64 val, blank;
2116 int i;
2117
81ab95b7 2118 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2119
2120 i = 0;
2121 if (out_height < height)
2122 i++;
2123 if (out_width < width)
2124 i++;
81ab95b7 2125 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2126 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2127 if (blank <= limits[i])
2128 return -EINVAL;
2129
e4998634
ID		 2130 /* FIXME add checks for 3-tap filter once the limitations are known */
2131 if (!five_taps)
2132 return 0;
2133
7faa9233
CM		 2134 /*
2135 * Pixel data should be prepared before visible display point starts.
2136 * So, atleast DS-2 lines must have already been fetched by DISPC
2137 * during nonactive - pos_x period.
2138 */
2139 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2140 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2141 val, max(0, ds - 2) * width);
2142 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2143 return -EINVAL;
2144
2145 /*
2146 * All lines need to be refilled during the nonactive period of which
2147 * only one line can be loaded during the active period. So, atleast
2148 * DS - 1 lines should be loaded during nonactive period.
2149 */
2150 val = div_u64((u64)nonactive * lclk, pclk);
2151 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2152 val, max(0, ds - 1) * width);
2153 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2154 return -EINVAL;
2155
2156 return 0;
2157}
2158
8702ee50 2159static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2160 const struct omap_video_timings *mgr_timings, u16 width,
2161 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2162 enum omap_color_mode color_mode)
80c39712 2163{
8b53d991 2164 u32 core_clk = 0;
3e8a6ff2 2165 u64 tmp;
80c39712 2166
7282f1b7
CM		 2167 if (height <= out_height && width <= out_width)
2168 return (unsigned long) pclk;
2169
80c39712 2170 if (height > out_height) {
81ab95b7 2171 unsigned int ppl = mgr_timings->x_res;
80c39712 2172
c582935c 2173 tmp = (u64)pclk * height * out_width;
80c39712 2174 do_div(tmp, 2 * out_height * ppl);
8b53d991 2175 core_clk = tmp;
80c39712 2176
2d9c5597
VS		 2177 if (height > 2 * out_height) {
2178 if (ppl == out_width)
2179 return 0;
2180
c582935c 2181 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
80c39712 2182 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2183 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2184 }
2185 }
2186
2187 if (width > out_width) {
c582935c 2188 tmp = (u64)pclk * width;
80c39712 2189 do_div(tmp, out_width);
8b53d991 2190 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2191
2192 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2193 core_clk <<= 1;
80c39712
TV		 2194 }
2195
8b53d991 2196 return core_clk;
80c39712
TV		 2197}
2198
8702ee50 2199static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2200 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2201{
dcbe765b
CM		 2202 if (height > out_height && width > out_width)
2203 return pclk * 4;
2204 else
2205 return pclk * 2;
2206}
2207
8702ee50 2208static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2209 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2210{
2211 unsigned int hf, vf;
2212
2213 /*
2214 * FIXME how to determine the 'A' factor
2215 * for the no downscaling case ?
2216 */
2217
2218 if (width > 3 * out_width)
2219 hf = 4;
2220 else if (width > 2 * out_width)
2221 hf = 3;
2222 else if (width > out_width)
2223 hf = 2;
2224 else
2225 hf = 1;
80c39712
TV		 2226 if (height > out_height)
2227 vf = 2;
2228 else
2229 vf = 1;
2230
dcbe765b
CM		 2231 return pclk * vf * hf;
2232}
2233
8702ee50 2234static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2235 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2236{
8ba85306
AT		 2237 /*
2238 * If the overlay/writeback is in mem to mem mode, there are no
2239 * downscaling limitations with respect to pixel clock, return 1 as
2240 * required core clock to represent that we have sufficient enough
2241 * core clock to do maximum downscaling
2242 */
2243 if (mem_to_mem)
2244 return 1;
2245
dcbe765b
CM		 2246 if (width > out_width)
2247 return DIV_ROUND_UP(pclk, out_width) * width;
2248 else
2249 return pclk;
2250}
2251
0c6921de 2252static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2253 const struct omap_video_timings *mgr_timings,
2254 u16 width, u16 height, u16 out_width, u16 out_height,
2255 enum omap_color_mode color_mode, bool *five_taps,
2256 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2257 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2258{
2259 int error;
2260 u16 in_width, in_height;
2261 int min_factor = min(*decim_x, *decim_y);
2262 const int maxsinglelinewidth =
2263 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2264
dcbe765b
CM		 2265 *five_taps = false;
2266
2267 do {
eec77da2
TV		 2268 in_height = height / *decim_y;
2269 in_width = width / *decim_x;
8702ee50 2270 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2271 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2272 error = (in_width > maxsinglelinewidth || !*core_clk ||
2273 *core_clk > dispc_core_clk_rate());
2274 if (error) {
2275 if (*decim_x == *decim_y) {
2276 *decim_x = min_factor;
2277 ++*decim_y;
2278 } else {
2279 swap(*decim_x, *decim_y);
2280 if (*decim_x < *decim_y)
2281 ++*decim_x;
2282 }
2283 }
2284 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2285
3ce17b48
TV		 2286 if (error) {
2287 DSSERR("failed to find scaling settings\n");
2288 return -EINVAL;
2289 }
2290
dcbe765b
CM		 2291 if (in_width > maxsinglelinewidth) {
2292 DSSERR("Cannot scale max input width exceeded");
2293 return -EINVAL;
2294 }
2295 return 0;
2296}
2297
0c6921de 2298static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2299 const struct omap_video_timings *mgr_timings,
2300 u16 width, u16 height, u16 out_width, u16 out_height,
2301 enum omap_color_mode color_mode, bool *five_taps,
2302 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2303 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2304{
2305 int error;
2306 u16 in_width, in_height;
dcbe765b
CM		 2307 const int maxsinglelinewidth =
2308 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2309
2310 do {
eec77da2
TV		 2311 in_height = height / *decim_y;
2312 in_width = width / *decim_x;
e4998634 2313 *five_taps = in_height > out_height;
dcbe765b
CM		 2314
2315 if (in_width > maxsinglelinewidth)
2316 if (in_height > out_height &&
2317 in_height < out_height * 2)
2318 *five_taps = false;
e4998634
ID		 2319again:
2320 if (*five_taps)
2321 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2322 in_width, in_height, out_width,
2323 out_height, color_mode);
2324 else
8702ee50 2325 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2326 in_height, out_width, out_height,
2327 mem_to_mem);
dcbe765b 2328
e4998634
ID		 2329 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2330 pos_x, in_width, in_height, out_width,
2331 out_height, *five_taps);
2332 if (error && *five_taps) {
2333 *five_taps = false;
2334 goto again;
2335 }
2336
dcbe765b
CM		 2337 error = (error || in_width > maxsinglelinewidth * 2 ||
2338 (in_width > maxsinglelinewidth && *five_taps) ||
2339 !*core_clk || *core_clk > dispc_core_clk_rate());
ab6b2582
TV		 2340
2341 if (!error) {
2342 /* verify that we're inside the limits of scaler */
2343 if (in_width / 4 > out_width)
2344 error = 1;
2345
2346 if (*five_taps) {
2347 if (in_height / 4 > out_height)
2348 error = 1;
dcbe765b 2349 } else {
ab6b2582
TV		 2350 if (in_height / 2 > out_height)
2351 error = 1;
dcbe765b
CM		 2352 }
2353 }
ab6b2582 2354
7059e3d8
TV		 2355 if (error)
2356 ++*decim_y;
dcbe765b
CM		 2357 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2358
3ce17b48
TV		 2359 if (error) {
2360 DSSERR("failed to find scaling settings\n");
2361 return -EINVAL;
2362 }
2363
f5a73482
TV		 2364 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2365 in_height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2366 DSSERR("horizontal timing too tight\n");
2367 return -EINVAL;
7282f1b7 2368 }
dcbe765b
CM		 2369
2370 if (in_width > (maxsinglelinewidth * 2)) {
2371 DSSERR("Cannot setup scaling");
2372 DSSERR("width exceeds maximum width possible");
2373 return -EINVAL;
2374 }
2375
2376 if (in_width > maxsinglelinewidth && *five_taps) {
2377 DSSERR("cannot setup scaling with five taps");
2378 return -EINVAL;
2379 }
2380 return 0;
2381}
2382
0c6921de 2383static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2384 const struct omap_video_timings *mgr_timings,
2385 u16 width, u16 height, u16 out_width, u16 out_height,
2386 enum omap_color_mode color_mode, bool *five_taps,
2387 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2388 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2389{
2390 u16 in_width, in_width_max;
2391 int decim_x_min = *decim_x;
eec77da2 2392 u16 in_height = height / *decim_y;
dcbe765b
CM		 2393 const int maxsinglelinewidth =
2394 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2395 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2396
5d501085
AT		 2397 if (mem_to_mem) {
2398 in_width_max = out_width * maxdownscale;
2399 } else {
8ba85306
AT		 2400 in_width_max = dispc_core_clk_rate() /
2401 DIV_ROUND_UP(pclk, out_width);
5d501085 2402 }
dcbe765b 2403
dcbe765b
CM		 2404 *decim_x = DIV_ROUND_UP(width, in_width_max);
2405
2406 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2407 if (*decim_x > *x_predecim)
2408 return -EINVAL;
2409
2410 do {
eec77da2 2411 in_width = width / *decim_x;
dcbe765b
CM		 2412 } while (*decim_x <= *x_predecim &&
2413 in_width > maxsinglelinewidth && ++*decim_x);
2414
2415 if (in_width > maxsinglelinewidth) {
2416 DSSERR("Cannot scale width exceeds max line width");
2417 return -EINVAL;
2418 }
2419
8702ee50 2420 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2421 out_width, out_height, mem_to_mem);
dcbe765b 2422 return 0;
80c39712
TV		 2423}
2424
e4c5ae7f
TV		 2425#define DIV_FRAC(dividend, divisor) \
2426 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2427
74e16458 2428static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2429 enum omap_overlay_caps caps,
81ab95b7
AT		 2430 const struct omap_video_timings *mgr_timings,
2431 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2432 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2433 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2434 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2435{
0373cac6 2436 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2437 const int max_decim_limit = 16;
8b53d991 2438 unsigned long core_clk = 0;
dcbe765b 2439 int decim_x, decim_y, ret;
79ad75f2 2440
f95cb5eb
TV		 2441 if (width == out_width && height == out_height)
2442 return 0;
2443
4e1d3ca0
TV		 2444 if (pclk == 0 || mgr_timings->pixelclock == 0) {
2445 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2446 return -EINVAL;
2447 }
2448
5b54ed3e 2449 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2450 return -EINVAL;
79ad75f2 2451
74e16458 2452 if (mem_to_mem) {
1c031441
AT		 2453 *x_predecim = *y_predecim = 1;
2454 } else {
2455 *x_predecim = max_decim_limit;
2456 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2457 dss_has_feature(FEAT_BURST_2D)) ?
2458 2 : max_decim_limit;
2459 }
aed74b55
CM		 2460
2461 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2462 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2463 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2464 color_mode == OMAP_DSS_COLOR_CLUT8) {
2465 *x_predecim = 1;
2466 *y_predecim = 1;
2467 *five_taps = false;
2468 return 0;
2469 }
2470
2471 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2472 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2473
aed74b55 2474 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2475 return -EINVAL;
2476
aed74b55 2477 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2478 return -EINVAL;
2479
0c6921de 2480 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2481 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2482 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2483 mem_to_mem);
dcbe765b
CM		 2484 if (ret)
2485 return ret;
79ad75f2 2486
e4c5ae7f
TV		 2487 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2488 width, height,
2489 out_width, out_height,
2490 out_width / width, DIV_FRAC(out_width, width),
2491 out_height / height, DIV_FRAC(out_height, height),
2492
2493 decim_x, decim_y,
2494 width / decim_x, height / decim_y,
2495 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2496 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2497
2498 *five_taps ? 5 : 3,
2499 core_clk, dispc_core_clk_rate());
79ad75f2 2500
8b53d991 2501 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2502 DSSERR("failed to set up scaling, "
8b53d991
CM		 2503 "required core clk rate = %lu Hz, "
2504 "current core clk rate = %lu Hz\n",
2505 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2506 return -EINVAL;
2507 }
2508
aed74b55
CM		 2509 *x_predecim = decim_x;
2510 *y_predecim = decim_y;
79ad75f2
AT		 2511 return 0;
2512}
2513
f9b719b6
TV		 2514int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2515 const struct omap_overlay_info *oi,
2516 const struct omap_video_timings *timings,
2517 int *x_predecim, int *y_predecim)
2518{
2519 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2520 bool five_taps = true;
62a83183 2521 bool fieldmode = false;
f9b719b6
TV		 2522 u16 in_height = oi->height;
2523 u16 in_width = oi->width;
2524 bool ilace = timings->interlace;
2525 u16 out_width, out_height;
2526 int pos_x = oi->pos_x;
2527 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2528 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2529
2530 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2531 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2532
2533 if (ilace && oi->height == out_height)
62a83183 2534 fieldmode = true;
f9b719b6
TV		 2535
2536 if (ilace) {
2537 if (fieldmode)
2538 in_height /= 2;
2539 out_height /= 2;
2540
2541 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2542 in_height, out_height);
2543 }
2544
2545 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2546 return -EINVAL;
2547
2548 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2549 in_height, out_width, out_height, oi->color_mode,
2550 &five_taps, x_predecim, y_predecim, pos_x,
2551 oi->rotation_type, false);
2552}
348be69d 2553EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2554
84a880fd 2555static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2556 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2557 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2558 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2559 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2560 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2561 bool replication, const struct omap_video_timings *mgr_timings,
2562 bool mem_to_mem)
80c39712 2563{
7282f1b7 2564 bool five_taps = true;
62a83183 2565 bool fieldmode = false;
79ad75f2 2566 int r, cconv = 0;
80c39712
TV		 2567 unsigned offset0, offset1;
2568 s32 row_inc;
2569 s32 pix_inc;
6be0d73e 2570 u16 frame_width, frame_height;
80c39712 2571 unsigned int field_offset = 0;
84a880fd
AT		 2572 u16 in_height = height;
2573 u16 in_width = width;
aed74b55 2574 int x_predecim = 1, y_predecim = 1;
8050cbe4 2575 bool ilace = mgr_timings->interlace;
74e16458
TV		 2576 unsigned long pclk = dispc_plane_pclk_rate(plane);
2577 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2578
e566658f 2579 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2580 return -EINVAL;
2581
c4661b33
TV		 2582 switch (color_mode) {
2583 case OMAP_DSS_COLOR_YUV2:
2584 case OMAP_DSS_COLOR_UYVY:
2585 case OMAP_DSS_COLOR_NV12:
2586 if (in_width & 1) {
2587 DSSERR("input width %d is not even for YUV format\n",
2588 in_width);
2589 return -EINVAL;
2590 }
2591 break;
2592
2593 default:
2594 break;
2595 }
2596
84a880fd
AT		 2597 out_width = out_width == 0 ? width : out_width;
2598 out_height = out_height == 0 ? height : out_height;
cf073668 2599
84a880fd 2600 if (ilace && height == out_height)
62a83183 2601 fieldmode = true;
80c39712
TV		 2602
2603 if (ilace) {
2604 if (fieldmode)
aed74b55 2605 in_height /= 2;
8eeb7019 2606 pos_y /= 2;
aed74b55 2607 out_height /= 2;
80c39712
TV		 2608
2609 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2610 "out_height %d\n", in_height, pos_y,
2611 out_height);
80c39712
TV		 2612 }
2613
84a880fd 2614 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2615 return -EINVAL;
2616
74e16458 2617 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2618 in_height, out_width, out_height, color_mode,
2619 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2620 rotation_type, mem_to_mem);
79ad75f2
AT		 2621 if (r)
2622 return r;
80c39712 2623
eec77da2
TV		 2624 in_width = in_width / x_predecim;
2625 in_height = in_height / y_predecim;
aed74b55 2626
c4661b33
TV		 2627 if (x_predecim > 1 || y_predecim > 1)
2628 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2629 x_predecim, y_predecim, in_width, in_height);
2630
2631 switch (color_mode) {
2632 case OMAP_DSS_COLOR_YUV2:
2633 case OMAP_DSS_COLOR_UYVY:
2634 case OMAP_DSS_COLOR_NV12:
2635 if (in_width & 1) {
2636 DSSDBG("predecimated input width is not even for YUV format\n");
2637 DSSDBG("adjusting input width %d -> %d\n",
2638 in_width, in_width & ~1);
2639
2640 in_width &= ~1;
2641 }
2642 break;
2643
2644 default:
2645 break;
2646 }
2647
84a880fd
AT		 2648 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2649 color_mode == OMAP_DSS_COLOR_UYVY ||
2650 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2651 cconv = 1;
80c39712
TV		 2652
2653 if (ilace && !fieldmode) {
2654 /*
2655 * when downscaling the bottom field may have to start several
2656 * source lines below the top field. Unfortunately ACCUI
2657 * registers will only hold the fractional part of the offset
2658 * so the integer part must be added to the base address of the
2659 * bottom field.
2660 */
aed74b55 2661 if (!in_height || in_height == out_height)
80c39712
TV		 2662 field_offset = 0;
2663 else
aed74b55 2664 field_offset = in_height / out_height / 2;
80c39712
TV		 2665 }
2666
2667 /* Fields are independent but interleaved in memory. */
2668 if (fieldmode)
2669 field_offset = 1;
2670
c6eee968
TV		 2671 offset0 = 0;
2672 offset1 = 0;
2673 row_inc = 0;
2674 pix_inc = 0;
2675
6be0d73e
AT		 2676 if (plane == OMAP_DSS_WB) {
2677 frame_width = out_width;
2678 frame_height = out_height;
2679 } else {
2680 frame_width = in_width;
2681 frame_height = height;
2682 }
2683
84a880fd 2684 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2685 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2686 color_mode, fieldmode, field_offset,
65e006ff
CM		 2687 &offset0, &offset1, &row_inc, &pix_inc,
2688 x_predecim, y_predecim);
84a880fd 2689 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2690 calc_dma_rotation_offset(rotation, mirror, screen_width,
2691 frame_width, frame_height,
84a880fd 2692 color_mode, fieldmode, field_offset,
aed74b55
CM		 2693 &offset0, &offset1, &row_inc, &pix_inc,
2694 x_predecim, y_predecim);
80c39712 2695 else
84a880fd 2696 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2697 screen_width, frame_width, frame_height,
84a880fd 2698 color_mode, fieldmode, field_offset,
aed74b55
CM		 2699 &offset0, &offset1, &row_inc, &pix_inc,
2700 x_predecim, y_predecim);
80c39712
TV		 2701
2702 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2703 offset0, offset1, row_inc, pix_inc);
2704
84a880fd 2705 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2706
84a880fd 2707 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2708
84a880fd
AT		 2709 dispc_ovl_set_ba0(plane, paddr + offset0);
2710 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2711
84a880fd
AT		 2712 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2713 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2714 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2715 }
2716
f2aee319
TV		 2717 if (dispc.feat->last_pixel_inc_missing)
2718 row_inc += pix_inc - 1;
2719
f0e5caab
TV		 2720 dispc_ovl_set_row_inc(plane, row_inc);
2721 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2722
84a880fd 2723 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2724 in_height, out_width, out_height);
80c39712 2725
84a880fd 2726 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2727
78b687fc 2728 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2729
5b54ed3e 2730 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2731 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2732 out_height, ilace, five_taps, fieldmode,
84a880fd 2733 color_mode, rotation);
78b687fc 2734 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2735 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2736 }
2737
c35eeb2e
AT		 2738 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2739 color_mode);
80c39712 2740
84a880fd
AT		 2741 dispc_ovl_set_zorder(plane, caps, zorder);
2742 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2743 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2744
d79db853 2745 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2746
80c39712
TV		 2747 return 0;
2748}
2749
84a880fd 2750int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2751 bool replication, const struct omap_video_timings *mgr_timings,
2752 bool mem_to_mem)
84a880fd
AT		 2753{
2754 int r;
16bf20c7 2755 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2756 enum omap_channel channel;
2757
2758 channel = dispc_ovl_get_channel_out(plane);
2759
24f13a66
AB		 2760 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2761 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2762 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd
AT		 2763 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2764 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2765
16bf20c7 2766 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2767 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2768 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2769 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2770 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2771
2772 return r;
2773}
348be69d 2774EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2775
749feffa 2776int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2777 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2778{
2779 int r;
9e4a0fc7 2780 u32 l;
749feffa
AT		 2781 enum omap_plane plane = OMAP_DSS_WB;
2782 const int pos_x = 0, pos_y = 0;
2783 const u8 zorder = 0, global_alpha = 0;
2784 const bool replication = false;
9e4a0fc7 2785 bool truncation;
749feffa
AT		 2786 int in_width = mgr_timings->x_res;
2787 int in_height = mgr_timings->y_res;
2788 enum omap_overlay_caps caps =
2789 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2790
2791 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2792 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2793 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2794 wi->mirror);
2795
2796 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2797 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2798 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2799 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2800 replication, mgr_timings, mem_to_mem);
2801
2802 switch (wi->color_mode) {
2803 case OMAP_DSS_COLOR_RGB16:
2804 case OMAP_DSS_COLOR_RGB24P:
2805 case OMAP_DSS_COLOR_ARGB16:
2806 case OMAP_DSS_COLOR_RGBA16:
2807 case OMAP_DSS_COLOR_RGB12U:
2808 case OMAP_DSS_COLOR_ARGB16_1555:
2809 case OMAP_DSS_COLOR_XRGB16_1555:
2810 case OMAP_DSS_COLOR_RGBX16:
2811 truncation = true;
2812 break;
2813 default:
2814 truncation = false;
2815 break;
2816 }
2817
2818 /* setup extra DISPC_WB_ATTRIBUTES */
2819 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2820 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2821 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2822 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2823
2824 return r;
2825}
2826
f0e5caab 2827int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2828{
e6d80f95
TV		 2829 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2830
9b372c2d 2831 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2832
2833 return 0;
80c39712 2834}
348be69d 2835EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2836
04bd8ac1
TV		 2837bool dispc_ovl_enabled(enum omap_plane plane)
2838{
2839 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2840}
348be69d 2841EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2842
f1a813d3 2843void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2844{
efa70b3b
CM		 2845 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2846 /* flush posted write */
2847 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2848}
348be69d 2849EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2850
65398511
TV		 2851bool dispc_mgr_is_enabled(enum omap_channel channel)
2852{
2853 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2854}
348be69d 2855EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2856
0b23e5b8
AT		 2857void dispc_wb_enable(bool enable)
2858{
916188a4 2859 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2860}
2861
2862bool dispc_wb_is_enabled(void)
2863{
916188a4 2864 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2865}
2866
fb2cec1f 2867static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2868{
6ced40bf
AT		 2869 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2870 return;
2871
80c39712 2872 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2873}
2874
2875void dispc_lcd_enable_signal(bool enable)
2876{
6ced40bf
AT		 2877 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2878 return;
2879
80c39712 2880 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2881}
2882
2883void dispc_pck_free_enable(bool enable)
2884{
6ced40bf
AT		 2885 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2886 return;
2887
80c39712 2888 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2889}
2890
fb2cec1f 2891static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2892{
efa70b3b 2893 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2894}
2895
2896
fb2cec1f 2897static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2898{
d21f43bc 2899 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2900}
2901
2902void dispc_set_loadmode(enum omap_dss_load_mode mode)
2903{
80c39712 2904 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2905}
2906
2907
c64dca40 2908static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2909{
8613b000 2910 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2911}
2912
c64dca40 2913static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2914 enum omap_dss_trans_key_type type,
2915 u32 trans_key)
2916{
efa70b3b 2917 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2918
8613b000 2919 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2920}
2921
c64dca40 2922static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2923{
efa70b3b 2924 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2925}
11354dd5 2926
c64dca40
TV		 2927static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2928 bool enable)
80c39712 2929{
11354dd5 2930 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2931 return;
2932
80c39712
TV		 2933 if (ch == OMAP_DSS_CHANNEL_LCD)
2934 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2935 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2936 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2937}
11354dd5 2938
c64dca40 2939void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2940 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2941{
2942 dispc_mgr_set_default_color(channel, info->default_color);
2943 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2944 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2945 dispc_mgr_enable_alpha_fixed_zorder(channel,
2946 info->partial_alpha_enabled);
2947 if (dss_has_feature(FEAT_CPR)) {
2948 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2949 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2950 }
2951}
348be69d 2952EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2953
fb2cec1f 2954static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2955{
2956 int code;
2957
2958 switch (data_lines) {
2959 case 12:
2960 code = 0;
2961 break;
2962 case 16:
2963 code = 1;
2964 break;
2965 case 18:
2966 code = 2;
2967 break;
2968 case 24:
2969 code = 3;
2970 break;
2971 default:
2972 BUG();
2973 return;
2974 }
2975
efa70b3b 2976 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2977}
2978
fb2cec1f 2979static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2980{
2981 u32 l;
569969d6 2982 int gpout0, gpout1;
80c39712
TV		 2983
2984 switch (mode) {
569969d6
AT		 2985 case DSS_IO_PAD_MODE_RESET:
2986 gpout0 = 0;
2987 gpout1 = 0;
80c39712 2988 break;
569969d6
AT		 2989 case DSS_IO_PAD_MODE_RFBI:
2990 gpout0 = 1;
80c39712
TV		 2991 gpout1 = 0;
2992 break;
569969d6
AT		 2993 case DSS_IO_PAD_MODE_BYPASS:
2994 gpout0 = 1;
80c39712
TV		 2995 gpout1 = 1;
2996 break;
80c39712
TV		 2997 default:
2998 BUG();
2999 return;
3000 }
3001
569969d6
AT		 3002 l = dispc_read_reg(DISPC_CONTROL);
3003 l = FLD_MOD(l, gpout0, 15, 15);
3004 l = FLD_MOD(l, gpout1, 16, 16);
3005 dispc_write_reg(DISPC_CONTROL, l);
3006}
3007
fb2cec1f 3008static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 3009{
efa70b3b 3010 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 3011}
3012
fb2cec1f
TV		 3013void dispc_mgr_set_lcd_config(enum omap_channel channel,
3014 const struct dss_lcd_mgr_config *config)
3015{
3016 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3017
3018 dispc_mgr_enable_stallmode(channel, config->stallmode);
3019 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3020
3021 dispc_mgr_set_clock_div(channel, &config->clock_info);
3022
3023 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3024
3025 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3026
3027 dispc_mgr_set_lcd_type_tft(channel);
3028}
348be69d 3029EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 3030
8f366162
AT		 3031static bool _dispc_mgr_size_ok(u16 width, u16 height)
3032{
33b89928
AT		 3033 return width <= dispc.feat->mgr_width_max &&
3034 height <= dispc.feat->mgr_height_max;
8f366162
AT		 3035}
3036
80c39712
TV		 3037static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3038 int vsw, int vfp, int vbp)
3039{
dcbe765b
CM		 3040 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3041 hfp < 1 || hfp > dispc.feat->hp_max ||
3042 hbp < 1 || hbp > dispc.feat->hp_max ||
3043 vsw < 1 || vsw > dispc.feat->sw_max ||
3044 vfp < 0 || vfp > dispc.feat->vp_max ||
3045 vbp < 0 || vbp > dispc.feat->vp_max)
3046 return false;
80c39712
TV		 3047 return true;
3048}
3049
ca5ca69c
AT		 3050static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3051 unsigned long pclk)
3052{
3053 if (dss_mgr_is_lcd(channel))
3054 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3055 else
3056 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3057}
3058
8f366162 3059bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 3060 const struct omap_video_timings *timings)
80c39712 3061{
eadd33bb
TV		 3062 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3063 return false;
8f366162 3064
eadd33bb
TV		 3065 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3066 return false;
ca5ca69c
AT		 3067
3068 if (dss_mgr_is_lcd(channel)) {
beb8384d 3069 /* TODO: OMAP4+ supports interlace for LCD outputs */
eadd33bb
TV		 3070 if (timings->interlace)
3071 return false;
beb8384d 3072
eadd33bb 3073 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
ca5ca69c 3074 timings->hbp, timings->vsw, timings->vfp,
eadd33bb
TV		 3075 timings->vbp))
3076 return false;
ca5ca69c 3077 }
8f366162 3078
eadd33bb 3079 return true;
80c39712
TV		 3080}
3081
26d9dd0d 3082static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3083 int hfp, int hbp, int vsw, int vfp, int vbp,
3084 enum omap_dss_signal_level vsync_level,
3085 enum omap_dss_signal_level hsync_level,
3086 enum omap_dss_signal_edge data_pclk_edge,
3087 enum omap_dss_signal_level de_level,
3088 enum omap_dss_signal_edge sync_pclk_edge)
3089
80c39712 3090{
655e2941 3091 u32 timing_h, timing_v, l;
ed351881 3092 bool onoff, rf, ipc, vs, hs, de;
80c39712 3093
dcbe765b
CM		 3094 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3095 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3096 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3097 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3098 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3099 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3100
64ba4f74
SS		 3101 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3102 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 3103
ed351881
TV		 3104 switch (vsync_level) {
3105 case OMAPDSS_SIG_ACTIVE_LOW:
3106 vs = true;
3107 break;
3108 case OMAPDSS_SIG_ACTIVE_HIGH:
3109 vs = false;
3110 break;
3111 default:
3112 BUG();
3113 }
3114
3115 switch (hsync_level) {
3116 case OMAPDSS_SIG_ACTIVE_LOW:
3117 hs = true;
3118 break;
3119 case OMAPDSS_SIG_ACTIVE_HIGH:
3120 hs = false;
3121 break;
3122 default:
3123 BUG();
3124 }
3125
3126 switch (de_level) {
3127 case OMAPDSS_SIG_ACTIVE_LOW:
3128 de = true;
3129 break;
3130 case OMAPDSS_SIG_ACTIVE_HIGH:
3131 de = false;
3132 break;
3133 default:
3134 BUG();
3135 }
3136
655e2941
AT		 3137 switch (data_pclk_edge) {
3138 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3139 ipc = false;
3140 break;
3141 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3142 ipc = true;
3143 break;
655e2941
AT		 3144 default:
3145 BUG();
3146 }
3147
7a16360d
TV		 3148 /* always use the 'rf' setting */
3149 onoff = true;
3150
655e2941 3151 switch (sync_pclk_edge) {
655e2941 3152 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
655e2941
AT		 3153 rf = false;
3154 break;
3155 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
655e2941
AT		 3156 rf = true;
3157 break;
3158 default:
3159 BUG();
cf6ac4ce 3160 }
655e2941 3161
d80e02ef
TV		 3162 l = FLD_VAL(onoff, 17, 17) |
3163 FLD_VAL(rf, 16, 16) |
ed351881 3164 FLD_VAL(de, 15, 15) |
d80e02ef 3165 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 3166 FLD_VAL(hs, 13, 13) |
3167 FLD_VAL(vs, 12, 12);
d80e02ef 3168
e5f80917
TV		 3169 /* always set ALIGN bit when available */
3170 if (dispc.feat->supports_sync_align)
3171 l |= (1 << 18);
3172
655e2941 3173 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 3174
3175 if (dispc.syscon_pol) {
3176 const int shifts[] = {
3177 [OMAP_DSS_CHANNEL_LCD] = 0,
3178 [OMAP_DSS_CHANNEL_LCD2] = 1,
3179 [OMAP_DSS_CHANNEL_LCD3] = 2,
3180 };
3181
3182 u32 mask, val;
3183
3184 mask = (1 << 0) | (1 << 3) | (1 << 6);
3185 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3186
3187 mask <<= 16 + shifts[channel];
3188 val <<= 16 + shifts[channel];
3189
3190 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3191 mask, val);
3192 }
80c39712
TV		 3193}
3194
3195/* change name to mode? */
c51d921a 3196void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3197 const struct omap_video_timings *timings)
80c39712
TV		 3198{
3199 unsigned xtot, ytot;
3200 unsigned long ht, vt;
2aefad49 3201 struct omap_video_timings t = *timings;
80c39712 3202
2aefad49 3203 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3204
2aefad49 3205 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3206 BUG();
c6eee968
TV		 3207 return;
3208 }
80c39712 3209
dd88b7a6 3210 if (dss_mgr_is_lcd(channel)) {
2aefad49 3211 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3212 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3213 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3214
2aefad49
AT		 3215 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3216 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3217
d8d78941
TV		 3218 ht = timings->pixelclock / xtot;
3219 vt = timings->pixelclock / xtot / ytot;
c51d921a 3220
d8d78941 3221 DSSDBG("pck %u\n", timings->pixelclock);
c51d921a 3222 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3223 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3224 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3225 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3226 t.de_level, t.sync_pclk_edge);
80c39712 3227
c51d921a 3228 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3229 } else {
23c8f88e 3230 if (t.interlace == true)
2aefad49 3231 t.y_res /= 2;
c51d921a 3232 }
8f366162 3233
2aefad49 3234 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 3235}
348be69d 3236EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3237
26d9dd0d 3238static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3239 u16 pck_div)
80c39712
TV		 3240{
3241 BUG_ON(lck_div < 1);
9eaaf207 3242 BUG_ON(pck_div < 1);
80c39712 3243
ce7fa5eb 3244 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3245 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 3246
3247 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3248 channel == OMAP_DSS_CHANNEL_LCD)
3249 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3250}
3251
26d9dd0d 3252static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3253 int *pck_div)
80c39712
TV		 3254{
3255 u32 l;
ce7fa5eb 3256 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3257 *lck_div = FLD_GET(l, 23, 16);
3258 *pck_div = FLD_GET(l, 7, 0);
3259}
3260
3261unsigned long dispc_fclk_rate(void)
3262{
2daea7af 3263 struct dss_pll *pll;
80c39712
TV		 3264 unsigned long r = 0;
3265
66534e8e 3266 switch (dss_get_dispc_clk_source()) {
89a35e51 3267 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3268 r = dss_get_dispc_clk_rate();
66534e8e 3269 break;
89a35e51 3270 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3271 pll = dss_pll_find("dsi0");
93550927
TV		 3272 if (!pll)
3273 pll = dss_pll_find("video0");
3274
2daea7af 3275 r = pll->cinfo.clkout[0];
66534e8e 3276 break;
5a8b572d 3277 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3278 pll = dss_pll_find("dsi1");
93550927
TV		 3279 if (!pll)
3280 pll = dss_pll_find("video1");
3281
2daea7af 3282 r = pll->cinfo.clkout[0];
5a8b572d 3283 break;
66534e8e
TA		 3284 default:
3285 BUG();
c6eee968 3286 return 0;
66534e8e
TA		 3287 }
3288
80c39712
TV		 3289 return r;
3290}
3291
26d9dd0d 3292unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3293{
2daea7af 3294 struct dss_pll *pll;
80c39712
TV		 3295 int lcd;
3296 unsigned long r;
3297 u32 l;
3298
c31cba8a
TV		 3299 if (dss_mgr_is_lcd(channel)) {
3300 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3301
c31cba8a 3302 lcd = FLD_GET(l, 23, 16);
80c39712 3303
c31cba8a
TV		 3304 switch (dss_get_lcd_clk_source(channel)) {
3305 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3306 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3307 break;
3308 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3309 pll = dss_pll_find("dsi0");
93550927
TV		 3310 if (!pll)
3311 pll = dss_pll_find("video0");
3312
2daea7af 3313 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3314 break;
3315 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3316 pll = dss_pll_find("dsi1");
93550927
TV		 3317 if (!pll)
3318 pll = dss_pll_find("video1");
3319
2daea7af 3320 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3321 break;
3322 default:
3323 BUG();
3324 return 0;
3325 }
80c39712 3326
c31cba8a
TV		 3327 return r / lcd;
3328 } else {
3329 return dispc_fclk_rate();
3330 }
80c39712
TV		 3331}
3332
26d9dd0d 3333unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3334{
80c39712 3335 unsigned long r;
80c39712 3336
dd88b7a6 3337 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3338 int pcd;
3339 u32 l;
80c39712 3340
c3dc6a7a 3341 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3342
c3dc6a7a 3343 pcd = FLD_GET(l, 7, 0);
80c39712 3344
c3dc6a7a
AT		 3345 r = dispc_mgr_lclk_rate(channel);
3346
3347 return r / pcd;
3348 } else {
5391e87d 3349 return dispc.tv_pclk_rate;
c3dc6a7a 3350 }
80c39712
TV		 3351}
3352
5391e87d
TV		 3353void dispc_set_tv_pclk(unsigned long pclk)
3354{
3355 dispc.tv_pclk_rate = pclk;
3356}
3357
8b53d991
CM		 3358unsigned long dispc_core_clk_rate(void)
3359{
7b3926b3 3360 return dispc.core_clk_rate;
8b53d991
CM		 3361}
3362
3e8a6ff2
AT		 3363static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3364{
251886d8
TV		 3365 enum omap_channel channel;
3366
3367 if (plane == OMAP_DSS_WB)
3368 return 0;
3369
3370 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3371
3372 return dispc_mgr_pclk_rate(channel);
3373}
3374
3375static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3376{
251886d8
TV		 3377 enum omap_channel channel;
3378
3379 if (plane == OMAP_DSS_WB)
3380 return 0;
3381
3382 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3383
c31cba8a 3384 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3385}
c31cba8a 3386
6f1891fc 3387static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3388{
3389 int lcd, pcd;
6f1891fc
CM		 3390 enum omap_dss_clk_source lcd_clk_src;
3391
3392 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3393
3394 lcd_clk_src = dss_get_lcd_clk_source(channel);
3395
3396 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3397 dss_get_generic_clk_source_name(lcd_clk_src),
3398 dss_feat_get_clk_source_name(lcd_clk_src));
3399
3400 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3401
3402 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3403 dispc_mgr_lclk_rate(channel), lcd);
3404 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3405 dispc_mgr_pclk_rate(channel), pcd);
3406}
3407
3408void dispc_dump_clocks(struct seq_file *s)
3409{
3410 int lcd;
0cf35df3 3411 u32 l;
89a35e51 3412 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3413
4fbafaf3
TV		 3414 if (dispc_runtime_get())
3415 return;
80c39712 3416
80c39712
TV		 3417 seq_printf(s, "- DISPC -\n");
3418
067a57e4
AT		 3419 seq_printf(s, "dispc fclk source = %s (%s)\n",
3420 dss_get_generic_clk_source_name(dispc_clk_src),
3421 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3422
3423 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3424
0cf35df3
MR		 3425 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3426 seq_printf(s, "- DISPC-CORE-CLK -\n");
3427 l = dispc_read_reg(DISPC_DIVISOR);
3428 lcd = FLD_GET(l, 23, 16);
3429
3430 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3431 (dispc_fclk_rate()/lcd), lcd);
3432 }
2a205f34 3433
6f1891fc 3434 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3435
6f1891fc
CM		 3436 if (dss_has_feature(FEAT_MGR_LCD2))
3437 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3438 if (dss_has_feature(FEAT_MGR_LCD3))
3439 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3440
3441 dispc_runtime_put();
80c39712
TV		 3442}
3443
e40402cf 3444static void dispc_dump_regs(struct seq_file *s)
80c39712 3445{
4dd2da15
AT		 3446 int i, j;
3447 const char *mgr_names[] = {
3448 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3449 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3450 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3451 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3452 };
3453 const char *ovl_names[] = {
3454 [OMAP_DSS_GFX] = "GFX",
3455 [OMAP_DSS_VIDEO1] = "VID1",
3456 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3457 [OMAP_DSS_VIDEO3] = "VID3",
06c525fe 3458 [OMAP_DSS_WB] = "WB",
4dd2da15
AT		 3459 };
3460 const char **p_names;
3461
9b372c2d 3462#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3463
4fbafaf3
TV		 3464 if (dispc_runtime_get())
3465 return;
80c39712 3466
5010be80 3467 /* DISPC common registers */
80c39712
TV		 3468 DUMPREG(DISPC_REVISION);
3469 DUMPREG(DISPC_SYSCONFIG);
3470 DUMPREG(DISPC_SYSSTATUS);
3471 DUMPREG(DISPC_IRQSTATUS);
3472 DUMPREG(DISPC_IRQENABLE);
3473 DUMPREG(DISPC_CONTROL);
3474 DUMPREG(DISPC_CONFIG);
3475 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3476 DUMPREG(DISPC_LINE_STATUS);
3477 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3478 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3479 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3480 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3481 if (dss_has_feature(FEAT_MGR_LCD2)) {
3482 DUMPREG(DISPC_CONTROL2);
3483 DUMPREG(DISPC_CONFIG2);
5010be80 3484 }
6f1891fc
CM		 3485 if (dss_has_feature(FEAT_MGR_LCD3)) {
3486 DUMPREG(DISPC_CONTROL3);
3487 DUMPREG(DISPC_CONFIG3);
3488 }
29fceeeb
TV		 3489 if (dss_has_feature(FEAT_MFLAG))
3490 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3491
3492#undef DUMPREG
3493
3494#define DISPC_REG(i, name) name(i)
4dd2da15 3495#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3496 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3497 dispc_read_reg(DISPC_REG(i, r)))
3498
4dd2da15 3499 p_names = mgr_names;
5010be80 3500
4dd2da15
AT		 3501 /* DISPC channel specific registers */
3502 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3503 DUMPREG(i, DISPC_DEFAULT_COLOR);
3504 DUMPREG(i, DISPC_TRANS_COLOR);
3505 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3506
4dd2da15
AT		 3507 if (i == OMAP_DSS_CHANNEL_DIGIT)
3508 continue;
5010be80 3509
4dd2da15
AT		 3510 DUMPREG(i, DISPC_TIMING_H);
3511 DUMPREG(i, DISPC_TIMING_V);
3512 DUMPREG(i, DISPC_POL_FREQ);
3513 DUMPREG(i, DISPC_DIVISORo);
5010be80 3514
4dd2da15
AT		 3515 DUMPREG(i, DISPC_DATA_CYCLE1);
3516 DUMPREG(i, DISPC_DATA_CYCLE2);
3517 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3518
332e9d70 3519 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3520 DUMPREG(i, DISPC_CPR_COEF_R);
3521 DUMPREG(i, DISPC_CPR_COEF_G);
3522 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3523 }
2a205f34 3524 }
80c39712 3525
4dd2da15
AT		 3526 p_names = ovl_names;
3527
3528 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3529 DUMPREG(i, DISPC_OVL_BA0);
3530 DUMPREG(i, DISPC_OVL_BA1);
3531 DUMPREG(i, DISPC_OVL_POSITION);
3532 DUMPREG(i, DISPC_OVL_SIZE);
3533 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3534 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3535 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3536 DUMPREG(i, DISPC_OVL_ROW_INC);
3537 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3538
4dd2da15
AT		 3539 if (dss_has_feature(FEAT_PRELOAD))
3540 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3541 if (dss_has_feature(FEAT_MFLAG))
3542 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3543
3544 if (i == OMAP_DSS_GFX) {
3545 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3546 DUMPREG(i, DISPC_OVL_TABLE_BA);
3547 continue;
3548 }
3549
3550 DUMPREG(i, DISPC_OVL_FIR);
3551 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3552 DUMPREG(i, DISPC_OVL_ACCU0);
3553 DUMPREG(i, DISPC_OVL_ACCU1);
3554 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3555 DUMPREG(i, DISPC_OVL_BA0_UV);
3556 DUMPREG(i, DISPC_OVL_BA1_UV);
3557 DUMPREG(i, DISPC_OVL_FIR2);
3558 DUMPREG(i, DISPC_OVL_ACCU2_0);
3559 DUMPREG(i, DISPC_OVL_ACCU2_1);
3560 }
3561 if (dss_has_feature(FEAT_ATTR2))
3562 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3563 }
5010be80 3564
06c525fe
TV		 3565 if (dss_feat_get_num_wbs()) {
3566 i = OMAP_DSS_WB;
3567 DUMPREG(i, DISPC_OVL_BA0);
3568 DUMPREG(i, DISPC_OVL_BA1);
3569 DUMPREG(i, DISPC_OVL_SIZE);
3570 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3571 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3572 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3573 DUMPREG(i, DISPC_OVL_ROW_INC);
3574 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3575
3576 if (dss_has_feature(FEAT_MFLAG))
3577 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3578
3579 DUMPREG(i, DISPC_OVL_FIR);
3580 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3581 DUMPREG(i, DISPC_OVL_ACCU0);
3582 DUMPREG(i, DISPC_OVL_ACCU1);
3583 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3584 DUMPREG(i, DISPC_OVL_BA0_UV);
3585 DUMPREG(i, DISPC_OVL_BA1_UV);
3586 DUMPREG(i, DISPC_OVL_FIR2);
3587 DUMPREG(i, DISPC_OVL_ACCU2_0);
3588 DUMPREG(i, DISPC_OVL_ACCU2_1);
3589 }
3590 if (dss_has_feature(FEAT_ATTR2))
3591 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3592 }
3593
5010be80
AT		 3594#undef DISPC_REG
3595#undef DUMPREG
3596
3597#define DISPC_REG(plane, name, i) name(plane, i)
3598#define DUMPREG(plane, name, i) \
4dd2da15 3599 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3600 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3601 dispc_read_reg(DISPC_REG(plane, name, i)))
3602
4dd2da15 3603 /* Video pipeline coefficient registers */
332e9d70 3604
4dd2da15
AT		 3605 /* start from OMAP_DSS_VIDEO1 */
3606 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3607 for (j = 0; j < 8; j++)
3608 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3609
4dd2da15
AT		 3610 for (j = 0; j < 8; j++)
3611 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3612
4dd2da15
AT		 3613 for (j = 0; j < 5; j++)
3614 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3615
4dd2da15
AT		 3616 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3617 for (j = 0; j < 8; j++)
3618 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3619 }
3620
3621 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3622 for (j = 0; j < 8; j++)
3623 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3624
3625 for (j = 0; j < 8; j++)
3626 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3627
3628 for (j = 0; j < 8; j++)
3629 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3630 }
332e9d70 3631 }
80c39712 3632
4fbafaf3 3633 dispc_runtime_put();
5010be80
AT		 3634
3635#undef DISPC_REG
80c39712
TV		 3636#undef DUMPREG
3637}
3638
80c39712
TV		 3639/* calculate clock rates using dividers in cinfo */
3640int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3641 struct dispc_clock_info *cinfo)
3642{
80c39712
TV		 3643 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3644 return -EINVAL;
9eaaf207 3645 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3646 return -EINVAL;
80c39712 3647
80c39712
TV		 3648 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3649 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3650
80c39712
TV		 3651 return 0;
3652}
80c39712 3653
7c284e6e
TV		 3654bool dispc_div_calc(unsigned long dispc,
3655 unsigned long pck_min, unsigned long pck_max,
3656 dispc_div_calc_func func, void *data)
3657{
3658 int lckd, lckd_start, lckd_stop;
3659 int pckd, pckd_start, pckd_stop;
3660 unsigned long pck, lck;
3661 unsigned long lck_max;
3662 unsigned long pckd_hw_min, pckd_hw_max;
3663 unsigned min_fck_per_pck;
3664 unsigned long fck;
80c39712 3665
7c284e6e
TV		 3666#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3667 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3668#else
3669 min_fck_per_pck = 0;
3670#endif
80c39712 3671
7c284e6e
TV		 3672 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3673 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3674
7c284e6e 3675 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3676
7c284e6e
TV		 3677 pck_min = pck_min ? pck_min : 1;
3678 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3679
7c284e6e
TV		 3680 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3681 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3682
7c284e6e
TV		 3683 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3684 lck = dispc / lckd;
80c39712 3685
7c284e6e
TV		 3686 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3687 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3688
7c284e6e
TV		 3689 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3690 pck = lck / pckd;
80c39712 3691
7c284e6e
TV		 3692 /*
3693 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3694 * clock, which means we're configuring DISPC fclk here
3695 * also. Thus we need to use the calculated lck. For
3696 * OMAP4+ the DISPC fclk is a separate clock.
3697 */
3698 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3699 fck = dispc_core_clk_rate();
3700 else
3701 fck = lck;
3702
3703 if (fck < pck * min_fck_per_pck)
3704 continue;
3705
3706 if (func(lckd, pckd, lck, pck, data))
3707 return true;
3708 }
3709 }
3710
3711 return false;
80c39712
TV		 3712}
3713
f0d08f89 3714void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3715 const struct dispc_clock_info *cinfo)
80c39712
TV		 3716{
3717 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3718 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3719
26d9dd0d 3720 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3721}
3722
26d9dd0d 3723int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3724 struct dispc_clock_info *cinfo)
80c39712
TV		 3725{
3726 unsigned long fck;
3727
3728 fck = dispc_fclk_rate();
3729
ce7fa5eb
MR		 3730 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3731 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3732
3733 cinfo->lck = fck / cinfo->lck_div;
3734 cinfo->pck = cinfo->lck / cinfo->pck_div;
3735
3736 return 0;
3737}
3738
4e0397cf
TV		 3739u32 dispc_read_irqstatus(void)
3740{
3741 return dispc_read_reg(DISPC_IRQSTATUS);
3742}
348be69d 3743EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3744
3745void dispc_clear_irqstatus(u32 mask)
3746{
3747 dispc_write_reg(DISPC_IRQSTATUS, mask);
3748}
348be69d 3749EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3750
3751u32 dispc_read_irqenable(void)
3752{
3753 return dispc_read_reg(DISPC_IRQENABLE);
3754}
348be69d 3755EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3756
3757void dispc_write_irqenable(u32 mask)
3758{
3759 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3760
3761 /* clear the irqstatus for newly enabled irqs */
3762 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3763
3764 dispc_write_reg(DISPC_IRQENABLE, mask);
3765}
348be69d 3766EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3767
80c39712
TV		 3768void dispc_enable_sidle(void)
3769{
3770 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3771}
3772
3773void dispc_disable_sidle(void)
3774{
3775 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3776}
3777
3778static void _omap_dispc_initial_config(void)
3779{
3780 u32 l;
3781
0cf35df3
MR		 3782 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3783 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3784 l = dispc_read_reg(DISPC_DIVISOR);
3785 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3786 l = FLD_MOD(l, 1, 0, 0);
3787 l = FLD_MOD(l, 1, 23, 16);
3788 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3789
3790 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3791 }
3792
80c39712 3793 /* FUNCGATED */
6ced40bf
AT		 3794 if (dss_has_feature(FEAT_FUNCGATED))
3795 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3796
6e5264b0 3797 dispc_setup_color_conv_coef();
80c39712
TV		 3798
3799 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3800
42a6961c 3801 dispc_init_fifos();
5ed8cf5b
TV		 3802
3803 dispc_configure_burst_sizes();
54128701
AT		 3804
3805 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3806
3807 if (dispc.feat->mstandby_workaround)
3808 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
c64aa3a6
TV		 3809
3810 if (dss_has_feature(FEAT_MFLAG))
3811 dispc_init_mflag();
80c39712
TV		 3812}
3813
ede92695 3814static const struct dispc_features omap24xx_dispc_feats = {
dcbe765b
CM		 3815 .sw_start = 5,
3816 .fp_start = 15,
3817 .bp_start = 27,
3818 .sw_max = 64,
3819 .vp_max = 255,
3820 .hp_max = 256,
33b89928
AT		 3821 .mgr_width_start = 10,
3822 .mgr_height_start = 26,
3823 .mgr_width_max = 2048,
3824 .mgr_height_max = 2048,
ca5ca69c 3825 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3826 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3827 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3828 .num_fifos = 3,
cffa947d 3829 .no_framedone_tv = true,
8bc65552 3830 .set_max_preload = false,
f2aee319 3831 .last_pixel_inc_missing = true,
dcbe765b
CM		 3832};
3833
ede92695 3834static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
dcbe765b
CM		 3835 .sw_start = 5,
3836 .fp_start = 15,
3837 .bp_start = 27,
3838 .sw_max = 64,
3839 .vp_max = 255,
3840 .hp_max = 256,
33b89928
AT		 3841 .mgr_width_start = 10,
3842 .mgr_height_start = 26,
3843 .mgr_width_max = 2048,
3844 .mgr_height_max = 2048,
ca5ca69c
AT		 3845 .max_lcd_pclk = 173000000,
3846 .max_tv_pclk = 59000000,
dcbe765b
CM		 3847 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3848 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3849 .num_fifos = 3,
cffa947d 3850 .no_framedone_tv = true,
8bc65552 3851 .set_max_preload = false,
f2aee319 3852 .last_pixel_inc_missing = true,
dcbe765b
CM		 3853};
3854
ede92695 3855static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
dcbe765b
CM		 3856 .sw_start = 7,
3857 .fp_start = 19,
3858 .bp_start = 31,
3859 .sw_max = 256,
3860 .vp_max = 4095,
3861 .hp_max = 4096,
33b89928
AT		 3862 .mgr_width_start = 10,
3863 .mgr_height_start = 26,
3864 .mgr_width_max = 2048,
3865 .mgr_height_max = 2048,
ca5ca69c
AT		 3866 .max_lcd_pclk = 173000000,
3867 .max_tv_pclk = 59000000,
dcbe765b
CM		 3868 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3869 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3870 .num_fifos = 3,
cffa947d 3871 .no_framedone_tv = true,
8bc65552 3872 .set_max_preload = false,
f2aee319 3873 .last_pixel_inc_missing = true,
dcbe765b
CM		 3874};
3875
ede92695 3876static const struct dispc_features omap44xx_dispc_feats = {
dcbe765b
CM		 3877 .sw_start = 7,
3878 .fp_start = 19,
3879 .bp_start = 31,
3880 .sw_max = 256,
3881 .vp_max = 4095,
3882 .hp_max = 4096,
33b89928
AT		 3883 .mgr_width_start = 10,
3884 .mgr_height_start = 26,
3885 .mgr_width_max = 2048,
3886 .mgr_height_max = 2048,
ca5ca69c
AT		 3887 .max_lcd_pclk = 170000000,
3888 .max_tv_pclk = 185625000,
dcbe765b
CM		 3889 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3890 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3891 .num_fifos = 5,
66a0f9e4 3892 .gfx_fifo_workaround = true,
8bc65552 3893 .set_max_preload = true,
e5f80917 3894 .supports_sync_align = true,
dcbe765b
CM		 3895};
3896
ede92695 3897static const struct dispc_features omap54xx_dispc_feats = {
264236f8
AT		 3898 .sw_start = 7,
3899 .fp_start = 19,
3900 .bp_start = 31,
3901 .sw_max = 256,
3902 .vp_max = 4095,
3903 .hp_max = 4096,
3904 .mgr_width_start = 11,
3905 .mgr_height_start = 27,
3906 .mgr_width_max = 4096,
3907 .mgr_height_max = 4096,
ca5ca69c
AT		 3908 .max_lcd_pclk = 170000000,
3909 .max_tv_pclk = 186000000,
264236f8
AT		 3910 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3911 .calc_core_clk = calc_core_clk_44xx,
3912 .num_fifos = 5,
3913 .gfx_fifo_workaround = true,
d0df9a2c 3914 .mstandby_workaround = true,
8bc65552 3915 .set_max_preload = true,
e5f80917 3916 .supports_sync_align = true,
264236f8
AT		 3917};
3918
ede92695 3919static int dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3920{
3921 const struct dispc_features *src;
3922 struct dispc_features *dst;
3923
84b47623 3924 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3925 if (!dst) {
84b47623 3926 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3927 return -ENOMEM;
3928 }
3929
b2c7d54f 3930 switch (omapdss_get_version()) {
84b47623 3931 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3932 src = &omap24xx_dispc_feats;
84b47623
TV		 3933 break;
3934
3935 case OMAPDSS_VER_OMAP34xx_ES1:
3936 src = &omap34xx_rev1_0_dispc_feats;
3937 break;
3938
3939 case OMAPDSS_VER_OMAP34xx_ES3:
3940 case OMAPDSS_VER_OMAP3630:
3941 case OMAPDSS_VER_AM35xx:
d6279d4a 3942 case OMAPDSS_VER_AM43xx:
84b47623
TV		 3943 src = &omap34xx_rev3_0_dispc_feats;
3944 break;
3945
3946 case OMAPDSS_VER_OMAP4430_ES1:
3947 case OMAPDSS_VER_OMAP4430_ES2:
3948 case OMAPDSS_VER_OMAP4:
dcbe765b 3949 src = &omap44xx_dispc_feats;
84b47623
TV		 3950 break;
3951
3952 case OMAPDSS_VER_OMAP5:
93550927 3953 case OMAPDSS_VER_DRA7xx:
264236f8 3954 src = &omap54xx_dispc_feats;
84b47623
TV		 3955 break;
3956
3957 default:
dcbe765b
CM		 3958 return -ENODEV;
3959 }
3960
3961 memcpy(dst, src, sizeof(*dst));
3962 dispc.feat = dst;
3963
3964 return 0;
3965}
3966
0925afc9
TV		 3967static irqreturn_t dispc_irq_handler(int irq, void *arg)
3968{
3969 if (!dispc.is_enabled)
3970 return IRQ_NONE;
3971
3972 return dispc.user_handler(irq, dispc.user_data);
3973}
3974
96e2e637
TV		 3975int dispc_request_irq(irq_handler_t handler, void *dev_id)
3976{
0925afc9
TV		 3977 int r;
3978
3979 if (dispc.user_handler != NULL)
3980 return -EBUSY;
3981
3982 dispc.user_handler = handler;
3983 dispc.user_data = dev_id;
3984
3985 /* ensure the dispc_irq_handler sees the values above */
3986 smp_wmb();
3987
3988 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3989 IRQF_SHARED, "OMAP DISPC", &dispc);
3990 if (r) {
3991 dispc.user_handler = NULL;
3992 dispc.user_data = NULL;
3993 }
3994
3995 return r;
96e2e637 3996}
348be69d 3997EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 3998
3999void dispc_free_irq(void *dev_id)
4000{
0925afc9
TV		 4001 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4002
4003 dispc.user_handler = NULL;
4004 dispc.user_data = NULL;
96e2e637 4005}
348be69d 4006EXPORT_SYMBOL(dispc_free_irq);
96e2e637 4007
060b6d9c 4008/* DISPC HW IP initialisation */
736e60dd 4009static int dispc_bind(struct device *dev, struct device *master, void *data)
060b6d9c 4010{
736e60dd 4011 struct platform_device *pdev = to_platform_device(dev);
060b6d9c 4012 u32 rev;
affe360d 4013 int r = 0;
ea9da36a 4014 struct resource *dispc_mem;
0006fd63 4015 struct device_node *np = pdev->dev.of_node;
ea9da36a 4016
060b6d9c
SG		 4017 dispc.pdev = pdev;
4018
d49cd155
TV		 4019 spin_lock_init(&dispc.control_lock);
4020
84b47623 4021 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4022 if (r)
4023 return r;
4024
ea9da36a
SG		 4025 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4026 if (!dispc_mem) {
4027 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4028 return -EINVAL;
ea9da36a 4029 }
cd3b3449 4030
6e2a14d2
JL		 4031 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4032 resource_size(dispc_mem));
060b6d9c
SG		 4033 if (!dispc.base) {
4034 DSSERR("can't ioremap DISPC\n");
cd3b3449 4035 return -ENOMEM;
affe360d 4036 }
cd3b3449 4037
affe360d 4038 dispc.irq = platform_get_irq(dispc.pdev, 0);
4039 if (dispc.irq < 0) {
4040 DSSERR("platform_get_irq failed\n");
cd3b3449 4041 return -ENODEV;
affe360d 4042 }
4043
0006fd63
TV		 4044 if (np && of_property_read_bool(np, "syscon-pol")) {
4045 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4046 if (IS_ERR(dispc.syscon_pol)) {
4047 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4048 return PTR_ERR(dispc.syscon_pol);
4049 }
4050
4051 if (of_property_read_u32_index(np, "syscon-pol", 1,
4052 &dispc.syscon_pol_offset)) {
4053 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4054 return -EINVAL;
4055 }
4056 }
4057
4fbafaf3
TV		 4058 pm_runtime_enable(&pdev->dev);
4059
4060 r = dispc_runtime_get();
4061 if (r)
4062 goto err_runtime_get;
060b6d9c
SG		 4063
4064 _omap_dispc_initial_config();
4065
060b6d9c 4066 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4067 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4068 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4069
4fbafaf3 4070 dispc_runtime_put();
060b6d9c 4071
04b1fc02
TV		 4072 dss_init_overlay_managers();
4073
e40402cf
TV		 4074 dss_debugfs_create_file("dispc", dispc_dump_regs);
4075
060b6d9c 4076 return 0;
4fbafaf3
TV		 4077
4078err_runtime_get:
4079 pm_runtime_disable(&pdev->dev);
affe360d 4080 return r;
060b6d9c
SG		 4081}
4082
736e60dd
TV		 4083static void dispc_unbind(struct device *dev, struct device *master,
4084 void *data)
060b6d9c 4085{
736e60dd 4086 pm_runtime_disable(dev);
4fbafaf3 4087
04b1fc02 4088 dss_uninit_overlay_managers();
736e60dd
TV		 4089}
4090
4091static const struct component_ops dispc_component_ops = {
4092 .bind = dispc_bind,
4093 .unbind = dispc_unbind,
4094};
04b1fc02 4095
736e60dd
TV		 4096static int dispc_probe(struct platform_device *pdev)
4097{
4098 return component_add(&pdev->dev, &dispc_component_ops);
4099}
4100
4101static int dispc_remove(struct platform_device *pdev)
4102{
4103 component_del(&pdev->dev, &dispc_component_ops);
060b6d9c
SG		 4104 return 0;
4105}
4106
4fbafaf3
TV		 4107static int dispc_runtime_suspend(struct device *dev)
4108{
0925afc9
TV		 4109 dispc.is_enabled = false;
4110 /* ensure the dispc_irq_handler sees the is_enabled value */
4111 smp_wmb();
4112 /* wait for current handler to finish before turning the DISPC off */
4113 synchronize_irq(dispc.irq);
4114
4fbafaf3 4115 dispc_save_context();
4fbafaf3
TV		 4116
4117 return 0;
4118}
4119
4120static int dispc_runtime_resume(struct device *dev)
4121{
9229b516
TV		 4122 /*
4123 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4124 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4125 * _omap_dispc_initial_config(). We can thus use it to detect if
4126 * we have lost register context.
4127 */
0925afc9
TV		 4128 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4129 _omap_dispc_initial_config();
9229b516 4130
0925afc9
TV		 4131 dispc_restore_context();
4132 }
be07dcd7 4133
0925afc9
TV		 4134 dispc.is_enabled = true;
4135 /* ensure the dispc_irq_handler sees the is_enabled value */
4136 smp_wmb();
4fbafaf3
TV		 4137
4138 return 0;
4139}
4140
4141static const struct dev_pm_ops dispc_pm_ops = {
4142 .runtime_suspend = dispc_runtime_suspend,
4143 .runtime_resume = dispc_runtime_resume,
4144};
4145
d7977f88
TV		 4146static const struct of_device_id dispc_of_match[] = {
4147 { .compatible = "ti,omap2-dispc", },
4148 { .compatible = "ti,omap3-dispc", },
4149 { .compatible = "ti,omap4-dispc", },
2e7e6b68 4150 { .compatible = "ti,omap5-dispc", },
93550927 4151 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 4152 {},
4153};
4154
060b6d9c 4155static struct platform_driver omap_dispchw_driver = {
736e60dd
TV		 4156 .probe = dispc_probe,
4157 .remove = dispc_remove,
060b6d9c
SG		 4158 .driver = {
4159 .name = "omapdss_dispc",
4fbafaf3 4160 .pm = &dispc_pm_ops,
d7977f88 4161 .of_match_table = dispc_of_match,
422ccbd5 4162 .suppress_bind_attrs = true,
060b6d9c
SG		 4163 },
4164};
4165
6e7e8f06 4166int __init dispc_init_platform_driver(void)
060b6d9c 4167{
736e60dd 4168 return platform_driver_register(&omap_dispchw_driver);
060b6d9c
SG		 4169}
4170
ede92695 4171void dispc_uninit_platform_driver(void)
060b6d9c 4172{
04c742c3 4173 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4174}
Linux kernel - Deliverables
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