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3de7a1dc TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dsi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "DSI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/mutex.h> | |
355b200b | 30 | #include <linux/module.h> |
b9eb5d7d | 31 | #include <linux/semaphore.h> |
3de7a1dc TV |
32 | #include <linux/seq_file.h> |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/regulator/consumer.h> | |
3de7a1dc | 35 | #include <linux/wait.h> |
18946f62 | 36 | #include <linux/workqueue.h> |
40885ab3 | 37 | #include <linux/sched.h> |
f1da39d9 | 38 | #include <linux/slab.h> |
5a8b572d | 39 | #include <linux/debugfs.h> |
4fbafaf3 | 40 | #include <linux/pm_runtime.h> |
6274a619 TV |
41 | #include <linux/of.h> |
42 | #include <linux/of_platform.h> | |
3de7a1dc | 43 | |
a0b38cc4 | 44 | #include <video/omapdss.h> |
7a7c48f9 | 45 | #include <video/mipi_display.h> |
3de7a1dc TV |
46 | |
47 | #include "dss.h" | |
819d807c | 48 | #include "dss_features.h" |
3de7a1dc | 49 | |
3de7a1dc TV |
50 | #define DSI_CATCH_MISSING_TE |
51 | ||
68104467 | 52 | struct dsi_reg { u16 module; u16 idx; }; |
3de7a1dc | 53 | |
68104467 | 54 | #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) |
3de7a1dc | 55 | |
3de7a1dc TV |
56 | /* DSI Protocol Engine */ |
57 | ||
68104467 TV |
58 | #define DSI_PROTO 0 |
59 | #define DSI_PROTO_SZ 0x200 | |
60 | ||
61 | #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) | |
62 | #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) | |
63 | #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) | |
64 | #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) | |
65 | #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) | |
66 | #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) | |
67 | #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) | |
68 | #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) | |
69 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) | |
70 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) | |
71 | #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) | |
72 | #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) | |
73 | #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) | |
74 | #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) | |
75 | #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) | |
76 | #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) | |
77 | #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) | |
78 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) | |
79 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) | |
80 | #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) | |
81 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) | |
82 | #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) | |
83 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) | |
84 | #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) | |
85 | #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) | |
86 | #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) | |
87 | #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) | |
88 | #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) | |
89 | #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) | |
90 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) | |
91 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) | |
92 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) | |
93 | #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) | |
94 | #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) | |
3de7a1dc TV |
95 | |
96 | /* DSIPHY_SCP */ | |
97 | ||
68104467 TV |
98 | #define DSI_PHY 1 |
99 | #define DSI_PHY_OFFSET 0x200 | |
100 | #define DSI_PHY_SZ 0x40 | |
101 | ||
102 | #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) | |
103 | #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) | |
104 | #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) | |
105 | #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) | |
106 | #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) | |
3de7a1dc TV |
107 | |
108 | /* DSI_PLL_CTRL_SCP */ | |
109 | ||
68104467 TV |
110 | #define DSI_PLL 2 |
111 | #define DSI_PLL_OFFSET 0x300 | |
112 | #define DSI_PLL_SZ 0x20 | |
113 | ||
114 | #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) | |
115 | #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) | |
116 | #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) | |
117 | #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) | |
118 | #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) | |
3de7a1dc | 119 | |
a72b64b9 AT |
120 | #define REG_GET(dsidev, idx, start, end) \ |
121 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) | |
3de7a1dc | 122 | |
a72b64b9 AT |
123 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ |
124 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) | |
3de7a1dc TV |
125 | |
126 | /* Global interrupts */ | |
127 | #define DSI_IRQ_VC0 (1 << 0) | |
128 | #define DSI_IRQ_VC1 (1 << 1) | |
129 | #define DSI_IRQ_VC2 (1 << 2) | |
130 | #define DSI_IRQ_VC3 (1 << 3) | |
131 | #define DSI_IRQ_WAKEUP (1 << 4) | |
132 | #define DSI_IRQ_RESYNC (1 << 5) | |
133 | #define DSI_IRQ_PLL_LOCK (1 << 7) | |
134 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) | |
135 | #define DSI_IRQ_PLL_RECALL (1 << 9) | |
136 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) | |
137 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) | |
138 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) | |
139 | #define DSI_IRQ_TE_TRIGGER (1 << 16) | |
140 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) | |
141 | #define DSI_IRQ_SYNC_LOST (1 << 18) | |
142 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) | |
143 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) | |
144 | #define DSI_IRQ_ERROR_MASK \ | |
145 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ | |
8af6ff01 | 146 | DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST) |
3de7a1dc TV |
147 | #define DSI_IRQ_CHANNEL_MASK 0xf |
148 | ||
149 | /* Virtual channel interrupts */ | |
150 | #define DSI_VC_IRQ_CS (1 << 0) | |
151 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) | |
152 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) | |
153 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) | |
154 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) | |
155 | #define DSI_VC_IRQ_BTA (1 << 5) | |
156 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) | |
157 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) | |
158 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) | |
159 | #define DSI_VC_IRQ_ERROR_MASK \ | |
160 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ | |
161 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ | |
162 | DSI_VC_IRQ_FIFO_TX_UDF) | |
163 | ||
164 | /* ComplexIO interrupts */ | |
165 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) | |
166 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) | |
167 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) | |
6705615e TV |
168 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
169 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) | |
3de7a1dc TV |
170 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
171 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) | |
172 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) | |
6705615e TV |
173 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
174 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) | |
3de7a1dc TV |
175 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
176 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) | |
177 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) | |
6705615e TV |
178 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
179 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) | |
3de7a1dc TV |
180 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
181 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) | |
182 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) | |
6705615e TV |
183 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
184 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) | |
3de7a1dc TV |
185 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
186 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) | |
187 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) | |
188 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) | |
189 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) | |
190 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) | |
6705615e TV |
191 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
192 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) | |
193 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) | |
194 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) | |
3de7a1dc TV |
195 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
196 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) | |
bbecb50b TV |
197 | #define DSI_CIO_IRQ_ERROR_MASK \ |
198 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ | |
6705615e TV |
199 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
200 | DSI_CIO_IRQ_ERRSYNCESC5 | \ | |
201 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ | |
202 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ | |
203 | DSI_CIO_IRQ_ERRESC5 | \ | |
204 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ | |
205 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ | |
206 | DSI_CIO_IRQ_ERRCONTROL5 | \ | |
bbecb50b TV |
207 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
208 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ | |
6705615e TV |
209 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
210 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ | |
211 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) | |
3de7a1dc | 212 | |
4ae2dddd TV |
213 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
214 | ||
b7dec9b6 TV |
215 | static int dsi_display_init_dispc(struct platform_device *dsidev, |
216 | struct omap_overlay_manager *mgr); | |
217 | static void dsi_display_uninit_dispc(struct platform_device *dsidev, | |
218 | struct omap_overlay_manager *mgr); | |
219 | ||
5cfc1c3c TV |
220 | static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); |
221 | ||
4ae2dddd | 222 | #define DSI_MAX_NR_ISRS 2 |
739a7f46 TV |
223 | #define DSI_MAX_NR_LANES 5 |
224 | ||
225 | enum dsi_lane_function { | |
226 | DSI_LANE_UNUSED = 0, | |
227 | DSI_LANE_CLK, | |
228 | DSI_LANE_DATA1, | |
229 | DSI_LANE_DATA2, | |
230 | DSI_LANE_DATA3, | |
231 | DSI_LANE_DATA4, | |
232 | }; | |
233 | ||
234 | struct dsi_lane_config { | |
235 | enum dsi_lane_function function; | |
236 | u8 polarity; | |
237 | }; | |
4ae2dddd TV |
238 | |
239 | struct dsi_isr_data { | |
240 | omap_dsi_isr_t isr; | |
241 | void *arg; | |
242 | u32 mask; | |
243 | }; | |
244 | ||
3de7a1dc TV |
245 | enum fifo_size { |
246 | DSI_FIFO_SIZE_0 = 0, | |
247 | DSI_FIFO_SIZE_32 = 1, | |
248 | DSI_FIFO_SIZE_64 = 2, | |
249 | DSI_FIFO_SIZE_96 = 3, | |
250 | DSI_FIFO_SIZE_128 = 4, | |
251 | }; | |
252 | ||
d6049144 AT |
253 | enum dsi_vc_source { |
254 | DSI_VC_SOURCE_L4 = 0, | |
255 | DSI_VC_SOURCE_VP, | |
3de7a1dc TV |
256 | }; |
257 | ||
dfc0fd8d TV |
258 | struct dsi_irq_stats { |
259 | unsigned long last_reset; | |
260 | unsigned irq_count; | |
261 | unsigned dsi_irqs[32]; | |
262 | unsigned vc_irqs[4][32]; | |
263 | unsigned cio_irqs[32]; | |
264 | }; | |
265 | ||
4ae2dddd TV |
266 | struct dsi_isr_tables { |
267 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; | |
268 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; | |
269 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; | |
270 | }; | |
271 | ||
f1e0001f TV |
272 | struct dsi_clk_calc_ctx { |
273 | struct platform_device *dsidev; | |
274 | ||
275 | /* inputs */ | |
276 | ||
277 | const struct omap_dss_dsi_config *config; | |
278 | ||
279 | unsigned long req_pck_min, req_pck_nom, req_pck_max; | |
280 | ||
281 | /* outputs */ | |
282 | ||
283 | struct dsi_clock_info dsi_cinfo; | |
284 | struct dispc_clock_info dispc_cinfo; | |
285 | ||
286 | struct omap_video_timings dispc_vm; | |
287 | struct omap_dss_dsi_videomode_timings dsi_vm; | |
288 | }; | |
289 | ||
f1da39d9 | 290 | struct dsi_data { |
c8aac01b | 291 | struct platform_device *pdev; |
68104467 TV |
292 | void __iomem *proto_base; |
293 | void __iomem *phy_base; | |
294 | void __iomem *pll_base; | |
4fbafaf3 | 295 | |
11ee9606 TV |
296 | int module_id; |
297 | ||
affe360d | 298 | int irq; |
3de7a1dc | 299 | |
0925afc9 TV |
300 | bool is_enabled; |
301 | ||
4fbafaf3 TV |
302 | struct clk *dss_clk; |
303 | struct clk *sys_clk; | |
304 | ||
a0d269ec TV |
305 | struct dispc_clock_info user_dispc_cinfo; |
306 | struct dsi_clock_info user_dsi_cinfo; | |
307 | ||
3de7a1dc TV |
308 | struct dsi_clock_info current_cinfo; |
309 | ||
2a89dc15 | 310 | bool vdds_dsi_enabled; |
3de7a1dc TV |
311 | struct regulator *vdds_dsi_reg; |
312 | ||
313 | struct { | |
d6049144 | 314 | enum dsi_vc_source source; |
3de7a1dc | 315 | struct omap_dss_device *dssdev; |
558c73e2 TV |
316 | enum fifo_size tx_fifo_size; |
317 | enum fifo_size rx_fifo_size; | |
5ee3c144 | 318 | int vc_id; |
3de7a1dc TV |
319 | } vc[4]; |
320 | ||
321 | struct mutex lock; | |
b9eb5d7d | 322 | struct semaphore bus_lock; |
3de7a1dc TV |
323 | |
324 | unsigned pll_locked; | |
325 | ||
4ae2dddd TV |
326 | spinlock_t irq_lock; |
327 | struct dsi_isr_tables isr_tables; | |
328 | /* space for a copy used by the interrupt handler */ | |
329 | struct dsi_isr_tables isr_tables_copy; | |
330 | ||
18946f62 | 331 | int update_channel; |
477fed70 | 332 | #ifdef DSI_PERF_MEASURE |
5476e74a TV |
333 | unsigned update_bytes; |
334 | #endif | |
3de7a1dc | 335 | |
3de7a1dc | 336 | bool te_enabled; |
40885ab3 | 337 | bool ulps_enabled; |
3de7a1dc | 338 | |
18946f62 TV |
339 | void (*framedone_callback)(int, void *); |
340 | void *framedone_data; | |
341 | ||
342 | struct delayed_work framedone_timeout_work; | |
343 | ||
3de7a1dc TV |
344 | #ifdef DSI_CATCH_MISSING_TE |
345 | struct timer_list te_timer; | |
346 | #endif | |
347 | ||
348 | unsigned long cache_req_pck; | |
349 | unsigned long cache_clk_freq; | |
350 | struct dsi_clock_info cache_cinfo; | |
351 | ||
352 | u32 errors; | |
353 | spinlock_t errors_lock; | |
477fed70 | 354 | #ifdef DSI_PERF_MEASURE |
3de7a1dc TV |
355 | ktime_t perf_setup_time; |
356 | ktime_t perf_start_time; | |
3de7a1dc TV |
357 | #endif |
358 | int debug_read; | |
359 | int debug_write; | |
dfc0fd8d TV |
360 | |
361 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
362 | spinlock_t irq_stats_lock; | |
363 | struct dsi_irq_stats irq_stats; | |
364 | #endif | |
49641116 TA |
365 | /* DSI PLL Parameter Ranges */ |
366 | unsigned long regm_max, regn_max; | |
367 | unsigned long regm_dispc_max, regm_dsi_max; | |
368 | unsigned long fint_min, fint_max; | |
369 | unsigned long lpdiv_max; | |
24c1ae41 | 370 | |
d9820850 | 371 | unsigned num_lanes_supported; |
99322577 | 372 | unsigned line_buffer_size; |
75d7247c | 373 | |
739a7f46 TV |
374 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; |
375 | unsigned num_lanes_used; | |
75d7247c | 376 | |
24c1ae41 | 377 | unsigned scp_clk_refcount; |
7d2572f8 AT |
378 | |
379 | struct dss_lcd_mgr_config mgr_config; | |
e67458a8 | 380 | struct omap_video_timings timings; |
02c3960b | 381 | enum omap_dss_dsi_pixel_format pix_fmt; |
dca2b152 | 382 | enum omap_dss_dsi_mode mode; |
0b3ffe39 | 383 | struct omap_dss_dsi_videomode_timings vm_timings; |
81b87f51 | 384 | |
1f68d9c4 | 385 | struct omap_dss_device output; |
f1da39d9 | 386 | }; |
3de7a1dc | 387 | |
2e868dbe AT |
388 | struct dsi_packet_sent_handler_data { |
389 | struct platform_device *dsidev; | |
390 | struct completion *completion; | |
391 | }; | |
392 | ||
6274a619 TV |
393 | struct dsi_module_id_data { |
394 | u32 address; | |
395 | int id; | |
396 | }; | |
397 | ||
398 | static const struct of_device_id dsi_of_match[]; | |
399 | ||
477fed70 | 400 | #ifdef DSI_PERF_MEASURE |
90ab5ee9 RR |
401 | static bool dsi_perf; |
402 | module_param(dsi_perf, bool, 0644); | |
3de7a1dc TV |
403 | #endif |
404 | ||
f1da39d9 AT |
405 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) |
406 | { | |
407 | return dev_get_drvdata(&dsidev->dev); | |
408 | } | |
409 | ||
a72b64b9 AT |
410 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) |
411 | { | |
5cfc1c3c | 412 | return to_platform_device(dssdev->dev); |
a72b64b9 AT |
413 | } |
414 | ||
415 | struct platform_device *dsi_get_dsidev_from_id(int module) | |
416 | { | |
1f68d9c4 | 417 | struct omap_dss_device *out; |
400e65d1 AT |
418 | enum omap_dss_output_id id; |
419 | ||
78e7f256 TV |
420 | switch (module) { |
421 | case 0: | |
422 | id = OMAP_DSS_OUTPUT_DSI1; | |
423 | break; | |
424 | case 1: | |
425 | id = OMAP_DSS_OUTPUT_DSI2; | |
426 | break; | |
427 | default: | |
428 | return NULL; | |
429 | } | |
400e65d1 AT |
430 | |
431 | out = omap_dss_get_output(id); | |
432 | ||
1f68d9c4 | 433 | return out ? to_platform_device(out->dev) : NULL; |
a72b64b9 AT |
434 | } |
435 | ||
436 | static inline void dsi_write_reg(struct platform_device *dsidev, | |
437 | const struct dsi_reg idx, u32 val) | |
3de7a1dc | 438 | { |
f1da39d9 | 439 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
68104467 TV |
440 | void __iomem *base; |
441 | ||
442 | switch(idx.module) { | |
443 | case DSI_PROTO: base = dsi->proto_base; break; | |
444 | case DSI_PHY: base = dsi->phy_base; break; | |
445 | case DSI_PLL: base = dsi->pll_base; break; | |
446 | default: return; | |
447 | } | |
f1da39d9 | 448 | |
68104467 | 449 | __raw_writel(val, base + idx.idx); |
3de7a1dc TV |
450 | } |
451 | ||
a72b64b9 AT |
452 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
453 | const struct dsi_reg idx) | |
3de7a1dc | 454 | { |
f1da39d9 | 455 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
68104467 | 456 | void __iomem *base; |
f1da39d9 | 457 | |
68104467 TV |
458 | switch(idx.module) { |
459 | case DSI_PROTO: base = dsi->proto_base; break; | |
460 | case DSI_PHY: base = dsi->phy_base; break; | |
461 | case DSI_PLL: base = dsi->pll_base; break; | |
462 | default: return 0; | |
463 | } | |
464 | ||
465 | return __raw_readl(base + idx.idx); | |
3de7a1dc TV |
466 | } |
467 | ||
5cfc1c3c | 468 | static void dsi_bus_lock(struct omap_dss_device *dssdev) |
3de7a1dc | 469 | { |
f1da39d9 AT |
470 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
471 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
472 | ||
473 | down(&dsi->bus_lock); | |
3de7a1dc | 474 | } |
3de7a1dc | 475 | |
5cfc1c3c | 476 | static void dsi_bus_unlock(struct omap_dss_device *dssdev) |
3de7a1dc | 477 | { |
f1da39d9 AT |
478 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
479 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
480 | ||
481 | up(&dsi->bus_lock); | |
3de7a1dc | 482 | } |
3de7a1dc | 483 | |
a72b64b9 | 484 | static bool dsi_bus_is_locked(struct platform_device *dsidev) |
4f765023 | 485 | { |
f1da39d9 AT |
486 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
487 | ||
488 | return dsi->bus_lock.count == 0; | |
4f765023 TV |
489 | } |
490 | ||
f36a06e7 TV |
491 | static void dsi_completion_handler(void *data, u32 mask) |
492 | { | |
493 | complete((struct completion *)data); | |
494 | } | |
495 | ||
a72b64b9 AT |
496 | static inline int wait_for_bit_change(struct platform_device *dsidev, |
497 | const struct dsi_reg idx, int bitnum, int value) | |
3de7a1dc | 498 | { |
3b98409e TV |
499 | unsigned long timeout; |
500 | ktime_t wait; | |
501 | int t; | |
3de7a1dc | 502 | |
3b98409e TV |
503 | /* first busyloop to see if the bit changes right away */ |
504 | t = 100; | |
505 | while (t-- > 0) { | |
506 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) | |
507 | return value; | |
3de7a1dc TV |
508 | } |
509 | ||
3b98409e TV |
510 | /* then loop for 500ms, sleeping for 1ms in between */ |
511 | timeout = jiffies + msecs_to_jiffies(500); | |
512 | while (time_before(jiffies, timeout)) { | |
513 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) | |
514 | return value; | |
3de7a1dc | 515 | |
3b98409e TV |
516 | wait = ns_to_ktime(1000 * 1000); |
517 | set_current_state(TASK_UNINTERRUPTIBLE); | |
518 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
3de7a1dc TV |
519 | } |
520 | ||
3b98409e | 521 | return !value; |
3de7a1dc TV |
522 | } |
523 | ||
a3b3cc2b AT |
524 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
525 | { | |
526 | switch (fmt) { | |
527 | case OMAP_DSS_DSI_FMT_RGB888: | |
528 | case OMAP_DSS_DSI_FMT_RGB666: | |
529 | return 24; | |
530 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
531 | return 18; | |
532 | case OMAP_DSS_DSI_FMT_RGB565: | |
533 | return 16; | |
534 | default: | |
535 | BUG(); | |
c6eee968 | 536 | return 0; |
a3b3cc2b AT |
537 | } |
538 | } | |
539 | ||
477fed70 | 540 | #ifdef DSI_PERF_MEASURE |
a72b64b9 | 541 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
3de7a1dc | 542 | { |
f1da39d9 AT |
543 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
544 | dsi->perf_setup_time = ktime_get(); | |
3de7a1dc TV |
545 | } |
546 | ||
a72b64b9 | 547 | static void dsi_perf_mark_start(struct platform_device *dsidev) |
3de7a1dc | 548 | { |
f1da39d9 AT |
549 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
550 | dsi->perf_start_time = ktime_get(); | |
3de7a1dc TV |
551 | } |
552 | ||
a72b64b9 | 553 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) |
3de7a1dc | 554 | { |
f1da39d9 | 555 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
556 | ktime_t t, setup_time, trans_time; |
557 | u32 total_bytes; | |
558 | u32 setup_us, trans_us, total_us; | |
559 | ||
560 | if (!dsi_perf) | |
561 | return; | |
562 | ||
3de7a1dc TV |
563 | t = ktime_get(); |
564 | ||
f1da39d9 | 565 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
3de7a1dc TV |
566 | setup_us = (u32)ktime_to_us(setup_time); |
567 | if (setup_us == 0) | |
568 | setup_us = 1; | |
569 | ||
f1da39d9 | 570 | trans_time = ktime_sub(t, dsi->perf_start_time); |
3de7a1dc TV |
571 | trans_us = (u32)ktime_to_us(trans_time); |
572 | if (trans_us == 0) | |
573 | trans_us = 1; | |
574 | ||
575 | total_us = setup_us + trans_us; | |
576 | ||
5476e74a | 577 | total_bytes = dsi->update_bytes; |
3de7a1dc | 578 | |
1bbb275e TV |
579 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
580 | "%u bytes, %u kbytes/sec\n", | |
581 | name, | |
582 | setup_us, | |
583 | trans_us, | |
584 | total_us, | |
585 | 1000*1000 / total_us, | |
586 | total_bytes, | |
587 | total_bytes * 1000 / total_us); | |
3de7a1dc TV |
588 | } |
589 | #else | |
4a9a5e39 TV |
590 | static inline void dsi_perf_mark_setup(struct platform_device *dsidev) |
591 | { | |
592 | } | |
593 | ||
594 | static inline void dsi_perf_mark_start(struct platform_device *dsidev) | |
595 | { | |
596 | } | |
597 | ||
598 | static inline void dsi_perf_show(struct platform_device *dsidev, | |
599 | const char *name) | |
600 | { | |
601 | } | |
3de7a1dc TV |
602 | #endif |
603 | ||
f30be7d3 CM |
604 | static int verbose_irq; |
605 | ||
3de7a1dc TV |
606 | static void print_irq_status(u32 status) |
607 | { | |
d80d499e TV |
608 | if (status == 0) |
609 | return; | |
610 | ||
f30be7d3 | 611 | if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
3de7a1dc | 612 | return; |
3de7a1dc | 613 | |
f30be7d3 CM |
614 | #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" |
615 | ||
616 | pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", | |
617 | status, | |
618 | verbose_irq ? PIS(VC0) : "", | |
619 | verbose_irq ? PIS(VC1) : "", | |
620 | verbose_irq ? PIS(VC2) : "", | |
621 | verbose_irq ? PIS(VC3) : "", | |
622 | PIS(WAKEUP), | |
623 | PIS(RESYNC), | |
624 | PIS(PLL_LOCK), | |
625 | PIS(PLL_UNLOCK), | |
626 | PIS(PLL_RECALL), | |
627 | PIS(COMPLEXIO_ERR), | |
628 | PIS(HS_TX_TIMEOUT), | |
629 | PIS(LP_RX_TIMEOUT), | |
630 | PIS(TE_TRIGGER), | |
631 | PIS(ACK_TRIGGER), | |
632 | PIS(SYNC_LOST), | |
633 | PIS(LDO_POWER_GOOD), | |
634 | PIS(TA_TIMEOUT)); | |
635 | #undef PIS | |
3de7a1dc TV |
636 | } |
637 | ||
638 | static void print_irq_status_vc(int channel, u32 status) | |
639 | { | |
d80d499e TV |
640 | if (status == 0) |
641 | return; | |
642 | ||
f30be7d3 | 643 | if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
3de7a1dc | 644 | return; |
f30be7d3 CM |
645 | |
646 | #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" | |
647 | ||
648 | pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", | |
649 | channel, | |
650 | status, | |
651 | PIS(CS), | |
652 | PIS(ECC_CORR), | |
653 | PIS(ECC_NO_CORR), | |
654 | verbose_irq ? PIS(PACKET_SENT) : "", | |
655 | PIS(BTA), | |
656 | PIS(FIFO_TX_OVF), | |
657 | PIS(FIFO_RX_OVF), | |
658 | PIS(FIFO_TX_UDF), | |
659 | PIS(PP_BUSY_CHANGE)); | |
3de7a1dc | 660 | #undef PIS |
3de7a1dc TV |
661 | } |
662 | ||
663 | static void print_irq_status_cio(u32 status) | |
664 | { | |
d80d499e TV |
665 | if (status == 0) |
666 | return; | |
667 | ||
f30be7d3 CM |
668 | #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" |
669 | ||
670 | pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", | |
671 | status, | |
672 | PIS(ERRSYNCESC1), | |
673 | PIS(ERRSYNCESC2), | |
674 | PIS(ERRSYNCESC3), | |
675 | PIS(ERRESC1), | |
676 | PIS(ERRESC2), | |
677 | PIS(ERRESC3), | |
678 | PIS(ERRCONTROL1), | |
679 | PIS(ERRCONTROL2), | |
680 | PIS(ERRCONTROL3), | |
681 | PIS(STATEULPS1), | |
682 | PIS(STATEULPS2), | |
683 | PIS(STATEULPS3), | |
684 | PIS(ERRCONTENTIONLP0_1), | |
685 | PIS(ERRCONTENTIONLP1_1), | |
686 | PIS(ERRCONTENTIONLP0_2), | |
687 | PIS(ERRCONTENTIONLP1_2), | |
688 | PIS(ERRCONTENTIONLP0_3), | |
689 | PIS(ERRCONTENTIONLP1_3), | |
690 | PIS(ULPSACTIVENOT_ALL0), | |
691 | PIS(ULPSACTIVENOT_ALL1)); | |
3de7a1dc | 692 | #undef PIS |
3de7a1dc TV |
693 | } |
694 | ||
69b281a6 | 695 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
a72b64b9 AT |
696 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
697 | u32 *vcstatus, u32 ciostatus) | |
3de7a1dc | 698 | { |
f1da39d9 | 699 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
700 | int i; |
701 | ||
f1da39d9 | 702 | spin_lock(&dsi->irq_stats_lock); |
69b281a6 | 703 | |
f1da39d9 AT |
704 | dsi->irq_stats.irq_count++; |
705 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); | |
69b281a6 TV |
706 | |
707 | for (i = 0; i < 4; ++i) | |
f1da39d9 | 708 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
69b281a6 | 709 | |
f1da39d9 | 710 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
69b281a6 | 711 | |
f1da39d9 | 712 | spin_unlock(&dsi->irq_stats_lock); |
69b281a6 TV |
713 | } |
714 | #else | |
a72b64b9 | 715 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
dfc0fd8d TV |
716 | #endif |
717 | ||
69b281a6 TV |
718 | static int debug_irq; |
719 | ||
a72b64b9 AT |
720 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, |
721 | u32 *vcstatus, u32 ciostatus) | |
69b281a6 | 722 | { |
f1da39d9 | 723 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
69b281a6 TV |
724 | int i; |
725 | ||
3de7a1dc TV |
726 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
727 | DSSERR("DSI error, irqstatus %x\n", irqstatus); | |
728 | print_irq_status(irqstatus); | |
f1da39d9 AT |
729 | spin_lock(&dsi->errors_lock); |
730 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; | |
731 | spin_unlock(&dsi->errors_lock); | |
3de7a1dc TV |
732 | } else if (debug_irq) { |
733 | print_irq_status(irqstatus); | |
734 | } | |
735 | ||
3de7a1dc | 736 | for (i = 0; i < 4; ++i) { |
69b281a6 TV |
737 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
738 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", | |
739 | i, vcstatus[i]); | |
740 | print_irq_status_vc(i, vcstatus[i]); | |
741 | } else if (debug_irq) { | |
742 | print_irq_status_vc(i, vcstatus[i]); | |
743 | } | |
744 | } | |
3de7a1dc | 745 | |
69b281a6 TV |
746 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
747 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); | |
748 | print_irq_status_cio(ciostatus); | |
749 | } else if (debug_irq) { | |
750 | print_irq_status_cio(ciostatus); | |
751 | } | |
752 | } | |
3de7a1dc | 753 | |
4ae2dddd TV |
754 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
755 | unsigned isr_array_size, u32 irqstatus) | |
756 | { | |
757 | struct dsi_isr_data *isr_data; | |
758 | int i; | |
759 | ||
760 | for (i = 0; i < isr_array_size; i++) { | |
761 | isr_data = &isr_array[i]; | |
762 | if (isr_data->isr && isr_data->mask & irqstatus) | |
763 | isr_data->isr(isr_data->arg, irqstatus); | |
764 | } | |
765 | } | |
766 | ||
767 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, | |
768 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
769 | { | |
770 | int i; | |
771 | ||
772 | dsi_call_isrs(isr_tables->isr_table, | |
773 | ARRAY_SIZE(isr_tables->isr_table), | |
774 | irqstatus); | |
775 | ||
776 | for (i = 0; i < 4; ++i) { | |
777 | if (vcstatus[i] == 0) | |
778 | continue; | |
779 | dsi_call_isrs(isr_tables->isr_table_vc[i], | |
780 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), | |
781 | vcstatus[i]); | |
782 | } | |
783 | ||
784 | if (ciostatus != 0) | |
785 | dsi_call_isrs(isr_tables->isr_table_cio, | |
786 | ARRAY_SIZE(isr_tables->isr_table_cio), | |
787 | ciostatus); | |
788 | } | |
789 | ||
69b281a6 TV |
790 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
791 | { | |
a72b64b9 | 792 | struct platform_device *dsidev; |
f1da39d9 | 793 | struct dsi_data *dsi; |
69b281a6 TV |
794 | u32 irqstatus, vcstatus[4], ciostatus; |
795 | int i; | |
dfc0fd8d | 796 | |
a72b64b9 | 797 | dsidev = (struct platform_device *) arg; |
f1da39d9 | 798 | dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 799 | |
0925afc9 TV |
800 | if (!dsi->is_enabled) |
801 | return IRQ_NONE; | |
802 | ||
f1da39d9 | 803 | spin_lock(&dsi->irq_lock); |
4ae2dddd | 804 | |
a72b64b9 | 805 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); |
3de7a1dc | 806 | |
69b281a6 | 807 | /* IRQ is not for us */ |
4ae2dddd | 808 | if (!irqstatus) { |
f1da39d9 | 809 | spin_unlock(&dsi->irq_lock); |
69b281a6 | 810 | return IRQ_NONE; |
4ae2dddd | 811 | } |
ab83b14c | 812 | |
a72b64b9 | 813 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
69b281a6 | 814 | /* flush posted write */ |
a72b64b9 | 815 | dsi_read_reg(dsidev, DSI_IRQSTATUS); |
69b281a6 TV |
816 | |
817 | for (i = 0; i < 4; ++i) { | |
818 | if ((irqstatus & (1 << i)) == 0) { | |
819 | vcstatus[i] = 0; | |
820 | continue; | |
3de7a1dc TV |
821 | } |
822 | ||
a72b64b9 | 823 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
69b281a6 | 824 | |
a72b64b9 | 825 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
3de7a1dc | 826 | /* flush posted write */ |
a72b64b9 | 827 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
3de7a1dc TV |
828 | } |
829 | ||
830 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { | |
a72b64b9 | 831 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
3de7a1dc | 832 | |
a72b64b9 | 833 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
3de7a1dc | 834 | /* flush posted write */ |
a72b64b9 | 835 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
69b281a6 TV |
836 | } else { |
837 | ciostatus = 0; | |
838 | } | |
3de7a1dc | 839 | |
69b281a6 TV |
840 | #ifdef DSI_CATCH_MISSING_TE |
841 | if (irqstatus & DSI_IRQ_TE_TRIGGER) | |
f1da39d9 | 842 | del_timer(&dsi->te_timer); |
69b281a6 TV |
843 | #endif |
844 | ||
4ae2dddd TV |
845 | /* make a copy and unlock, so that isrs can unregister |
846 | * themselves */ | |
f1da39d9 AT |
847 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
848 | sizeof(dsi->isr_tables)); | |
4ae2dddd | 849 | |
f1da39d9 | 850 | spin_unlock(&dsi->irq_lock); |
4ae2dddd | 851 | |
f1da39d9 | 852 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
4ae2dddd | 853 | |
a72b64b9 | 854 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); |
69b281a6 | 855 | |
a72b64b9 | 856 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); |
dfc0fd8d | 857 | |
affe360d | 858 | return IRQ_HANDLED; |
3de7a1dc TV |
859 | } |
860 | ||
f1da39d9 | 861 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 AT |
862 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, |
863 | struct dsi_isr_data *isr_array, | |
4ae2dddd TV |
864 | unsigned isr_array_size, u32 default_mask, |
865 | const struct dsi_reg enable_reg, | |
866 | const struct dsi_reg status_reg) | |
3de7a1dc | 867 | { |
4ae2dddd TV |
868 | struct dsi_isr_data *isr_data; |
869 | u32 mask; | |
870 | u32 old_mask; | |
3de7a1dc TV |
871 | int i; |
872 | ||
4ae2dddd | 873 | mask = default_mask; |
3de7a1dc | 874 | |
4ae2dddd TV |
875 | for (i = 0; i < isr_array_size; i++) { |
876 | isr_data = &isr_array[i]; | |
3de7a1dc | 877 | |
4ae2dddd TV |
878 | if (isr_data->isr == NULL) |
879 | continue; | |
880 | ||
881 | mask |= isr_data->mask; | |
3de7a1dc TV |
882 | } |
883 | ||
a72b64b9 | 884 | old_mask = dsi_read_reg(dsidev, enable_reg); |
4ae2dddd | 885 | /* clear the irqstatus for newly enabled irqs */ |
a72b64b9 AT |
886 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); |
887 | dsi_write_reg(dsidev, enable_reg, mask); | |
4ae2dddd TV |
888 | |
889 | /* flush posted writes */ | |
a72b64b9 AT |
890 | dsi_read_reg(dsidev, enable_reg); |
891 | dsi_read_reg(dsidev, status_reg); | |
4ae2dddd | 892 | } |
3de7a1dc | 893 | |
f1da39d9 | 894 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 895 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) |
4ae2dddd | 896 | { |
f1da39d9 | 897 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd | 898 | u32 mask = DSI_IRQ_ERROR_MASK; |
3de7a1dc | 899 | #ifdef DSI_CATCH_MISSING_TE |
4ae2dddd | 900 | mask |= DSI_IRQ_TE_TRIGGER; |
3de7a1dc | 901 | #endif |
f1da39d9 AT |
902 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, |
903 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, | |
4ae2dddd TV |
904 | DSI_IRQENABLE, DSI_IRQSTATUS); |
905 | } | |
3de7a1dc | 906 | |
f1da39d9 | 907 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 908 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) |
4ae2dddd | 909 | { |
f1da39d9 AT |
910 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
911 | ||
912 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], | |
913 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), | |
4ae2dddd TV |
914 | DSI_VC_IRQ_ERROR_MASK, |
915 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); | |
916 | } | |
917 | ||
f1da39d9 | 918 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 919 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) |
4ae2dddd | 920 | { |
f1da39d9 AT |
921 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
922 | ||
923 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, | |
924 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), | |
4ae2dddd TV |
925 | DSI_CIO_IRQ_ERROR_MASK, |
926 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); | |
927 | } | |
928 | ||
a72b64b9 | 929 | static void _dsi_initialize_irq(struct platform_device *dsidev) |
4ae2dddd | 930 | { |
f1da39d9 | 931 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
932 | unsigned long flags; |
933 | int vc; | |
934 | ||
f1da39d9 | 935 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 936 | |
f1da39d9 | 937 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
4ae2dddd | 938 | |
a72b64b9 | 939 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 940 | for (vc = 0; vc < 4; ++vc) |
a72b64b9 AT |
941 | _omap_dsi_set_irqs_vc(dsidev, vc); |
942 | _omap_dsi_set_irqs_cio(dsidev); | |
4ae2dddd | 943 | |
f1da39d9 | 944 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd | 945 | } |
3de7a1dc | 946 | |
4ae2dddd TV |
947 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
948 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
949 | { | |
950 | struct dsi_isr_data *isr_data; | |
951 | int free_idx; | |
952 | int i; | |
953 | ||
954 | BUG_ON(isr == NULL); | |
955 | ||
956 | /* check for duplicate entry and find a free slot */ | |
957 | free_idx = -1; | |
958 | for (i = 0; i < isr_array_size; i++) { | |
959 | isr_data = &isr_array[i]; | |
960 | ||
961 | if (isr_data->isr == isr && isr_data->arg == arg && | |
962 | isr_data->mask == mask) { | |
963 | return -EINVAL; | |
964 | } | |
965 | ||
966 | if (isr_data->isr == NULL && free_idx == -1) | |
967 | free_idx = i; | |
968 | } | |
969 | ||
970 | if (free_idx == -1) | |
971 | return -EBUSY; | |
972 | ||
973 | isr_data = &isr_array[free_idx]; | |
974 | isr_data->isr = isr; | |
975 | isr_data->arg = arg; | |
976 | isr_data->mask = mask; | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
981 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
982 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
983 | { | |
984 | struct dsi_isr_data *isr_data; | |
985 | int i; | |
986 | ||
987 | for (i = 0; i < isr_array_size; i++) { | |
988 | isr_data = &isr_array[i]; | |
989 | if (isr_data->isr != isr || isr_data->arg != arg || | |
990 | isr_data->mask != mask) | |
991 | continue; | |
992 | ||
993 | isr_data->isr = NULL; | |
994 | isr_data->arg = NULL; | |
995 | isr_data->mask = 0; | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
1000 | return -EINVAL; | |
1001 | } | |
1002 | ||
a72b64b9 AT |
1003 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, |
1004 | void *arg, u32 mask) | |
4ae2dddd | 1005 | { |
f1da39d9 | 1006 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1007 | unsigned long flags; |
1008 | int r; | |
1009 | ||
f1da39d9 | 1010 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1011 | |
f1da39d9 AT |
1012 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
1013 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
1014 | |
1015 | if (r == 0) | |
a72b64b9 | 1016 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 1017 | |
f1da39d9 | 1018 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1019 | |
1020 | return r; | |
1021 | } | |
1022 | ||
a72b64b9 AT |
1023 | static int dsi_unregister_isr(struct platform_device *dsidev, |
1024 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1025 | { |
f1da39d9 | 1026 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1027 | unsigned long flags; |
1028 | int r; | |
1029 | ||
f1da39d9 | 1030 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1031 | |
f1da39d9 AT |
1032 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
1033 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
1034 | |
1035 | if (r == 0) | |
a72b64b9 | 1036 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 1037 | |
f1da39d9 | 1038 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1039 | |
1040 | return r; | |
1041 | } | |
1042 | ||
a72b64b9 AT |
1043 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, |
1044 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1045 | { |
f1da39d9 | 1046 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1047 | unsigned long flags; |
1048 | int r; | |
1049 | ||
f1da39d9 | 1050 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
1051 | |
1052 | r = _dsi_register_isr(isr, arg, mask, | |
f1da39d9 AT |
1053 | dsi->isr_tables.isr_table_vc[channel], |
1054 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
1055 | |
1056 | if (r == 0) | |
a72b64b9 | 1057 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 1058 | |
f1da39d9 | 1059 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1060 | |
1061 | return r; | |
1062 | } | |
1063 | ||
a72b64b9 AT |
1064 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, |
1065 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1066 | { |
f1da39d9 | 1067 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1068 | unsigned long flags; |
1069 | int r; | |
1070 | ||
f1da39d9 | 1071 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
1072 | |
1073 | r = _dsi_unregister_isr(isr, arg, mask, | |
f1da39d9 AT |
1074 | dsi->isr_tables.isr_table_vc[channel], |
1075 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
1076 | |
1077 | if (r == 0) | |
a72b64b9 | 1078 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 1079 | |
f1da39d9 | 1080 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1081 | |
1082 | return r; | |
1083 | } | |
1084 | ||
a72b64b9 AT |
1085 | static int dsi_register_isr_cio(struct platform_device *dsidev, |
1086 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1087 | { |
f1da39d9 | 1088 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1089 | unsigned long flags; |
1090 | int r; | |
1091 | ||
f1da39d9 | 1092 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1093 | |
f1da39d9 AT |
1094 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1095 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1096 | |
1097 | if (r == 0) | |
a72b64b9 | 1098 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1099 | |
f1da39d9 | 1100 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1101 | |
1102 | return r; | |
1103 | } | |
1104 | ||
a72b64b9 AT |
1105 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, |
1106 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1107 | { |
f1da39d9 | 1108 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1109 | unsigned long flags; |
1110 | int r; | |
1111 | ||
f1da39d9 | 1112 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1113 | |
f1da39d9 AT |
1114 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1115 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1116 | |
1117 | if (r == 0) | |
a72b64b9 | 1118 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1119 | |
f1da39d9 | 1120 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1121 | |
1122 | return r; | |
3de7a1dc TV |
1123 | } |
1124 | ||
a72b64b9 | 1125 | static u32 dsi_get_errors(struct platform_device *dsidev) |
3de7a1dc | 1126 | { |
f1da39d9 | 1127 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1128 | unsigned long flags; |
1129 | u32 e; | |
f1da39d9 AT |
1130 | spin_lock_irqsave(&dsi->errors_lock, flags); |
1131 | e = dsi->errors; | |
1132 | dsi->errors = 0; | |
1133 | spin_unlock_irqrestore(&dsi->errors_lock, flags); | |
3de7a1dc TV |
1134 | return e; |
1135 | } | |
1136 | ||
4fbafaf3 | 1137 | int dsi_runtime_get(struct platform_device *dsidev) |
3de7a1dc | 1138 | { |
4fbafaf3 TV |
1139 | int r; |
1140 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1141 | ||
1142 | DSSDBG("dsi_runtime_get\n"); | |
1143 | ||
1144 | r = pm_runtime_get_sync(&dsi->pdev->dev); | |
1145 | WARN_ON(r < 0); | |
1146 | return r < 0 ? r : 0; | |
1147 | } | |
1148 | ||
1149 | void dsi_runtime_put(struct platform_device *dsidev) | |
1150 | { | |
1151 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1152 | int r; | |
1153 | ||
1154 | DSSDBG("dsi_runtime_put\n"); | |
1155 | ||
0eaf9f52 | 1156 | r = pm_runtime_put_sync(&dsi->pdev->dev); |
5be3aebd | 1157 | WARN_ON(r < 0 && r != -ENOSYS); |
3de7a1dc TV |
1158 | } |
1159 | ||
b2541c40 TV |
1160 | static int dsi_regulator_init(struct platform_device *dsidev) |
1161 | { | |
1162 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1163 | struct regulator *vdds_dsi; | |
02b7a320 | 1164 | int r; |
b2541c40 TV |
1165 | |
1166 | if (dsi->vdds_dsi_reg != NULL) | |
1167 | return 0; | |
1168 | ||
931d4bd6 | 1169 | vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); |
b2541c40 TV |
1170 | |
1171 | if (IS_ERR(vdds_dsi)) { | |
40359a9b | 1172 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) |
931d4bd6 | 1173 | DSSERR("can't get DSI VDD regulator\n"); |
b2541c40 TV |
1174 | return PTR_ERR(vdds_dsi); |
1175 | } | |
1176 | ||
02b7a320 TV |
1177 | if (regulator_can_change_voltage(vdds_dsi)) { |
1178 | r = regulator_set_voltage(vdds_dsi, 1800000, 1800000); | |
1179 | if (r) { | |
1180 | devm_regulator_put(vdds_dsi); | |
1181 | DSSERR("can't set the DSI regulator voltage\n"); | |
1182 | return r; | |
1183 | } | |
1184 | } | |
1185 | ||
b2541c40 TV |
1186 | dsi->vdds_dsi_reg = vdds_dsi; |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
3de7a1dc | 1191 | /* source clock for DSI PLL. this could also be PCLKFREE */ |
a72b64b9 AT |
1192 | static inline void dsi_enable_pll_clock(struct platform_device *dsidev, |
1193 | bool enable) | |
3de7a1dc | 1194 | { |
f1da39d9 AT |
1195 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1196 | ||
3de7a1dc | 1197 | if (enable) |
f11766d1 | 1198 | clk_prepare_enable(dsi->sys_clk); |
3de7a1dc | 1199 | else |
f11766d1 | 1200 | clk_disable_unprepare(dsi->sys_clk); |
3de7a1dc | 1201 | |
f1da39d9 | 1202 | if (enable && dsi->pll_locked) { |
a72b64b9 | 1203 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) |
3de7a1dc TV |
1204 | DSSERR("cannot lock PLL when enabling clocks\n"); |
1205 | } | |
1206 | } | |
1207 | ||
a72b64b9 | 1208 | static void _dsi_print_reset_status(struct platform_device *dsidev) |
3de7a1dc TV |
1209 | { |
1210 | u32 l; | |
c335cbf9 | 1211 | int b0, b1, b2; |
3de7a1dc | 1212 | |
3de7a1dc TV |
1213 | /* A dummy read using the SCP interface to any DSIPHY register is |
1214 | * required after DSIPHY reset to complete the reset of the DSI complex | |
1215 | * I/O. */ | |
a72b64b9 | 1216 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc | 1217 | |
c335cbf9 TV |
1218 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
1219 | b0 = 28; | |
1220 | b1 = 27; | |
1221 | b2 = 26; | |
1222 | } else { | |
1223 | b0 = 24; | |
1224 | b1 = 25; | |
1225 | b2 = 26; | |
1226 | } | |
1227 | ||
f30be7d3 CM |
1228 | #define DSI_FLD_GET(fld, start, end)\ |
1229 | FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) | |
1230 | ||
1231 | pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", | |
1232 | DSI_FLD_GET(PLL_STATUS, 0, 0), | |
1233 | DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), | |
1234 | DSI_FLD_GET(DSIPHY_CFG5, b0, b0), | |
1235 | DSI_FLD_GET(DSIPHY_CFG5, b1, b1), | |
1236 | DSI_FLD_GET(DSIPHY_CFG5, b2, b2), | |
1237 | DSI_FLD_GET(DSIPHY_CFG5, 29, 29), | |
1238 | DSI_FLD_GET(DSIPHY_CFG5, 30, 30), | |
1239 | DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); | |
1240 | ||
1241 | #undef DSI_FLD_GET | |
3de7a1dc | 1242 | } |
3de7a1dc | 1243 | |
a72b64b9 | 1244 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) |
3de7a1dc TV |
1245 | { |
1246 | DSSDBG("dsi_if_enable(%d)\n", enable); | |
1247 | ||
1248 | enable = enable ? 1 : 0; | |
a72b64b9 | 1249 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
3de7a1dc | 1250 | |
a72b64b9 | 1251 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { |
3de7a1dc TV |
1252 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
1253 | return -EIO; | |
1254 | } | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
a72b64b9 | 1259 | unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) |
3de7a1dc | 1260 | { |
f1da39d9 AT |
1261 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1262 | ||
1263 | return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk; | |
3de7a1dc TV |
1264 | } |
1265 | ||
a72b64b9 | 1266 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) |
3de7a1dc | 1267 | { |
f1da39d9 AT |
1268 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1269 | ||
1270 | return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk; | |
3de7a1dc TV |
1271 | } |
1272 | ||
a72b64b9 | 1273 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) |
3de7a1dc | 1274 | { |
f1da39d9 AT |
1275 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1276 | ||
1277 | return dsi->current_cinfo.clkin4ddr / 16; | |
3de7a1dc TV |
1278 | } |
1279 | ||
a72b64b9 | 1280 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) |
3de7a1dc TV |
1281 | { |
1282 | unsigned long r; | |
4fbafaf3 | 1283 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc | 1284 | |
11ee9606 | 1285 | if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { |
1bb47835 | 1286 | /* DSI FCLK source is DSS_CLK_FCK */ |
4fbafaf3 | 1287 | r = clk_get_rate(dsi->dss_clk); |
3de7a1dc | 1288 | } else { |
1bb47835 | 1289 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
a72b64b9 | 1290 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); |
3de7a1dc TV |
1291 | } |
1292 | ||
1293 | return r; | |
1294 | } | |
1295 | ||
f1e0001f TV |
1296 | static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo, |
1297 | unsigned long lp_clk_min, unsigned long lp_clk_max) | |
1298 | { | |
1299 | unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk; | |
1300 | unsigned lp_clk_div; | |
1301 | unsigned long lp_clk; | |
1302 | ||
1303 | lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); | |
1304 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1305 | ||
1306 | if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) | |
1307 | return -EINVAL; | |
1308 | ||
1309 | cinfo->lp_clk_div = lp_clk_div; | |
1310 | cinfo->lp_clk = lp_clk; | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
5761217a | 1315 | static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) |
3de7a1dc | 1316 | { |
f1da39d9 | 1317 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1318 | unsigned long dsi_fclk; |
1319 | unsigned lp_clk_div; | |
1320 | unsigned long lp_clk; | |
1321 | ||
a0d269ec | 1322 | lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div; |
3de7a1dc | 1323 | |
f1da39d9 | 1324 | if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max) |
3de7a1dc TV |
1325 | return -EINVAL; |
1326 | ||
a72b64b9 | 1327 | dsi_fclk = dsi_fclk_rate(dsidev); |
3de7a1dc TV |
1328 | |
1329 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1330 | ||
1331 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); | |
f1da39d9 AT |
1332 | dsi->current_cinfo.lp_clk = lp_clk; |
1333 | dsi->current_cinfo.lp_clk_div = lp_clk_div; | |
3de7a1dc | 1334 | |
a72b64b9 AT |
1335 | /* LP_CLK_DIVISOR */ |
1336 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); | |
3de7a1dc | 1337 | |
a72b64b9 AT |
1338 | /* LP_RX_SYNCHRO_ENABLE */ |
1339 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); | |
3de7a1dc TV |
1340 | |
1341 | return 0; | |
1342 | } | |
1343 | ||
a72b64b9 | 1344 | static void dsi_enable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1345 | { |
f1da39d9 AT |
1346 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1347 | ||
1348 | if (dsi->scp_clk_refcount++ == 0) | |
a72b64b9 | 1349 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 TV |
1350 | } |
1351 | ||
a72b64b9 | 1352 | static void dsi_disable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1353 | { |
f1da39d9 AT |
1354 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1355 | ||
1356 | WARN_ON(dsi->scp_clk_refcount == 0); | |
1357 | if (--dsi->scp_clk_refcount == 0) | |
a72b64b9 | 1358 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 | 1359 | } |
3de7a1dc TV |
1360 | |
1361 | enum dsi_pll_power_state { | |
1362 | DSI_PLL_POWER_OFF = 0x0, | |
1363 | DSI_PLL_POWER_ON_HSCLK = 0x1, | |
1364 | DSI_PLL_POWER_ON_ALL = 0x2, | |
1365 | DSI_PLL_POWER_ON_DIV = 0x3, | |
1366 | }; | |
1367 | ||
a72b64b9 AT |
1368 | static int dsi_pll_power(struct platform_device *dsidev, |
1369 | enum dsi_pll_power_state state) | |
3de7a1dc TV |
1370 | { |
1371 | int t = 0; | |
1372 | ||
c94dfe05 TV |
1373 | /* DSI-PLL power command 0x3 is not working */ |
1374 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && | |
1375 | state == DSI_PLL_POWER_ON_DIV) | |
1376 | state = DSI_PLL_POWER_ON_ALL; | |
1377 | ||
a72b64b9 AT |
1378 | /* PLL_PWR_CMD */ |
1379 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); | |
3de7a1dc TV |
1380 | |
1381 | /* PLL_PWR_STATUS */ | |
a72b64b9 | 1382 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
24be78b3 | 1383 | if (++t > 1000) { |
3de7a1dc TV |
1384 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
1385 | state); | |
1386 | return -ENODEV; | |
1387 | } | |
24be78b3 | 1388 | udelay(1); |
3de7a1dc TV |
1389 | } |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
72658f07 TV |
1394 | unsigned long dsi_get_pll_clkin(struct platform_device *dsidev) |
1395 | { | |
1396 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1397 | return clk_get_rate(dsi->sys_clk); | |
1398 | } | |
1399 | ||
1400 | bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll, | |
1401 | unsigned long out_min, dsi_hsdiv_calc_func func, void *data) | |
1402 | { | |
1403 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1404 | int regm, regm_start, regm_stop; | |
1405 | unsigned long out_max; | |
1406 | unsigned long out; | |
1407 | ||
1408 | out_min = out_min ? out_min : 1; | |
1409 | out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); | |
1410 | ||
1411 | regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul); | |
1412 | regm_stop = min(pll / out_min, dsi->regm_dispc_max); | |
1413 | ||
1414 | for (regm = regm_start; regm <= regm_stop; ++regm) { | |
1415 | out = pll / regm; | |
1416 | ||
1417 | if (func(regm, out, data)) | |
1418 | return true; | |
1419 | } | |
1420 | ||
1421 | return false; | |
1422 | } | |
1423 | ||
1424 | bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin, | |
1425 | unsigned long pll_min, unsigned long pll_max, | |
1426 | dsi_pll_calc_func func, void *data) | |
1427 | { | |
1428 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1429 | int regn, regn_start, regn_stop; | |
1430 | int regm, regm_start, regm_stop; | |
1431 | unsigned long fint, pll; | |
1432 | const unsigned long pll_hw_max = 1800000000; | |
1433 | unsigned long fint_hw_min, fint_hw_max; | |
1434 | ||
1435 | fint_hw_min = dsi->fint_min; | |
1436 | fint_hw_max = dsi->fint_max; | |
1437 | ||
1438 | regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); | |
1439 | regn_stop = min(clkin / fint_hw_min, dsi->regn_max); | |
1440 | ||
1441 | pll_max = pll_max ? pll_max : ULONG_MAX; | |
1442 | ||
1443 | for (regn = regn_start; regn <= regn_stop; ++regn) { | |
1444 | fint = clkin / regn; | |
1445 | ||
1446 | regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), | |
1447 | 1ul); | |
1448 | regm_stop = min3(pll_max / fint / 2, | |
1449 | pll_hw_max / fint / 2, | |
1450 | dsi->regm_max); | |
1451 | ||
1452 | for (regm = regm_start; regm <= regm_stop; ++regm) { | |
1453 | pll = 2 * regm * fint; | |
1454 | ||
1455 | if (func(regn, regm, fint, pll, data)) | |
1456 | return true; | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | return false; | |
1461 | } | |
1462 | ||
3de7a1dc | 1463 | /* calculate clock rates using dividers in cinfo */ |
b6e695ab | 1464 | static int dsi_calc_clock_rates(struct platform_device *dsidev, |
ff1b2cde | 1465 | struct dsi_clock_info *cinfo) |
3de7a1dc | 1466 | { |
f1da39d9 AT |
1467 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1468 | ||
1469 | if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max) | |
3de7a1dc TV |
1470 | return -EINVAL; |
1471 | ||
f1da39d9 | 1472 | if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max) |
3de7a1dc TV |
1473 | return -EINVAL; |
1474 | ||
f1da39d9 | 1475 | if (cinfo->regm_dispc > dsi->regm_dispc_max) |
3de7a1dc TV |
1476 | return -EINVAL; |
1477 | ||
f1da39d9 | 1478 | if (cinfo->regm_dsi > dsi->regm_dsi_max) |
3de7a1dc TV |
1479 | return -EINVAL; |
1480 | ||
b6e695ab TV |
1481 | cinfo->clkin = clk_get_rate(dsi->sys_clk); |
1482 | cinfo->fint = cinfo->clkin / cinfo->regn; | |
3de7a1dc | 1483 | |
f1da39d9 | 1484 | if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) |
3de7a1dc TV |
1485 | return -EINVAL; |
1486 | ||
1487 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; | |
1488 | ||
1489 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) | |
1490 | return -EINVAL; | |
1491 | ||
1bb47835 AT |
1492 | if (cinfo->regm_dispc > 0) |
1493 | cinfo->dsi_pll_hsdiv_dispc_clk = | |
1494 | cinfo->clkin4ddr / cinfo->regm_dispc; | |
3de7a1dc | 1495 | else |
1bb47835 | 1496 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
3de7a1dc | 1497 | |
1bb47835 AT |
1498 | if (cinfo->regm_dsi > 0) |
1499 | cinfo->dsi_pll_hsdiv_dsi_clk = | |
1500 | cinfo->clkin4ddr / cinfo->regm_dsi; | |
3de7a1dc | 1501 | else |
1bb47835 | 1502 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
3de7a1dc TV |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
f1e0001f | 1507 | static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo) |
d66b1581 TV |
1508 | { |
1509 | unsigned long max_dsi_fck; | |
1510 | ||
1511 | max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); | |
1512 | ||
1513 | cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck); | |
1514 | cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi; | |
1515 | } | |
1516 | ||
544bfb68 TV |
1517 | static int dsi_wait_hsdiv_ack(struct platform_device *dsidev, u32 hsdiv_ack_mask) |
1518 | { | |
1519 | int t = 100; | |
1520 | ||
1521 | while (t-- > 0) { | |
1522 | u32 v = dsi_read_reg(dsidev, DSI_PLL_STATUS); | |
1523 | v &= hsdiv_ack_mask; | |
1524 | if (v == hsdiv_ack_mask) | |
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | return -ETIMEDOUT; | |
1529 | } | |
1530 | ||
a72b64b9 AT |
1531 | int dsi_pll_set_clock_div(struct platform_device *dsidev, |
1532 | struct dsi_clock_info *cinfo) | |
3de7a1dc | 1533 | { |
f1da39d9 | 1534 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1535 | int r = 0; |
1536 | u32 l; | |
9613c02b | 1537 | int f = 0; |
49641116 TA |
1538 | u8 regn_start, regn_end, regm_start, regm_end; |
1539 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; | |
3de7a1dc | 1540 | |
702d267e | 1541 | DSSDBG("DSI PLL clock config starts"); |
3de7a1dc | 1542 | |
b6e695ab | 1543 | dsi->current_cinfo.clkin = cinfo->clkin; |
f1da39d9 AT |
1544 | dsi->current_cinfo.fint = cinfo->fint; |
1545 | dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; | |
1546 | dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = | |
1bb47835 | 1547 | cinfo->dsi_pll_hsdiv_dispc_clk; |
f1da39d9 | 1548 | dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk = |
1bb47835 | 1549 | cinfo->dsi_pll_hsdiv_dsi_clk; |
3de7a1dc | 1550 | |
f1da39d9 AT |
1551 | dsi->current_cinfo.regn = cinfo->regn; |
1552 | dsi->current_cinfo.regm = cinfo->regm; | |
1553 | dsi->current_cinfo.regm_dispc = cinfo->regm_dispc; | |
1554 | dsi->current_cinfo.regm_dsi = cinfo->regm_dsi; | |
3de7a1dc TV |
1555 | |
1556 | DSSDBG("DSI Fint %ld\n", cinfo->fint); | |
1557 | ||
b6e695ab | 1558 | DSSDBG("clkin rate %ld\n", cinfo->clkin); |
3de7a1dc TV |
1559 | |
1560 | /* DSIPHY == CLKIN4DDR */ | |
b6e695ab | 1561 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n", |
3de7a1dc TV |
1562 | cinfo->regm, |
1563 | cinfo->regn, | |
1564 | cinfo->clkin, | |
3de7a1dc TV |
1565 | cinfo->clkin4ddr); |
1566 | ||
1567 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", | |
1568 | cinfo->clkin4ddr / 1000 / 1000 / 2); | |
1569 | ||
1570 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); | |
1571 | ||
1bb47835 | 1572 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
89a35e51 AT |
1573 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1574 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), | |
1bb47835 AT |
1575 | cinfo->dsi_pll_hsdiv_dispc_clk); |
1576 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, | |
89a35e51 AT |
1577 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
1578 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | |
1bb47835 | 1579 | cinfo->dsi_pll_hsdiv_dsi_clk); |
3de7a1dc | 1580 | |
49641116 TA |
1581 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
1582 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); | |
1583 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, | |
1584 | ®m_dispc_end); | |
1585 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, | |
1586 | ®m_dsi_end); | |
1587 | ||
a72b64b9 AT |
1588 | /* DSI_PLL_AUTOMODE = manual */ |
1589 | REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); | |
3de7a1dc | 1590 | |
a72b64b9 | 1591 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1); |
3de7a1dc | 1592 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
49641116 TA |
1593 | /* DSI_PLL_REGN */ |
1594 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); | |
1595 | /* DSI_PLL_REGM */ | |
1596 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); | |
1597 | /* DSI_CLOCK_DIV */ | |
1bb47835 | 1598 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
49641116 TA |
1599 | regm_dispc_start, regm_dispc_end); |
1600 | /* DSIPROTO_CLOCK_DIV */ | |
1bb47835 | 1601 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
49641116 | 1602 | regm_dsi_start, regm_dsi_end); |
a72b64b9 | 1603 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l); |
3de7a1dc | 1604 | |
f1da39d9 | 1605 | BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max); |
9613c02b | 1606 | |
f8ef3d69 TV |
1607 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
1608 | ||
9613c02b AT |
1609 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { |
1610 | f = cinfo->fint < 1000000 ? 0x3 : | |
1611 | cinfo->fint < 1250000 ? 0x4 : | |
1612 | cinfo->fint < 1500000 ? 0x5 : | |
1613 | cinfo->fint < 1750000 ? 0x6 : | |
1614 | 0x7; | |
3de7a1dc | 1615 | |
9613c02b | 1616 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ |
f8ef3d69 TV |
1617 | } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) { |
1618 | f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4; | |
1619 | ||
a7f91edf | 1620 | l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */ |
f8ef3d69 TV |
1621 | } |
1622 | ||
3de7a1dc TV |
1623 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
1624 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ | |
1625 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ | |
6d44610f TV |
1626 | if (dss_has_feature(FEAT_DSI_PLL_REFSEL)) |
1627 | l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */ | |
a72b64b9 | 1628 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc | 1629 | |
a72b64b9 | 1630 | REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
3de7a1dc | 1631 | |
a72b64b9 | 1632 | if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) { |
3de7a1dc TV |
1633 | DSSERR("dsi pll go bit not going down.\n"); |
1634 | r = -EIO; | |
1635 | goto err; | |
1636 | } | |
1637 | ||
a72b64b9 | 1638 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) { |
3de7a1dc TV |
1639 | DSSERR("cannot lock PLL\n"); |
1640 | r = -EIO; | |
1641 | goto err; | |
1642 | } | |
1643 | ||
f1da39d9 | 1644 | dsi->pll_locked = 1; |
3de7a1dc | 1645 | |
a72b64b9 | 1646 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
3de7a1dc TV |
1647 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
1648 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ | |
1649 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ | |
1650 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ | |
1651 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ | |
1652 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ | |
1653 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1654 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ | |
1655 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ | |
1656 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ | |
1657 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ | |
1658 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ | |
1659 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ | |
1660 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ | |
a72b64b9 | 1661 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc | 1662 | |
544bfb68 TV |
1663 | r = dsi_wait_hsdiv_ack(dsidev, BIT(7) | BIT(8)); |
1664 | if (r) { | |
1665 | DSSERR("failed to enable HSDIV clocks: %d\n", r); | |
1666 | goto err; | |
1667 | } | |
1668 | ||
1669 | ||
3de7a1dc TV |
1670 | DSSDBG("PLL config done\n"); |
1671 | err: | |
1672 | return r; | |
1673 | } | |
1674 | ||
a72b64b9 AT |
1675 | int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, |
1676 | bool enable_hsdiv) | |
3de7a1dc | 1677 | { |
f1da39d9 | 1678 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1679 | int r = 0; |
1680 | enum dsi_pll_power_state pwstate; | |
1681 | ||
1682 | DSSDBG("PLL init\n"); | |
1683 | ||
7a98786c TV |
1684 | /* |
1685 | * It seems that on many OMAPs we need to enable both to have a | |
1686 | * functional HSDivider. | |
1687 | */ | |
1688 | enable_hsclk = enable_hsdiv = true; | |
1689 | ||
b2541c40 TV |
1690 | r = dsi_regulator_init(dsidev); |
1691 | if (r) | |
1692 | return r; | |
f2988ab9 | 1693 | |
a72b64b9 | 1694 | dsi_enable_pll_clock(dsidev, 1); |
24c1ae41 TV |
1695 | /* |
1696 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. | |
1697 | */ | |
a72b64b9 | 1698 | dsi_enable_scp_clk(dsidev); |
3de7a1dc | 1699 | |
f1da39d9 AT |
1700 | if (!dsi->vdds_dsi_enabled) { |
1701 | r = regulator_enable(dsi->vdds_dsi_reg); | |
2a89dc15 TV |
1702 | if (r) |
1703 | goto err0; | |
f1da39d9 | 1704 | dsi->vdds_dsi_enabled = true; |
2a89dc15 | 1705 | } |
3de7a1dc TV |
1706 | |
1707 | /* XXX PLL does not come out of reset without this... */ | |
1708 | dispc_pck_free_enable(1); | |
1709 | ||
a72b64b9 | 1710 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { |
3de7a1dc TV |
1711 | DSSERR("PLL not coming out of reset.\n"); |
1712 | r = -ENODEV; | |
481dfa0e | 1713 | dispc_pck_free_enable(0); |
3de7a1dc TV |
1714 | goto err1; |
1715 | } | |
1716 | ||
1717 | /* XXX ... but if left on, we get problems when planes do not | |
1718 | * fill the whole display. No idea about this */ | |
1719 | dispc_pck_free_enable(0); | |
1720 | ||
1721 | if (enable_hsclk && enable_hsdiv) | |
1722 | pwstate = DSI_PLL_POWER_ON_ALL; | |
1723 | else if (enable_hsclk) | |
1724 | pwstate = DSI_PLL_POWER_ON_HSCLK; | |
1725 | else if (enable_hsdiv) | |
1726 | pwstate = DSI_PLL_POWER_ON_DIV; | |
1727 | else | |
1728 | pwstate = DSI_PLL_POWER_OFF; | |
1729 | ||
a72b64b9 | 1730 | r = dsi_pll_power(dsidev, pwstate); |
3de7a1dc TV |
1731 | |
1732 | if (r) | |
1733 | goto err1; | |
1734 | ||
1735 | DSSDBG("PLL init done\n"); | |
1736 | ||
1737 | return 0; | |
1738 | err1: | |
f1da39d9 AT |
1739 | if (dsi->vdds_dsi_enabled) { |
1740 | regulator_disable(dsi->vdds_dsi_reg); | |
1741 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1742 | } |
3de7a1dc | 1743 | err0: |
a72b64b9 | 1744 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1745 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc TV |
1746 | return r; |
1747 | } | |
1748 | ||
a72b64b9 | 1749 | void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) |
3de7a1dc | 1750 | { |
f1da39d9 AT |
1751 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1752 | ||
1753 | dsi->pll_locked = 0; | |
a72b64b9 | 1754 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); |
2a89dc15 | 1755 | if (disconnect_lanes) { |
f1da39d9 AT |
1756 | WARN_ON(!dsi->vdds_dsi_enabled); |
1757 | regulator_disable(dsi->vdds_dsi_reg); | |
1758 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1759 | } |
24c1ae41 | 1760 | |
a72b64b9 | 1761 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1762 | dsi_enable_pll_clock(dsidev, 0); |
24c1ae41 | 1763 | |
3de7a1dc TV |
1764 | DSSDBG("PLL uninit done\n"); |
1765 | } | |
1766 | ||
5a8b572d AT |
1767 | static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, |
1768 | struct seq_file *s) | |
3de7a1dc | 1769 | { |
f1da39d9 AT |
1770 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1771 | struct dsi_clock_info *cinfo = &dsi->current_cinfo; | |
89a35e51 | 1772 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
11ee9606 | 1773 | int dsi_module = dsi->module_id; |
067a57e4 AT |
1774 | |
1775 | dispc_clk_src = dss_get_dispc_clk_source(); | |
5a8b572d | 1776 | dsi_clk_src = dss_get_dsi_clk_source(dsi_module); |
3de7a1dc | 1777 | |
4fbafaf3 TV |
1778 | if (dsi_runtime_get(dsidev)) |
1779 | return; | |
3de7a1dc | 1780 | |
5a8b572d | 1781 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); |
3de7a1dc | 1782 | |
b6e695ab | 1783 | seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin); |
3de7a1dc TV |
1784 | |
1785 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); | |
1786 | ||
1787 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", | |
1788 | cinfo->clkin4ddr, cinfo->regm); | |
1789 | ||
84309f16 AT |
1790 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n", |
1791 | dss_feat_get_clk_source_name(dsi_module == 0 ? | |
1792 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : | |
1793 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), | |
1bb47835 AT |
1794 | cinfo->dsi_pll_hsdiv_dispc_clk, |
1795 | cinfo->regm_dispc, | |
89a35e51 | 1796 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1797 | "off" : "on"); |
3de7a1dc | 1798 | |
84309f16 AT |
1799 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n", |
1800 | dss_feat_get_clk_source_name(dsi_module == 0 ? | |
1801 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : | |
1802 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), | |
1bb47835 AT |
1803 | cinfo->dsi_pll_hsdiv_dsi_clk, |
1804 | cinfo->regm_dsi, | |
89a35e51 | 1805 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1806 | "off" : "on"); |
3de7a1dc | 1807 | |
5a8b572d | 1808 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
3de7a1dc | 1809 | |
067a57e4 AT |
1810 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
1811 | dss_get_generic_clk_source_name(dsi_clk_src), | |
1812 | dss_feat_get_clk_source_name(dsi_clk_src)); | |
3de7a1dc | 1813 | |
a72b64b9 | 1814 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); |
3de7a1dc TV |
1815 | |
1816 | seq_printf(s, "DDR_CLK\t\t%lu\n", | |
1817 | cinfo->clkin4ddr / 4); | |
1818 | ||
a72b64b9 | 1819 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); |
3de7a1dc TV |
1820 | |
1821 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); | |
1822 | ||
4fbafaf3 | 1823 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
1824 | } |
1825 | ||
5a8b572d AT |
1826 | void dsi_dump_clocks(struct seq_file *s) |
1827 | { | |
1828 | struct platform_device *dsidev; | |
1829 | int i; | |
1830 | ||
1831 | for (i = 0; i < MAX_NUM_DSI; i++) { | |
1832 | dsidev = dsi_get_dsidev_from_id(i); | |
1833 | if (dsidev) | |
1834 | dsi_dump_dsidev_clocks(dsidev, s); | |
1835 | } | |
1836 | } | |
1837 | ||
dfc0fd8d | 1838 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
5a8b572d AT |
1839 | static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, |
1840 | struct seq_file *s) | |
dfc0fd8d | 1841 | { |
f1da39d9 | 1842 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
dfc0fd8d TV |
1843 | unsigned long flags; |
1844 | struct dsi_irq_stats stats; | |
1845 | ||
f1da39d9 | 1846 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
dfc0fd8d | 1847 | |
f1da39d9 AT |
1848 | stats = dsi->irq_stats; |
1849 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); | |
1850 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d | 1851 | |
f1da39d9 | 1852 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
dfc0fd8d TV |
1853 | |
1854 | seq_printf(s, "period %u ms\n", | |
1855 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
1856 | ||
1857 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
1858 | #define PIS(x) \ | |
1859 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); | |
1860 | ||
11ee9606 | 1861 | seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); |
dfc0fd8d TV |
1862 | PIS(VC0); |
1863 | PIS(VC1); | |
1864 | PIS(VC2); | |
1865 | PIS(VC3); | |
1866 | PIS(WAKEUP); | |
1867 | PIS(RESYNC); | |
1868 | PIS(PLL_LOCK); | |
1869 | PIS(PLL_UNLOCK); | |
1870 | PIS(PLL_RECALL); | |
1871 | PIS(COMPLEXIO_ERR); | |
1872 | PIS(HS_TX_TIMEOUT); | |
1873 | PIS(LP_RX_TIMEOUT); | |
1874 | PIS(TE_TRIGGER); | |
1875 | PIS(ACK_TRIGGER); | |
1876 | PIS(SYNC_LOST); | |
1877 | PIS(LDO_POWER_GOOD); | |
1878 | PIS(TA_TIMEOUT); | |
1879 | #undef PIS | |
1880 | ||
1881 | #define PIS(x) \ | |
1882 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ | |
1883 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ | |
1884 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ | |
1885 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ | |
1886 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); | |
1887 | ||
1888 | seq_printf(s, "-- VC interrupts --\n"); | |
1889 | PIS(CS); | |
1890 | PIS(ECC_CORR); | |
1891 | PIS(PACKET_SENT); | |
1892 | PIS(FIFO_TX_OVF); | |
1893 | PIS(FIFO_RX_OVF); | |
1894 | PIS(BTA); | |
1895 | PIS(ECC_NO_CORR); | |
1896 | PIS(FIFO_TX_UDF); | |
1897 | PIS(PP_BUSY_CHANGE); | |
1898 | #undef PIS | |
1899 | ||
1900 | #define PIS(x) \ | |
1901 | seq_printf(s, "%-20s %10d\n", #x, \ | |
1902 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); | |
1903 | ||
1904 | seq_printf(s, "-- CIO interrupts --\n"); | |
1905 | PIS(ERRSYNCESC1); | |
1906 | PIS(ERRSYNCESC2); | |
1907 | PIS(ERRSYNCESC3); | |
1908 | PIS(ERRESC1); | |
1909 | PIS(ERRESC2); | |
1910 | PIS(ERRESC3); | |
1911 | PIS(ERRCONTROL1); | |
1912 | PIS(ERRCONTROL2); | |
1913 | PIS(ERRCONTROL3); | |
1914 | PIS(STATEULPS1); | |
1915 | PIS(STATEULPS2); | |
1916 | PIS(STATEULPS3); | |
1917 | PIS(ERRCONTENTIONLP0_1); | |
1918 | PIS(ERRCONTENTIONLP1_1); | |
1919 | PIS(ERRCONTENTIONLP0_2); | |
1920 | PIS(ERRCONTENTIONLP1_2); | |
1921 | PIS(ERRCONTENTIONLP0_3); | |
1922 | PIS(ERRCONTENTIONLP1_3); | |
1923 | PIS(ULPSACTIVENOT_ALL0); | |
1924 | PIS(ULPSACTIVENOT_ALL1); | |
1925 | #undef PIS | |
1926 | } | |
dfc0fd8d | 1927 | |
5a8b572d | 1928 | static void dsi1_dump_irqs(struct seq_file *s) |
3de7a1dc | 1929 | { |
a72b64b9 AT |
1930 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
1931 | ||
5a8b572d AT |
1932 | dsi_dump_dsidev_irqs(dsidev, s); |
1933 | } | |
1934 | ||
1935 | static void dsi2_dump_irqs(struct seq_file *s) | |
1936 | { | |
1937 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1938 | ||
1939 | dsi_dump_dsidev_irqs(dsidev, s); | |
1940 | } | |
5a8b572d AT |
1941 | #endif |
1942 | ||
1943 | static void dsi_dump_dsidev_regs(struct platform_device *dsidev, | |
1944 | struct seq_file *s) | |
1945 | { | |
a72b64b9 | 1946 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
3de7a1dc | 1947 | |
4fbafaf3 TV |
1948 | if (dsi_runtime_get(dsidev)) |
1949 | return; | |
a72b64b9 | 1950 | dsi_enable_scp_clk(dsidev); |
3de7a1dc TV |
1951 | |
1952 | DUMPREG(DSI_REVISION); | |
1953 | DUMPREG(DSI_SYSCONFIG); | |
1954 | DUMPREG(DSI_SYSSTATUS); | |
1955 | DUMPREG(DSI_IRQSTATUS); | |
1956 | DUMPREG(DSI_IRQENABLE); | |
1957 | DUMPREG(DSI_CTRL); | |
1958 | DUMPREG(DSI_COMPLEXIO_CFG1); | |
1959 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); | |
1960 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); | |
1961 | DUMPREG(DSI_CLK_CTRL); | |
1962 | DUMPREG(DSI_TIMING1); | |
1963 | DUMPREG(DSI_TIMING2); | |
1964 | DUMPREG(DSI_VM_TIMING1); | |
1965 | DUMPREG(DSI_VM_TIMING2); | |
1966 | DUMPREG(DSI_VM_TIMING3); | |
1967 | DUMPREG(DSI_CLK_TIMING); | |
1968 | DUMPREG(DSI_TX_FIFO_VC_SIZE); | |
1969 | DUMPREG(DSI_RX_FIFO_VC_SIZE); | |
1970 | DUMPREG(DSI_COMPLEXIO_CFG2); | |
1971 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); | |
1972 | DUMPREG(DSI_VM_TIMING4); | |
1973 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); | |
1974 | DUMPREG(DSI_VM_TIMING5); | |
1975 | DUMPREG(DSI_VM_TIMING6); | |
1976 | DUMPREG(DSI_VM_TIMING7); | |
1977 | DUMPREG(DSI_STOPCLK_TIMING); | |
1978 | ||
1979 | DUMPREG(DSI_VC_CTRL(0)); | |
1980 | DUMPREG(DSI_VC_TE(0)); | |
1981 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); | |
1982 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); | |
1983 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); | |
1984 | DUMPREG(DSI_VC_IRQSTATUS(0)); | |
1985 | DUMPREG(DSI_VC_IRQENABLE(0)); | |
1986 | ||
1987 | DUMPREG(DSI_VC_CTRL(1)); | |
1988 | DUMPREG(DSI_VC_TE(1)); | |
1989 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); | |
1990 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); | |
1991 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); | |
1992 | DUMPREG(DSI_VC_IRQSTATUS(1)); | |
1993 | DUMPREG(DSI_VC_IRQENABLE(1)); | |
1994 | ||
1995 | DUMPREG(DSI_VC_CTRL(2)); | |
1996 | DUMPREG(DSI_VC_TE(2)); | |
1997 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); | |
1998 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); | |
1999 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); | |
2000 | DUMPREG(DSI_VC_IRQSTATUS(2)); | |
2001 | DUMPREG(DSI_VC_IRQENABLE(2)); | |
2002 | ||
2003 | DUMPREG(DSI_VC_CTRL(3)); | |
2004 | DUMPREG(DSI_VC_TE(3)); | |
2005 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); | |
2006 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); | |
2007 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); | |
2008 | DUMPREG(DSI_VC_IRQSTATUS(3)); | |
2009 | DUMPREG(DSI_VC_IRQENABLE(3)); | |
2010 | ||
2011 | DUMPREG(DSI_DSIPHY_CFG0); | |
2012 | DUMPREG(DSI_DSIPHY_CFG1); | |
2013 | DUMPREG(DSI_DSIPHY_CFG2); | |
2014 | DUMPREG(DSI_DSIPHY_CFG5); | |
2015 | ||
2016 | DUMPREG(DSI_PLL_CONTROL); | |
2017 | DUMPREG(DSI_PLL_STATUS); | |
2018 | DUMPREG(DSI_PLL_GO); | |
2019 | DUMPREG(DSI_PLL_CONFIGURATION1); | |
2020 | DUMPREG(DSI_PLL_CONFIGURATION2); | |
2021 | ||
a72b64b9 | 2022 | dsi_disable_scp_clk(dsidev); |
4fbafaf3 | 2023 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
2024 | #undef DUMPREG |
2025 | } | |
2026 | ||
5a8b572d AT |
2027 | static void dsi1_dump_regs(struct seq_file *s) |
2028 | { | |
2029 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); | |
2030 | ||
2031 | dsi_dump_dsidev_regs(dsidev, s); | |
2032 | } | |
2033 | ||
2034 | static void dsi2_dump_regs(struct seq_file *s) | |
2035 | { | |
2036 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
2037 | ||
2038 | dsi_dump_dsidev_regs(dsidev, s); | |
2039 | } | |
2040 | ||
cc5c1850 | 2041 | enum dsi_cio_power_state { |
3de7a1dc TV |
2042 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
2043 | DSI_COMPLEXIO_POWER_ON = 0x1, | |
2044 | DSI_COMPLEXIO_POWER_ULPS = 0x2, | |
2045 | }; | |
2046 | ||
a72b64b9 AT |
2047 | static int dsi_cio_power(struct platform_device *dsidev, |
2048 | enum dsi_cio_power_state state) | |
3de7a1dc TV |
2049 | { |
2050 | int t = 0; | |
2051 | ||
2052 | /* PWR_CMD */ | |
a72b64b9 | 2053 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); |
3de7a1dc TV |
2054 | |
2055 | /* PWR_STATUS */ | |
a72b64b9 AT |
2056 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), |
2057 | 26, 25) != state) { | |
24be78b3 | 2058 | if (++t > 1000) { |
3de7a1dc TV |
2059 | DSSERR("failed to set complexio power state to " |
2060 | "%d\n", state); | |
2061 | return -ENODEV; | |
2062 | } | |
24be78b3 | 2063 | udelay(1); |
3de7a1dc TV |
2064 | } |
2065 | ||
2066 | return 0; | |
2067 | } | |
2068 | ||
0c65622b AT |
2069 | static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) |
2070 | { | |
2071 | int val; | |
2072 | ||
2073 | /* line buffer on OMAP3 is 1024 x 24bits */ | |
2074 | /* XXX: for some reason using full buffer size causes | |
2075 | * considerable TX slowdown with update sizes that fill the | |
2076 | * whole buffer */ | |
2077 | if (!dss_has_feature(FEAT_DSI_GNQ)) | |
2078 | return 1023 * 3; | |
2079 | ||
2080 | val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ | |
2081 | ||
2082 | switch (val) { | |
2083 | case 1: | |
2084 | return 512 * 3; /* 512x24 bits */ | |
2085 | case 2: | |
2086 | return 682 * 3; /* 682x24 bits */ | |
2087 | case 3: | |
2088 | return 853 * 3; /* 853x24 bits */ | |
2089 | case 4: | |
2090 | return 1024 * 3; /* 1024x24 bits */ | |
2091 | case 5: | |
2092 | return 1194 * 3; /* 1194x24 bits */ | |
2093 | case 6: | |
2094 | return 1365 * 3; /* 1365x24 bits */ | |
2ac80fbe TV |
2095 | case 7: |
2096 | return 1920 * 3; /* 1920x24 bits */ | |
0c65622b AT |
2097 | default: |
2098 | BUG(); | |
c6eee968 | 2099 | return 0; |
0c65622b AT |
2100 | } |
2101 | } | |
2102 | ||
9e7e9372 | 2103 | static int dsi_set_lane_config(struct platform_device *dsidev) |
3de7a1dc | 2104 | { |
48368395 TV |
2105 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2106 | static const u8 offsets[] = { 0, 4, 8, 12, 16 }; | |
2107 | static const enum dsi_lane_function functions[] = { | |
2108 | DSI_LANE_CLK, | |
2109 | DSI_LANE_DATA1, | |
2110 | DSI_LANE_DATA2, | |
2111 | DSI_LANE_DATA3, | |
2112 | DSI_LANE_DATA4, | |
2113 | }; | |
3de7a1dc | 2114 | u32 r; |
48368395 | 2115 | int i; |
3de7a1dc | 2116 | |
a72b64b9 | 2117 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
48368395 TV |
2118 | |
2119 | for (i = 0; i < dsi->num_lanes_used; ++i) { | |
2120 | unsigned offset = offsets[i]; | |
2121 | unsigned polarity, lane_number; | |
2122 | unsigned t; | |
2123 | ||
2124 | for (t = 0; t < dsi->num_lanes_supported; ++t) | |
2125 | if (dsi->lanes[t].function == functions[i]) | |
2126 | break; | |
2127 | ||
2128 | if (t == dsi->num_lanes_supported) | |
2129 | return -EINVAL; | |
2130 | ||
2131 | lane_number = t; | |
2132 | polarity = dsi->lanes[t].polarity; | |
2133 | ||
2134 | r = FLD_MOD(r, lane_number + 1, offset + 2, offset); | |
2135 | r = FLD_MOD(r, polarity, offset + 3, offset + 3); | |
75d7247c | 2136 | } |
75d7247c | 2137 | |
48368395 TV |
2138 | /* clear the unused lanes */ |
2139 | for (; i < dsi->num_lanes_supported; ++i) { | |
2140 | unsigned offset = offsets[i]; | |
2141 | ||
2142 | r = FLD_MOD(r, 0, offset + 2, offset); | |
2143 | r = FLD_MOD(r, 0, offset + 3, offset + 3); | |
75d7247c | 2144 | } |
3de7a1dc | 2145 | |
48368395 | 2146 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); |
3de7a1dc | 2147 | |
48368395 | 2148 | return 0; |
3de7a1dc TV |
2149 | } |
2150 | ||
a72b64b9 | 2151 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) |
3de7a1dc | 2152 | { |
f1da39d9 AT |
2153 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2154 | ||
3de7a1dc | 2155 | /* convert time in ns to ddr ticks, rounding up */ |
f1da39d9 | 2156 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
3de7a1dc TV |
2157 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
2158 | } | |
2159 | ||
a72b64b9 | 2160 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) |
3de7a1dc | 2161 | { |
f1da39d9 AT |
2162 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2163 | ||
2164 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; | |
3de7a1dc TV |
2165 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
2166 | } | |
2167 | ||
a72b64b9 | 2168 | static void dsi_cio_timings(struct platform_device *dsidev) |
3de7a1dc TV |
2169 | { |
2170 | u32 r; | |
2171 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; | |
2172 | u32 tlpx_half, tclk_trail, tclk_zero; | |
2173 | u32 tclk_prepare; | |
2174 | ||
2175 | /* calculate timings */ | |
2176 | ||
2177 | /* 1 * DDR_CLK = 2 * UI */ | |
2178 | ||
2179 | /* min 40ns + 4*UI max 85ns + 6*UI */ | |
a72b64b9 | 2180 | ths_prepare = ns2ddr(dsidev, 70) + 2; |
3de7a1dc TV |
2181 | |
2182 | /* min 145ns + 10*UI */ | |
a72b64b9 | 2183 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; |
3de7a1dc TV |
2184 | |
2185 | /* min max(8*UI, 60ns+4*UI) */ | |
a72b64b9 | 2186 | ths_trail = ns2ddr(dsidev, 60) + 5; |
3de7a1dc TV |
2187 | |
2188 | /* min 100ns */ | |
a72b64b9 | 2189 | ths_exit = ns2ddr(dsidev, 145); |
3de7a1dc TV |
2190 | |
2191 | /* tlpx min 50n */ | |
a72b64b9 | 2192 | tlpx_half = ns2ddr(dsidev, 25); |
3de7a1dc TV |
2193 | |
2194 | /* min 60ns */ | |
a72b64b9 | 2195 | tclk_trail = ns2ddr(dsidev, 60) + 2; |
3de7a1dc TV |
2196 | |
2197 | /* min 38ns, max 95ns */ | |
a72b64b9 | 2198 | tclk_prepare = ns2ddr(dsidev, 65); |
3de7a1dc TV |
2199 | |
2200 | /* min tclk-prepare + tclk-zero = 300ns */ | |
a72b64b9 | 2201 | tclk_zero = ns2ddr(dsidev, 260); |
3de7a1dc TV |
2202 | |
2203 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", | |
a72b64b9 AT |
2204 | ths_prepare, ddr2ns(dsidev, ths_prepare), |
2205 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); | |
3de7a1dc | 2206 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
a72b64b9 AT |
2207 | ths_trail, ddr2ns(dsidev, ths_trail), |
2208 | ths_exit, ddr2ns(dsidev, ths_exit)); | |
3de7a1dc TV |
2209 | |
2210 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " | |
2211 | "tclk_zero %u (%uns)\n", | |
a72b64b9 AT |
2212 | tlpx_half, ddr2ns(dsidev, tlpx_half), |
2213 | tclk_trail, ddr2ns(dsidev, tclk_trail), | |
2214 | tclk_zero, ddr2ns(dsidev, tclk_zero)); | |
3de7a1dc | 2215 | DSSDBG("tclk_prepare %u (%uns)\n", |
a72b64b9 | 2216 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); |
3de7a1dc TV |
2217 | |
2218 | /* program timings */ | |
2219 | ||
a72b64b9 | 2220 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
2221 | r = FLD_MOD(r, ths_prepare, 31, 24); |
2222 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); | |
2223 | r = FLD_MOD(r, ths_trail, 15, 8); | |
2224 | r = FLD_MOD(r, ths_exit, 7, 0); | |
a72b64b9 | 2225 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); |
3de7a1dc | 2226 | |
a72b64b9 | 2227 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
e84dc1cc | 2228 | r = FLD_MOD(r, tlpx_half, 20, 16); |
3de7a1dc TV |
2229 | r = FLD_MOD(r, tclk_trail, 15, 8); |
2230 | r = FLD_MOD(r, tclk_zero, 7, 0); | |
77ccbfbb TV |
2231 | |
2232 | if (dss_has_feature(FEAT_DSI_PHY_DCC)) { | |
2233 | r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ | |
2234 | r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ | |
2235 | r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ | |
2236 | } | |
2237 | ||
a72b64b9 | 2238 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); |
3de7a1dc | 2239 | |
a72b64b9 | 2240 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc | 2241 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
a72b64b9 | 2242 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); |
3de7a1dc TV |
2243 | } |
2244 | ||
9b4362f2 | 2245 | /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ |
9e7e9372 | 2246 | static void dsi_cio_enable_lane_override(struct platform_device *dsidev, |
9b4362f2 | 2247 | unsigned mask_p, unsigned mask_n) |
0a0ee46b | 2248 | { |
75d7247c | 2249 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
9b4362f2 TV |
2250 | int i; |
2251 | u32 l; | |
d9820850 | 2252 | u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; |
0a0ee46b | 2253 | |
9b4362f2 TV |
2254 | l = 0; |
2255 | ||
2256 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
2257 | unsigned p = dsi->lanes[i].polarity; | |
2258 | ||
2259 | if (mask_p & (1 << i)) | |
2260 | l |= 1 << (i * 2 + (p ? 0 : 1)); | |
2261 | ||
2262 | if (mask_n & (1 << i)) | |
2263 | l |= 1 << (i * 2 + (p ? 1 : 0)); | |
2264 | } | |
2265 | ||
0a0ee46b TV |
2266 | /* |
2267 | * Bits in REGLPTXSCPDAT4TO0DXDY: | |
2268 | * 17: DY0 18: DX0 | |
2269 | * 19: DY1 20: DX1 | |
2270 | * 21: DY2 22: DX2 | |
75d7247c AT |
2271 | * 23: DY3 24: DX3 |
2272 | * 25: DY4 26: DX4 | |
0a0ee46b TV |
2273 | */ |
2274 | ||
2275 | /* Set the lane override configuration */ | |
a72b64b9 AT |
2276 | |
2277 | /* REGLPTXSCPDAT4TO0DXDY */ | |
75d7247c | 2278 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); |
0a0ee46b TV |
2279 | |
2280 | /* Enable lane override */ | |
a72b64b9 AT |
2281 | |
2282 | /* ENLPTXSCPDAT */ | |
2283 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); | |
0a0ee46b TV |
2284 | } |
2285 | ||
a72b64b9 | 2286 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) |
0a0ee46b TV |
2287 | { |
2288 | /* Disable lane override */ | |
a72b64b9 | 2289 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
0a0ee46b | 2290 | /* Reset the lane override configuration */ |
a72b64b9 AT |
2291 | /* REGLPTXSCPDAT4TO0DXDY */ |
2292 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); | |
0a0ee46b | 2293 | } |
3de7a1dc | 2294 | |
9e7e9372 | 2295 | static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) |
03329ace | 2296 | { |
8dc0766f TV |
2297 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2298 | int t, i; | |
2299 | bool in_use[DSI_MAX_NR_LANES]; | |
2300 | static const u8 offsets_old[] = { 28, 27, 26 }; | |
2301 | static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; | |
2302 | const u8 *offsets; | |
2303 | ||
2304 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) | |
2305 | offsets = offsets_old; | |
2306 | else | |
2307 | offsets = offsets_new; | |
03329ace | 2308 | |
8dc0766f TV |
2309 | for (i = 0; i < dsi->num_lanes_supported; ++i) |
2310 | in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; | |
03329ace TV |
2311 | |
2312 | t = 100000; | |
2313 | while (true) { | |
2314 | u32 l; | |
03329ace TV |
2315 | int ok; |
2316 | ||
a72b64b9 | 2317 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
03329ace TV |
2318 | |
2319 | ok = 0; | |
8dc0766f TV |
2320 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2321 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
03329ace TV |
2322 | ok++; |
2323 | } | |
2324 | ||
8dc0766f | 2325 | if (ok == dsi->num_lanes_supported) |
03329ace TV |
2326 | break; |
2327 | ||
2328 | if (--t == 0) { | |
8dc0766f TV |
2329 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2330 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
03329ace TV |
2331 | continue; |
2332 | ||
2333 | DSSERR("CIO TXCLKESC%d domain not coming " \ | |
2334 | "out of reset\n", i); | |
2335 | } | |
2336 | return -EIO; | |
2337 | } | |
2338 | } | |
2339 | ||
2340 | return 0; | |
2341 | } | |
2342 | ||
85f17e8e | 2343 | /* return bitmask of enabled lanes, lane0 being the lsb */ |
9e7e9372 | 2344 | static unsigned dsi_get_lane_mask(struct platform_device *dsidev) |
5bc416cb | 2345 | { |
85f17e8e TV |
2346 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2347 | unsigned mask = 0; | |
2348 | int i; | |
5bc416cb | 2349 | |
85f17e8e TV |
2350 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2351 | if (dsi->lanes[i].function != DSI_LANE_UNUSED) | |
2352 | mask |= 1 << i; | |
2353 | } | |
5bc416cb | 2354 | |
85f17e8e | 2355 | return mask; |
5bc416cb TV |
2356 | } |
2357 | ||
9e7e9372 | 2358 | static int dsi_cio_init(struct platform_device *dsidev) |
3de7a1dc | 2359 | { |
f1da39d9 | 2360 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
65c62bb9 | 2361 | int r; |
40885ab3 | 2362 | u32 l; |
3de7a1dc | 2363 | |
702d267e | 2364 | DSSDBG("DSI CIO init starts"); |
3de7a1dc | 2365 | |
9e7e9372 | 2366 | r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); |
5bc416cb TV |
2367 | if (r) |
2368 | return r; | |
d1f5857e | 2369 | |
a72b64b9 | 2370 | dsi_enable_scp_clk(dsidev); |
40885ab3 | 2371 | |
3de7a1dc TV |
2372 | /* A dummy read using the SCP interface to any DSIPHY register is |
2373 | * required after DSIPHY reset to complete the reset of the DSI complex | |
2374 | * I/O. */ | |
a72b64b9 | 2375 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc | 2376 | |
a72b64b9 | 2377 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { |
65c62bb9 TV |
2378 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
2379 | r = -EIO; | |
2380 | goto err_scp_clk_dom; | |
3de7a1dc TV |
2381 | } |
2382 | ||
9e7e9372 | 2383 | r = dsi_set_lane_config(dsidev); |
48368395 TV |
2384 | if (r) |
2385 | goto err_scp_clk_dom; | |
3de7a1dc | 2386 | |
40885ab3 | 2387 | /* set TX STOP MODE timer to maximum for this operation */ |
a72b64b9 | 2388 | l = dsi_read_reg(dsidev, DSI_TIMING1); |
40885ab3 TV |
2389 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
2390 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ | |
2391 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ | |
2392 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ | |
a72b64b9 | 2393 | dsi_write_reg(dsidev, DSI_TIMING1, l); |
40885ab3 | 2394 | |
f1da39d9 | 2395 | if (dsi->ulps_enabled) { |
9b4362f2 TV |
2396 | unsigned mask_p; |
2397 | int i; | |
75d7247c | 2398 | |
65c62bb9 TV |
2399 | DSSDBG("manual ulps exit\n"); |
2400 | ||
40885ab3 TV |
2401 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
2402 | * stop state. DSS HW cannot do this via the normal | |
2403 | * ULPS exit sequence, as after reset the DSS HW thinks | |
2404 | * that we are not in ULPS mode, and refuses to send the | |
2405 | * sequence. So we need to send the ULPS exit sequence | |
9b4362f2 TV |
2406 | * manually by setting positive lines high and negative lines |
2407 | * low for 1ms. | |
40885ab3 TV |
2408 | */ |
2409 | ||
9b4362f2 | 2410 | mask_p = 0; |
75d7247c | 2411 | |
9b4362f2 TV |
2412 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2413 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
2414 | continue; | |
2415 | mask_p |= 1 << i; | |
2416 | } | |
75d7247c | 2417 | |
9e7e9372 | 2418 | dsi_cio_enable_lane_override(dsidev, mask_p, 0); |
40885ab3 | 2419 | } |
3de7a1dc | 2420 | |
a72b64b9 | 2421 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); |
3de7a1dc | 2422 | if (r) |
65c62bb9 TV |
2423 | goto err_cio_pwr; |
2424 | ||
a72b64b9 | 2425 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
65c62bb9 TV |
2426 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
2427 | r = -ENODEV; | |
2428 | goto err_cio_pwr_dom; | |
2429 | } | |
2430 | ||
a72b64b9 AT |
2431 | dsi_if_enable(dsidev, true); |
2432 | dsi_if_enable(dsidev, false); | |
2433 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ | |
3de7a1dc | 2434 | |
9e7e9372 | 2435 | r = dsi_cio_wait_tx_clk_esc_reset(dsidev); |
03329ace TV |
2436 | if (r) |
2437 | goto err_tx_clk_esc_rst; | |
2438 | ||
f1da39d9 | 2439 | if (dsi->ulps_enabled) { |
40885ab3 TV |
2440 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
2441 | ktime_t wait = ns_to_ktime(1000 * 1000); | |
2442 | set_current_state(TASK_UNINTERRUPTIBLE); | |
2443 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
2444 | ||
2445 | /* Disable the override. The lanes should be set to Mark-11 | |
2446 | * state by the HW */ | |
a72b64b9 | 2447 | dsi_cio_disable_lane_override(dsidev); |
40885ab3 TV |
2448 | } |
2449 | ||
2450 | /* FORCE_TX_STOP_MODE_IO */ | |
a72b64b9 | 2451 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); |
40885ab3 | 2452 | |
a72b64b9 | 2453 | dsi_cio_timings(dsidev); |
3de7a1dc | 2454 | |
dca2b152 | 2455 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
8af6ff01 AT |
2456 | /* DDR_CLK_ALWAYS_ON */ |
2457 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, | |
0b3ffe39 | 2458 | dsi->vm_timings.ddr_clk_always_on, 13, 13); |
8af6ff01 AT |
2459 | } |
2460 | ||
f1da39d9 | 2461 | dsi->ulps_enabled = false; |
3de7a1dc TV |
2462 | |
2463 | DSSDBG("CIO init done\n"); | |
65c62bb9 TV |
2464 | |
2465 | return 0; | |
2466 | ||
03329ace | 2467 | err_tx_clk_esc_rst: |
a72b64b9 | 2468 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
65c62bb9 | 2469 | err_cio_pwr_dom: |
a72b64b9 | 2470 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
65c62bb9 | 2471 | err_cio_pwr: |
f1da39d9 | 2472 | if (dsi->ulps_enabled) |
a72b64b9 | 2473 | dsi_cio_disable_lane_override(dsidev); |
65c62bb9 | 2474 | err_scp_clk_dom: |
a72b64b9 | 2475 | dsi_disable_scp_clk(dsidev); |
9e7e9372 | 2476 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); |
3de7a1dc TV |
2477 | return r; |
2478 | } | |
2479 | ||
9e7e9372 | 2480 | static void dsi_cio_uninit(struct platform_device *dsidev) |
3de7a1dc | 2481 | { |
11ee9606 | 2482 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
f1da39d9 | 2483 | |
8af6ff01 AT |
2484 | /* DDR_CLK_ALWAYS_ON */ |
2485 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); | |
2486 | ||
a72b64b9 AT |
2487 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
2488 | dsi_disable_scp_clk(dsidev); | |
9e7e9372 | 2489 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); |
3de7a1dc TV |
2490 | } |
2491 | ||
a72b64b9 AT |
2492 | static void dsi_config_tx_fifo(struct platform_device *dsidev, |
2493 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2494 | enum fifo_size size3, enum fifo_size size4) |
2495 | { | |
f1da39d9 | 2496 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2497 | u32 r = 0; |
2498 | int add = 0; | |
2499 | int i; | |
2500 | ||
558c73e2 TV |
2501 | dsi->vc[0].tx_fifo_size = size1; |
2502 | dsi->vc[1].tx_fifo_size = size2; | |
2503 | dsi->vc[2].tx_fifo_size = size3; | |
2504 | dsi->vc[3].tx_fifo_size = size4; | |
3de7a1dc TV |
2505 | |
2506 | for (i = 0; i < 4; i++) { | |
2507 | u8 v; | |
558c73e2 | 2508 | int size = dsi->vc[i].tx_fifo_size; |
3de7a1dc TV |
2509 | |
2510 | if (add + size > 4) { | |
2511 | DSSERR("Illegal FIFO configuration\n"); | |
2512 | BUG(); | |
c6eee968 | 2513 | return; |
3de7a1dc TV |
2514 | } |
2515 | ||
2516 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2517 | r |= v << (8 * i); | |
2518 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2519 | add += size; | |
2520 | } | |
2521 | ||
a72b64b9 | 2522 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2523 | } |
2524 | ||
a72b64b9 AT |
2525 | static void dsi_config_rx_fifo(struct platform_device *dsidev, |
2526 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2527 | enum fifo_size size3, enum fifo_size size4) |
2528 | { | |
f1da39d9 | 2529 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2530 | u32 r = 0; |
2531 | int add = 0; | |
2532 | int i; | |
2533 | ||
558c73e2 TV |
2534 | dsi->vc[0].rx_fifo_size = size1; |
2535 | dsi->vc[1].rx_fifo_size = size2; | |
2536 | dsi->vc[2].rx_fifo_size = size3; | |
2537 | dsi->vc[3].rx_fifo_size = size4; | |
3de7a1dc TV |
2538 | |
2539 | for (i = 0; i < 4; i++) { | |
2540 | u8 v; | |
558c73e2 | 2541 | int size = dsi->vc[i].rx_fifo_size; |
3de7a1dc TV |
2542 | |
2543 | if (add + size > 4) { | |
2544 | DSSERR("Illegal FIFO configuration\n"); | |
2545 | BUG(); | |
c6eee968 | 2546 | return; |
3de7a1dc TV |
2547 | } |
2548 | ||
2549 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2550 | r |= v << (8 * i); | |
2551 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2552 | add += size; | |
2553 | } | |
2554 | ||
a72b64b9 | 2555 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2556 | } |
2557 | ||
a72b64b9 | 2558 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) |
3de7a1dc TV |
2559 | { |
2560 | u32 r; | |
2561 | ||
a72b64b9 | 2562 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 2563 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
a72b64b9 | 2564 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 2565 | |
a72b64b9 | 2566 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { |
3de7a1dc TV |
2567 | DSSERR("TX_STOP bit not going down\n"); |
2568 | return -EIO; | |
2569 | } | |
2570 | ||
2571 | return 0; | |
2572 | } | |
2573 | ||
a72b64b9 | 2574 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) |
cf398fb3 | 2575 | { |
a72b64b9 | 2576 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); |
cf398fb3 AT |
2577 | } |
2578 | ||
2579 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) | |
2580 | { | |
2e868dbe AT |
2581 | struct dsi_packet_sent_handler_data *vp_data = |
2582 | (struct dsi_packet_sent_handler_data *) data; | |
2583 | struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); | |
f1da39d9 AT |
2584 | const int channel = dsi->update_channel; |
2585 | u8 bit = dsi->te_enabled ? 30 : 31; | |
cf398fb3 | 2586 | |
2e868dbe AT |
2587 | if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) |
2588 | complete(vp_data->completion); | |
cf398fb3 AT |
2589 | } |
2590 | ||
a72b64b9 | 2591 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) |
cf398fb3 | 2592 | { |
f1da39d9 | 2593 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2e868dbe | 2594 | DECLARE_COMPLETION_ONSTACK(completion); |
39917f08 JL |
2595 | struct dsi_packet_sent_handler_data vp_data = { |
2596 | .dsidev = dsidev, | |
2597 | .completion = &completion | |
2598 | }; | |
cf398fb3 AT |
2599 | int r = 0; |
2600 | u8 bit; | |
2601 | ||
f1da39d9 | 2602 | bit = dsi->te_enabled ? 30 : 31; |
cf398fb3 | 2603 | |
a72b64b9 | 2604 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2605 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2606 | if (r) |
2607 | goto err0; | |
2608 | ||
2609 | /* Wait for completion only if TE_EN/TE_START is still set */ | |
a72b64b9 | 2610 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { |
cf398fb3 AT |
2611 | if (wait_for_completion_timeout(&completion, |
2612 | msecs_to_jiffies(10)) == 0) { | |
2613 | DSSERR("Failed to complete previous frame transfer\n"); | |
2614 | r = -EIO; | |
2615 | goto err1; | |
2616 | } | |
2617 | } | |
2618 | ||
a72b64b9 | 2619 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2620 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2621 | |
2622 | return 0; | |
2623 | err1: | |
a72b64b9 | 2624 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2625 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2626 | err0: |
2627 | return r; | |
2628 | } | |
2629 | ||
2630 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) | |
2631 | { | |
2e868dbe AT |
2632 | struct dsi_packet_sent_handler_data *l4_data = |
2633 | (struct dsi_packet_sent_handler_data *) data; | |
2634 | struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); | |
f1da39d9 | 2635 | const int channel = dsi->update_channel; |
cf398fb3 | 2636 | |
2e868dbe AT |
2637 | if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) |
2638 | complete(l4_data->completion); | |
cf398fb3 AT |
2639 | } |
2640 | ||
a72b64b9 | 2641 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) |
cf398fb3 | 2642 | { |
cf398fb3 | 2643 | DECLARE_COMPLETION_ONSTACK(completion); |
39917f08 JL |
2644 | struct dsi_packet_sent_handler_data l4_data = { |
2645 | .dsidev = dsidev, | |
2646 | .completion = &completion | |
2647 | }; | |
2e868dbe | 2648 | int r = 0; |
cf398fb3 | 2649 | |
a72b64b9 | 2650 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2651 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2652 | if (r) |
2653 | goto err0; | |
2654 | ||
2655 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ | |
a72b64b9 | 2656 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { |
cf398fb3 AT |
2657 | if (wait_for_completion_timeout(&completion, |
2658 | msecs_to_jiffies(10)) == 0) { | |
2659 | DSSERR("Failed to complete previous l4 transfer\n"); | |
2660 | r = -EIO; | |
2661 | goto err1; | |
2662 | } | |
2663 | } | |
2664 | ||
a72b64b9 | 2665 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2666 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2667 | |
2668 | return 0; | |
2669 | err1: | |
a72b64b9 | 2670 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2671 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2672 | err0: |
2673 | return r; | |
2674 | } | |
2675 | ||
a72b64b9 | 2676 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) |
cf398fb3 | 2677 | { |
f1da39d9 AT |
2678 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2679 | ||
a72b64b9 | 2680 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
cf398fb3 AT |
2681 | |
2682 | WARN_ON(in_interrupt()); | |
2683 | ||
a72b64b9 | 2684 | if (!dsi_vc_is_enabled(dsidev, channel)) |
cf398fb3 AT |
2685 | return 0; |
2686 | ||
d6049144 AT |
2687 | switch (dsi->vc[channel].source) { |
2688 | case DSI_VC_SOURCE_VP: | |
a72b64b9 | 2689 | return dsi_sync_vc_vp(dsidev, channel); |
d6049144 | 2690 | case DSI_VC_SOURCE_L4: |
a72b64b9 | 2691 | return dsi_sync_vc_l4(dsidev, channel); |
cf398fb3 AT |
2692 | default: |
2693 | BUG(); | |
c6eee968 | 2694 | return -EINVAL; |
cf398fb3 AT |
2695 | } |
2696 | } | |
2697 | ||
a72b64b9 AT |
2698 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, |
2699 | bool enable) | |
3de7a1dc | 2700 | { |
446f7bff TV |
2701 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
2702 | channel, enable); | |
3de7a1dc TV |
2703 | |
2704 | enable = enable ? 1 : 0; | |
2705 | ||
a72b64b9 | 2706 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); |
3de7a1dc | 2707 | |
a72b64b9 AT |
2708 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), |
2709 | 0, enable) != enable) { | |
3de7a1dc TV |
2710 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
2711 | return -EIO; | |
2712 | } | |
2713 | ||
2714 | return 0; | |
2715 | } | |
2716 | ||
a72b64b9 | 2717 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) |
3de7a1dc | 2718 | { |
2c1a3ea0 | 2719 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2720 | u32 r; |
2721 | ||
702d267e | 2722 | DSSDBG("Initial config of virtual channel %d", channel); |
3de7a1dc | 2723 | |
a72b64b9 | 2724 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
3de7a1dc TV |
2725 | |
2726 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ | |
2727 | DSSERR("VC(%d) busy when trying to configure it!\n", | |
2728 | channel); | |
2729 | ||
2730 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2731 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ | |
2732 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ | |
2733 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ | |
2734 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ | |
2735 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ | |
2736 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ | |
9613c02b AT |
2737 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
2738 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ | |
3de7a1dc TV |
2739 | |
2740 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ | |
2741 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ | |
2742 | ||
a72b64b9 | 2743 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); |
2c1a3ea0 TV |
2744 | |
2745 | dsi->vc[channel].source = DSI_VC_SOURCE_L4; | |
3de7a1dc TV |
2746 | } |
2747 | ||
d6049144 AT |
2748 | static int dsi_vc_config_source(struct platform_device *dsidev, int channel, |
2749 | enum dsi_vc_source source) | |
3de7a1dc | 2750 | { |
f1da39d9 AT |
2751 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2752 | ||
d6049144 | 2753 | if (dsi->vc[channel].source == source) |
9ecd9684 | 2754 | return 0; |
3de7a1dc | 2755 | |
702d267e | 2756 | DSSDBG("Source config of virtual channel %d", channel); |
3de7a1dc | 2757 | |
a72b64b9 | 2758 | dsi_sync_vc(dsidev, channel); |
cf398fb3 | 2759 | |
a72b64b9 | 2760 | dsi_vc_enable(dsidev, channel, 0); |
3de7a1dc | 2761 | |
9ecd9684 | 2762 | /* VC_BUSY */ |
a72b64b9 | 2763 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
3de7a1dc | 2764 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
9ecd9684 TV |
2765 | return -EIO; |
2766 | } | |
3de7a1dc | 2767 | |
d6049144 AT |
2768 | /* SOURCE, 0 = L4, 1 = video port */ |
2769 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); | |
3de7a1dc | 2770 | |
9613c02b | 2771 | /* DCS_CMD_ENABLE */ |
d6049144 AT |
2772 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
2773 | bool enable = source == DSI_VC_SOURCE_VP; | |
2774 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); | |
2775 | } | |
9613c02b | 2776 | |
a72b64b9 | 2777 | dsi_vc_enable(dsidev, channel, 1); |
3de7a1dc | 2778 | |
d6049144 | 2779 | dsi->vc[channel].source = source; |
9ecd9684 TV |
2780 | |
2781 | return 0; | |
3de7a1dc TV |
2782 | } |
2783 | ||
5cfc1c3c | 2784 | static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
1ffefe75 | 2785 | bool enable) |
3de7a1dc | 2786 | { |
a72b64b9 | 2787 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
0b3ffe39 | 2788 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 2789 | |
3de7a1dc TV |
2790 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
2791 | ||
a72b64b9 | 2792 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
61140c9a | 2793 | |
a72b64b9 AT |
2794 | dsi_vc_enable(dsidev, channel, 0); |
2795 | dsi_if_enable(dsidev, 0); | |
3de7a1dc | 2796 | |
a72b64b9 | 2797 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); |
3de7a1dc | 2798 | |
a72b64b9 AT |
2799 | dsi_vc_enable(dsidev, channel, 1); |
2800 | dsi_if_enable(dsidev, 1); | |
3de7a1dc | 2801 | |
a72b64b9 | 2802 | dsi_force_tx_stop_mode_io(dsidev); |
8af6ff01 AT |
2803 | |
2804 | /* start the DDR clock by sending a NULL packet */ | |
0b3ffe39 | 2805 | if (dsi->vm_timings.ddr_clk_always_on && enable) |
8af6ff01 | 2806 | dsi_vc_send_null(dssdev, channel); |
3de7a1dc TV |
2807 | } |
2808 | ||
a72b64b9 | 2809 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) |
3de7a1dc | 2810 | { |
a72b64b9 | 2811 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc | 2812 | u32 val; |
a72b64b9 | 2813 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
3de7a1dc TV |
2814 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
2815 | (val >> 0) & 0xff, | |
2816 | (val >> 8) & 0xff, | |
2817 | (val >> 16) & 0xff, | |
2818 | (val >> 24) & 0xff); | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | static void dsi_show_rx_ack_with_err(u16 err) | |
2823 | { | |
2824 | DSSERR("\tACK with ERROR (%#x):\n", err); | |
2825 | if (err & (1 << 0)) | |
2826 | DSSERR("\t\tSoT Error\n"); | |
2827 | if (err & (1 << 1)) | |
2828 | DSSERR("\t\tSoT Sync Error\n"); | |
2829 | if (err & (1 << 2)) | |
2830 | DSSERR("\t\tEoT Sync Error\n"); | |
2831 | if (err & (1 << 3)) | |
2832 | DSSERR("\t\tEscape Mode Entry Command Error\n"); | |
2833 | if (err & (1 << 4)) | |
2834 | DSSERR("\t\tLP Transmit Sync Error\n"); | |
2835 | if (err & (1 << 5)) | |
2836 | DSSERR("\t\tHS Receive Timeout Error\n"); | |
2837 | if (err & (1 << 6)) | |
2838 | DSSERR("\t\tFalse Control Error\n"); | |
2839 | if (err & (1 << 7)) | |
2840 | DSSERR("\t\t(reserved7)\n"); | |
2841 | if (err & (1 << 8)) | |
2842 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); | |
2843 | if (err & (1 << 9)) | |
2844 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); | |
2845 | if (err & (1 << 10)) | |
2846 | DSSERR("\t\tChecksum Error\n"); | |
2847 | if (err & (1 << 11)) | |
2848 | DSSERR("\t\tData type not recognized\n"); | |
2849 | if (err & (1 << 12)) | |
2850 | DSSERR("\t\tInvalid VC ID\n"); | |
2851 | if (err & (1 << 13)) | |
2852 | DSSERR("\t\tInvalid Transmission Length\n"); | |
2853 | if (err & (1 << 14)) | |
2854 | DSSERR("\t\t(reserved14)\n"); | |
2855 | if (err & (1 << 15)) | |
2856 | DSSERR("\t\tDSI Protocol Violation\n"); | |
2857 | } | |
2858 | ||
a72b64b9 AT |
2859 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, |
2860 | int channel) | |
3de7a1dc TV |
2861 | { |
2862 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 2863 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc TV |
2864 | u32 val; |
2865 | u8 dt; | |
a72b64b9 | 2866 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
86a7867e | 2867 | DSSERR("\trawval %#08x\n", val); |
3de7a1dc | 2868 | dt = FLD_GET(val, 5, 0); |
7a7c48f9 | 2869 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
2870 | u16 err = FLD_GET(val, 23, 8); |
2871 | dsi_show_rx_ack_with_err(err); | |
7a7c48f9 | 2872 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { |
86a7867e | 2873 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
3de7a1dc | 2874 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2875 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { |
86a7867e | 2876 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
3de7a1dc | 2877 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2878 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { |
86a7867e | 2879 | DSSERR("\tDCS long response, len %d\n", |
3de7a1dc | 2880 | FLD_GET(val, 23, 8)); |
a72b64b9 | 2881 | dsi_vc_flush_long_data(dsidev, channel); |
3de7a1dc TV |
2882 | } else { |
2883 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
2884 | } | |
2885 | } | |
2886 | return 0; | |
2887 | } | |
2888 | ||
a72b64b9 | 2889 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) |
3de7a1dc | 2890 | { |
f1da39d9 AT |
2891 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2892 | ||
2893 | if (dsi->debug_write || dsi->debug_read) | |
3de7a1dc TV |
2894 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
2895 | ||
a72b64b9 | 2896 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2897 | |
a72b64b9 AT |
2898 | /* RX_FIFO_NOT_EMPTY */ |
2899 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
3de7a1dc | 2900 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
a72b64b9 | 2901 | dsi_vc_flush_receive_data(dsidev, channel); |
3de7a1dc TV |
2902 | } |
2903 | ||
a72b64b9 | 2904 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
3de7a1dc | 2905 | |
968f8e97 TV |
2906 | /* flush posted write */ |
2907 | dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); | |
2908 | ||
3de7a1dc TV |
2909 | return 0; |
2910 | } | |
2911 | ||
5cfc1c3c | 2912 | static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 2913 | { |
a72b64b9 | 2914 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f36a06e7 | 2915 | DECLARE_COMPLETION_ONSTACK(completion); |
3de7a1dc TV |
2916 | int r = 0; |
2917 | u32 err; | |
2918 | ||
a72b64b9 | 2919 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2920 | &completion, DSI_VC_IRQ_BTA); |
2921 | if (r) | |
2922 | goto err0; | |
3de7a1dc | 2923 | |
a72b64b9 | 2924 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2925 | DSI_IRQ_ERROR_MASK); |
3de7a1dc | 2926 | if (r) |
f36a06e7 | 2927 | goto err1; |
3de7a1dc | 2928 | |
a72b64b9 | 2929 | r = dsi_vc_send_bta(dsidev, channel); |
773b30b2 TV |
2930 | if (r) |
2931 | goto err2; | |
2932 | ||
f36a06e7 | 2933 | if (wait_for_completion_timeout(&completion, |
3de7a1dc TV |
2934 | msecs_to_jiffies(500)) == 0) { |
2935 | DSSERR("Failed to receive BTA\n"); | |
2936 | r = -EIO; | |
773b30b2 | 2937 | goto err2; |
3de7a1dc TV |
2938 | } |
2939 | ||
a72b64b9 | 2940 | err = dsi_get_errors(dsidev); |
3de7a1dc TV |
2941 | if (err) { |
2942 | DSSERR("Error while sending BTA: %x\n", err); | |
2943 | r = -EIO; | |
773b30b2 | 2944 | goto err2; |
3de7a1dc | 2945 | } |
773b30b2 | 2946 | err2: |
a72b64b9 | 2947 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2948 | DSI_IRQ_ERROR_MASK); |
f36a06e7 | 2949 | err1: |
a72b64b9 | 2950 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2951 | &completion, DSI_VC_IRQ_BTA); |
2952 | err0: | |
3de7a1dc TV |
2953 | return r; |
2954 | } | |
3de7a1dc | 2955 | |
a72b64b9 AT |
2956 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, |
2957 | int channel, u8 data_type, u16 len, u8 ecc) | |
3de7a1dc | 2958 | { |
f1da39d9 | 2959 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2960 | u32 val; |
2961 | u8 data_id; | |
2962 | ||
a72b64b9 | 2963 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2964 | |
f1da39d9 | 2965 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
2966 | |
2967 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | | |
2968 | FLD_VAL(ecc, 31, 24); | |
2969 | ||
a72b64b9 | 2970 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); |
3de7a1dc TV |
2971 | } |
2972 | ||
a72b64b9 AT |
2973 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, |
2974 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) | |
3de7a1dc TV |
2975 | { |
2976 | u32 val; | |
2977 | ||
2978 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; | |
2979 | ||
2980 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", | |
2981 | b1, b2, b3, b4, val); */ | |
2982 | ||
a72b64b9 | 2983 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
3de7a1dc TV |
2984 | } |
2985 | ||
a72b64b9 AT |
2986 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, |
2987 | u8 data_type, u8 *data, u16 len, u8 ecc) | |
3de7a1dc TV |
2988 | { |
2989 | /*u32 val; */ | |
f1da39d9 | 2990 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2991 | int i; |
2992 | u8 *p; | |
2993 | int r = 0; | |
2994 | u8 b1, b2, b3, b4; | |
2995 | ||
f1da39d9 | 2996 | if (dsi->debug_write) |
3de7a1dc TV |
2997 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
2998 | ||
2999 | /* len + header */ | |
558c73e2 | 3000 | if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { |
3de7a1dc TV |
3001 | DSSERR("unable to send long packet: packet too long.\n"); |
3002 | return -EINVAL; | |
3003 | } | |
3004 | ||
d6049144 | 3005 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 3006 | |
a72b64b9 | 3007 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); |
3de7a1dc | 3008 | |
3de7a1dc TV |
3009 | p = data; |
3010 | for (i = 0; i < len >> 2; i++) { | |
f1da39d9 | 3011 | if (dsi->debug_write) |
3de7a1dc | 3012 | DSSDBG("\tsending full packet %d\n", i); |
3de7a1dc TV |
3013 | |
3014 | b1 = *p++; | |
3015 | b2 = *p++; | |
3016 | b3 = *p++; | |
3017 | b4 = *p++; | |
3018 | ||
a72b64b9 | 3019 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); |
3de7a1dc TV |
3020 | } |
3021 | ||
3022 | i = len % 4; | |
3023 | if (i) { | |
3024 | b1 = 0; b2 = 0; b3 = 0; | |
3025 | ||
f1da39d9 | 3026 | if (dsi->debug_write) |
3de7a1dc TV |
3027 | DSSDBG("\tsending remainder bytes %d\n", i); |
3028 | ||
3029 | switch (i) { | |
3030 | case 3: | |
3031 | b1 = *p++; | |
3032 | b2 = *p++; | |
3033 | b3 = *p++; | |
3034 | break; | |
3035 | case 2: | |
3036 | b1 = *p++; | |
3037 | b2 = *p++; | |
3038 | break; | |
3039 | case 1: | |
3040 | b1 = *p++; | |
3041 | break; | |
3042 | } | |
3043 | ||
a72b64b9 | 3044 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); |
3de7a1dc TV |
3045 | } |
3046 | ||
3047 | return r; | |
3048 | } | |
3049 | ||
a72b64b9 AT |
3050 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, |
3051 | u8 data_type, u16 data, u8 ecc) | |
3de7a1dc | 3052 | { |
f1da39d9 | 3053 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3054 | u32 r; |
3055 | u8 data_id; | |
3056 | ||
a72b64b9 | 3057 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 3058 | |
f1da39d9 | 3059 | if (dsi->debug_write) |
3de7a1dc TV |
3060 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
3061 | channel, | |
3062 | data_type, data & 0xff, (data >> 8) & 0xff); | |
3063 | ||
d6049144 | 3064 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 3065 | |
a72b64b9 | 3066 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { |
3de7a1dc TV |
3067 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
3068 | return -EINVAL; | |
3069 | } | |
3070 | ||
f1da39d9 | 3071 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
3072 | |
3073 | r = (data_id << 0) | (data << 8) | (ecc << 24); | |
3074 | ||
a72b64b9 | 3075 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
3de7a1dc TV |
3076 | |
3077 | return 0; | |
3078 | } | |
3079 | ||
5cfc1c3c | 3080 | static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 3081 | { |
a72b64b9 | 3082 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
a72b64b9 | 3083 | |
18b7d099 AT |
3084 | return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, |
3085 | 0, 0); | |
3de7a1dc | 3086 | } |
3de7a1dc | 3087 | |
9e7e9372 | 3088 | static int dsi_vc_write_nosync_common(struct platform_device *dsidev, |
6ff8aa31 | 3089 | int channel, u8 *data, int len, enum dss_dsi_content_type type) |
3de7a1dc TV |
3090 | { |
3091 | int r; | |
3092 | ||
6ff8aa31 AT |
3093 | if (len == 0) { |
3094 | BUG_ON(type == DSS_DSI_CONTENT_DCS); | |
7a7c48f9 | 3095 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3096 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); |
3097 | } else if (len == 1) { | |
3098 | r = dsi_vc_send_short(dsidev, channel, | |
3099 | type == DSS_DSI_CONTENT_GENERIC ? | |
3100 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : | |
7a7c48f9 | 3101 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); |
3de7a1dc | 3102 | } else if (len == 2) { |
7a7c48f9 | 3103 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3104 | type == DSS_DSI_CONTENT_GENERIC ? |
3105 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : | |
7a7c48f9 | 3106 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
3de7a1dc TV |
3107 | data[0] | (data[1] << 8), 0); |
3108 | } else { | |
6ff8aa31 AT |
3109 | r = dsi_vc_send_long(dsidev, channel, |
3110 | type == DSS_DSI_CONTENT_GENERIC ? | |
3111 | MIPI_DSI_GENERIC_LONG_WRITE : | |
3112 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); | |
3de7a1dc TV |
3113 | } |
3114 | ||
3115 | return r; | |
3116 | } | |
6ff8aa31 | 3117 | |
5cfc1c3c | 3118 | static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
6ff8aa31 AT |
3119 | u8 *data, int len) |
3120 | { | |
9e7e9372 AT |
3121 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3122 | ||
3123 | return dsi_vc_write_nosync_common(dsidev, channel, data, len, | |
6ff8aa31 AT |
3124 | DSS_DSI_CONTENT_DCS); |
3125 | } | |
3de7a1dc | 3126 | |
5cfc1c3c | 3127 | static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
6ff8aa31 AT |
3128 | u8 *data, int len) |
3129 | { | |
9e7e9372 AT |
3130 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3131 | ||
3132 | return dsi_vc_write_nosync_common(dsidev, channel, data, len, | |
6ff8aa31 AT |
3133 | DSS_DSI_CONTENT_GENERIC); |
3134 | } | |
6ff8aa31 AT |
3135 | |
3136 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, | |
3137 | u8 *data, int len, enum dss_dsi_content_type type) | |
3de7a1dc | 3138 | { |
a72b64b9 | 3139 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3140 | int r; |
3141 | ||
9e7e9372 | 3142 | r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); |
3de7a1dc | 3143 | if (r) |
5d68e032 | 3144 | goto err; |
3de7a1dc | 3145 | |
1ffefe75 | 3146 | r = dsi_vc_send_bta_sync(dssdev, channel); |
5d68e032 TV |
3147 | if (r) |
3148 | goto err; | |
3de7a1dc | 3149 | |
a72b64b9 AT |
3150 | /* RX_FIFO_NOT_EMPTY */ |
3151 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
b63ac1e3 | 3152 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
a72b64b9 | 3153 | dsi_vc_flush_receive_data(dsidev, channel); |
b63ac1e3 TV |
3154 | r = -EIO; |
3155 | goto err; | |
3156 | } | |
3157 | ||
5d68e032 TV |
3158 | return 0; |
3159 | err: | |
6ff8aa31 | 3160 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", |
5d68e032 | 3161 | channel, data[0], len); |
3de7a1dc TV |
3162 | return r; |
3163 | } | |
6ff8aa31 | 3164 | |
5cfc1c3c | 3165 | static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
6ff8aa31 AT |
3166 | int len) |
3167 | { | |
3168 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3169 | DSS_DSI_CONTENT_DCS); | |
3170 | } | |
3de7a1dc | 3171 | |
5cfc1c3c | 3172 | static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
6ff8aa31 AT |
3173 | int len) |
3174 | { | |
3175 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3176 | DSS_DSI_CONTENT_GENERIC); | |
3177 | } | |
6ff8aa31 | 3178 | |
9e7e9372 | 3179 | static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, |
b850975c | 3180 | int channel, u8 dcs_cmd) |
3de7a1dc | 3181 | { |
f1da39d9 | 3182 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3183 | int r; |
3184 | ||
f1da39d9 | 3185 | if (dsi->debug_read) |
b850975c AT |
3186 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", |
3187 | channel, dcs_cmd); | |
3de7a1dc | 3188 | |
7a7c48f9 | 3189 | r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); |
b850975c AT |
3190 | if (r) { |
3191 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" | |
3192 | " failed\n", channel, dcs_cmd); | |
3193 | return r; | |
3194 | } | |
3de7a1dc | 3195 | |
b850975c AT |
3196 | return 0; |
3197 | } | |
3198 | ||
9e7e9372 | 3199 | static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, |
b3b89c05 AT |
3200 | int channel, u8 *reqdata, int reqlen) |
3201 | { | |
b3b89c05 AT |
3202 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3203 | u16 data; | |
3204 | u8 data_type; | |
3205 | int r; | |
3206 | ||
3207 | if (dsi->debug_read) | |
3208 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", | |
3209 | channel, reqlen); | |
3210 | ||
3211 | if (reqlen == 0) { | |
3212 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; | |
3213 | data = 0; | |
3214 | } else if (reqlen == 1) { | |
3215 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; | |
3216 | data = reqdata[0]; | |
3217 | } else if (reqlen == 2) { | |
3218 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; | |
3219 | data = reqdata[0] | (reqdata[1] << 8); | |
3220 | } else { | |
3221 | BUG(); | |
c6eee968 | 3222 | return -EINVAL; |
b3b89c05 AT |
3223 | } |
3224 | ||
3225 | r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); | |
3226 | if (r) { | |
3227 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" | |
3228 | " failed\n", channel, reqlen); | |
3229 | return r; | |
3230 | } | |
3231 | ||
3232 | return 0; | |
3233 | } | |
3234 | ||
3235 | static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, | |
3236 | u8 *buf, int buflen, enum dss_dsi_content_type type) | |
b850975c AT |
3237 | { |
3238 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3239 | u32 val; | |
3240 | u8 dt; | |
3241 | int r; | |
3de7a1dc TV |
3242 | |
3243 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 3244 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { |
3de7a1dc | 3245 | DSSERR("RX fifo empty when trying to read.\n"); |
5d68e032 TV |
3246 | r = -EIO; |
3247 | goto err; | |
3de7a1dc TV |
3248 | } |
3249 | ||
a72b64b9 | 3250 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
f1da39d9 | 3251 | if (dsi->debug_read) |
3de7a1dc TV |
3252 | DSSDBG("\theader: %08x\n", val); |
3253 | dt = FLD_GET(val, 5, 0); | |
7a7c48f9 | 3254 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
3255 | u16 err = FLD_GET(val, 23, 8); |
3256 | dsi_show_rx_ack_with_err(err); | |
5d68e032 TV |
3257 | r = -EIO; |
3258 | goto err; | |
3de7a1dc | 3259 | |
b3b89c05 AT |
3260 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3261 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : | |
3262 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { | |
3de7a1dc | 3263 | u8 data = FLD_GET(val, 15, 8); |
f1da39d9 | 3264 | if (dsi->debug_read) |
b3b89c05 AT |
3265 | DSSDBG("\t%s short response, 1 byte: %02x\n", |
3266 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3267 | "DCS", data); | |
3de7a1dc | 3268 | |
5d68e032 TV |
3269 | if (buflen < 1) { |
3270 | r = -EIO; | |
3271 | goto err; | |
3272 | } | |
3de7a1dc TV |
3273 | |
3274 | buf[0] = data; | |
3275 | ||
3276 | return 1; | |
b3b89c05 AT |
3277 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3278 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : | |
3279 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { | |
3de7a1dc | 3280 | u16 data = FLD_GET(val, 23, 8); |
f1da39d9 | 3281 | if (dsi->debug_read) |
b3b89c05 AT |
3282 | DSSDBG("\t%s short response, 2 byte: %04x\n", |
3283 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3284 | "DCS", data); | |
3de7a1dc | 3285 | |
5d68e032 TV |
3286 | if (buflen < 2) { |
3287 | r = -EIO; | |
3288 | goto err; | |
3289 | } | |
3de7a1dc TV |
3290 | |
3291 | buf[0] = data & 0xff; | |
3292 | buf[1] = (data >> 8) & 0xff; | |
3293 | ||
3294 | return 2; | |
b3b89c05 AT |
3295 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3296 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : | |
3297 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { | |
3de7a1dc TV |
3298 | int w; |
3299 | int len = FLD_GET(val, 23, 8); | |
f1da39d9 | 3300 | if (dsi->debug_read) |
b3b89c05 AT |
3301 | DSSDBG("\t%s long response, len %d\n", |
3302 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3303 | "DCS", len); | |
3de7a1dc | 3304 | |
5d68e032 TV |
3305 | if (len > buflen) { |
3306 | r = -EIO; | |
3307 | goto err; | |
3308 | } | |
3de7a1dc TV |
3309 | |
3310 | /* two byte checksum ends the packet, not included in len */ | |
3311 | for (w = 0; w < len + 2;) { | |
3312 | int b; | |
a72b64b9 AT |
3313 | val = dsi_read_reg(dsidev, |
3314 | DSI_VC_SHORT_PACKET_HEADER(channel)); | |
f1da39d9 | 3315 | if (dsi->debug_read) |
3de7a1dc TV |
3316 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
3317 | (val >> 0) & 0xff, | |
3318 | (val >> 8) & 0xff, | |
3319 | (val >> 16) & 0xff, | |
3320 | (val >> 24) & 0xff); | |
3321 | ||
3322 | for (b = 0; b < 4; ++b) { | |
3323 | if (w < len) | |
3324 | buf[w] = (val >> (b * 8)) & 0xff; | |
3325 | /* we discard the 2 byte checksum */ | |
3326 | ++w; | |
3327 | } | |
3328 | } | |
3329 | ||
3330 | return len; | |
3de7a1dc TV |
3331 | } else { |
3332 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
5d68e032 TV |
3333 | r = -EIO; |
3334 | goto err; | |
3de7a1dc | 3335 | } |
5d68e032 | 3336 | |
5d68e032 | 3337 | err: |
b3b89c05 AT |
3338 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, |
3339 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); | |
b850975c | 3340 | |
5d68e032 | 3341 | return r; |
b850975c AT |
3342 | } |
3343 | ||
5cfc1c3c | 3344 | static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
b850975c AT |
3345 | u8 *buf, int buflen) |
3346 | { | |
3347 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3348 | int r; | |
3349 | ||
9e7e9372 | 3350 | r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); |
b850975c AT |
3351 | if (r) |
3352 | goto err; | |
5d68e032 | 3353 | |
b850975c AT |
3354 | r = dsi_vc_send_bta_sync(dssdev, channel); |
3355 | if (r) | |
3356 | goto err; | |
3357 | ||
b3b89c05 AT |
3358 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
3359 | DSS_DSI_CONTENT_DCS); | |
b850975c AT |
3360 | if (r < 0) |
3361 | goto err; | |
3362 | ||
3363 | if (r != buflen) { | |
3364 | r = -EIO; | |
3365 | goto err; | |
3366 | } | |
3367 | ||
3368 | return 0; | |
3369 | err: | |
3370 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); | |
3371 | return r; | |
3de7a1dc | 3372 | } |
3de7a1dc | 3373 | |
b3b89c05 AT |
3374 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, |
3375 | u8 *reqdata, int reqlen, u8 *buf, int buflen) | |
3376 | { | |
3377 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3378 | int r; | |
3379 | ||
9e7e9372 | 3380 | r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); |
b3b89c05 AT |
3381 | if (r) |
3382 | return r; | |
3383 | ||
3384 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
3385 | if (r) | |
3386 | return r; | |
3387 | ||
3388 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, | |
3389 | DSS_DSI_CONTENT_GENERIC); | |
3390 | if (r < 0) | |
3391 | return r; | |
3392 | ||
3393 | if (r != buflen) { | |
3394 | r = -EIO; | |
3395 | return r; | |
3396 | } | |
3397 | ||
3398 | return 0; | |
3399 | } | |
3400 | ||
5cfc1c3c | 3401 | static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
1ffefe75 | 3402 | u16 len) |
3de7a1dc | 3403 | { |
a72b64b9 AT |
3404 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3405 | ||
7a7c48f9 AT |
3406 | return dsi_vc_send_short(dsidev, channel, |
3407 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); | |
3de7a1dc | 3408 | } |
3de7a1dc | 3409 | |
a72b64b9 | 3410 | static int dsi_enter_ulps(struct platform_device *dsidev) |
40885ab3 | 3411 | { |
f1da39d9 | 3412 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
40885ab3 | 3413 | DECLARE_COMPLETION_ONSTACK(completion); |
522a0c2f TV |
3414 | int r, i; |
3415 | unsigned mask; | |
40885ab3 | 3416 | |
702d267e | 3417 | DSSDBG("Entering ULPS"); |
40885ab3 | 3418 | |
a72b64b9 | 3419 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
40885ab3 | 3420 | |
f1da39d9 | 3421 | WARN_ON(dsi->ulps_enabled); |
40885ab3 | 3422 | |
f1da39d9 | 3423 | if (dsi->ulps_enabled) |
40885ab3 TV |
3424 | return 0; |
3425 | ||
6cc78aa9 | 3426 | /* DDR_CLK_ALWAYS_ON */ |
a72b64b9 | 3427 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { |
6cc78aa9 TV |
3428 | dsi_if_enable(dsidev, 0); |
3429 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); | |
3430 | dsi_if_enable(dsidev, 1); | |
40885ab3 TV |
3431 | } |
3432 | ||
a72b64b9 AT |
3433 | dsi_sync_vc(dsidev, 0); |
3434 | dsi_sync_vc(dsidev, 1); | |
3435 | dsi_sync_vc(dsidev, 2); | |
3436 | dsi_sync_vc(dsidev, 3); | |
40885ab3 | 3437 | |
a72b64b9 | 3438 | dsi_force_tx_stop_mode_io(dsidev); |
40885ab3 | 3439 | |
a72b64b9 AT |
3440 | dsi_vc_enable(dsidev, 0, false); |
3441 | dsi_vc_enable(dsidev, 1, false); | |
3442 | dsi_vc_enable(dsidev, 2, false); | |
3443 | dsi_vc_enable(dsidev, 3, false); | |
40885ab3 | 3444 | |
a72b64b9 | 3445 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
40885ab3 TV |
3446 | DSSERR("HS busy when enabling ULPS\n"); |
3447 | return -EIO; | |
3448 | } | |
3449 | ||
a72b64b9 | 3450 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
40885ab3 TV |
3451 | DSSERR("LP busy when enabling ULPS\n"); |
3452 | return -EIO; | |
3453 | } | |
3454 | ||
a72b64b9 | 3455 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3456 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3457 | if (r) | |
3458 | return r; | |
3459 | ||
522a0c2f TV |
3460 | mask = 0; |
3461 | ||
3462 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
3463 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
3464 | continue; | |
3465 | mask |= 1 << i; | |
3466 | } | |
40885ab3 TV |
3467 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ |
3468 | /* LANEx_ULPS_SIG2 */ | |
522a0c2f | 3469 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); |
40885ab3 | 3470 | |
a702c859 TV |
3471 | /* flush posted write and wait for SCP interface to finish the write */ |
3472 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); | |
40885ab3 TV |
3473 | |
3474 | if (wait_for_completion_timeout(&completion, | |
3475 | msecs_to_jiffies(1000)) == 0) { | |
3476 | DSSERR("ULPS enable timeout\n"); | |
3477 | r = -EIO; | |
3478 | goto err; | |
3479 | } | |
3480 | ||
a72b64b9 | 3481 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3482 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3483 | ||
8ef0e614 | 3484 | /* Reset LANEx_ULPS_SIG2 */ |
522a0c2f | 3485 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); |
8ef0e614 | 3486 | |
a702c859 TV |
3487 | /* flush posted write and wait for SCP interface to finish the write */ |
3488 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); | |
8ef0e614 | 3489 | |
a72b64b9 | 3490 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); |
40885ab3 | 3491 | |
a72b64b9 | 3492 | dsi_if_enable(dsidev, false); |
40885ab3 | 3493 | |
f1da39d9 | 3494 | dsi->ulps_enabled = true; |
40885ab3 TV |
3495 | |
3496 | return 0; | |
3497 | ||
3498 | err: | |
a72b64b9 | 3499 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3500 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3501 | return r; | |
3502 | } | |
3503 | ||
a72b64b9 AT |
3504 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, |
3505 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3506 | { |
3de7a1dc | 3507 | unsigned long fck; |
4ffa3571 TV |
3508 | unsigned long total_ticks; |
3509 | u32 r; | |
3de7a1dc | 3510 | |
4ffa3571 | 3511 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3512 | |
4ffa3571 | 3513 | /* ticks in DSI_FCK */ |
a72b64b9 | 3514 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3515 | |
a72b64b9 | 3516 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3517 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
4ffa3571 TV |
3518 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
3519 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ | |
3de7a1dc | 3520 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
a72b64b9 | 3521 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3522 | |
4ffa3571 TV |
3523 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3524 | ||
3525 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3526 | total_ticks, | |
3527 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3528 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3529 | } |
3530 | ||
a72b64b9 AT |
3531 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, |
3532 | bool x8, bool x16) | |
3de7a1dc | 3533 | { |
3de7a1dc | 3534 | unsigned long fck; |
4ffa3571 TV |
3535 | unsigned long total_ticks; |
3536 | u32 r; | |
3537 | ||
3538 | BUG_ON(ticks > 0x1fff); | |
3de7a1dc TV |
3539 | |
3540 | /* ticks in DSI_FCK */ | |
a72b64b9 | 3541 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3542 | |
a72b64b9 | 3543 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3544 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
4ffa3571 TV |
3545 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
3546 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ | |
3de7a1dc | 3547 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
a72b64b9 | 3548 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3549 | |
4ffa3571 TV |
3550 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
3551 | ||
3552 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3553 | total_ticks, | |
3554 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", | |
3555 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3556 | } |
3557 | ||
a72b64b9 AT |
3558 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, |
3559 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3560 | { |
3de7a1dc | 3561 | unsigned long fck; |
4ffa3571 TV |
3562 | unsigned long total_ticks; |
3563 | u32 r; | |
3de7a1dc | 3564 | |
4ffa3571 | 3565 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3566 | |
4ffa3571 | 3567 | /* ticks in DSI_FCK */ |
a72b64b9 | 3568 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3569 | |
a72b64b9 | 3570 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3571 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
4ffa3571 TV |
3572 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
3573 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ | |
3de7a1dc | 3574 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
a72b64b9 | 3575 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3576 | |
4ffa3571 TV |
3577 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3578 | ||
3579 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", | |
3580 | total_ticks, | |
3581 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3582 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3583 | } |
3584 | ||
a72b64b9 AT |
3585 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, |
3586 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3587 | { |
3de7a1dc | 3588 | unsigned long fck; |
4ffa3571 TV |
3589 | unsigned long total_ticks; |
3590 | u32 r; | |
3de7a1dc | 3591 | |
4ffa3571 | 3592 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3593 | |
4ffa3571 | 3594 | /* ticks in TxByteClkHS */ |
a72b64b9 | 3595 | fck = dsi_get_txbyteclkhs(dsidev); |
3de7a1dc | 3596 | |
a72b64b9 | 3597 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3598 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
4ffa3571 TV |
3599 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
3600 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ | |
3de7a1dc | 3601 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
a72b64b9 | 3602 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3603 | |
4ffa3571 TV |
3604 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3605 | ||
3606 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3607 | total_ticks, | |
3608 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3609 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc | 3610 | } |
8af6ff01 | 3611 | |
9e7e9372 | 3612 | static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) |
8af6ff01 | 3613 | { |
dca2b152 | 3614 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
8af6ff01 AT |
3615 | int num_line_buffers; |
3616 | ||
dca2b152 | 3617 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
02c3960b | 3618 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
e67458a8 | 3619 | struct omap_video_timings *timings = &dsi->timings; |
8af6ff01 AT |
3620 | /* |
3621 | * Don't use line buffers if width is greater than the video | |
3622 | * port's line buffer size | |
3623 | */ | |
99322577 | 3624 | if (dsi->line_buffer_size <= timings->x_res * bpp / 8) |
8af6ff01 AT |
3625 | num_line_buffers = 0; |
3626 | else | |
3627 | num_line_buffers = 2; | |
3628 | } else { | |
3629 | /* Use maximum number of line buffers in command mode */ | |
3630 | num_line_buffers = 2; | |
3631 | } | |
3632 | ||
3633 | /* LINE_BUFFER */ | |
3634 | REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); | |
3635 | } | |
3636 | ||
9e7e9372 | 3637 | static void dsi_config_vp_sync_events(struct platform_device *dsidev) |
8af6ff01 | 3638 | { |
0b3ffe39 | 3639 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
478d7df8 | 3640 | bool sync_end; |
8af6ff01 AT |
3641 | u32 r; |
3642 | ||
478d7df8 TV |
3643 | if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) |
3644 | sync_end = true; | |
3645 | else | |
3646 | sync_end = false; | |
3647 | ||
8af6ff01 | 3648 | r = dsi_read_reg(dsidev, DSI_CTRL); |
bd5a7b11 AT |
3649 | r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ |
3650 | r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ | |
3651 | r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ | |
8af6ff01 | 3652 | r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ |
478d7df8 | 3653 | r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ |
8af6ff01 | 3654 | r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ |
478d7df8 | 3655 | r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ |
8af6ff01 AT |
3656 | dsi_write_reg(dsidev, DSI_CTRL, r); |
3657 | } | |
3658 | ||
9e7e9372 | 3659 | static void dsi_config_blanking_modes(struct platform_device *dsidev) |
8af6ff01 | 3660 | { |
0b3ffe39 AT |
3661 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3662 | int blanking_mode = dsi->vm_timings.blanking_mode; | |
3663 | int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; | |
3664 | int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; | |
3665 | int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; | |
8af6ff01 AT |
3666 | u32 r; |
3667 | ||
3668 | /* | |
3669 | * 0 = TX FIFO packets sent or LPS in corresponding blanking periods | |
3670 | * 1 = Long blanking packets are sent in corresponding blanking periods | |
3671 | */ | |
3672 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3673 | r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ | |
3674 | r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ | |
3675 | r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ | |
3676 | r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ | |
3677 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3678 | } | |
3679 | ||
6f28c296 AT |
3680 | /* |
3681 | * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 | |
3682 | * results in maximum transition time for data and clock lanes to enter and | |
3683 | * exit HS mode. Hence, this is the scenario where the least amount of command | |
3684 | * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS | |
3685 | * clock cycles that can be used to interleave command mode data in HS so that | |
3686 | * all scenarios are satisfied. | |
3687 | */ | |
3688 | static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, | |
3689 | int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) | |
3690 | { | |
3691 | int transition; | |
3692 | ||
3693 | /* | |
3694 | * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition | |
3695 | * time of data lanes only, if it isn't set, we need to consider HS | |
3696 | * transition time of both data and clock lanes. HS transition time | |
3697 | * of Scenario 3 is considered. | |
3698 | */ | |
3699 | if (ddr_alwon) { | |
3700 | transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3701 | } else { | |
3702 | int trans1, trans2; | |
3703 | trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3704 | trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + | |
3705 | enter_hs + 1; | |
3706 | transition = max(trans1, trans2); | |
3707 | } | |
3708 | ||
3709 | return blank > transition ? blank - transition : 0; | |
3710 | } | |
3711 | ||
3712 | /* | |
3713 | * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 | |
3714 | * results in maximum transition time for data lanes to enter and exit LP mode. | |
3715 | * Hence, this is the scenario where the least amount of command mode data can | |
3716 | * be interleaved. We program the minimum amount of bytes that can be | |
3717 | * interleaved in LP so that all scenarios are satisfied. | |
3718 | */ | |
3719 | static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, | |
3720 | int lp_clk_div, int tdsi_fclk) | |
3721 | { | |
3722 | int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ | |
3723 | int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ | |
3724 | int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ | |
3725 | int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ | |
3726 | int lp_inter; /* cmd mode data that can be interleaved, in bytes */ | |
3727 | ||
3728 | /* maximum LP transition time according to Scenario 1 */ | |
3729 | trans_lp = exit_hs + max(enter_hs, 2) + 1; | |
3730 | ||
3731 | /* CLKIN4DDR = 16 * TXBYTECLKHS */ | |
3732 | tlp_avail = thsbyte_clk * (blank - trans_lp); | |
3733 | ||
2e063c30 | 3734 | ttxclkesc = tdsi_fclk * lp_clk_div; |
6f28c296 AT |
3735 | |
3736 | lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - | |
3737 | 26) / 16; | |
3738 | ||
3739 | return max(lp_inter, 0); | |
3740 | } | |
3741 | ||
5761217a | 3742 | static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) |
6f28c296 | 3743 | { |
6f28c296 AT |
3744 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3745 | int blanking_mode; | |
3746 | int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; | |
3747 | int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; | |
3748 | int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; | |
3749 | int tclk_trail, ths_exit, exiths_clk; | |
3750 | bool ddr_alwon; | |
e67458a8 | 3751 | struct omap_video_timings *timings = &dsi->timings; |
02c3960b | 3752 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
6f28c296 | 3753 | int ndl = dsi->num_lanes_used - 1; |
a0d269ec | 3754 | int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1; |
6f28c296 AT |
3755 | int hsa_interleave_hs = 0, hsa_interleave_lp = 0; |
3756 | int hfp_interleave_hs = 0, hfp_interleave_lp = 0; | |
3757 | int hbp_interleave_hs = 0, hbp_interleave_lp = 0; | |
3758 | int bl_interleave_hs = 0, bl_interleave_lp = 0; | |
3759 | u32 r; | |
3760 | ||
3761 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3762 | blanking_mode = FLD_GET(r, 20, 20); | |
3763 | hfp_blanking_mode = FLD_GET(r, 21, 21); | |
3764 | hbp_blanking_mode = FLD_GET(r, 22, 22); | |
3765 | hsa_blanking_mode = FLD_GET(r, 23, 23); | |
3766 | ||
3767 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); | |
3768 | hbp = FLD_GET(r, 11, 0); | |
3769 | hfp = FLD_GET(r, 23, 12); | |
3770 | hsa = FLD_GET(r, 31, 24); | |
3771 | ||
3772 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); | |
3773 | ddr_clk_post = FLD_GET(r, 7, 0); | |
3774 | ddr_clk_pre = FLD_GET(r, 15, 8); | |
3775 | ||
3776 | r = dsi_read_reg(dsidev, DSI_VM_TIMING7); | |
3777 | exit_hs_mode_lat = FLD_GET(r, 15, 0); | |
3778 | enter_hs_mode_lat = FLD_GET(r, 31, 16); | |
3779 | ||
3780 | r = dsi_read_reg(dsidev, DSI_CLK_CTRL); | |
3781 | lp_clk_div = FLD_GET(r, 12, 0); | |
3782 | ddr_alwon = FLD_GET(r, 13, 13); | |
3783 | ||
3784 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); | |
3785 | ths_exit = FLD_GET(r, 7, 0); | |
3786 | ||
3787 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); | |
3788 | tclk_trail = FLD_GET(r, 15, 8); | |
3789 | ||
3790 | exiths_clk = ths_exit + tclk_trail; | |
3791 | ||
3792 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); | |
3793 | bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); | |
3794 | ||
3795 | if (!hsa_blanking_mode) { | |
3796 | hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, | |
3797 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3798 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3799 | hsa_interleave_lp = dsi_compute_interleave_lp(hsa, | |
3800 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3801 | lp_clk_div, dsi_fclk_hsdiv); | |
3802 | } | |
3803 | ||
3804 | if (!hfp_blanking_mode) { | |
3805 | hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, | |
3806 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3807 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3808 | hfp_interleave_lp = dsi_compute_interleave_lp(hfp, | |
3809 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3810 | lp_clk_div, dsi_fclk_hsdiv); | |
3811 | } | |
3812 | ||
3813 | if (!hbp_blanking_mode) { | |
3814 | hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, | |
3815 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3816 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3817 | ||
3818 | hbp_interleave_lp = dsi_compute_interleave_lp(hbp, | |
3819 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3820 | lp_clk_div, dsi_fclk_hsdiv); | |
3821 | } | |
3822 | ||
3823 | if (!blanking_mode) { | |
3824 | bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, | |
3825 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3826 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3827 | ||
3828 | bl_interleave_lp = dsi_compute_interleave_lp(bllp, | |
3829 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3830 | lp_clk_div, dsi_fclk_hsdiv); | |
3831 | } | |
3832 | ||
3833 | DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3834 | hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, | |
3835 | bl_interleave_hs); | |
3836 | ||
3837 | DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3838 | hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, | |
3839 | bl_interleave_lp); | |
3840 | ||
3841 | r = dsi_read_reg(dsidev, DSI_VM_TIMING4); | |
3842 | r = FLD_MOD(r, hsa_interleave_hs, 23, 16); | |
3843 | r = FLD_MOD(r, hfp_interleave_hs, 15, 8); | |
3844 | r = FLD_MOD(r, hbp_interleave_hs, 7, 0); | |
3845 | dsi_write_reg(dsidev, DSI_VM_TIMING4, r); | |
3846 | ||
3847 | r = dsi_read_reg(dsidev, DSI_VM_TIMING5); | |
3848 | r = FLD_MOD(r, hsa_interleave_lp, 23, 16); | |
3849 | r = FLD_MOD(r, hfp_interleave_lp, 15, 8); | |
3850 | r = FLD_MOD(r, hbp_interleave_lp, 7, 0); | |
3851 | dsi_write_reg(dsidev, DSI_VM_TIMING5, r); | |
3852 | ||
3853 | r = dsi_read_reg(dsidev, DSI_VM_TIMING6); | |
3854 | r = FLD_MOD(r, bl_interleave_hs, 31, 15); | |
3855 | r = FLD_MOD(r, bl_interleave_lp, 16, 0); | |
3856 | dsi_write_reg(dsidev, DSI_VM_TIMING6, r); | |
3857 | } | |
3858 | ||
5761217a | 3859 | static int dsi_proto_config(struct platform_device *dsidev) |
3de7a1dc | 3860 | { |
02c3960b | 3861 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3862 | u32 r; |
3863 | int buswidth = 0; | |
3864 | ||
a72b64b9 | 3865 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3866 | DSI_FIFO_SIZE_32, |
3867 | DSI_FIFO_SIZE_32, | |
3868 | DSI_FIFO_SIZE_32); | |
3de7a1dc | 3869 | |
a72b64b9 | 3870 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3871 | DSI_FIFO_SIZE_32, |
3872 | DSI_FIFO_SIZE_32, | |
3873 | DSI_FIFO_SIZE_32); | |
3de7a1dc TV |
3874 | |
3875 | /* XXX what values for the timeouts? */ | |
a72b64b9 AT |
3876 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); |
3877 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); | |
3878 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); | |
3879 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); | |
3de7a1dc | 3880 | |
02c3960b | 3881 | switch (dsi_get_pixel_size(dsi->pix_fmt)) { |
3de7a1dc TV |
3882 | case 16: |
3883 | buswidth = 0; | |
3884 | break; | |
3885 | case 18: | |
3886 | buswidth = 1; | |
3887 | break; | |
3888 | case 24: | |
3889 | buswidth = 2; | |
3890 | break; | |
3891 | default: | |
3892 | BUG(); | |
c6eee968 | 3893 | return -EINVAL; |
3de7a1dc TV |
3894 | } |
3895 | ||
a72b64b9 | 3896 | r = dsi_read_reg(dsidev, DSI_CTRL); |
3de7a1dc TV |
3897 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
3898 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | |
3899 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | |
3900 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ | |
3901 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | |
3902 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | |
3de7a1dc TV |
3903 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
3904 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ | |
9613c02b AT |
3905 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
3906 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ | |
3907 | /* DCS_CMD_CODE, 1=start, 0=continue */ | |
3908 | r = FLD_MOD(r, 0, 25, 25); | |
3909 | } | |
3de7a1dc | 3910 | |
a72b64b9 | 3911 | dsi_write_reg(dsidev, DSI_CTRL, r); |
3de7a1dc | 3912 | |
9e7e9372 | 3913 | dsi_config_vp_num_line_buffers(dsidev); |
8af6ff01 | 3914 | |
dca2b152 | 3915 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
9e7e9372 AT |
3916 | dsi_config_vp_sync_events(dsidev); |
3917 | dsi_config_blanking_modes(dsidev); | |
5761217a | 3918 | dsi_config_cmd_mode_interleaving(dsidev); |
8af6ff01 AT |
3919 | } |
3920 | ||
a72b64b9 AT |
3921 | dsi_vc_initial_config(dsidev, 0); |
3922 | dsi_vc_initial_config(dsidev, 1); | |
3923 | dsi_vc_initial_config(dsidev, 2); | |
3924 | dsi_vc_initial_config(dsidev, 3); | |
3de7a1dc TV |
3925 | |
3926 | return 0; | |
3927 | } | |
3928 | ||
9e7e9372 | 3929 | static void dsi_proto_timings(struct platform_device *dsidev) |
3de7a1dc | 3930 | { |
db18644f | 3931 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3932 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
3933 | unsigned tclk_pre, tclk_post; | |
3934 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; | |
3935 | unsigned ths_trail, ths_exit; | |
3936 | unsigned ddr_clk_pre, ddr_clk_post; | |
3937 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; | |
3938 | unsigned ths_eot; | |
db18644f | 3939 | int ndl = dsi->num_lanes_used - 1; |
3de7a1dc TV |
3940 | u32 r; |
3941 | ||
a72b64b9 | 3942 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
3943 | ths_prepare = FLD_GET(r, 31, 24); |
3944 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); | |
3945 | ths_zero = ths_prepare_ths_zero - ths_prepare; | |
3946 | ths_trail = FLD_GET(r, 15, 8); | |
3947 | ths_exit = FLD_GET(r, 7, 0); | |
3948 | ||
a72b64b9 | 3949 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
e84dc1cc | 3950 | tlpx = FLD_GET(r, 20, 16) * 2; |
3de7a1dc TV |
3951 | tclk_trail = FLD_GET(r, 15, 8); |
3952 | tclk_zero = FLD_GET(r, 7, 0); | |
3953 | ||
a72b64b9 | 3954 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc TV |
3955 | tclk_prepare = FLD_GET(r, 7, 0); |
3956 | ||
3957 | /* min 8*UI */ | |
3958 | tclk_pre = 20; | |
3959 | /* min 60ns + 52*UI */ | |
a72b64b9 | 3960 | tclk_post = ns2ddr(dsidev, 60) + 26; |
3de7a1dc | 3961 | |
8af6ff01 | 3962 | ths_eot = DIV_ROUND_UP(4, ndl); |
3de7a1dc TV |
3963 | |
3964 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, | |
3965 | 4); | |
3966 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; | |
3967 | ||
3968 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); | |
3969 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); | |
3970 | ||
a72b64b9 | 3971 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
3de7a1dc TV |
3972 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
3973 | r = FLD_MOD(r, ddr_clk_post, 7, 0); | |
a72b64b9 | 3974 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); |
3de7a1dc TV |
3975 | |
3976 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", | |
3977 | ddr_clk_pre, | |
3978 | ddr_clk_post); | |
3979 | ||
3980 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + | |
3981 | DIV_ROUND_UP(ths_prepare, 4) + | |
3982 | DIV_ROUND_UP(ths_zero + 3, 4); | |
3983 | ||
3984 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; | |
3985 | ||
3986 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | | |
3987 | FLD_VAL(exit_hs_mode_lat, 15, 0); | |
a72b64b9 | 3988 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); |
3de7a1dc TV |
3989 | |
3990 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", | |
3991 | enter_hs_mode_lat, exit_hs_mode_lat); | |
8af6ff01 | 3992 | |
dca2b152 | 3993 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
8af6ff01 | 3994 | /* TODO: Implement a video mode check_timings function */ |
0b3ffe39 AT |
3995 | int hsa = dsi->vm_timings.hsa; |
3996 | int hfp = dsi->vm_timings.hfp; | |
3997 | int hbp = dsi->vm_timings.hbp; | |
3998 | int vsa = dsi->vm_timings.vsa; | |
3999 | int vfp = dsi->vm_timings.vfp; | |
4000 | int vbp = dsi->vm_timings.vbp; | |
4001 | int window_sync = dsi->vm_timings.window_sync; | |
478d7df8 | 4002 | bool hsync_end; |
e67458a8 | 4003 | struct omap_video_timings *timings = &dsi->timings; |
02c3960b | 4004 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
8af6ff01 AT |
4005 | int tl, t_he, width_bytes; |
4006 | ||
478d7df8 | 4007 | hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; |
8af6ff01 AT |
4008 | t_he = hsync_end ? |
4009 | ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; | |
4010 | ||
4011 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); | |
4012 | ||
4013 | /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ | |
4014 | tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + | |
4015 | DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; | |
4016 | ||
4017 | DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, | |
4018 | hfp, hsync_end ? hsa : 0, tl); | |
4019 | DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, | |
4020 | vsa, timings->y_res); | |
4021 | ||
4022 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); | |
4023 | r = FLD_MOD(r, hbp, 11, 0); /* HBP */ | |
4024 | r = FLD_MOD(r, hfp, 23, 12); /* HFP */ | |
4025 | r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ | |
4026 | dsi_write_reg(dsidev, DSI_VM_TIMING1, r); | |
4027 | ||
4028 | r = dsi_read_reg(dsidev, DSI_VM_TIMING2); | |
4029 | r = FLD_MOD(r, vbp, 7, 0); /* VBP */ | |
4030 | r = FLD_MOD(r, vfp, 15, 8); /* VFP */ | |
4031 | r = FLD_MOD(r, vsa, 23, 16); /* VSA */ | |
4032 | r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ | |
4033 | dsi_write_reg(dsidev, DSI_VM_TIMING2, r); | |
4034 | ||
4035 | r = dsi_read_reg(dsidev, DSI_VM_TIMING3); | |
4036 | r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ | |
4037 | r = FLD_MOD(r, tl, 31, 16); /* TL */ | |
4038 | dsi_write_reg(dsidev, DSI_VM_TIMING3, r); | |
4039 | } | |
4040 | } | |
4041 | ||
5cfc1c3c | 4042 | static int dsi_configure_pins(struct omap_dss_device *dssdev, |
e4a9e94c TV |
4043 | const struct omap_dsi_pin_config *pin_cfg) |
4044 | { | |
4045 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4046 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4047 | int num_pins; | |
4048 | const int *pins; | |
4049 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; | |
4050 | int num_lanes; | |
4051 | int i; | |
4052 | ||
4053 | static const enum dsi_lane_function functions[] = { | |
4054 | DSI_LANE_CLK, | |
4055 | DSI_LANE_DATA1, | |
4056 | DSI_LANE_DATA2, | |
4057 | DSI_LANE_DATA3, | |
4058 | DSI_LANE_DATA4, | |
4059 | }; | |
4060 | ||
4061 | num_pins = pin_cfg->num_pins; | |
4062 | pins = pin_cfg->pins; | |
4063 | ||
4064 | if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 | |
4065 | || num_pins % 2 != 0) | |
4066 | return -EINVAL; | |
4067 | ||
4068 | for (i = 0; i < DSI_MAX_NR_LANES; ++i) | |
4069 | lanes[i].function = DSI_LANE_UNUSED; | |
4070 | ||
4071 | num_lanes = 0; | |
4072 | ||
4073 | for (i = 0; i < num_pins; i += 2) { | |
4074 | u8 lane, pol; | |
4075 | int dx, dy; | |
4076 | ||
4077 | dx = pins[i]; | |
4078 | dy = pins[i + 1]; | |
4079 | ||
4080 | if (dx < 0 || dx >= dsi->num_lanes_supported * 2) | |
4081 | return -EINVAL; | |
4082 | ||
4083 | if (dy < 0 || dy >= dsi->num_lanes_supported * 2) | |
4084 | return -EINVAL; | |
4085 | ||
4086 | if (dx & 1) { | |
4087 | if (dy != dx - 1) | |
4088 | return -EINVAL; | |
4089 | pol = 1; | |
4090 | } else { | |
4091 | if (dy != dx + 1) | |
4092 | return -EINVAL; | |
4093 | pol = 0; | |
4094 | } | |
4095 | ||
4096 | lane = dx / 2; | |
4097 | ||
4098 | lanes[lane].function = functions[i / 2]; | |
4099 | lanes[lane].polarity = pol; | |
4100 | num_lanes++; | |
4101 | } | |
4102 | ||
4103 | memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); | |
4104 | dsi->num_lanes_used = num_lanes; | |
4105 | ||
4106 | return 0; | |
4107 | } | |
e4a9e94c | 4108 | |
5cfc1c3c | 4109 | static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) |
8af6ff01 AT |
4110 | { |
4111 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
e67458a8 | 4112 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5761217a | 4113 | struct omap_overlay_manager *mgr = dsi->output.manager; |
02c3960b | 4114 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
1f68d9c4 | 4115 | struct omap_dss_device *out = &dsi->output; |
8af6ff01 AT |
4116 | u8 data_type; |
4117 | u16 word_count; | |
33ca237f | 4118 | int r; |
8af6ff01 | 4119 | |
b7dec9b6 TV |
4120 | if (out == NULL || out->manager == NULL) { |
4121 | DSSERR("failed to enable display: no output/manager\n"); | |
4122 | return -ENODEV; | |
4123 | } | |
4124 | ||
4125 | r = dsi_display_init_dispc(dsidev, mgr); | |
4126 | if (r) | |
4127 | goto err_init_dispc; | |
4128 | ||
dca2b152 | 4129 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
02c3960b | 4130 | switch (dsi->pix_fmt) { |
9a147a65 TV |
4131 | case OMAP_DSS_DSI_FMT_RGB888: |
4132 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
4133 | break; | |
4134 | case OMAP_DSS_DSI_FMT_RGB666: | |
4135 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
4136 | break; | |
4137 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
4138 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
4139 | break; | |
4140 | case OMAP_DSS_DSI_FMT_RGB565: | |
4141 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
4142 | break; | |
4143 | default: | |
b7dec9b6 TV |
4144 | r = -EINVAL; |
4145 | goto err_pix_fmt; | |
cf6ac4ce | 4146 | } |
8af6ff01 | 4147 | |
9a147a65 TV |
4148 | dsi_if_enable(dsidev, false); |
4149 | dsi_vc_enable(dsidev, channel, false); | |
8af6ff01 | 4150 | |
9a147a65 TV |
4151 | /* MODE, 1 = video mode */ |
4152 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); | |
8af6ff01 | 4153 | |
e67458a8 | 4154 | word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); |
8af6ff01 | 4155 | |
9a147a65 TV |
4156 | dsi_vc_write_long_header(dsidev, channel, data_type, |
4157 | word_count, 0); | |
8af6ff01 | 4158 | |
9a147a65 TV |
4159 | dsi_vc_enable(dsidev, channel, true); |
4160 | dsi_if_enable(dsidev, true); | |
4161 | } | |
8af6ff01 | 4162 | |
eea8340a | 4163 | r = dss_mgr_enable(mgr); |
b7dec9b6 TV |
4164 | if (r) |
4165 | goto err_mgr_enable; | |
8af6ff01 AT |
4166 | |
4167 | return 0; | |
b7dec9b6 TV |
4168 | |
4169 | err_mgr_enable: | |
4170 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
4171 | dsi_if_enable(dsidev, false); | |
4172 | dsi_vc_enable(dsidev, channel, false); | |
4173 | } | |
4174 | err_pix_fmt: | |
4175 | dsi_display_uninit_dispc(dsidev, mgr); | |
4176 | err_init_dispc: | |
4177 | return r; | |
8af6ff01 | 4178 | } |
8af6ff01 | 4179 | |
5cfc1c3c | 4180 | static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) |
8af6ff01 AT |
4181 | { |
4182 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
dca2b152 | 4183 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5761217a | 4184 | struct omap_overlay_manager *mgr = dsi->output.manager; |
8af6ff01 | 4185 | |
dca2b152 | 4186 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
9a147a65 TV |
4187 | dsi_if_enable(dsidev, false); |
4188 | dsi_vc_enable(dsidev, channel, false); | |
8af6ff01 | 4189 | |
9a147a65 TV |
4190 | /* MODE, 0 = command mode */ |
4191 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); | |
8af6ff01 | 4192 | |
9a147a65 TV |
4193 | dsi_vc_enable(dsidev, channel, true); |
4194 | dsi_if_enable(dsidev, true); | |
4195 | } | |
8af6ff01 | 4196 | |
eea8340a | 4197 | dss_mgr_disable(mgr); |
b7dec9b6 TV |
4198 | |
4199 | dsi_display_uninit_dispc(dsidev, mgr); | |
3de7a1dc TV |
4200 | } |
4201 | ||
5761217a | 4202 | static void dsi_update_screen_dispc(struct platform_device *dsidev) |
3de7a1dc | 4203 | { |
f1da39d9 | 4204 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5761217a | 4205 | struct omap_overlay_manager *mgr = dsi->output.manager; |
3de7a1dc TV |
4206 | unsigned bytespp; |
4207 | unsigned bytespl; | |
4208 | unsigned bytespf; | |
4209 | unsigned total_len; | |
4210 | unsigned packet_payload; | |
4211 | unsigned packet_len; | |
4212 | u32 l; | |
0f16aa0a | 4213 | int r; |
f1da39d9 | 4214 | const unsigned channel = dsi->update_channel; |
99322577 | 4215 | const unsigned line_buf_size = dsi->line_buffer_size; |
55cd63ac AT |
4216 | u16 w = dsi->timings.x_res; |
4217 | u16 h = dsi->timings.y_res; | |
3de7a1dc | 4218 | |
5476e74a | 4219 | DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); |
3de7a1dc | 4220 | |
d6049144 | 4221 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); |
18946f62 | 4222 | |
02c3960b | 4223 | bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; |
3de7a1dc TV |
4224 | bytespl = w * bytespp; |
4225 | bytespf = bytespl * h; | |
4226 | ||
4227 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is | |
4228 | * number of lines in a packet. See errata about VP_CLK_RATIO */ | |
4229 | ||
4230 | if (bytespf < line_buf_size) | |
4231 | packet_payload = bytespf; | |
4232 | else | |
4233 | packet_payload = (line_buf_size) / bytespl * bytespl; | |
4234 | ||
4235 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ | |
4236 | total_len = (bytespf / packet_payload) * packet_len; | |
4237 | ||
4238 | if (bytespf % packet_payload) | |
4239 | total_len += (bytespf % packet_payload) + 1; | |
4240 | ||
3de7a1dc | 4241 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
a72b64b9 | 4242 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc | 4243 | |
7a7c48f9 | 4244 | dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, |
a72b64b9 | 4245 | packet_len, 0); |
3de7a1dc | 4246 | |
f1da39d9 | 4247 | if (dsi->te_enabled) |
3de7a1dc TV |
4248 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
4249 | else | |
4250 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ | |
a72b64b9 | 4251 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc TV |
4252 | |
4253 | /* We put SIDLEMODE to no-idle for the duration of the transfer, | |
4254 | * because DSS interrupts are not capable of waking up the CPU and the | |
4255 | * framedone interrupt could be delayed for quite a long time. I think | |
4256 | * the same goes for any DSS interrupts, but for some reason I have not | |
4257 | * seen the problem anywhere else than here. | |
4258 | */ | |
4259 | dispc_disable_sidle(); | |
4260 | ||
a72b64b9 | 4261 | dsi_perf_mark_start(dsidev); |
18946f62 | 4262 | |
49dbf589 AT |
4263 | r = schedule_delayed_work(&dsi->framedone_timeout_work, |
4264 | msecs_to_jiffies(250)); | |
0f16aa0a | 4265 | BUG_ON(r == 0); |
18946f62 | 4266 | |
eea8340a | 4267 | dss_mgr_set_timings(mgr, &dsi->timings); |
55cd63ac | 4268 | |
eea8340a | 4269 | dss_mgr_start_update(mgr); |
3de7a1dc | 4270 | |
f1da39d9 | 4271 | if (dsi->te_enabled) { |
3de7a1dc TV |
4272 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
4273 | * for TE is longer than the timer allows */ | |
a72b64b9 | 4274 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
3de7a1dc | 4275 | |
a72b64b9 | 4276 | dsi_vc_send_bta(dsidev, channel); |
3de7a1dc TV |
4277 | |
4278 | #ifdef DSI_CATCH_MISSING_TE | |
f1da39d9 | 4279 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
3de7a1dc TV |
4280 | #endif |
4281 | } | |
4282 | } | |
4283 | ||
4284 | #ifdef DSI_CATCH_MISSING_TE | |
4285 | static void dsi_te_timeout(unsigned long arg) | |
4286 | { | |
4287 | DSSERR("TE not received for 250ms!\n"); | |
4288 | } | |
4289 | #endif | |
4290 | ||
a72b64b9 | 4291 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) |
3de7a1dc | 4292 | { |
f1da39d9 AT |
4293 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4294 | ||
3de7a1dc TV |
4295 | /* SIDLEMODE back to smart-idle */ |
4296 | dispc_enable_sidle(); | |
4297 | ||
f1da39d9 | 4298 | if (dsi->te_enabled) { |
18946f62 | 4299 | /* enable LP_RX_TO again after the TE */ |
a72b64b9 | 4300 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
3de7a1dc TV |
4301 | } |
4302 | ||
f1da39d9 | 4303 | dsi->framedone_callback(error, dsi->framedone_data); |
ab83b14c TV |
4304 | |
4305 | if (!error) | |
a72b64b9 | 4306 | dsi_perf_show(dsidev, "DISPC"); |
18946f62 | 4307 | } |
3de7a1dc | 4308 | |
ab83b14c | 4309 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
18946f62 | 4310 | { |
f1da39d9 AT |
4311 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
4312 | framedone_timeout_work.work); | |
ab83b14c TV |
4313 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
4314 | * 250ms which would conflict with this timeout work. What should be | |
4315 | * done is first cancel the transfer on the HW, and then cancel the | |
4316 | * possibly scheduled framedone work. However, cancelling the transfer | |
4317 | * on the HW is buggy, and would probably require resetting the whole | |
4318 | * DSI */ | |
18946f62 | 4319 | |
ab83b14c | 4320 | DSSERR("Framedone not received for 250ms!\n"); |
3de7a1dc | 4321 | |
f1da39d9 | 4322 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); |
3de7a1dc TV |
4323 | } |
4324 | ||
1550202d | 4325 | static void dsi_framedone_irq_callback(void *data) |
3de7a1dc | 4326 | { |
9e7e9372 | 4327 | struct platform_device *dsidev = (struct platform_device *) data; |
f1da39d9 AT |
4328 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4329 | ||
ab83b14c TV |
4330 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
4331 | * turns itself off. However, DSI still has the pixels in its buffers, | |
4332 | * and is sending the data. | |
4333 | */ | |
3de7a1dc | 4334 | |
136b5721 | 4335 | cancel_delayed_work(&dsi->framedone_timeout_work); |
3de7a1dc | 4336 | |
a72b64b9 | 4337 | dsi_handle_framedone(dsidev, 0); |
18946f62 | 4338 | } |
3de7a1dc | 4339 | |
5cfc1c3c | 4340 | static int dsi_update(struct omap_dss_device *dssdev, int channel, |
5476e74a | 4341 | void (*callback)(int, void *), void *data) |
18946f62 | 4342 | { |
a72b64b9 | 4343 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
5476e74a | 4344 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
18946f62 | 4345 | u16 dw, dh; |
3de7a1dc | 4346 | |
a72b64b9 | 4347 | dsi_perf_mark_setup(dsidev); |
3de7a1dc | 4348 | |
f1da39d9 | 4349 | dsi->update_channel = channel; |
3de7a1dc | 4350 | |
4a9e78ab TV |
4351 | dsi->framedone_callback = callback; |
4352 | dsi->framedone_data = data; | |
e9c31afc | 4353 | |
e352574d AT |
4354 | dw = dsi->timings.x_res; |
4355 | dh = dsi->timings.y_res; | |
e9c31afc | 4356 | |
477fed70 | 4357 | #ifdef DSI_PERF_MEASURE |
5476e74a | 4358 | dsi->update_bytes = dw * dh * |
02c3960b | 4359 | dsi_get_pixel_size(dsi->pix_fmt) / 8; |
5476e74a | 4360 | #endif |
5761217a | 4361 | dsi_update_screen_dispc(dsidev); |
3de7a1dc | 4362 | |
3de7a1dc TV |
4363 | return 0; |
4364 | } | |
3de7a1dc TV |
4365 | |
4366 | /* Display funcs */ | |
4367 | ||
5761217a | 4368 | static int dsi_configure_dispc_clocks(struct platform_device *dsidev) |
3de7a1dc | 4369 | { |
7d2572f8 AT |
4370 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4371 | struct dispc_clock_info dispc_cinfo; | |
3de7a1dc | 4372 | int r; |
17518189 | 4373 | unsigned long fck; |
7d2572f8 AT |
4374 | |
4375 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
4376 | ||
a0d269ec TV |
4377 | dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; |
4378 | dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; | |
7d2572f8 AT |
4379 | |
4380 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); | |
4381 | if (r) { | |
4382 | DSSERR("Failed to calc dispc clocks\n"); | |
4383 | return r; | |
4384 | } | |
4385 | ||
4386 | dsi->mgr_config.clock_info = dispc_cinfo; | |
4387 | ||
4388 | return 0; | |
4389 | } | |
4390 | ||
b7dec9b6 TV |
4391 | static int dsi_display_init_dispc(struct platform_device *dsidev, |
4392 | struct omap_overlay_manager *mgr) | |
7d2572f8 | 4393 | { |
7d2572f8 | 4394 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
7d2572f8 | 4395 | int r; |
3de7a1dc | 4396 | |
4ce9e33c TV |
4397 | dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ? |
4398 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : | |
4399 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); | |
5476e74a | 4400 | |
dca2b152 | 4401 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { |
1550202d TV |
4402 | r = dss_mgr_register_framedone_handler(mgr, |
4403 | dsi_framedone_irq_callback, dsidev); | |
8af6ff01 | 4404 | if (r) { |
1550202d | 4405 | DSSERR("can't register FRAMEDONE handler\n"); |
7d2572f8 | 4406 | goto err; |
8af6ff01 AT |
4407 | } |
4408 | ||
7d2572f8 AT |
4409 | dsi->mgr_config.stallmode = true; |
4410 | dsi->mgr_config.fifohandcheck = true; | |
8af6ff01 | 4411 | } else { |
7d2572f8 AT |
4412 | dsi->mgr_config.stallmode = false; |
4413 | dsi->mgr_config.fifohandcheck = false; | |
3de7a1dc TV |
4414 | } |
4415 | ||
bd5a7b11 AT |
4416 | /* |
4417 | * override interlace, logic level and edge related parameters in | |
4418 | * omap_video_timings with default values | |
4419 | */ | |
e67458a8 AT |
4420 | dsi->timings.interlace = false; |
4421 | dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4422 | dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4423 | dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; | |
4424 | dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4425 | dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES; | |
bd5a7b11 | 4426 | |
eea8340a | 4427 | dss_mgr_set_timings(mgr, &dsi->timings); |
bd5a7b11 | 4428 | |
5761217a | 4429 | r = dsi_configure_dispc_clocks(dsidev); |
7d2572f8 AT |
4430 | if (r) |
4431 | goto err1; | |
4432 | ||
4433 | dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; | |
4434 | dsi->mgr_config.video_port_width = | |
02c3960b | 4435 | dsi_get_pixel_size(dsi->pix_fmt); |
7d2572f8 AT |
4436 | dsi->mgr_config.lcden_sig_polarity = 0; |
4437 | ||
eea8340a | 4438 | dss_mgr_set_lcd_config(mgr, &dsi->mgr_config); |
d21f43bc | 4439 | |
3de7a1dc | 4440 | return 0; |
7d2572f8 | 4441 | err1: |
dca2b152 | 4442 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) |
1550202d TV |
4443 | dss_mgr_unregister_framedone_handler(mgr, |
4444 | dsi_framedone_irq_callback, dsidev); | |
7d2572f8 | 4445 | err: |
b7dec9b6 | 4446 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); |
7d2572f8 | 4447 | return r; |
3de7a1dc TV |
4448 | } |
4449 | ||
b7dec9b6 TV |
4450 | static void dsi_display_uninit_dispc(struct platform_device *dsidev, |
4451 | struct omap_overlay_manager *mgr) | |
3de7a1dc | 4452 | { |
dca2b152 AT |
4453 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4454 | ||
1550202d TV |
4455 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) |
4456 | dss_mgr_unregister_framedone_handler(mgr, | |
4457 | dsi_framedone_irq_callback, dsidev); | |
b7dec9b6 TV |
4458 | |
4459 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); | |
3de7a1dc TV |
4460 | } |
4461 | ||
5761217a | 4462 | static int dsi_configure_dsi_clocks(struct platform_device *dsidev) |
3de7a1dc | 4463 | { |
a0d269ec | 4464 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4465 | struct dsi_clock_info cinfo; |
4466 | int r; | |
4467 | ||
a0d269ec TV |
4468 | cinfo = dsi->user_dsi_cinfo; |
4469 | ||
b6e695ab | 4470 | r = dsi_calc_clock_rates(dsidev, &cinfo); |
ebf0a3fe VS |
4471 | if (r) { |
4472 | DSSERR("Failed to calc dsi clocks\n"); | |
3de7a1dc | 4473 | return r; |
ebf0a3fe | 4474 | } |
3de7a1dc | 4475 | |
a72b64b9 | 4476 | r = dsi_pll_set_clock_div(dsidev, &cinfo); |
3de7a1dc TV |
4477 | if (r) { |
4478 | DSSERR("Failed to set dsi clocks\n"); | |
4479 | return r; | |
4480 | } | |
4481 | ||
4482 | return 0; | |
4483 | } | |
4484 | ||
5761217a | 4485 | static int dsi_display_init_dsi(struct platform_device *dsidev) |
3de7a1dc | 4486 | { |
11ee9606 | 4487 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4488 | int r; |
4489 | ||
a72b64b9 | 4490 | r = dsi_pll_init(dsidev, true, true); |
3de7a1dc TV |
4491 | if (r) |
4492 | goto err0; | |
4493 | ||
5761217a | 4494 | r = dsi_configure_dsi_clocks(dsidev); |
3de7a1dc TV |
4495 | if (r) |
4496 | goto err1; | |
4497 | ||
4ce9e33c TV |
4498 | dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? |
4499 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : | |
4500 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); | |
3de7a1dc TV |
4501 | |
4502 | DSSDBG("PLL OK\n"); | |
4503 | ||
9e7e9372 | 4504 | r = dsi_cio_init(dsidev); |
3de7a1dc TV |
4505 | if (r) |
4506 | goto err2; | |
4507 | ||
a72b64b9 | 4508 | _dsi_print_reset_status(dsidev); |
3de7a1dc | 4509 | |
9e7e9372 | 4510 | dsi_proto_timings(dsidev); |
5761217a | 4511 | dsi_set_lp_clk_divisor(dsidev); |
3de7a1dc TV |
4512 | |
4513 | if (1) | |
a72b64b9 | 4514 | _dsi_print_reset_status(dsidev); |
3de7a1dc | 4515 | |
5761217a | 4516 | r = dsi_proto_config(dsidev); |
3de7a1dc TV |
4517 | if (r) |
4518 | goto err3; | |
4519 | ||
4520 | /* enable interface */ | |
a72b64b9 AT |
4521 | dsi_vc_enable(dsidev, 0, 1); |
4522 | dsi_vc_enable(dsidev, 1, 1); | |
4523 | dsi_vc_enable(dsidev, 2, 1); | |
4524 | dsi_vc_enable(dsidev, 3, 1); | |
4525 | dsi_if_enable(dsidev, 1); | |
4526 | dsi_force_tx_stop_mode_io(dsidev); | |
3de7a1dc | 4527 | |
3de7a1dc | 4528 | return 0; |
3de7a1dc | 4529 | err3: |
9e7e9372 | 4530 | dsi_cio_uninit(dsidev); |
3de7a1dc | 4531 | err2: |
11ee9606 | 4532 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); |
3de7a1dc | 4533 | err1: |
a72b64b9 | 4534 | dsi_pll_uninit(dsidev, true); |
3de7a1dc TV |
4535 | err0: |
4536 | return r; | |
4537 | } | |
4538 | ||
5761217a | 4539 | static void dsi_display_uninit_dsi(struct platform_device *dsidev, |
22d6d676 | 4540 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4541 | { |
f1da39d9 | 4542 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 4543 | |
f1da39d9 | 4544 | if (enter_ulps && !dsi->ulps_enabled) |
a72b64b9 | 4545 | dsi_enter_ulps(dsidev); |
40885ab3 | 4546 | |
d7370104 | 4547 | /* disable interface */ |
a72b64b9 AT |
4548 | dsi_if_enable(dsidev, 0); |
4549 | dsi_vc_enable(dsidev, 0, 0); | |
4550 | dsi_vc_enable(dsidev, 1, 0); | |
4551 | dsi_vc_enable(dsidev, 2, 0); | |
4552 | dsi_vc_enable(dsidev, 3, 0); | |
d7370104 | 4553 | |
11ee9606 | 4554 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); |
9e7e9372 | 4555 | dsi_cio_uninit(dsidev); |
a72b64b9 | 4556 | dsi_pll_uninit(dsidev, disconnect_lanes); |
3de7a1dc TV |
4557 | } |
4558 | ||
5cfc1c3c | 4559 | static int dsi_display_enable(struct omap_dss_device *dssdev) |
3de7a1dc | 4560 | { |
a72b64b9 | 4561 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4562 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4563 | int r = 0; |
4564 | ||
4565 | DSSDBG("dsi_display_enable\n"); | |
4566 | ||
a72b64b9 | 4567 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
37ac60e4 | 4568 | |
f1da39d9 | 4569 | mutex_lock(&dsi->lock); |
3de7a1dc | 4570 | |
4fbafaf3 | 4571 | r = dsi_runtime_get(dsidev); |
3de7a1dc | 4572 | if (r) |
4fbafaf3 TV |
4573 | goto err_get_dsi; |
4574 | ||
4575 | dsi_enable_pll_clock(dsidev, 1); | |
3de7a1dc | 4576 | |
4fbafaf3 | 4577 | _dsi_initialize_irq(dsidev); |
3de7a1dc | 4578 | |
5761217a | 4579 | r = dsi_display_init_dsi(dsidev); |
3de7a1dc | 4580 | if (r) |
4fbafaf3 | 4581 | goto err_init_dsi; |
3de7a1dc | 4582 | |
f1da39d9 | 4583 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4584 | |
4585 | return 0; | |
4586 | ||
4fbafaf3 | 4587 | err_init_dsi: |
a72b64b9 | 4588 | dsi_enable_pll_clock(dsidev, 0); |
4fbafaf3 TV |
4589 | dsi_runtime_put(dsidev); |
4590 | err_get_dsi: | |
f1da39d9 | 4591 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4592 | DSSDBG("dsi_display_enable FAILED\n"); |
4593 | return r; | |
4594 | } | |
4595 | ||
5cfc1c3c | 4596 | static void dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 4597 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4598 | { |
a72b64b9 | 4599 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4600 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 4601 | |
3de7a1dc TV |
4602 | DSSDBG("dsi_display_disable\n"); |
4603 | ||
a72b64b9 | 4604 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 4605 | |
f1da39d9 | 4606 | mutex_lock(&dsi->lock); |
3de7a1dc | 4607 | |
15ffa1da TV |
4608 | dsi_sync_vc(dsidev, 0); |
4609 | dsi_sync_vc(dsidev, 1); | |
4610 | dsi_sync_vc(dsidev, 2); | |
4611 | dsi_sync_vc(dsidev, 3); | |
4612 | ||
5761217a | 4613 | dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); |
3de7a1dc | 4614 | |
4fbafaf3 | 4615 | dsi_runtime_put(dsidev); |
a72b64b9 | 4616 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc | 4617 | |
f1da39d9 | 4618 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4619 | } |
4620 | ||
5cfc1c3c | 4621 | static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
3de7a1dc | 4622 | { |
f1da39d9 AT |
4623 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4624 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4625 | ||
4626 | dsi->te_enabled = enable; | |
225b650d | 4627 | return 0; |
3de7a1dc TV |
4628 | } |
4629 | ||
f1e0001f TV |
4630 | #ifdef PRINT_VERBOSE_VM_TIMINGS |
4631 | static void print_dsi_vm(const char *str, | |
4632 | const struct omap_dss_dsi_videomode_timings *t) | |
4633 | { | |
4634 | unsigned long byteclk = t->hsclk / 4; | |
4635 | int bl, wc, pps, tot; | |
4636 | ||
4637 | wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); | |
4638 | pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ | |
4639 | bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; | |
4640 | tot = bl + pps; | |
4641 | ||
4642 | #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) | |
4643 | ||
4644 | pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " | |
4645 | "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", | |
4646 | str, | |
4647 | byteclk, | |
4648 | t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, | |
4649 | bl, pps, tot, | |
4650 | TO_DSI_T(t->hss), | |
4651 | TO_DSI_T(t->hsa), | |
4652 | TO_DSI_T(t->hse), | |
4653 | TO_DSI_T(t->hbp), | |
4654 | TO_DSI_T(pps), | |
4655 | TO_DSI_T(t->hfp), | |
4656 | ||
4657 | TO_DSI_T(bl), | |
4658 | TO_DSI_T(pps), | |
4659 | ||
4660 | TO_DSI_T(tot)); | |
4661 | #undef TO_DSI_T | |
4662 | } | |
4663 | ||
4664 | static void print_dispc_vm(const char *str, const struct omap_video_timings *t) | |
4665 | { | |
d8d78941 | 4666 | unsigned long pck = t->pixelclock; |
f1e0001f TV |
4667 | int hact, bl, tot; |
4668 | ||
4669 | hact = t->x_res; | |
4670 | bl = t->hsw + t->hbp + t->hfp; | |
4671 | tot = hact + bl; | |
4672 | ||
4673 | #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) | |
4674 | ||
4675 | pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " | |
4676 | "%u/%u/%u/%u = %u + %u = %u\n", | |
4677 | str, | |
4678 | pck, | |
4679 | t->hsw, t->hbp, hact, t->hfp, | |
4680 | bl, hact, tot, | |
4681 | TO_DISPC_T(t->hsw), | |
4682 | TO_DISPC_T(t->hbp), | |
4683 | TO_DISPC_T(hact), | |
4684 | TO_DISPC_T(t->hfp), | |
4685 | TO_DISPC_T(bl), | |
4686 | TO_DISPC_T(hact), | |
4687 | TO_DISPC_T(tot)); | |
4688 | #undef TO_DISPC_T | |
4689 | } | |
4690 | ||
4691 | /* note: this is not quite accurate */ | |
4692 | static void print_dsi_dispc_vm(const char *str, | |
4693 | const struct omap_dss_dsi_videomode_timings *t) | |
4694 | { | |
4695 | struct omap_video_timings vm = { 0 }; | |
4696 | unsigned long byteclk = t->hsclk / 4; | |
4697 | unsigned long pck; | |
4698 | u64 dsi_tput; | |
4699 | int dsi_hact, dsi_htot; | |
4700 | ||
4701 | dsi_tput = (u64)byteclk * t->ndl * 8; | |
4702 | pck = (u32)div64_u64(dsi_tput, t->bitspp); | |
4703 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); | |
4704 | dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; | |
4705 | ||
d8d78941 | 4706 | vm.pixelclock = pck; |
f1e0001f TV |
4707 | vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); |
4708 | vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); | |
4709 | vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); | |
4710 | vm.x_res = t->hact; | |
4711 | ||
4712 | print_dispc_vm(str, &vm); | |
4713 | } | |
4714 | #endif /* PRINT_VERBOSE_VM_TIMINGS */ | |
4715 | ||
4716 | static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
4717 | unsigned long pck, void *data) | |
e67458a8 | 4718 | { |
f1e0001f TV |
4719 | struct dsi_clk_calc_ctx *ctx = data; |
4720 | struct omap_video_timings *t = &ctx->dispc_vm; | |
e67458a8 | 4721 | |
f1e0001f TV |
4722 | ctx->dispc_cinfo.lck_div = lckd; |
4723 | ctx->dispc_cinfo.pck_div = pckd; | |
4724 | ctx->dispc_cinfo.lck = lck; | |
4725 | ctx->dispc_cinfo.pck = pck; | |
e67458a8 | 4726 | |
f1e0001f | 4727 | *t = *ctx->config->timings; |
d8d78941 | 4728 | t->pixelclock = pck; |
f1e0001f TV |
4729 | t->x_res = ctx->config->timings->x_res; |
4730 | t->y_res = ctx->config->timings->y_res; | |
4731 | t->hsw = t->hfp = t->hbp = t->vsw = 1; | |
4732 | t->vfp = t->vbp = 0; | |
e67458a8 | 4733 | |
f1e0001f | 4734 | return true; |
e67458a8 | 4735 | } |
e67458a8 | 4736 | |
f1e0001f TV |
4737 | static bool dsi_cm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc, |
4738 | void *data) | |
e352574d | 4739 | { |
f1e0001f | 4740 | struct dsi_clk_calc_ctx *ctx = data; |
e352574d | 4741 | |
f1e0001f TV |
4742 | ctx->dsi_cinfo.regm_dispc = regm_dispc; |
4743 | ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc; | |
e352574d | 4744 | |
f1e0001f TV |
4745 | return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, |
4746 | dsi_cm_calc_dispc_cb, ctx); | |
4747 | } | |
e352574d | 4748 | |
f1e0001f TV |
4749 | static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint, |
4750 | unsigned long pll, void *data) | |
4751 | { | |
4752 | struct dsi_clk_calc_ctx *ctx = data; | |
4753 | ||
4754 | ctx->dsi_cinfo.regn = regn; | |
4755 | ctx->dsi_cinfo.regm = regm; | |
4756 | ctx->dsi_cinfo.fint = fint; | |
4757 | ctx->dsi_cinfo.clkin4ddr = pll; | |
4758 | ||
4759 | return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min, | |
4760 | dsi_cm_calc_hsdiv_cb, ctx); | |
e352574d | 4761 | } |
e352574d | 4762 | |
f1e0001f TV |
4763 | static bool dsi_cm_calc(struct dsi_data *dsi, |
4764 | const struct omap_dss_dsi_config *cfg, | |
4765 | struct dsi_clk_calc_ctx *ctx) | |
02c3960b | 4766 | { |
f1e0001f TV |
4767 | unsigned long clkin; |
4768 | int bitspp, ndl; | |
4769 | unsigned long pll_min, pll_max; | |
4770 | unsigned long pck, txbyteclk; | |
02c3960b | 4771 | |
f1e0001f TV |
4772 | clkin = clk_get_rate(dsi->sys_clk); |
4773 | bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
4774 | ndl = dsi->num_lanes_used - 1; | |
4775 | ||
4776 | /* | |
4777 | * Here we should calculate minimum txbyteclk to be able to send the | |
4778 | * frame in time, and also to handle TE. That's not very simple, though, | |
4779 | * especially as we go to LP between each pixel packet due to HW | |
4780 | * "feature". So let's just estimate very roughly and multiply by 1.5. | |
4781 | */ | |
d8d78941 | 4782 | pck = cfg->timings->pixelclock; |
f1e0001f TV |
4783 | pck = pck * 3 / 2; |
4784 | txbyteclk = pck * bitspp / 8 / ndl; | |
02c3960b | 4785 | |
f1e0001f TV |
4786 | memset(ctx, 0, sizeof(*ctx)); |
4787 | ctx->dsidev = dsi->pdev; | |
4788 | ctx->config = cfg; | |
4789 | ctx->req_pck_min = pck; | |
4790 | ctx->req_pck_nom = pck; | |
4791 | ctx->req_pck_max = pck * 3 / 2; | |
4792 | ctx->dsi_cinfo.clkin = clkin; | |
02c3960b | 4793 | |
f1e0001f TV |
4794 | pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); |
4795 | pll_max = cfg->hs_clk_max * 4; | |
4796 | ||
4797 | return dsi_pll_calc(dsi->pdev, clkin, | |
4798 | pll_min, pll_max, | |
4799 | dsi_cm_calc_pll_cb, ctx); | |
02c3960b | 4800 | } |
02c3960b | 4801 | |
f1e0001f | 4802 | static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) |
dca2b152 | 4803 | { |
f1e0001f TV |
4804 | struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); |
4805 | const struct omap_dss_dsi_config *cfg = ctx->config; | |
4806 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
4807 | int ndl = dsi->num_lanes_used - 1; | |
4808 | unsigned long hsclk = ctx->dsi_cinfo.clkin4ddr / 4; | |
4809 | unsigned long byteclk = hsclk / 4; | |
dca2b152 | 4810 | |
f1e0001f TV |
4811 | unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; |
4812 | int xres; | |
4813 | int panel_htot, panel_hbl; /* pixels */ | |
4814 | int dispc_htot, dispc_hbl; /* pixels */ | |
4815 | int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ | |
4816 | int hfp, hsa, hbp; | |
4817 | const struct omap_video_timings *req_vm; | |
4818 | struct omap_video_timings *dispc_vm; | |
4819 | struct omap_dss_dsi_videomode_timings *dsi_vm; | |
4820 | u64 dsi_tput, dispc_tput; | |
dca2b152 | 4821 | |
f1e0001f | 4822 | dsi_tput = (u64)byteclk * ndl * 8; |
dca2b152 | 4823 | |
f1e0001f TV |
4824 | req_vm = cfg->timings; |
4825 | req_pck_min = ctx->req_pck_min; | |
4826 | req_pck_max = ctx->req_pck_max; | |
4827 | req_pck_nom = ctx->req_pck_nom; | |
4828 | ||
4829 | dispc_pck = ctx->dispc_cinfo.pck; | |
4830 | dispc_tput = (u64)dispc_pck * bitspp; | |
4831 | ||
4832 | xres = req_vm->x_res; | |
4833 | ||
4834 | panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw; | |
4835 | panel_htot = xres + panel_hbl; | |
4836 | ||
4837 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); | |
4838 | ||
4839 | /* | |
4840 | * When there are no line buffers, DISPC and DSI must have the | |
4841 | * same tput. Otherwise DISPC tput needs to be higher than DSI's. | |
4842 | */ | |
4843 | if (dsi->line_buffer_size < xres * bitspp / 8) { | |
4844 | if (dispc_tput != dsi_tput) | |
4845 | return false; | |
4846 | } else { | |
4847 | if (dispc_tput < dsi_tput) | |
4848 | return false; | |
4849 | } | |
4850 | ||
4851 | /* DSI tput must be over the min requirement */ | |
4852 | if (dsi_tput < (u64)bitspp * req_pck_min) | |
4853 | return false; | |
4854 | ||
4855 | /* When non-burst mode, DSI tput must be below max requirement. */ | |
4856 | if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { | |
4857 | if (dsi_tput > (u64)bitspp * req_pck_max) | |
4858 | return false; | |
4859 | } | |
4860 | ||
4861 | hss = DIV_ROUND_UP(4, ndl); | |
4862 | ||
4863 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { | |
4864 | if (ndl == 3 && req_vm->hsw == 0) | |
4865 | hse = 1; | |
4866 | else | |
4867 | hse = DIV_ROUND_UP(4, ndl); | |
4868 | } else { | |
4869 | hse = 0; | |
4870 | } | |
4871 | ||
4872 | /* DSI htot to match the panel's nominal pck */ | |
4873 | dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); | |
4874 | ||
4875 | /* fail if there would be no time for blanking */ | |
4876 | if (dsi_htot < hss + hse + dsi_hact) | |
4877 | return false; | |
4878 | ||
4879 | /* total DSI blanking needed to achieve panel's TL */ | |
4880 | dsi_hbl = dsi_htot - dsi_hact; | |
4881 | ||
4882 | /* DISPC htot to match the DSI TL */ | |
4883 | dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); | |
4884 | ||
4885 | /* verify that the DSI and DISPC TLs are the same */ | |
4886 | if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) | |
4887 | return false; | |
4888 | ||
4889 | dispc_hbl = dispc_htot - xres; | |
4890 | ||
4891 | /* setup DSI videomode */ | |
4892 | ||
4893 | dsi_vm = &ctx->dsi_vm; | |
4894 | memset(dsi_vm, 0, sizeof(*dsi_vm)); | |
4895 | ||
4896 | dsi_vm->hsclk = hsclk; | |
4897 | ||
4898 | dsi_vm->ndl = ndl; | |
4899 | dsi_vm->bitspp = bitspp; | |
4900 | ||
4901 | if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { | |
4902 | hsa = 0; | |
4903 | } else if (ndl == 3 && req_vm->hsw == 0) { | |
4904 | hsa = 0; | |
4905 | } else { | |
4906 | hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom); | |
4907 | hsa = max(hsa - hse, 1); | |
4908 | } | |
4909 | ||
4910 | hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); | |
4911 | hbp = max(hbp, 1); | |
4912 | ||
4913 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4914 | if (hfp < 1) { | |
4915 | int t; | |
4916 | /* we need to take cycles from hbp */ | |
4917 | ||
4918 | t = 1 - hfp; | |
4919 | hbp = max(hbp - t, 1); | |
4920 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4921 | ||
4922 | if (hfp < 1 && hsa > 0) { | |
4923 | /* we need to take cycles from hsa */ | |
4924 | t = 1 - hfp; | |
4925 | hsa = max(hsa - t, 1); | |
4926 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4927 | } | |
4928 | } | |
4929 | ||
4930 | if (hfp < 1) | |
4931 | return false; | |
4932 | ||
4933 | dsi_vm->hss = hss; | |
4934 | dsi_vm->hsa = hsa; | |
4935 | dsi_vm->hse = hse; | |
4936 | dsi_vm->hbp = hbp; | |
4937 | dsi_vm->hact = xres; | |
4938 | dsi_vm->hfp = hfp; | |
4939 | ||
4940 | dsi_vm->vsa = req_vm->vsw; | |
4941 | dsi_vm->vbp = req_vm->vbp; | |
4942 | dsi_vm->vact = req_vm->y_res; | |
4943 | dsi_vm->vfp = req_vm->vfp; | |
4944 | ||
4945 | dsi_vm->trans_mode = cfg->trans_mode; | |
4946 | ||
4947 | dsi_vm->blanking_mode = 0; | |
4948 | dsi_vm->hsa_blanking_mode = 1; | |
4949 | dsi_vm->hfp_blanking_mode = 1; | |
4950 | dsi_vm->hbp_blanking_mode = 1; | |
4951 | ||
4952 | dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; | |
4953 | dsi_vm->window_sync = 4; | |
4954 | ||
4955 | /* setup DISPC videomode */ | |
4956 | ||
4957 | dispc_vm = &ctx->dispc_vm; | |
4958 | *dispc_vm = *req_vm; | |
d8d78941 | 4959 | dispc_vm->pixelclock = dispc_pck; |
f1e0001f TV |
4960 | |
4961 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { | |
4962 | hsa = div64_u64((u64)req_vm->hsw * dispc_pck, | |
4963 | req_pck_nom); | |
4964 | hsa = max(hsa, 1); | |
4965 | } else { | |
4966 | hsa = 1; | |
4967 | } | |
4968 | ||
4969 | hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); | |
4970 | hbp = max(hbp, 1); | |
4971 | ||
4972 | hfp = dispc_hbl - hsa - hbp; | |
4973 | if (hfp < 1) { | |
4974 | int t; | |
4975 | /* we need to take cycles from hbp */ | |
4976 | ||
4977 | t = 1 - hfp; | |
4978 | hbp = max(hbp - t, 1); | |
4979 | hfp = dispc_hbl - hsa - hbp; | |
4980 | ||
4981 | if (hfp < 1) { | |
4982 | /* we need to take cycles from hsa */ | |
4983 | t = 1 - hfp; | |
4984 | hsa = max(hsa - t, 1); | |
4985 | hfp = dispc_hbl - hsa - hbp; | |
4986 | } | |
4987 | } | |
4988 | ||
4989 | if (hfp < 1) | |
4990 | return false; | |
4991 | ||
4992 | dispc_vm->hfp = hfp; | |
4993 | dispc_vm->hsw = hsa; | |
4994 | dispc_vm->hbp = hbp; | |
4995 | ||
4996 | return true; | |
4997 | } | |
4998 | ||
4999 | ||
5000 | static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
5001 | unsigned long pck, void *data) | |
5002 | { | |
5003 | struct dsi_clk_calc_ctx *ctx = data; | |
5004 | ||
5005 | ctx->dispc_cinfo.lck_div = lckd; | |
5006 | ctx->dispc_cinfo.pck_div = pckd; | |
5007 | ctx->dispc_cinfo.lck = lck; | |
5008 | ctx->dispc_cinfo.pck = pck; | |
5009 | ||
5010 | if (dsi_vm_calc_blanking(ctx) == false) | |
5011 | return false; | |
5012 | ||
5013 | #ifdef PRINT_VERBOSE_VM_TIMINGS | |
5014 | print_dispc_vm("dispc", &ctx->dispc_vm); | |
5015 | print_dsi_vm("dsi ", &ctx->dsi_vm); | |
5016 | print_dispc_vm("req ", ctx->config->timings); | |
5017 | print_dsi_dispc_vm("act ", &ctx->dsi_vm); | |
5018 | #endif | |
5019 | ||
5020 | return true; | |
5021 | } | |
5022 | ||
5023 | static bool dsi_vm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc, | |
5024 | void *data) | |
5025 | { | |
5026 | struct dsi_clk_calc_ctx *ctx = data; | |
5027 | unsigned long pck_max; | |
5028 | ||
5029 | ctx->dsi_cinfo.regm_dispc = regm_dispc; | |
5030 | ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc; | |
5031 | ||
5032 | /* | |
5033 | * In burst mode we can let the dispc pck be arbitrarily high, but it | |
5034 | * limits our scaling abilities. So for now, don't aim too high. | |
5035 | */ | |
5036 | ||
5037 | if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) | |
5038 | pck_max = ctx->req_pck_max + 10000000; | |
5039 | else | |
5040 | pck_max = ctx->req_pck_max; | |
5041 | ||
5042 | return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, | |
5043 | dsi_vm_calc_dispc_cb, ctx); | |
5044 | } | |
5045 | ||
5046 | static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint, | |
5047 | unsigned long pll, void *data) | |
5048 | { | |
5049 | struct dsi_clk_calc_ctx *ctx = data; | |
5050 | ||
5051 | ctx->dsi_cinfo.regn = regn; | |
5052 | ctx->dsi_cinfo.regm = regm; | |
5053 | ctx->dsi_cinfo.fint = fint; | |
5054 | ctx->dsi_cinfo.clkin4ddr = pll; | |
5055 | ||
5056 | return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min, | |
5057 | dsi_vm_calc_hsdiv_cb, ctx); | |
5058 | } | |
5059 | ||
5060 | static bool dsi_vm_calc(struct dsi_data *dsi, | |
5061 | const struct omap_dss_dsi_config *cfg, | |
5062 | struct dsi_clk_calc_ctx *ctx) | |
5063 | { | |
5064 | const struct omap_video_timings *t = cfg->timings; | |
5065 | unsigned long clkin; | |
5066 | unsigned long pll_min; | |
5067 | unsigned long pll_max; | |
5068 | int ndl = dsi->num_lanes_used - 1; | |
5069 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
5070 | unsigned long byteclk_min; | |
5071 | ||
5072 | clkin = clk_get_rate(dsi->sys_clk); | |
5073 | ||
5074 | memset(ctx, 0, sizeof(*ctx)); | |
5075 | ctx->dsidev = dsi->pdev; | |
5076 | ctx->config = cfg; | |
5077 | ||
5078 | ctx->dsi_cinfo.clkin = clkin; | |
5079 | ||
5080 | /* these limits should come from the panel driver */ | |
d8d78941 TV |
5081 | ctx->req_pck_min = t->pixelclock - 1000; |
5082 | ctx->req_pck_nom = t->pixelclock; | |
5083 | ctx->req_pck_max = t->pixelclock + 1000; | |
f1e0001f TV |
5084 | |
5085 | byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); | |
5086 | pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); | |
5087 | ||
5088 | if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { | |
5089 | pll_max = cfg->hs_clk_max * 4; | |
5090 | } else { | |
5091 | unsigned long byteclk_max; | |
5092 | byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, | |
5093 | ndl * 8); | |
5094 | ||
5095 | pll_max = byteclk_max * 4 * 4; | |
5096 | } | |
5097 | ||
5098 | return dsi_pll_calc(dsi->pdev, clkin, | |
5099 | pll_min, pll_max, | |
5100 | dsi_vm_calc_pll_cb, ctx); | |
dca2b152 | 5101 | } |
dca2b152 | 5102 | |
5cfc1c3c | 5103 | static int dsi_set_config(struct omap_dss_device *dssdev, |
777f05cc | 5104 | const struct omap_dss_dsi_config *config) |
0b3ffe39 AT |
5105 | { |
5106 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
5107 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
f1e0001f TV |
5108 | struct dsi_clk_calc_ctx ctx; |
5109 | bool ok; | |
5110 | int r; | |
0b3ffe39 AT |
5111 | |
5112 | mutex_lock(&dsi->lock); | |
5113 | ||
777f05cc TV |
5114 | dsi->pix_fmt = config->pixel_format; |
5115 | dsi->mode = config->mode; | |
e352574d | 5116 | |
f1e0001f TV |
5117 | if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) |
5118 | ok = dsi_vm_calc(dsi, config, &ctx); | |
5119 | else | |
5120 | ok = dsi_cm_calc(dsi, config, &ctx); | |
5121 | ||
5122 | if (!ok) { | |
5123 | DSSERR("failed to find suitable DSI clock settings\n"); | |
5124 | r = -EINVAL; | |
5125 | goto err; | |
5126 | } | |
5127 | ||
5128 | dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); | |
5129 | ||
5130 | r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min, | |
5131 | config->lp_clk_max); | |
5132 | if (r) { | |
5133 | DSSERR("failed to find suitable DSI LP clock settings\n"); | |
5134 | goto err; | |
5135 | } | |
5136 | ||
5137 | dsi->user_dsi_cinfo = ctx.dsi_cinfo; | |
5138 | dsi->user_dispc_cinfo = ctx.dispc_cinfo; | |
5139 | ||
5140 | dsi->timings = ctx.dispc_vm; | |
5141 | dsi->vm_timings = ctx.dsi_vm; | |
0b3ffe39 AT |
5142 | |
5143 | mutex_unlock(&dsi->lock); | |
e352574d | 5144 | |
777f05cc | 5145 | return 0; |
f1e0001f TV |
5146 | err: |
5147 | mutex_unlock(&dsi->lock); | |
5148 | ||
5149 | return r; | |
0b3ffe39 | 5150 | } |
0b3ffe39 | 5151 | |
2eea5ae6 TV |
5152 | /* |
5153 | * Return a hardcoded channel for the DSI output. This should work for | |
5154 | * current use cases, but this can be later expanded to either resolve | |
5155 | * the channel in some more dynamic manner, or get the channel as a user | |
5156 | * parameter. | |
5157 | */ | |
5158 | static enum omap_channel dsi_get_channel(int module_id) | |
5159 | { | |
5160 | switch (omapdss_get_version()) { | |
5161 | case OMAPDSS_VER_OMAP24xx: | |
d6279d4a | 5162 | case OMAPDSS_VER_AM43xx: |
2eea5ae6 TV |
5163 | DSSWARN("DSI not supported\n"); |
5164 | return OMAP_DSS_CHANNEL_LCD; | |
5165 | ||
5166 | case OMAPDSS_VER_OMAP34xx_ES1: | |
5167 | case OMAPDSS_VER_OMAP34xx_ES3: | |
5168 | case OMAPDSS_VER_OMAP3630: | |
5169 | case OMAPDSS_VER_AM35xx: | |
5170 | return OMAP_DSS_CHANNEL_LCD; | |
5171 | ||
5172 | case OMAPDSS_VER_OMAP4430_ES1: | |
5173 | case OMAPDSS_VER_OMAP4430_ES2: | |
5174 | case OMAPDSS_VER_OMAP4: | |
5175 | switch (module_id) { | |
5176 | case 0: | |
5177 | return OMAP_DSS_CHANNEL_LCD; | |
5178 | case 1: | |
5179 | return OMAP_DSS_CHANNEL_LCD2; | |
5180 | default: | |
5181 | DSSWARN("unsupported module id\n"); | |
5182 | return OMAP_DSS_CHANNEL_LCD; | |
5183 | } | |
5184 | ||
5185 | case OMAPDSS_VER_OMAP5: | |
5186 | switch (module_id) { | |
5187 | case 0: | |
5188 | return OMAP_DSS_CHANNEL_LCD; | |
5189 | case 1: | |
5190 | return OMAP_DSS_CHANNEL_LCD3; | |
5191 | default: | |
5192 | DSSWARN("unsupported module id\n"); | |
5193 | return OMAP_DSS_CHANNEL_LCD; | |
5194 | } | |
5195 | ||
5196 | default: | |
5197 | DSSWARN("unsupported DSS version\n"); | |
5198 | return OMAP_DSS_CHANNEL_LCD; | |
5199 | } | |
0b3ffe39 | 5200 | } |
0b3ffe39 | 5201 | |
5cfc1c3c | 5202 | static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
5ee3c144 | 5203 | { |
f1da39d9 AT |
5204 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
5205 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5ee3c144 AT |
5206 | int i; |
5207 | ||
f1da39d9 AT |
5208 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
5209 | if (!dsi->vc[i].dssdev) { | |
5210 | dsi->vc[i].dssdev = dssdev; | |
5ee3c144 AT |
5211 | *channel = i; |
5212 | return 0; | |
5213 | } | |
5214 | } | |
5215 | ||
5216 | DSSERR("cannot get VC for display %s", dssdev->name); | |
5217 | return -ENOSPC; | |
5218 | } | |
5ee3c144 | 5219 | |
5cfc1c3c | 5220 | static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) |
5ee3c144 | 5221 | { |
f1da39d9 AT |
5222 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
5223 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5224 | ||
5ee3c144 AT |
5225 | if (vc_id < 0 || vc_id > 3) { |
5226 | DSSERR("VC ID out of range\n"); | |
5227 | return -EINVAL; | |
5228 | } | |
5229 | ||
5230 | if (channel < 0 || channel > 3) { | |
5231 | DSSERR("Virtual Channel out of range\n"); | |
5232 | return -EINVAL; | |
5233 | } | |
5234 | ||
f1da39d9 | 5235 | if (dsi->vc[channel].dssdev != dssdev) { |
5ee3c144 AT |
5236 | DSSERR("Virtual Channel not allocated to display %s\n", |
5237 | dssdev->name); | |
5238 | return -EINVAL; | |
5239 | } | |
5240 | ||
f1da39d9 | 5241 | dsi->vc[channel].vc_id = vc_id; |
5ee3c144 AT |
5242 | |
5243 | return 0; | |
5244 | } | |
5ee3c144 | 5245 | |
5cfc1c3c | 5246 | static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) |
5ee3c144 | 5247 | { |
f1da39d9 AT |
5248 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
5249 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5250 | ||
5ee3c144 | 5251 | if ((channel >= 0 && channel <= 3) && |
f1da39d9 AT |
5252 | dsi->vc[channel].dssdev == dssdev) { |
5253 | dsi->vc[channel].dssdev = NULL; | |
5254 | dsi->vc[channel].vc_id = 0; | |
5ee3c144 AT |
5255 | } |
5256 | } | |
5ee3c144 | 5257 | |
e406f907 | 5258 | |
a72b64b9 | 5259 | static void dsi_calc_clock_param_ranges(struct platform_device *dsidev) |
49641116 | 5260 | { |
f1da39d9 AT |
5261 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5262 | ||
5263 | dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); | |
5264 | dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); | |
5265 | dsi->regm_dispc_max = | |
5266 | dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); | |
5267 | dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); | |
5268 | dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); | |
5269 | dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); | |
5270 | dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); | |
49641116 TA |
5271 | } |
5272 | ||
4fbafaf3 TV |
5273 | static int dsi_get_clocks(struct platform_device *dsidev) |
5274 | { | |
5275 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5276 | struct clk *clk; | |
5277 | ||
5303b3aa | 5278 | clk = devm_clk_get(&dsidev->dev, "fck"); |
4fbafaf3 TV |
5279 | if (IS_ERR(clk)) { |
5280 | DSSERR("can't get fck\n"); | |
5281 | return PTR_ERR(clk); | |
5282 | } | |
5283 | ||
5284 | dsi->dss_clk = clk; | |
5285 | ||
5303b3aa | 5286 | clk = devm_clk_get(&dsidev->dev, "sys_clk"); |
4fbafaf3 TV |
5287 | if (IS_ERR(clk)) { |
5288 | DSSERR("can't get sys_clk\n"); | |
4fbafaf3 TV |
5289 | return PTR_ERR(clk); |
5290 | } | |
5291 | ||
5292 | dsi->sys_clk = clk; | |
5293 | ||
5294 | return 0; | |
5295 | } | |
5296 | ||
deb16df8 TV |
5297 | static int dsi_connect(struct omap_dss_device *dssdev, |
5298 | struct omap_dss_device *dst) | |
5299 | { | |
5300 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
5301 | struct omap_overlay_manager *mgr; | |
5302 | int r; | |
5303 | ||
5304 | r = dsi_regulator_init(dsidev); | |
5305 | if (r) | |
5306 | return r; | |
5307 | ||
5308 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
5309 | if (!mgr) | |
5310 | return -ENODEV; | |
5311 | ||
5312 | r = dss_mgr_connect(mgr, dssdev); | |
5313 | if (r) | |
5314 | return r; | |
5315 | ||
5316 | r = omapdss_output_set_device(dssdev, dst); | |
5317 | if (r) { | |
5318 | DSSERR("failed to connect output to new device: %s\n", | |
5319 | dssdev->name); | |
5320 | dss_mgr_disconnect(mgr, dssdev); | |
5321 | return r; | |
5322 | } | |
5323 | ||
5324 | return 0; | |
5325 | } | |
5326 | ||
5327 | static void dsi_disconnect(struct omap_dss_device *dssdev, | |
5328 | struct omap_dss_device *dst) | |
5329 | { | |
9560dc10 | 5330 | WARN_ON(dst != dssdev->dst); |
deb16df8 | 5331 | |
9560dc10 | 5332 | if (dst != dssdev->dst) |
deb16df8 TV |
5333 | return; |
5334 | ||
5335 | omapdss_output_unset_device(dssdev); | |
5336 | ||
5337 | if (dssdev->manager) | |
5338 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
5339 | } | |
5340 | ||
5341 | static const struct omapdss_dsi_ops dsi_ops = { | |
5342 | .connect = dsi_connect, | |
5343 | .disconnect = dsi_disconnect, | |
5344 | ||
5345 | .bus_lock = dsi_bus_lock, | |
5346 | .bus_unlock = dsi_bus_unlock, | |
5347 | ||
5cfc1c3c TV |
5348 | .enable = dsi_display_enable, |
5349 | .disable = dsi_display_disable, | |
deb16df8 | 5350 | |
5cfc1c3c | 5351 | .enable_hs = dsi_vc_enable_hs, |
deb16df8 | 5352 | |
5cfc1c3c TV |
5353 | .configure_pins = dsi_configure_pins, |
5354 | .set_config = dsi_set_config, | |
deb16df8 TV |
5355 | |
5356 | .enable_video_output = dsi_enable_video_output, | |
5357 | .disable_video_output = dsi_disable_video_output, | |
5358 | ||
5cfc1c3c | 5359 | .update = dsi_update, |
deb16df8 | 5360 | |
5cfc1c3c | 5361 | .enable_te = dsi_enable_te, |
deb16df8 | 5362 | |
5cfc1c3c TV |
5363 | .request_vc = dsi_request_vc, |
5364 | .set_vc_id = dsi_set_vc_id, | |
5365 | .release_vc = dsi_release_vc, | |
deb16df8 TV |
5366 | |
5367 | .dcs_write = dsi_vc_dcs_write, | |
5368 | .dcs_write_nosync = dsi_vc_dcs_write_nosync, | |
5369 | .dcs_read = dsi_vc_dcs_read, | |
5370 | ||
5371 | .gen_write = dsi_vc_generic_write, | |
5372 | .gen_write_nosync = dsi_vc_generic_write_nosync, | |
5373 | .gen_read = dsi_vc_generic_read, | |
5374 | ||
5375 | .bta_sync = dsi_vc_send_bta_sync, | |
5376 | ||
5377 | .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, | |
5378 | }; | |
5379 | ||
ee4a24e2 | 5380 | static void dsi_init_output(struct platform_device *dsidev) |
81b87f51 AT |
5381 | { |
5382 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1f68d9c4 | 5383 | struct omap_dss_device *out = &dsi->output; |
81b87f51 | 5384 | |
1f68d9c4 | 5385 | out->dev = &dsidev->dev; |
81b87f51 AT |
5386 | out->id = dsi->module_id == 0 ? |
5387 | OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; | |
5388 | ||
1f68d9c4 | 5389 | out->output_type = OMAP_DISPLAY_TYPE_DSI; |
7286a08f | 5390 | out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; |
2eea5ae6 | 5391 | out->dispc_channel = dsi_get_channel(dsi->module_id); |
deb16df8 | 5392 | out->ops.dsi = &dsi_ops; |
b7328e14 | 5393 | out->owner = THIS_MODULE; |
81b87f51 | 5394 | |
5d47dbc8 | 5395 | omapdss_register_output(out); |
81b87f51 AT |
5396 | } |
5397 | ||
d1890a68 | 5398 | static void dsi_uninit_output(struct platform_device *dsidev) |
81b87f51 AT |
5399 | { |
5400 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1f68d9c4 | 5401 | struct omap_dss_device *out = &dsi->output; |
81b87f51 | 5402 | |
5d47dbc8 | 5403 | omapdss_unregister_output(out); |
81b87f51 AT |
5404 | } |
5405 | ||
6274a619 TV |
5406 | static int dsi_probe_of(struct platform_device *pdev) |
5407 | { | |
5408 | struct device_node *node = pdev->dev.of_node; | |
5409 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); | |
5410 | struct property *prop; | |
5411 | u32 lane_arr[10]; | |
5412 | int len, num_pins; | |
5413 | int r, i; | |
5414 | struct device_node *ep; | |
5415 | struct omap_dsi_pin_config pin_cfg; | |
5416 | ||
5417 | ep = omapdss_of_get_first_endpoint(node); | |
5418 | if (!ep) | |
5419 | return 0; | |
5420 | ||
5421 | prop = of_find_property(ep, "lanes", &len); | |
5422 | if (prop == NULL) { | |
5423 | dev_err(&pdev->dev, "failed to find lane data\n"); | |
5424 | r = -EINVAL; | |
5425 | goto err; | |
5426 | } | |
5427 | ||
5428 | num_pins = len / sizeof(u32); | |
5429 | ||
5430 | if (num_pins < 4 || num_pins % 2 != 0 || | |
5431 | num_pins > dsi->num_lanes_supported * 2) { | |
5432 | dev_err(&pdev->dev, "bad number of lanes\n"); | |
5433 | r = -EINVAL; | |
5434 | goto err; | |
5435 | } | |
5436 | ||
5437 | r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); | |
5438 | if (r) { | |
5439 | dev_err(&pdev->dev, "failed to read lane data\n"); | |
5440 | goto err; | |
5441 | } | |
5442 | ||
5443 | pin_cfg.num_pins = num_pins; | |
5444 | for (i = 0; i < num_pins; ++i) | |
5445 | pin_cfg.pins[i] = (int)lane_arr[i]; | |
5446 | ||
5447 | r = dsi_configure_pins(&dsi->output, &pin_cfg); | |
5448 | if (r) { | |
5449 | dev_err(&pdev->dev, "failed to configure pins"); | |
5450 | goto err; | |
5451 | } | |
5452 | ||
5453 | of_node_put(ep); | |
5454 | ||
5455 | return 0; | |
5456 | ||
5457 | err: | |
5458 | of_node_put(ep); | |
5459 | return r; | |
5460 | } | |
5461 | ||
b98482ed | 5462 | /* DSI1 HW IP initialisation */ |
ee4a24e2 | 5463 | static int omap_dsihw_probe(struct platform_device *dsidev) |
3de7a1dc TV |
5464 | { |
5465 | u32 rev; | |
11ee9606 | 5466 | int r, i; |
f1da39d9 | 5467 | struct dsi_data *dsi; |
6274a619 | 5468 | struct resource *dsi_mem; |
68104467 TV |
5469 | struct resource *res; |
5470 | struct resource temp_res; | |
f1da39d9 | 5471 | |
6e2a14d2 | 5472 | dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); |
cd3b3449 TV |
5473 | if (!dsi) |
5474 | return -ENOMEM; | |
3de7a1dc | 5475 | |
f1da39d9 | 5476 | dsi->pdev = dsidev; |
f1da39d9 | 5477 | dev_set_drvdata(&dsidev->dev, dsi); |
a72b64b9 | 5478 | |
f1da39d9 AT |
5479 | spin_lock_init(&dsi->irq_lock); |
5480 | spin_lock_init(&dsi->errors_lock); | |
5481 | dsi->errors = 0; | |
3de7a1dc | 5482 | |
dfc0fd8d | 5483 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
f1da39d9 AT |
5484 | spin_lock_init(&dsi->irq_stats_lock); |
5485 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d TV |
5486 | #endif |
5487 | ||
f1da39d9 AT |
5488 | mutex_init(&dsi->lock); |
5489 | sema_init(&dsi->bus_lock, 1); | |
3de7a1dc | 5490 | |
203b42f7 TH |
5491 | INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, |
5492 | dsi_framedone_timeout_work_callback); | |
18946f62 | 5493 | |
3de7a1dc | 5494 | #ifdef DSI_CATCH_MISSING_TE |
f1da39d9 AT |
5495 | init_timer(&dsi->te_timer); |
5496 | dsi->te_timer.function = dsi_te_timeout; | |
5497 | dsi->te_timer.data = 0; | |
3de7a1dc | 5498 | #endif |
68104467 TV |
5499 | |
5500 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); | |
5501 | if (!res) { | |
5502 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | |
5503 | if (!res) { | |
5504 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
5505 | return -EINVAL; | |
5506 | } | |
5507 | ||
5508 | temp_res.start = res->start; | |
5509 | temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; | |
5510 | res = &temp_res; | |
5511 | } | |
5512 | ||
6274a619 TV |
5513 | dsi_mem = res; |
5514 | ||
68104467 TV |
5515 | dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, |
5516 | resource_size(res)); | |
5517 | if (!dsi->proto_base) { | |
5518 | DSSERR("can't ioremap DSI protocol engine\n"); | |
5519 | return -ENOMEM; | |
5520 | } | |
5521 | ||
5522 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); | |
5523 | if (!res) { | |
5524 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | |
5525 | if (!res) { | |
5526 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
5527 | return -EINVAL; | |
5528 | } | |
5529 | ||
5530 | temp_res.start = res->start + DSI_PHY_OFFSET; | |
5531 | temp_res.end = temp_res.start + DSI_PHY_SZ - 1; | |
5532 | res = &temp_res; | |
5533 | } | |
5534 | ||
5535 | dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, | |
5536 | resource_size(res)); | |
5537 | if (!dsi->proto_base) { | |
5538 | DSSERR("can't ioremap DSI PHY\n"); | |
5539 | return -ENOMEM; | |
5540 | } | |
5541 | ||
5542 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); | |
5543 | if (!res) { | |
5544 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | |
5545 | if (!res) { | |
5546 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
5547 | return -EINVAL; | |
5548 | } | |
5549 | ||
5550 | temp_res.start = res->start + DSI_PLL_OFFSET; | |
5551 | temp_res.end = temp_res.start + DSI_PLL_SZ - 1; | |
5552 | res = &temp_res; | |
ea9da36a | 5553 | } |
cd3b3449 | 5554 | |
68104467 TV |
5555 | dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, |
5556 | resource_size(res)); | |
5557 | if (!dsi->proto_base) { | |
5558 | DSSERR("can't ioremap DSI PLL\n"); | |
cd3b3449 | 5559 | return -ENOMEM; |
3de7a1dc | 5560 | } |
cd3b3449 | 5561 | |
f1da39d9 AT |
5562 | dsi->irq = platform_get_irq(dsi->pdev, 0); |
5563 | if (dsi->irq < 0) { | |
affe360d | 5564 | DSSERR("platform_get_irq failed\n"); |
cd3b3449 | 5565 | return -ENODEV; |
affe360d | 5566 | } |
5567 | ||
6e2a14d2 JL |
5568 | r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, |
5569 | IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); | |
affe360d | 5570 | if (r < 0) { |
5571 | DSSERR("request_irq failed\n"); | |
cd3b3449 | 5572 | return r; |
affe360d | 5573 | } |
3de7a1dc | 5574 | |
6274a619 TV |
5575 | if (dsidev->dev.of_node) { |
5576 | const struct of_device_id *match; | |
5577 | const struct dsi_module_id_data *d; | |
5578 | ||
5579 | match = of_match_node(dsi_of_match, dsidev->dev.of_node); | |
5580 | if (!match) { | |
5581 | DSSERR("unsupported DSI module\n"); | |
5582 | return -ENODEV; | |
5583 | } | |
5584 | ||
5585 | d = match->data; | |
5586 | ||
5587 | while (d->address != 0 && d->address != dsi_mem->start) | |
5588 | d++; | |
5589 | ||
5590 | if (d->address == 0) { | |
5591 | DSSERR("unsupported DSI module\n"); | |
5592 | return -ENODEV; | |
5593 | } | |
5594 | ||
5595 | dsi->module_id = d->id; | |
5596 | } else { | |
5597 | dsi->module_id = dsidev->id; | |
5598 | } | |
5599 | ||
5ee3c144 | 5600 | /* DSI VCs initialization */ |
f1da39d9 | 5601 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
d6049144 | 5602 | dsi->vc[i].source = DSI_VC_SOURCE_L4; |
f1da39d9 AT |
5603 | dsi->vc[i].dssdev = NULL; |
5604 | dsi->vc[i].vc_id = 0; | |
5ee3c144 AT |
5605 | } |
5606 | ||
a72b64b9 | 5607 | dsi_calc_clock_param_ranges(dsidev); |
49641116 | 5608 | |
cd3b3449 TV |
5609 | r = dsi_get_clocks(dsidev); |
5610 | if (r) | |
5611 | return r; | |
5612 | ||
5613 | pm_runtime_enable(&dsidev->dev); | |
5614 | ||
4fbafaf3 TV |
5615 | r = dsi_runtime_get(dsidev); |
5616 | if (r) | |
cd3b3449 | 5617 | goto err_runtime_get; |
3de7a1dc | 5618 | |
a72b64b9 AT |
5619 | rev = dsi_read_reg(dsidev, DSI_REVISION); |
5620 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", | |
3de7a1dc TV |
5621 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
5622 | ||
d9820850 TV |
5623 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number |
5624 | * of data to 3 by default */ | |
5625 | if (dss_has_feature(FEAT_DSI_GNQ)) | |
5626 | /* NB_DATA_LANES */ | |
5627 | dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); | |
5628 | else | |
5629 | dsi->num_lanes_supported = 3; | |
75d7247c | 5630 | |
99322577 TV |
5631 | dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); |
5632 | ||
81b87f51 AT |
5633 | dsi_init_output(dsidev); |
5634 | ||
6274a619 TV |
5635 | if (dsidev->dev.of_node) { |
5636 | r = dsi_probe_of(dsidev); | |
5637 | if (r) { | |
5638 | DSSERR("Invalid DSI DT data\n"); | |
5639 | goto err_probe_of; | |
5640 | } | |
5641 | ||
5642 | r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, | |
5643 | &dsidev->dev); | |
5644 | if (r) | |
5645 | DSSERR("Failed to populate DSI child devices: %d\n", r); | |
5646 | } | |
5647 | ||
4fbafaf3 | 5648 | dsi_runtime_put(dsidev); |
3de7a1dc | 5649 | |
11ee9606 | 5650 | if (dsi->module_id == 0) |
e40402cf | 5651 | dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); |
11ee9606 | 5652 | else if (dsi->module_id == 1) |
e40402cf TV |
5653 | dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); |
5654 | ||
5655 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
11ee9606 | 5656 | if (dsi->module_id == 0) |
e40402cf | 5657 | dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); |
11ee9606 | 5658 | else if (dsi->module_id == 1) |
e40402cf TV |
5659 | dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); |
5660 | #endif | |
6274a619 | 5661 | |
3de7a1dc | 5662 | return 0; |
4fbafaf3 | 5663 | |
6274a619 TV |
5664 | err_probe_of: |
5665 | dsi_uninit_output(dsidev); | |
5666 | dsi_runtime_put(dsidev); | |
5667 | ||
cd3b3449 | 5668 | err_runtime_get: |
4fbafaf3 | 5669 | pm_runtime_disable(&dsidev->dev); |
3de7a1dc TV |
5670 | return r; |
5671 | } | |
5672 | ||
6e7e8f06 | 5673 | static int __exit omap_dsihw_remove(struct platform_device *dsidev) |
3de7a1dc | 5674 | { |
f1da39d9 AT |
5675 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5676 | ||
e4e42b8a | 5677 | of_platform_depopulate(&dsidev->dev); |
6274a619 | 5678 | |
b98482ed TV |
5679 | WARN_ON(dsi->scp_clk_refcount > 0); |
5680 | ||
81b87f51 AT |
5681 | dsi_uninit_output(dsidev); |
5682 | ||
4fbafaf3 TV |
5683 | pm_runtime_disable(&dsidev->dev); |
5684 | ||
b2541c40 TV |
5685 | if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { |
5686 | regulator_disable(dsi->vdds_dsi_reg); | |
5687 | dsi->vdds_dsi_enabled = false; | |
c8aac01b SG |
5688 | } |
5689 | ||
c8aac01b SG |
5690 | return 0; |
5691 | } | |
5692 | ||
4fbafaf3 TV |
5693 | static int dsi_runtime_suspend(struct device *dev) |
5694 | { | |
0925afc9 TV |
5695 | struct platform_device *pdev = to_platform_device(dev); |
5696 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); | |
5697 | ||
5698 | dsi->is_enabled = false; | |
5699 | /* ensure the irq handler sees the is_enabled value */ | |
5700 | smp_wmb(); | |
5701 | /* wait for current handler to finish before turning the DSI off */ | |
5702 | synchronize_irq(dsi->irq); | |
5703 | ||
4fbafaf3 | 5704 | dispc_runtime_put(); |
4fbafaf3 TV |
5705 | |
5706 | return 0; | |
5707 | } | |
5708 | ||
5709 | static int dsi_runtime_resume(struct device *dev) | |
5710 | { | |
0925afc9 TV |
5711 | struct platform_device *pdev = to_platform_device(dev); |
5712 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); | |
4fbafaf3 TV |
5713 | int r; |
5714 | ||
4fbafaf3 TV |
5715 | r = dispc_runtime_get(); |
5716 | if (r) | |
852f0838 | 5717 | return r; |
4fbafaf3 | 5718 | |
0925afc9 TV |
5719 | dsi->is_enabled = true; |
5720 | /* ensure the irq handler sees the is_enabled value */ | |
5721 | smp_wmb(); | |
5722 | ||
4fbafaf3 | 5723 | return 0; |
4fbafaf3 TV |
5724 | } |
5725 | ||
5726 | static const struct dev_pm_ops dsi_pm_ops = { | |
5727 | .runtime_suspend = dsi_runtime_suspend, | |
5728 | .runtime_resume = dsi_runtime_resume, | |
5729 | }; | |
5730 | ||
6274a619 TV |
5731 | static const struct dsi_module_id_data dsi_of_data_omap3[] = { |
5732 | { .address = 0x4804fc00, .id = 0, }, | |
5733 | { }, | |
5734 | }; | |
5735 | ||
5736 | static const struct dsi_module_id_data dsi_of_data_omap4[] = { | |
5737 | { .address = 0x58004000, .id = 0, }, | |
5738 | { .address = 0x58005000, .id = 1, }, | |
5739 | { }, | |
5740 | }; | |
5741 | ||
bd3ad6a4 TV |
5742 | static const struct dsi_module_id_data dsi_of_data_omap5[] = { |
5743 | { .address = 0x58004000, .id = 0, }, | |
5744 | { .address = 0x58009000, .id = 1, }, | |
5745 | { }, | |
5746 | }; | |
5747 | ||
6274a619 TV |
5748 | static const struct of_device_id dsi_of_match[] = { |
5749 | { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, | |
5750 | { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, | |
bd3ad6a4 | 5751 | { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, |
6274a619 TV |
5752 | {}, |
5753 | }; | |
5754 | ||
7c68dd96 | 5755 | static struct platform_driver omap_dsihw_driver = { |
ee4a24e2 | 5756 | .probe = omap_dsihw_probe, |
6e7e8f06 | 5757 | .remove = __exit_p(omap_dsihw_remove), |
c8aac01b | 5758 | .driver = { |
7c68dd96 | 5759 | .name = "omapdss_dsi", |
c8aac01b | 5760 | .owner = THIS_MODULE, |
4fbafaf3 | 5761 | .pm = &dsi_pm_ops, |
6274a619 | 5762 | .of_match_table = dsi_of_match, |
422ccbd5 | 5763 | .suppress_bind_attrs = true, |
c8aac01b SG |
5764 | }, |
5765 | }; | |
5766 | ||
6e7e8f06 | 5767 | int __init dsi_init_platform_driver(void) |
c8aac01b | 5768 | { |
ee4a24e2 | 5769 | return platform_driver_register(&omap_dsihw_driver); |
c8aac01b SG |
5770 | } |
5771 | ||
6e7e8f06 | 5772 | void __exit dsi_uninit_platform_driver(void) |
c8aac01b | 5773 | { |
04c742c3 | 5774 | platform_driver_unregister(&omap_dsihw_driver); |
c8aac01b | 5775 | } |