Commit | Line | Data |
---|---|---|
94c52987 | 1 | /* |
ef26958a | 2 | * HDMI driver definition for TI OMAP4 Processor. |
94c52987 M |
3 | * |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
ef26958a AT |
19 | #ifndef _HDMI_H |
20 | #define _HDMI_H | |
94c52987 | 21 | |
bdb8bfc6 AT |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
f382d9eb | 24 | #include <linux/platform_device.h> |
db85ca7c | 25 | #include <linux/hdmi.h> |
bdb8bfc6 AT |
26 | #include <video/omapdss.h> |
27 | ||
28 | #include "dss.h" | |
29 | ||
30 | /* HDMI Wrapper */ | |
31 | ||
32 | #define HDMI_WP_REVISION 0x0 | |
33 | #define HDMI_WP_SYSCONFIG 0x10 | |
34 | #define HDMI_WP_IRQSTATUS_RAW 0x24 | |
35 | #define HDMI_WP_IRQSTATUS 0x28 | |
36 | #define HDMI_WP_IRQENABLE_SET 0x2C | |
37 | #define HDMI_WP_IRQENABLE_CLR 0x30 | |
38 | #define HDMI_WP_IRQWAKEEN 0x34 | |
39 | #define HDMI_WP_PWR_CTRL 0x40 | |
40 | #define HDMI_WP_DEBOUNCE 0x44 | |
41 | #define HDMI_WP_VIDEO_CFG 0x50 | |
42 | #define HDMI_WP_VIDEO_SIZE 0x60 | |
43 | #define HDMI_WP_VIDEO_TIMING_H 0x68 | |
44 | #define HDMI_WP_VIDEO_TIMING_V 0x6C | |
42116517 | 45 | #define HDMI_WP_CLK 0x70 |
bdb8bfc6 AT |
46 | #define HDMI_WP_AUDIO_CFG 0x80 |
47 | #define HDMI_WP_AUDIO_CFG2 0x84 | |
48 | #define HDMI_WP_AUDIO_CTRL 0x88 | |
49 | #define HDMI_WP_AUDIO_DATA 0x8C | |
50 | ||
8696131f | 51 | /* HDMI WP IRQ flags */ |
6873efe1 | 52 | #define HDMI_IRQ_CORE (1 << 0) |
8696131f AT |
53 | #define HDMI_IRQ_OCP_TIMEOUT (1 << 4) |
54 | #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8) | |
55 | #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9) | |
56 | #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10) | |
57 | #define HDMI_IRQ_VIDEO_VSYNC (1 << 16) | |
58 | #define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17) | |
59 | #define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24) | |
60 | #define HDMI_IRQ_LINK_CONNECT (1 << 25) | |
61 | #define HDMI_IRQ_LINK_DISCONNECT (1 << 26) | |
62 | #define HDMI_IRQ_PLL_LOCK (1 << 29) | |
63 | #define HDMI_IRQ_PLL_UNLOCK (1 << 30) | |
64 | #define HDMI_IRQ_PLL_RECAL (1 << 31) | |
65 | ||
bdb8bfc6 AT |
66 | /* HDMI PLL */ |
67 | ||
68 | #define PLLCTRL_PLL_CONTROL 0x0 | |
69 | #define PLLCTRL_PLL_STATUS 0x4 | |
70 | #define PLLCTRL_PLL_GO 0x8 | |
71 | #define PLLCTRL_CFG1 0xC | |
72 | #define PLLCTRL_CFG2 0x10 | |
73 | #define PLLCTRL_CFG3 0x14 | |
74 | #define PLLCTRL_SSC_CFG1 0x18 | |
75 | #define PLLCTRL_SSC_CFG2 0x1C | |
76 | #define PLLCTRL_CFG4 0x20 | |
77 | ||
78 | /* HDMI PHY */ | |
79 | ||
80 | #define HDMI_TXPHY_TX_CTRL 0x0 | |
81 | #define HDMI_TXPHY_DIGITAL_CTRL 0x4 | |
82 | #define HDMI_TXPHY_POWER_CTRL 0x8 | |
83 | #define HDMI_TXPHY_PAD_CFG_CTRL 0xC | |
19289fdc | 84 | #define HDMI_TXPHY_BIST_CONTROL 0x1C |
f382d9eb | 85 | |
94c52987 M |
86 | enum hdmi_pll_pwr { |
87 | HDMI_PLLPWRCMD_ALLOFF = 0, | |
88 | HDMI_PLLPWRCMD_PLLONLY = 1, | |
89 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, | |
90 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 | |
91 | }; | |
92 | ||
f382d9eb AT |
93 | enum hdmi_phy_pwr { |
94 | HDMI_PHYPWRCMD_OFF = 0, | |
95 | HDMI_PHYPWRCMD_LDOON = 1, | |
96 | HDMI_PHYPWRCMD_TXON = 2 | |
97 | }; | |
98 | ||
94c52987 M |
99 | enum hdmi_core_hdmi_dvi { |
100 | HDMI_DVI = 0, | |
101 | HDMI_HDMI = 1 | |
102 | }; | |
103 | ||
f382d9eb AT |
104 | enum hdmi_packing_mode { |
105 | HDMI_PACK_10b_RGB_YUV444 = 0, | |
106 | HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, | |
107 | HDMI_PACK_20b_YUV422 = 2, | |
108 | HDMI_PACK_ALREADYPACKED = 7 | |
109 | }; | |
110 | ||
111 | enum hdmi_stereo_channels { | |
112 | HDMI_AUDIO_STEREO_NOCHANNELS = 0, | |
113 | HDMI_AUDIO_STEREO_ONECHANNEL = 1, | |
114 | HDMI_AUDIO_STEREO_TWOCHANNELS = 2, | |
115 | HDMI_AUDIO_STEREO_THREECHANNELS = 3, | |
116 | HDMI_AUDIO_STEREO_FOURCHANNELS = 4 | |
117 | }; | |
118 | ||
119 | enum hdmi_audio_type { | |
120 | HDMI_AUDIO_TYPE_LPCM = 0, | |
121 | HDMI_AUDIO_TYPE_IEC = 1 | |
122 | }; | |
123 | ||
124 | enum hdmi_audio_justify { | |
125 | HDMI_AUDIO_JUSTIFY_LEFT = 0, | |
126 | HDMI_AUDIO_JUSTIFY_RIGHT = 1 | |
127 | }; | |
128 | ||
129 | enum hdmi_audio_sample_order { | |
130 | HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0, | |
131 | HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1 | |
132 | }; | |
133 | ||
134 | enum hdmi_audio_samples_perword { | |
135 | HDMI_AUDIO_ONEWORD_ONESAMPLE = 0, | |
136 | HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 | |
137 | }; | |
138 | ||
d27d20c8 | 139 | enum hdmi_audio_sample_size_omap { |
f382d9eb AT |
140 | HDMI_AUDIO_SAMPLE_16BITS = 0, |
141 | HDMI_AUDIO_SAMPLE_24BITS = 1 | |
142 | }; | |
143 | ||
144 | enum hdmi_audio_transf_mode { | |
145 | HDMI_AUDIO_TRANSF_DMA = 0, | |
146 | HDMI_AUDIO_TRANSF_IRQ = 1 | |
147 | }; | |
148 | ||
149 | enum hdmi_audio_blk_strt_end_sig { | |
150 | HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0, | |
151 | HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 | |
152 | }; | |
153 | ||
bdb8bfc6 AT |
154 | enum hdmi_core_audio_layout { |
155 | HDMI_AUDIO_LAYOUT_2CH = 0, | |
156 | HDMI_AUDIO_LAYOUT_8CH = 1 | |
157 | }; | |
158 | ||
159 | enum hdmi_core_cts_mode { | |
160 | HDMI_AUDIO_CTS_MODE_HW = 0, | |
161 | HDMI_AUDIO_CTS_MODE_SW = 1 | |
162 | }; | |
163 | ||
164 | enum hdmi_audio_mclk_mode { | |
165 | HDMI_AUDIO_MCLK_128FS = 0, | |
166 | HDMI_AUDIO_MCLK_256FS = 1, | |
167 | HDMI_AUDIO_MCLK_384FS = 2, | |
168 | HDMI_AUDIO_MCLK_512FS = 3, | |
169 | HDMI_AUDIO_MCLK_768FS = 4, | |
170 | HDMI_AUDIO_MCLK_1024FS = 5, | |
171 | HDMI_AUDIO_MCLK_1152FS = 6, | |
172 | HDMI_AUDIO_MCLK_192FS = 7 | |
173 | }; | |
174 | ||
f382d9eb AT |
175 | struct hdmi_video_format { |
176 | enum hdmi_packing_mode packing_mode; | |
177 | u32 y_res; /* Line per panel */ | |
178 | u32 x_res; /* pixel per line */ | |
179 | }; | |
180 | ||
94c52987 | 181 | struct hdmi_config { |
cc937e5e | 182 | struct omap_video_timings timings; |
c9d2c799 TV |
183 | struct hdmi_avi_infoframe infoframe; |
184 | enum hdmi_core_hdmi_dvi hdmi_dvi_mode; | |
94c52987 M |
185 | }; |
186 | ||
f382d9eb AT |
187 | struct hdmi_audio_format { |
188 | enum hdmi_stereo_channels stereo_channels; | |
189 | u8 active_chnnls_msk; | |
190 | enum hdmi_audio_type type; | |
191 | enum hdmi_audio_justify justification; | |
192 | enum hdmi_audio_sample_order sample_order; | |
193 | enum hdmi_audio_samples_perword samples_per_word; | |
d27d20c8 | 194 | enum hdmi_audio_sample_size_omap sample_size; |
f382d9eb AT |
195 | enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; |
196 | }; | |
197 | ||
198 | struct hdmi_audio_dma { | |
199 | u8 transfer_size; | |
200 | u8 block_size; | |
201 | enum hdmi_audio_transf_mode mode; | |
202 | u16 fifo_threshold; | |
203 | }; | |
204 | ||
bdb8bfc6 AT |
205 | struct hdmi_core_audio_i2s_config { |
206 | u8 in_length_bits; | |
207 | u8 justification; | |
208 | u8 sck_edge_mode; | |
209 | u8 vbit; | |
210 | u8 direction; | |
211 | u8 shift; | |
212 | u8 active_sds; | |
213 | }; | |
214 | ||
215 | struct hdmi_core_audio_config { | |
216 | struct hdmi_core_audio_i2s_config i2s_cfg; | |
217 | struct snd_aes_iec958 *iec60958_cfg; | |
218 | bool fs_override; | |
219 | u32 n; | |
220 | u32 cts; | |
221 | u32 aud_par_busclk; | |
222 | enum hdmi_core_audio_layout layout; | |
223 | enum hdmi_core_cts_mode cts_mode; | |
224 | bool use_mclk; | |
225 | enum hdmi_audio_mclk_mode mclk_mode; | |
226 | bool en_acr_pkt; | |
227 | bool en_dsd_audio; | |
228 | bool en_parallel_aud_input; | |
229 | bool en_spdif; | |
230 | }; | |
231 | ||
f382d9eb AT |
232 | struct hdmi_wp_data { |
233 | void __iomem *base; | |
234 | }; | |
235 | ||
c1577c1e | 236 | struct hdmi_pll_data { |
c84c3a5b TV |
237 | struct dss_pll pll; |
238 | ||
c1577c1e AT |
239 | void __iomem *base; |
240 | ||
03aafa2c | 241 | struct hdmi_wp_data *wp; |
c1577c1e AT |
242 | }; |
243 | ||
5cac5aee AT |
244 | struct hdmi_phy_data { |
245 | void __iomem *base; | |
246 | ||
2f5dc676 TV |
247 | u8 lane_function[4]; |
248 | u8 lane_polarity[4]; | |
5cac5aee AT |
249 | }; |
250 | ||
425f02fd AT |
251 | struct hdmi_core_data { |
252 | void __iomem *base; | |
425f02fd AT |
253 | }; |
254 | ||
8955b727 | 255 | static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, |
bdb8bfc6 AT |
256 | u32 val) |
257 | { | |
258 | __raw_writel(val, base_addr + idx); | |
259 | } | |
260 | ||
8955b727 | 261 | static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) |
bdb8bfc6 AT |
262 | { |
263 | return __raw_readl(base_addr + idx); | |
264 | } | |
265 | ||
266 | #define REG_FLD_MOD(base, idx, val, start, end) \ | |
267 | hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ | |
268 | val, start, end)) | |
269 | #define REG_GET(base, idx, start, end) \ | |
270 | FLD_GET(hdmi_read_reg(base, idx), start, end) | |
271 | ||
272 | static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, | |
91b53e6a | 273 | const u32 idx, int b2, int b1, u32 val) |
bdb8bfc6 | 274 | { |
91b53e6a TV |
275 | u32 t = 0, v; |
276 | while (val != (v = REG_GET(base_addr, idx, b2, b1))) { | |
bdb8bfc6 | 277 | if (t++ > 10000) |
91b53e6a TV |
278 | return v; |
279 | udelay(1); | |
bdb8bfc6 | 280 | } |
91b53e6a | 281 | return v; |
bdb8bfc6 AT |
282 | } |
283 | ||
f382d9eb AT |
284 | /* HDMI wrapper funcs */ |
285 | int hdmi_wp_video_start(struct hdmi_wp_data *wp); | |
286 | void hdmi_wp_video_stop(struct hdmi_wp_data *wp); | |
287 | void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); | |
288 | u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); | |
289 | void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); | |
290 | void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); | |
291 | void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); | |
292 | int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); | |
293 | int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); | |
294 | void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, | |
295 | struct hdmi_video_format *video_fmt); | |
296 | void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, | |
297 | struct omap_video_timings *timings); | |
298 | void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, | |
299 | struct omap_video_timings *timings); | |
300 | void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, | |
301 | struct omap_video_timings *timings, struct hdmi_config *param); | |
302 | int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); | |
303 | ||
c1577c1e | 304 | /* HDMI PLL funcs */ |
c1577c1e | 305 | void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); |
c84c3a5b TV |
306 | void hdmi_pll_compute(struct hdmi_pll_data *pll, |
307 | unsigned long target_tmds, struct dss_pll_clock_info *pi); | |
03aafa2c TV |
308 | int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, |
309 | struct hdmi_wp_data *wp); | |
c84c3a5b | 310 | void hdmi_pll_uninit(struct hdmi_pll_data *hpll); |
c1577c1e | 311 | |
5cac5aee | 312 | /* HDMI PHY funcs */ |
33f13120 TV |
313 | int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk, |
314 | unsigned long lfbitclk); | |
5cac5aee AT |
315 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); |
316 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); | |
2f5dc676 | 317 | int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes); |
5cac5aee | 318 | |
08d83e4e | 319 | /* HDMI common funcs */ |
2f5dc676 TV |
320 | int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, |
321 | struct hdmi_phy_data *phy); | |
08d83e4e | 322 | |
f5bab222 | 323 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO) |
08d83e4e | 324 | int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts); |
f382d9eb AT |
325 | int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); |
326 | int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); | |
327 | void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, | |
328 | struct hdmi_audio_format *aud_fmt); | |
329 | void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, | |
330 | struct hdmi_audio_dma *aud_dma); | |
08d83e4e AT |
331 | static inline bool hdmi_mode_has_audio(int mode) |
332 | { | |
333 | return mode == HDMI_HDMI ? true : false; | |
334 | } | |
80a48596 | 335 | #endif |
94c52987 | 336 | #endif |