Commit | Line | Data |
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23c0a7a6 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/sdi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "SDI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23c0a7a6 TV |
23 | #include <linux/delay.h> |
24 | #include <linux/err.h> | |
508886cf | 25 | #include <linux/regulator/consumer.h> |
a8a35931 | 26 | #include <linux/export.h> |
a57dd4fe | 27 | #include <linux/platform_device.h> |
13b1ba7d | 28 | #include <linux/string.h> |
2ecef246 | 29 | #include <linux/of.h> |
23c0a7a6 | 30 | |
a0b38cc4 | 31 | #include <video/omapdss.h> |
23c0a7a6 TV |
32 | #include "dss.h" |
33 | ||
34 | static struct { | |
46c4b645 TV |
35 | struct platform_device *pdev; |
36 | ||
23c0a7a6 | 37 | bool update_enabled; |
508886cf | 38 | struct regulator *vdds_sdi_reg; |
23c0a7a6 | 39 | |
37a57990 | 40 | struct dss_lcd_mgr_config mgr_config; |
9b4a5716 | 41 | struct omap_video_timings timings; |
889b4fd7 | 42 | int datapairs; |
81b87f51 | 43 | |
1f68d9c4 | 44 | struct omap_dss_device output; |
2ecef246 TV |
45 | |
46 | bool port_initialized; | |
37a57990 | 47 | } sdi; |
64ba4f74 | 48 | |
36816faa TV |
49 | struct sdi_clk_calc_ctx { |
50 | unsigned long pck_min, pck_max; | |
51 | ||
c56812fc | 52 | unsigned long fck; |
36816faa TV |
53 | struct dispc_clock_info dispc_cinfo; |
54 | }; | |
55 | ||
56 | static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
57 | unsigned long pck, void *data) | |
58 | { | |
59 | struct sdi_clk_calc_ctx *ctx = data; | |
60 | ||
61 | ctx->dispc_cinfo.lck_div = lckd; | |
62 | ctx->dispc_cinfo.pck_div = pckd; | |
63 | ctx->dispc_cinfo.lck = lck; | |
64 | ctx->dispc_cinfo.pck = pck; | |
65 | ||
66 | return true; | |
67 | } | |
68 | ||
d0f58bd3 | 69 | static bool dpi_calc_dss_cb(unsigned long fck, void *data) |
36816faa TV |
70 | { |
71 | struct sdi_clk_calc_ctx *ctx = data; | |
72 | ||
d0f58bd3 | 73 | ctx->fck = fck; |
36816faa TV |
74 | |
75 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, | |
76 | dpi_calc_dispc_cb, ctx); | |
77 | } | |
78 | ||
79 | static int sdi_calc_clock_div(unsigned long pclk, | |
d0f58bd3 | 80 | unsigned long *fck, |
36816faa TV |
81 | struct dispc_clock_info *dispc_cinfo) |
82 | { | |
83 | int i; | |
84 | struct sdi_clk_calc_ctx ctx; | |
85 | ||
86 | /* | |
87 | * DSS fclk gives us very few possibilities, so finding a good pixel | |
88 | * clock may not be possible. We try multiple times to find the clock, | |
89 | * each time widening the pixel clock range we look for, up to | |
90 | * +/- 1MHz. | |
91 | */ | |
92 | ||
93 | for (i = 0; i < 10; ++i) { | |
94 | bool ok; | |
95 | ||
96 | memset(&ctx, 0, sizeof(ctx)); | |
97 | if (pclk > 1000 * i * i * i) | |
98 | ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); | |
99 | else | |
100 | ctx.pck_min = 0; | |
101 | ctx.pck_max = pclk + 1000 * i * i * i; | |
102 | ||
688af02d | 103 | ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx); |
36816faa | 104 | if (ok) { |
d0f58bd3 | 105 | *fck = ctx.fck; |
36816faa TV |
106 | *dispc_cinfo = ctx.dispc_cinfo; |
107 | return 0; | |
108 | } | |
109 | } | |
110 | ||
111 | return -EINVAL; | |
112 | } | |
113 | ||
37a57990 | 114 | static void sdi_config_lcd_manager(struct omap_dss_device *dssdev) |
23c0a7a6 | 115 | { |
7ae9a71e | 116 | struct omap_overlay_manager *mgr = sdi.output.manager; |
7d6069e5 | 117 | |
37a57990 | 118 | sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; |
64ba4f74 | 119 | |
37a57990 AT |
120 | sdi.mgr_config.stallmode = false; |
121 | sdi.mgr_config.fifohandcheck = false; | |
122 | ||
123 | sdi.mgr_config.video_port_width = 24; | |
124 | sdi.mgr_config.lcden_sig_polarity = 1; | |
125 | ||
7d6069e5 | 126 | dss_mgr_set_lcd_config(mgr, &sdi.mgr_config); |
23c0a7a6 TV |
127 | } |
128 | ||
cd6e915b | 129 | static int sdi_display_enable(struct omap_dss_device *dssdev) |
23c0a7a6 | 130 | { |
1f68d9c4 | 131 | struct omap_dss_device *out = &sdi.output; |
9b4a5716 | 132 | struct omap_video_timings *t = &sdi.timings; |
d0f58bd3 | 133 | unsigned long fck; |
23c0a7a6 | 134 | struct dispc_clock_info dispc_cinfo; |
23c0a7a6 TV |
135 | unsigned long pck; |
136 | int r; | |
137 | ||
7d6069e5 AT |
138 | if (out == NULL || out->manager == NULL) { |
139 | DSSERR("failed to enable display: no output/manager\n"); | |
05e1d606 TV |
140 | return -ENODEV; |
141 | } | |
142 | ||
508886cf RQ |
143 | r = regulator_enable(sdi.vdds_sdi_reg); |
144 | if (r) | |
4fbafaf3 | 145 | goto err_reg_enable; |
508886cf | 146 | |
4fbafaf3 TV |
147 | r = dispc_runtime_get(); |
148 | if (r) | |
149 | goto err_get_dispc; | |
23c0a7a6 | 150 | |
23c0a7a6 | 151 | /* 15.5.9.1.2 */ |
9b4a5716 AT |
152 | t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; |
153 | t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; | |
a8d5e41c | 154 | |
d8d78941 | 155 | r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo); |
23c0a7a6 | 156 | if (r) |
4fbafaf3 | 157 | goto err_calc_clock_div; |
23c0a7a6 | 158 | |
37a57990 | 159 | sdi.mgr_config.clock_info = dispc_cinfo; |
23c0a7a6 | 160 | |
d8d78941 | 161 | pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; |
23c0a7a6 | 162 | |
d8d78941 TV |
163 | if (pck != t->pixelclock) { |
164 | DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n", | |
165 | t->pixelclock, pck); | |
23c0a7a6 | 166 | |
d8d78941 | 167 | t->pixelclock = pck; |
23c0a7a6 TV |
168 | } |
169 | ||
170 | ||
7d6069e5 | 171 | dss_mgr_set_timings(out->manager, t); |
23c0a7a6 | 172 | |
d0f58bd3 | 173 | r = dss_set_fck_rate(fck); |
23c0a7a6 | 174 | if (r) |
4fbafaf3 | 175 | goto err_set_dss_clock_div; |
23c0a7a6 | 176 | |
37a57990 | 177 | sdi_config_lcd_manager(dssdev); |
23c0a7a6 | 178 | |
35d67866 TV |
179 | /* |
180 | * LCLK and PCLK divisors are located in shadow registers, and we | |
181 | * normally write them to DISPC registers when enabling the output. | |
182 | * However, SDI uses pck-free as source clock for its PLL, and pck-free | |
183 | * is affected by the divisors. And as we need the PLL before enabling | |
184 | * the output, we need to write the divisors early. | |
185 | * | |
186 | * It seems just writing to the DISPC register is enough, and we don't | |
187 | * need to care about the shadow register mechanism for pck-free. The | |
188 | * exact reason for this is unknown. | |
189 | */ | |
7d6069e5 | 190 | dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info); |
889b4fd7 | 191 | |
66591457 | 192 | dss_sdi_init(sdi.datapairs); |
42c9dee8 TV |
193 | r = dss_sdi_enable(); |
194 | if (r) | |
4fbafaf3 | 195 | goto err_sdi_enable; |
42c9dee8 | 196 | mdelay(2); |
23c0a7a6 | 197 | |
7d6069e5 | 198 | r = dss_mgr_enable(out->manager); |
33ca237f TV |
199 | if (r) |
200 | goto err_mgr_enable; | |
23c0a7a6 | 201 | |
23c0a7a6 | 202 | return 0; |
4fbafaf3 | 203 | |
33ca237f TV |
204 | err_mgr_enable: |
205 | dss_sdi_disable(); | |
4fbafaf3 | 206 | err_sdi_enable: |
4fbafaf3 TV |
207 | err_set_dss_clock_div: |
208 | err_calc_clock_div: | |
209 | dispc_runtime_put(); | |
210 | err_get_dispc: | |
508886cf | 211 | regulator_disable(sdi.vdds_sdi_reg); |
4fbafaf3 | 212 | err_reg_enable: |
23c0a7a6 TV |
213 | return r; |
214 | } | |
215 | ||
cd6e915b | 216 | static void sdi_display_disable(struct omap_dss_device *dssdev) |
23c0a7a6 | 217 | { |
7ae9a71e | 218 | struct omap_overlay_manager *mgr = sdi.output.manager; |
7d6069e5 AT |
219 | |
220 | dss_mgr_disable(mgr); | |
23c0a7a6 TV |
221 | |
222 | dss_sdi_disable(); | |
223 | ||
4fbafaf3 | 224 | dispc_runtime_put(); |
23c0a7a6 | 225 | |
508886cf | 226 | regulator_disable(sdi.vdds_sdi_reg); |
23c0a7a6 | 227 | } |
23c0a7a6 | 228 | |
cd6e915b | 229 | static void sdi_set_timings(struct omap_dss_device *dssdev, |
c7833f7b AT |
230 | struct omap_video_timings *timings) |
231 | { | |
9b4a5716 | 232 | sdi.timings = *timings; |
c7833f7b | 233 | } |
c7833f7b | 234 | |
b1082dfd TV |
235 | static void sdi_get_timings(struct omap_dss_device *dssdev, |
236 | struct omap_video_timings *timings) | |
237 | { | |
238 | *timings = sdi.timings; | |
239 | } | |
240 | ||
241 | static int sdi_check_timings(struct omap_dss_device *dssdev, | |
242 | struct omap_video_timings *timings) | |
243 | { | |
244 | struct omap_overlay_manager *mgr = sdi.output.manager; | |
245 | ||
246 | if (mgr && !dispc_mgr_timings_ok(mgr->id, timings)) | |
247 | return -EINVAL; | |
248 | ||
d8d78941 | 249 | if (timings->pixelclock == 0) |
b1082dfd TV |
250 | return -EINVAL; |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
cd6e915b | 255 | static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs) |
889b4fd7 AT |
256 | { |
257 | sdi.datapairs = datapairs; | |
258 | } | |
889b4fd7 | 259 | |
d37801b3 | 260 | static int sdi_init_regulator(void) |
23c0a7a6 | 261 | { |
d37801b3 | 262 | struct regulator *vdds_sdi; |
23c0a7a6 | 263 | |
d37801b3 TV |
264 | if (sdi.vdds_sdi_reg) |
265 | return 0; | |
5f42f2ce | 266 | |
349c3d95 | 267 | vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi"); |
d37801b3 | 268 | if (IS_ERR(vdds_sdi)) { |
40359a9b TV |
269 | if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER) |
270 | DSSERR("can't get VDDS_SDI regulator\n"); | |
349c3d95 | 271 | return PTR_ERR(vdds_sdi); |
5f42f2ce TV |
272 | } |
273 | ||
d37801b3 TV |
274 | sdi.vdds_sdi_reg = vdds_sdi; |
275 | ||
23c0a7a6 TV |
276 | return 0; |
277 | } | |
278 | ||
b1082dfd TV |
279 | static int sdi_connect(struct omap_dss_device *dssdev, |
280 | struct omap_dss_device *dst) | |
281 | { | |
282 | struct omap_overlay_manager *mgr; | |
283 | int r; | |
284 | ||
285 | r = sdi_init_regulator(); | |
286 | if (r) | |
287 | return r; | |
288 | ||
289 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
290 | if (!mgr) | |
291 | return -ENODEV; | |
292 | ||
293 | r = dss_mgr_connect(mgr, dssdev); | |
294 | if (r) | |
295 | return r; | |
296 | ||
297 | r = omapdss_output_set_device(dssdev, dst); | |
298 | if (r) { | |
299 | DSSERR("failed to connect output to new device: %s\n", | |
300 | dst->name); | |
301 | dss_mgr_disconnect(mgr, dssdev); | |
302 | return r; | |
303 | } | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | static void sdi_disconnect(struct omap_dss_device *dssdev, | |
309 | struct omap_dss_device *dst) | |
310 | { | |
9560dc10 | 311 | WARN_ON(dst != dssdev->dst); |
b1082dfd | 312 | |
9560dc10 | 313 | if (dst != dssdev->dst) |
b1082dfd TV |
314 | return; |
315 | ||
316 | omapdss_output_unset_device(dssdev); | |
317 | ||
318 | if (dssdev->manager) | |
319 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
320 | } | |
321 | ||
322 | static const struct omapdss_sdi_ops sdi_ops = { | |
323 | .connect = sdi_connect, | |
324 | .disconnect = sdi_disconnect, | |
325 | ||
cd6e915b TV |
326 | .enable = sdi_display_enable, |
327 | .disable = sdi_display_disable, | |
b1082dfd TV |
328 | |
329 | .check_timings = sdi_check_timings, | |
cd6e915b | 330 | .set_timings = sdi_set_timings, |
b1082dfd TV |
331 | .get_timings = sdi_get_timings, |
332 | ||
cd6e915b | 333 | .set_datapairs = sdi_set_datapairs, |
b1082dfd TV |
334 | }; |
335 | ||
d23b3357 | 336 | static void sdi_init_output(struct platform_device *pdev) |
81b87f51 | 337 | { |
1f68d9c4 | 338 | struct omap_dss_device *out = &sdi.output; |
81b87f51 | 339 | |
1f68d9c4 | 340 | out->dev = &pdev->dev; |
81b87f51 | 341 | out->id = OMAP_DSS_OUTPUT_SDI; |
1f68d9c4 | 342 | out->output_type = OMAP_DISPLAY_TYPE_SDI; |
7286a08f | 343 | out->name = "sdi.0"; |
2eea5ae6 | 344 | out->dispc_channel = OMAP_DSS_CHANNEL_LCD; |
a32442d4 TV |
345 | /* We have SDI only on OMAP3, where it's on port 1 */ |
346 | out->port_num = 1; | |
b1082dfd | 347 | out->ops.sdi = &sdi_ops; |
b7328e14 | 348 | out->owner = THIS_MODULE; |
81b87f51 | 349 | |
5d47dbc8 | 350 | omapdss_register_output(out); |
81b87f51 AT |
351 | } |
352 | ||
ede92695 | 353 | static void sdi_uninit_output(struct platform_device *pdev) |
81b87f51 | 354 | { |
1f68d9c4 | 355 | struct omap_dss_device *out = &sdi.output; |
81b87f51 | 356 | |
5d47dbc8 | 357 | omapdss_unregister_output(out); |
81b87f51 AT |
358 | } |
359 | ||
d23b3357 | 360 | static int omap_sdi_probe(struct platform_device *pdev) |
38f3daf6 | 361 | { |
46c4b645 TV |
362 | sdi.pdev = pdev; |
363 | ||
81b87f51 AT |
364 | sdi_init_output(pdev); |
365 | ||
23c0a7a6 TV |
366 | return 0; |
367 | } | |
368 | ||
ede92695 | 369 | static int omap_sdi_remove(struct platform_device *pdev) |
23c0a7a6 | 370 | { |
81b87f51 AT |
371 | sdi_uninit_output(pdev); |
372 | ||
a57dd4fe TV |
373 | return 0; |
374 | } | |
375 | ||
376 | static struct platform_driver omap_sdi_driver = { | |
d23b3357 | 377 | .probe = omap_sdi_probe, |
ede92695 | 378 | .remove = omap_sdi_remove, |
a57dd4fe TV |
379 | .driver = { |
380 | .name = "omapdss_sdi", | |
422ccbd5 | 381 | .suppress_bind_attrs = true, |
a57dd4fe TV |
382 | }, |
383 | }; | |
384 | ||
6e7e8f06 | 385 | int __init sdi_init_platform_driver(void) |
a57dd4fe | 386 | { |
d23b3357 | 387 | return platform_driver_register(&omap_sdi_driver); |
a57dd4fe TV |
388 | } |
389 | ||
ede92695 | 390 | void sdi_uninit_platform_driver(void) |
a57dd4fe TV |
391 | { |
392 | platform_driver_unregister(&omap_sdi_driver); | |
23c0a7a6 | 393 | } |
2ecef246 | 394 | |
ede92695 | 395 | int sdi_init_port(struct platform_device *pdev, struct device_node *port) |
2ecef246 TV |
396 | { |
397 | struct device_node *ep; | |
398 | u32 datapairs; | |
399 | int r; | |
400 | ||
401 | ep = omapdss_of_get_next_endpoint(port, NULL); | |
402 | if (!ep) | |
403 | return 0; | |
404 | ||
405 | r = of_property_read_u32(ep, "datapairs", &datapairs); | |
406 | if (r) { | |
407 | DSSERR("failed to parse datapairs\n"); | |
408 | goto err_datapairs; | |
409 | } | |
410 | ||
411 | sdi.datapairs = datapairs; | |
412 | ||
413 | of_node_put(ep); | |
414 | ||
415 | sdi.pdev = pdev; | |
416 | ||
417 | sdi_init_output(pdev); | |
418 | ||
419 | sdi.port_initialized = true; | |
420 | ||
421 | return 0; | |
422 | ||
423 | err_datapairs: | |
424 | of_node_put(ep); | |
425 | ||
426 | return r; | |
427 | } | |
428 | ||
ede92695 | 429 | void sdi_uninit_port(struct device_node *port) |
2ecef246 TV |
430 | { |
431 | if (!sdi.port_initialized) | |
432 | return; | |
433 | ||
434 | sdi_uninit_output(sdi.pdev); | |
435 | } |