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9b53a9e2 YS |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * Freescale DIU Frame Buffer device driver | |
5 | * | |
6 | * Authors: Hongjun Chen <hong-jun.chen@freescale.com> | |
7 | * Paul Widmer <paul.widmer@freescale.com> | |
8 | * Srikanth Srinivasan <srikanth.srinivasan@freescale.com> | |
9 | * York Sun <yorksun@freescale.com> | |
10 | * | |
11 | * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/fb.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/uaccess.h> | |
32 | #include <linux/vmalloc.h> | |
b715f9f0 | 33 | #include <linux/spinlock.h> |
9b53a9e2 | 34 | |
9b53a9e2 | 35 | #include <sysdev/fsl_soc.h> |
0814a979 | 36 | #include <linux/fsl-diu-fb.h> |
8b856f04 | 37 | #include "edid.h" |
9b53a9e2 | 38 | |
ddd3d905 | 39 | #define NUM_AOIS 5 /* 1 for plane 0, 2 for planes 1 & 2 each */ |
b715f9f0 TT |
40 | |
41 | /* HW cursor parameters */ | |
42 | #define MAX_CURS 32 | |
43 | ||
44 | /* INT_STATUS/INT_MASK field descriptions */ | |
45 | #define INT_VSYNC 0x01 /* Vsync interrupt */ | |
46 | #define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */ | |
47 | #define INT_UNDRUN 0x04 /* Under run exception interrupt */ | |
48 | #define INT_PARERR 0x08 /* Display parameters error interrupt */ | |
49 | #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */ | |
50 | ||
9b53a9e2 | 51 | /* |
63cf8df4 TT |
52 | * List of supported video modes |
53 | * | |
760af8f8 TT |
54 | * The first entry is the default video mode. The remain entries are in |
55 | * order if increasing resolution and frequency. The 320x240-60 mode is | |
56 | * the initial AOI for the second and third planes. | |
9b53a9e2 | 57 | */ |
9b53a9e2 YS |
58 | static struct fb_videomode __devinitdata fsl_diu_mode_db[] = { |
59 | { | |
9b53a9e2 YS |
60 | .refresh = 60, |
61 | .xres = 1024, | |
62 | .yres = 768, | |
63 | .pixclock = 15385, | |
64 | .left_margin = 160, | |
65 | .right_margin = 24, | |
66 | .upper_margin = 29, | |
67 | .lower_margin = 3, | |
68 | .hsync_len = 136, | |
69 | .vsync_len = 6, | |
70 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
71 | .vmode = FB_VMODE_NONINTERLACED | |
72 | }, | |
73 | { | |
760af8f8 TT |
74 | .refresh = 60, |
75 | .xres = 320, | |
76 | .yres = 240, | |
77 | .pixclock = 79440, | |
78 | .left_margin = 16, | |
79 | .right_margin = 16, | |
80 | .upper_margin = 16, | |
81 | .lower_margin = 5, | |
82 | .hsync_len = 48, | |
83 | .vsync_len = 1, | |
84 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
85 | .vmode = FB_VMODE_NONINTERLACED | |
86 | }, | |
87 | { | |
88 | .refresh = 60, | |
89 | .xres = 640, | |
90 | .yres = 480, | |
91 | .pixclock = 39722, | |
92 | .left_margin = 48, | |
93 | .right_margin = 16, | |
94 | .upper_margin = 33, | |
95 | .lower_margin = 10, | |
96 | .hsync_len = 96, | |
97 | .vsync_len = 2, | |
98 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
99 | .vmode = FB_VMODE_NONINTERLACED | |
100 | }, | |
101 | { | |
102 | .refresh = 72, | |
103 | .xres = 640, | |
104 | .yres = 480, | |
105 | .pixclock = 32052, | |
106 | .left_margin = 128, | |
107 | .right_margin = 24, | |
108 | .upper_margin = 28, | |
109 | .lower_margin = 9, | |
110 | .hsync_len = 40, | |
111 | .vsync_len = 3, | |
112 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
113 | .vmode = FB_VMODE_NONINTERLACED | |
114 | }, | |
115 | { | |
116 | .refresh = 75, | |
117 | .xres = 640, | |
118 | .yres = 480, | |
119 | .pixclock = 31747, | |
120 | .left_margin = 120, | |
121 | .right_margin = 16, | |
122 | .upper_margin = 16, | |
123 | .lower_margin = 1, | |
124 | .hsync_len = 64, | |
125 | .vsync_len = 3, | |
126 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
127 | .vmode = FB_VMODE_NONINTERLACED | |
128 | }, | |
129 | { | |
130 | .refresh = 90, | |
131 | .xres = 640, | |
132 | .yres = 480, | |
133 | .pixclock = 25057, | |
134 | .left_margin = 120, | |
135 | .right_margin = 32, | |
136 | .upper_margin = 14, | |
137 | .lower_margin = 25, | |
138 | .hsync_len = 40, | |
139 | .vsync_len = 14, | |
140 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
141 | .vmode = FB_VMODE_NONINTERLACED | |
142 | }, | |
143 | { | |
144 | .refresh = 100, | |
145 | .xres = 640, | |
146 | .yres = 480, | |
147 | .pixclock = 22272, | |
148 | .left_margin = 48, | |
149 | .right_margin = 32, | |
150 | .upper_margin = 17, | |
151 | .lower_margin = 22, | |
152 | .hsync_len = 128, | |
153 | .vsync_len = 12, | |
154 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
155 | .vmode = FB_VMODE_NONINTERLACED | |
156 | }, | |
157 | { | |
158 | .refresh = 60, | |
159 | .xres = 800, | |
160 | .yres = 480, | |
161 | .pixclock = 33805, | |
162 | .left_margin = 96, | |
163 | .right_margin = 24, | |
164 | .upper_margin = 10, | |
165 | .lower_margin = 3, | |
166 | .hsync_len = 72, | |
167 | .vsync_len = 7, | |
168 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
169 | .vmode = FB_VMODE_NONINTERLACED | |
170 | }, | |
171 | { | |
172 | .refresh = 60, | |
173 | .xres = 800, | |
174 | .yres = 600, | |
175 | .pixclock = 25000, | |
176 | .left_margin = 88, | |
177 | .right_margin = 40, | |
178 | .upper_margin = 23, | |
179 | .lower_margin = 1, | |
180 | .hsync_len = 128, | |
181 | .vsync_len = 4, | |
182 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
183 | .vmode = FB_VMODE_NONINTERLACED | |
184 | }, | |
185 | { | |
186 | .refresh = 60, | |
187 | .xres = 854, | |
188 | .yres = 480, | |
189 | .pixclock = 31518, | |
190 | .left_margin = 104, | |
191 | .right_margin = 16, | |
192 | .upper_margin = 13, | |
193 | .lower_margin = 1, | |
194 | .hsync_len = 88, | |
195 | .vsync_len = 3, | |
196 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
197 | .vmode = FB_VMODE_NONINTERLACED | |
198 | }, | |
199 | { | |
9b53a9e2 YS |
200 | .refresh = 70, |
201 | .xres = 1024, | |
202 | .yres = 768, | |
203 | .pixclock = 16886, | |
204 | .left_margin = 3, | |
205 | .right_margin = 3, | |
206 | .upper_margin = 2, | |
207 | .lower_margin = 2, | |
208 | .hsync_len = 40, | |
209 | .vsync_len = 18, | |
210 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
211 | .vmode = FB_VMODE_NONINTERLACED | |
212 | }, | |
213 | { | |
9b53a9e2 YS |
214 | .refresh = 75, |
215 | .xres = 1024, | |
216 | .yres = 768, | |
217 | .pixclock = 15009, | |
218 | .left_margin = 3, | |
219 | .right_margin = 3, | |
220 | .upper_margin = 2, | |
221 | .lower_margin = 2, | |
222 | .hsync_len = 80, | |
223 | .vsync_len = 32, | |
224 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
225 | .vmode = FB_VMODE_NONINTERLACED | |
226 | }, | |
227 | { | |
760af8f8 TT |
228 | .refresh = 60, |
229 | .xres = 1280, | |
230 | .yres = 480, | |
231 | .pixclock = 18939, | |
232 | .left_margin = 353, | |
233 | .right_margin = 47, | |
234 | .upper_margin = 39, | |
235 | .lower_margin = 4, | |
236 | .hsync_len = 8, | |
237 | .vsync_len = 2, | |
238 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
239 | .vmode = FB_VMODE_NONINTERLACED | |
240 | }, | |
241 | { | |
242 | .refresh = 60, | |
243 | .xres = 1280, | |
244 | .yres = 720, | |
245 | .pixclock = 13426, | |
246 | .left_margin = 192, | |
247 | .right_margin = 64, | |
248 | .upper_margin = 22, | |
249 | .lower_margin = 1, | |
250 | .hsync_len = 136, | |
251 | .vsync_len = 3, | |
252 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
253 | .vmode = FB_VMODE_NONINTERLACED | |
254 | }, | |
255 | { | |
9b53a9e2 YS |
256 | .refresh = 60, |
257 | .xres = 1280, | |
258 | .yres = 1024, | |
259 | .pixclock = 9375, | |
260 | .left_margin = 38, | |
261 | .right_margin = 128, | |
262 | .upper_margin = 2, | |
263 | .lower_margin = 7, | |
264 | .hsync_len = 216, | |
265 | .vsync_len = 37, | |
266 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
267 | .vmode = FB_VMODE_NONINTERLACED | |
268 | }, | |
269 | { | |
9b53a9e2 YS |
270 | .refresh = 70, |
271 | .xres = 1280, | |
272 | .yres = 1024, | |
273 | .pixclock = 9380, | |
274 | .left_margin = 6, | |
275 | .right_margin = 6, | |
276 | .upper_margin = 4, | |
277 | .lower_margin = 4, | |
278 | .hsync_len = 60, | |
279 | .vsync_len = 94, | |
280 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
281 | .vmode = FB_VMODE_NONINTERLACED | |
282 | }, | |
283 | { | |
9b53a9e2 YS |
284 | .refresh = 75, |
285 | .xres = 1280, | |
286 | .yres = 1024, | |
287 | .pixclock = 9380, | |
288 | .left_margin = 6, | |
289 | .right_margin = 6, | |
290 | .upper_margin = 4, | |
291 | .lower_margin = 4, | |
292 | .hsync_len = 60, | |
293 | .vsync_len = 15, | |
294 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
295 | .vmode = FB_VMODE_NONINTERLACED | |
296 | }, | |
297 | { | |
9b53a9e2 | 298 | .refresh = 60, |
760af8f8 TT |
299 | .xres = 1920, |
300 | .yres = 1080, | |
301 | .pixclock = 5787, | |
302 | .left_margin = 328, | |
303 | .right_margin = 120, | |
304 | .upper_margin = 34, | |
305 | .lower_margin = 1, | |
306 | .hsync_len = 208, | |
307 | .vsync_len = 3, | |
9b53a9e2 YS |
308 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
309 | .vmode = FB_VMODE_NONINTERLACED | |
310 | }, | |
311 | }; | |
312 | ||
760af8f8 | 313 | static char *fb_mode; |
9b53a9e2 | 314 | static unsigned long default_bpp = 32; |
7653aaab TT |
315 | static enum fsl_diu_monitor_port monitor_port; |
316 | static char *monitor_string; | |
9b53a9e2 YS |
317 | |
318 | #if defined(CONFIG_NOT_COHERENT_CACHE) | |
319 | static u8 *coherence_data; | |
320 | static size_t coherence_data_size; | |
321 | static unsigned int d_cache_line_size; | |
322 | #endif | |
323 | ||
324 | static DEFINE_SPINLOCK(diu_lock); | |
325 | ||
2572df91 TT |
326 | enum mfb_index { |
327 | PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */ | |
328 | PLANE1_AOI0, /* Plane 1, first AOI */ | |
329 | PLANE1_AOI1, /* Plane 1, second AOI */ | |
330 | PLANE2_AOI0, /* Plane 2, first AOI */ | |
331 | PLANE2_AOI1, /* Plane 2, second AOI */ | |
332 | }; | |
333 | ||
9b53a9e2 | 334 | struct mfb_info { |
2572df91 | 335 | enum mfb_index index; |
9b53a9e2 YS |
336 | char *id; |
337 | int registered; | |
9b53a9e2 YS |
338 | unsigned long pseudo_palette[16]; |
339 | struct diu_ad *ad; | |
340 | int cursor_reset; | |
341 | unsigned char g_alpha; | |
342 | unsigned int count; | |
343 | int x_aoi_d; /* aoi display x offset to physical screen */ | |
344 | int y_aoi_d; /* aoi display y offset to physical screen */ | |
345 | struct fsl_diu_data *parent; | |
8b856f04 | 346 | u8 *edid_data; |
9b53a9e2 YS |
347 | }; |
348 | ||
ddd3d905 TT |
349 | /** |
350 | * struct fsl_diu_data - per-DIU data structure | |
351 | * @dma_addr: DMA address of this structure | |
352 | * @fsl_diu_info: fb_info objects, one per AOI | |
353 | * @dev_attr: sysfs structure | |
354 | * @irq: IRQ | |
355 | * @fb_enabled: TRUE if the DIU is enabled, FALSE if not | |
356 | * @monitor_port: the monitor port this DIU is connected to | |
357 | * @diu_reg: pointer to the DIU hardware registers | |
358 | * @reg_lock: spinlock for register access | |
359 | * @dummy_aoi: video buffer for the 4x4 32-bit dummy AOI | |
360 | * dummy_ad: DIU Area Descriptor for the dummy AOI | |
361 | * @ad[]: Area Descriptors for each real AOI | |
362 | * @gamma: gamma color table | |
363 | * @cursor: hardware cursor data | |
364 | * | |
365 | * This data structure must be allocated with 32-byte alignment, so that the | |
366 | * internal fields can be aligned properly. | |
367 | */ | |
368 | struct fsl_diu_data { | |
369 | dma_addr_t dma_addr; | |
370 | struct fb_info fsl_diu_info[NUM_AOIS]; | |
371 | struct mfb_info mfb[NUM_AOIS]; | |
372 | struct device_attribute dev_attr; | |
373 | unsigned int irq; | |
374 | int fb_enabled; | |
375 | enum fsl_diu_monitor_port monitor_port; | |
376 | struct diu __iomem *diu_reg; | |
377 | spinlock_t reg_lock; | |
378 | u8 dummy_aoi[4 * 4 * 4]; | |
379 | struct diu_ad dummy_ad __aligned(8); | |
380 | struct diu_ad ad[NUM_AOIS] __aligned(8); | |
381 | u8 gamma[256 * 3] __aligned(32); | |
382 | u8 cursor[MAX_CURS * MAX_CURS * 2] __aligned(32); | |
383 | } __aligned(32); | |
384 | ||
385 | /* Determine the DMA address of a member of the fsl_diu_data structure */ | |
386 | #define DMA_ADDR(p, f) ((p)->dma_addr + offsetof(struct fsl_diu_data, f)) | |
9b53a9e2 YS |
387 | |
388 | static struct mfb_info mfb_template[] = { | |
2572df91 TT |
389 | { |
390 | .index = PLANE0, | |
4a85dc8b TT |
391 | .id = "Panel0", |
392 | .registered = 0, | |
393 | .count = 0, | |
394 | .x_aoi_d = 0, | |
395 | .y_aoi_d = 0, | |
9b53a9e2 | 396 | }, |
2572df91 TT |
397 | { |
398 | .index = PLANE1_AOI0, | |
4a85dc8b TT |
399 | .id = "Panel1 AOI0", |
400 | .registered = 0, | |
401 | .g_alpha = 0xff, | |
402 | .count = 0, | |
403 | .x_aoi_d = 0, | |
404 | .y_aoi_d = 0, | |
9b53a9e2 | 405 | }, |
2572df91 TT |
406 | { |
407 | .index = PLANE1_AOI1, | |
4a85dc8b TT |
408 | .id = "Panel1 AOI1", |
409 | .registered = 0, | |
410 | .g_alpha = 0xff, | |
411 | .count = 0, | |
412 | .x_aoi_d = 0, | |
413 | .y_aoi_d = 480, | |
9b53a9e2 | 414 | }, |
2572df91 TT |
415 | { |
416 | .index = PLANE2_AOI0, | |
4a85dc8b TT |
417 | .id = "Panel2 AOI0", |
418 | .registered = 0, | |
419 | .g_alpha = 0xff, | |
420 | .count = 0, | |
421 | .x_aoi_d = 640, | |
422 | .y_aoi_d = 0, | |
9b53a9e2 | 423 | }, |
2572df91 TT |
424 | { |
425 | .index = PLANE2_AOI1, | |
4a85dc8b TT |
426 | .id = "Panel2 AOI1", |
427 | .registered = 0, | |
428 | .g_alpha = 0xff, | |
429 | .count = 0, | |
430 | .x_aoi_d = 640, | |
431 | .y_aoi_d = 480, | |
9b53a9e2 YS |
432 | }, |
433 | }; | |
434 | ||
7653aaab TT |
435 | /** |
436 | * fsl_diu_name_to_port - convert a port name to a monitor port enum | |
437 | * | |
438 | * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns | |
439 | * the enum fsl_diu_monitor_port that corresponds to that string. | |
440 | * | |
441 | * For compatibility with older versions, a number ("0", "1", or "2") is also | |
442 | * supported. | |
443 | * | |
444 | * If the string is unknown, DVI is assumed. | |
445 | * | |
446 | * If the particular port is not supported by the platform, another port | |
447 | * (platform-specific) is chosen instead. | |
448 | */ | |
449 | static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s) | |
450 | { | |
451 | enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI; | |
452 | unsigned long val; | |
453 | ||
454 | if (s) { | |
455 | if (!strict_strtoul(s, 10, &val) && (val <= 2)) | |
456 | port = (enum fsl_diu_monitor_port) val; | |
457 | else if (strncmp(s, "lvds", 4) == 0) | |
458 | port = FSL_DIU_PORT_LVDS; | |
459 | else if (strncmp(s, "dlvds", 5) == 0) | |
460 | port = FSL_DIU_PORT_DLVDS; | |
461 | } | |
462 | ||
463 | return diu_ops.valid_monitor_port(port); | |
464 | } | |
465 | ||
6b51d51a TT |
466 | /** |
467 | * fsl_diu_alloc - allocate memory for the DIU | |
468 | * @size: number of bytes to allocate | |
469 | * @param: returned physical address of memory | |
470 | * | |
471 | * This function allocates a physically-contiguous block of memory. | |
9b53a9e2 | 472 | */ |
6b51d51a | 473 | static void *fsl_diu_alloc(size_t size, phys_addr_t *phys) |
9b53a9e2 YS |
474 | { |
475 | void *virt; | |
476 | ||
6b51d51a | 477 | virt = alloc_pages_exact(size, GFP_DMA | __GFP_ZERO); |
154152ae | 478 | if (virt) |
9b53a9e2 | 479 | *phys = virt_to_phys(virt); |
9b53a9e2 | 480 | |
9b53a9e2 YS |
481 | return virt; |
482 | } | |
483 | ||
6b51d51a TT |
484 | /** |
485 | * fsl_diu_free - release DIU memory | |
486 | * @virt: pointer returned by fsl_diu_alloc() | |
487 | * @size: number of bytes allocated by fsl_diu_alloc() | |
488 | * | |
489 | * This function releases memory allocated by fsl_diu_alloc(). | |
490 | */ | |
491 | static void fsl_diu_free(void *virt, size_t size) | |
9b53a9e2 | 492 | { |
6b51d51a TT |
493 | if (virt && size) |
494 | free_pages_exact(virt, size); | |
9b53a9e2 YS |
495 | } |
496 | ||
0d9dab39 AG |
497 | /* |
498 | * Workaround for failed writing desc register of planes. | |
499 | * Needed with MPC5121 DIU rev 2.0 silicon. | |
500 | */ | |
501 | void wr_reg_wa(u32 *reg, u32 val) | |
502 | { | |
503 | do { | |
504 | out_be32(reg, val); | |
505 | } while (in_be32(reg) != val); | |
506 | } | |
507 | ||
7e47c211 | 508 | static void fsl_diu_enable_panel(struct fb_info *info) |
9b53a9e2 YS |
509 | { |
510 | struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par; | |
9b53a9e2 | 511 | struct diu_ad *ad = mfbi->ad; |
b7795052 TT |
512 | struct fsl_diu_data *data = mfbi->parent; |
513 | struct diu __iomem *hw = data->diu_reg; | |
9b53a9e2 | 514 | |
7e47c211 TT |
515 | switch (mfbi->index) { |
516 | case PLANE0: | |
517 | if (hw->desc[0] != ad->paddr) | |
518 | wr_reg_wa(&hw->desc[0], ad->paddr); | |
519 | break; | |
520 | case PLANE1_AOI0: | |
b7795052 | 521 | cmfbi = &data->mfb[2]; |
7e47c211 TT |
522 | if (hw->desc[1] != ad->paddr) { /* AOI0 closed */ |
523 | if (cmfbi->count > 0) /* AOI1 open */ | |
524 | ad->next_ad = | |
525 | cpu_to_le32(cmfbi->ad->paddr); | |
526 | else | |
527 | ad->next_ad = 0; | |
528 | wr_reg_wa(&hw->desc[1], ad->paddr); | |
9b53a9e2 | 529 | } |
7e47c211 TT |
530 | break; |
531 | case PLANE2_AOI0: | |
b7795052 | 532 | cmfbi = &data->mfb[4]; |
7e47c211 TT |
533 | if (hw->desc[2] != ad->paddr) { /* AOI0 closed */ |
534 | if (cmfbi->count > 0) /* AOI1 open */ | |
535 | ad->next_ad = | |
536 | cpu_to_le32(cmfbi->ad->paddr); | |
537 | else | |
538 | ad->next_ad = 0; | |
539 | wr_reg_wa(&hw->desc[2], ad->paddr); | |
540 | } | |
541 | break; | |
542 | case PLANE1_AOI1: | |
b7795052 | 543 | pmfbi = &data->mfb[1]; |
7e47c211 | 544 | ad->next_ad = 0; |
b7795052 | 545 | if (hw->desc[1] == data->dummy_ad.paddr) |
7e47c211 TT |
546 | wr_reg_wa(&hw->desc[1], ad->paddr); |
547 | else /* AOI0 open */ | |
548 | pmfbi->ad->next_ad = cpu_to_le32(ad->paddr); | |
549 | break; | |
550 | case PLANE2_AOI1: | |
b7795052 | 551 | pmfbi = &data->mfb[3]; |
7e47c211 | 552 | ad->next_ad = 0; |
b7795052 | 553 | if (hw->desc[2] == data->dummy_ad.paddr) |
7e47c211 TT |
554 | wr_reg_wa(&hw->desc[2], ad->paddr); |
555 | else /* AOI0 was open */ | |
556 | pmfbi->ad->next_ad = cpu_to_le32(ad->paddr); | |
557 | break; | |
558 | } | |
9b53a9e2 YS |
559 | } |
560 | ||
2572df91 | 561 | static void fsl_diu_disable_panel(struct fb_info *info) |
9b53a9e2 YS |
562 | { |
563 | struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par; | |
9b53a9e2 | 564 | struct diu_ad *ad = mfbi->ad; |
b7795052 TT |
565 | struct fsl_diu_data *data = mfbi->parent; |
566 | struct diu __iomem *hw = data->diu_reg; | |
9b53a9e2 YS |
567 | |
568 | switch (mfbi->index) { | |
2572df91 | 569 | case PLANE0: |
b7795052 TT |
570 | if (hw->desc[0] != data->dummy_ad.paddr) |
571 | wr_reg_wa(&hw->desc[0], data->dummy_ad.paddr); | |
9b53a9e2 | 572 | break; |
2572df91 | 573 | case PLANE1_AOI0: |
b7795052 | 574 | cmfbi = &data->mfb[2]; |
9b53a9e2 | 575 | if (cmfbi->count > 0) /* AOI1 is open */ |
0d9dab39 | 576 | wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr); |
9b53a9e2 YS |
577 | /* move AOI1 to the first */ |
578 | else /* AOI1 was closed */ | |
b7795052 | 579 | wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr); |
9b53a9e2 YS |
580 | /* close AOI 0 */ |
581 | break; | |
2572df91 | 582 | case PLANE2_AOI0: |
b7795052 | 583 | cmfbi = &data->mfb[4]; |
9b53a9e2 | 584 | if (cmfbi->count > 0) /* AOI1 is open */ |
0d9dab39 | 585 | wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr); |
9b53a9e2 YS |
586 | /* move AOI1 to the first */ |
587 | else /* AOI1 was closed */ | |
b7795052 | 588 | wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr); |
9b53a9e2 YS |
589 | /* close AOI 0 */ |
590 | break; | |
2572df91 | 591 | case PLANE1_AOI1: |
b7795052 | 592 | pmfbi = &data->mfb[1]; |
9b53a9e2 YS |
593 | if (hw->desc[1] != ad->paddr) { |
594 | /* AOI1 is not the first in the chain */ | |
595 | if (pmfbi->count > 0) | |
596 | /* AOI0 is open, must be the first */ | |
597 | pmfbi->ad->next_ad = 0; | |
598 | } else /* AOI1 is the first in the chain */ | |
b7795052 | 599 | wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr); |
9b53a9e2 YS |
600 | /* close AOI 1 */ |
601 | break; | |
2572df91 | 602 | case PLANE2_AOI1: |
b7795052 | 603 | pmfbi = &data->mfb[3]; |
9b53a9e2 YS |
604 | if (hw->desc[2] != ad->paddr) { |
605 | /* AOI1 is not the first in the chain */ | |
606 | if (pmfbi->count > 0) | |
607 | /* AOI0 is open, must be the first */ | |
608 | pmfbi->ad->next_ad = 0; | |
609 | } else /* AOI1 is the first in the chain */ | |
b7795052 | 610 | wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr); |
9b53a9e2 YS |
611 | /* close AOI 1 */ |
612 | break; | |
9b53a9e2 | 613 | } |
9b53a9e2 YS |
614 | } |
615 | ||
616 | static void enable_lcdc(struct fb_info *info) | |
617 | { | |
9b53a9e2 | 618 | struct mfb_info *mfbi = info->par; |
b7795052 TT |
619 | struct fsl_diu_data *data = mfbi->parent; |
620 | struct diu __iomem *hw = data->diu_reg; | |
9b53a9e2 | 621 | |
b7795052 | 622 | if (!data->fb_enabled) { |
c4e5a023 | 623 | out_be32(&hw->diu_mode, MFB_MODE1); |
b7795052 | 624 | data->fb_enabled++; |
9b53a9e2 YS |
625 | } |
626 | } | |
627 | ||
628 | static void disable_lcdc(struct fb_info *info) | |
629 | { | |
9b53a9e2 | 630 | struct mfb_info *mfbi = info->par; |
b7795052 TT |
631 | struct fsl_diu_data *data = mfbi->parent; |
632 | struct diu __iomem *hw = data->diu_reg; | |
9b53a9e2 | 633 | |
b7795052 | 634 | if (data->fb_enabled) { |
9b53a9e2 | 635 | out_be32(&hw->diu_mode, 0); |
b7795052 | 636 | data->fb_enabled = 0; |
9b53a9e2 YS |
637 | } |
638 | } | |
639 | ||
640 | static void adjust_aoi_size_position(struct fb_var_screeninfo *var, | |
641 | struct fb_info *info) | |
642 | { | |
643 | struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par; | |
b7795052 | 644 | struct fsl_diu_data *data = mfbi->parent; |
2572df91 TT |
645 | int available_height, upper_aoi_bottom; |
646 | enum mfb_index index = mfbi->index; | |
9b53a9e2 YS |
647 | int lower_aoi_is_open, upper_aoi_is_open; |
648 | __u32 base_plane_width, base_plane_height, upper_aoi_height; | |
649 | ||
b7795052 TT |
650 | base_plane_width = data->fsl_diu_info[0].var.xres; |
651 | base_plane_height = data->fsl_diu_info[0].var.yres; | |
9b53a9e2 | 652 | |
fdfaa483 YS |
653 | if (mfbi->x_aoi_d < 0) |
654 | mfbi->x_aoi_d = 0; | |
655 | if (mfbi->y_aoi_d < 0) | |
656 | mfbi->y_aoi_d = 0; | |
9b53a9e2 | 657 | switch (index) { |
2572df91 | 658 | case PLANE0: |
9b53a9e2 YS |
659 | if (mfbi->x_aoi_d != 0) |
660 | mfbi->x_aoi_d = 0; | |
661 | if (mfbi->y_aoi_d != 0) | |
662 | mfbi->y_aoi_d = 0; | |
663 | break; | |
2572df91 TT |
664 | case PLANE1_AOI0: |
665 | case PLANE2_AOI0: | |
b7795052 | 666 | lower_aoi_mfbi = data->fsl_diu_info[index+1].par; |
9b53a9e2 YS |
667 | lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0; |
668 | if (var->xres > base_plane_width) | |
669 | var->xres = base_plane_width; | |
670 | if ((mfbi->x_aoi_d + var->xres) > base_plane_width) | |
671 | mfbi->x_aoi_d = base_plane_width - var->xres; | |
672 | ||
673 | if (lower_aoi_is_open) | |
674 | available_height = lower_aoi_mfbi->y_aoi_d; | |
675 | else | |
676 | available_height = base_plane_height; | |
677 | if (var->yres > available_height) | |
678 | var->yres = available_height; | |
679 | if ((mfbi->y_aoi_d + var->yres) > available_height) | |
680 | mfbi->y_aoi_d = available_height - var->yres; | |
681 | break; | |
2572df91 TT |
682 | case PLANE1_AOI1: |
683 | case PLANE2_AOI1: | |
b7795052 TT |
684 | upper_aoi_mfbi = data->fsl_diu_info[index-1].par; |
685 | upper_aoi_height = data->fsl_diu_info[index-1].var.yres; | |
9b53a9e2 YS |
686 | upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height; |
687 | upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0; | |
688 | if (var->xres > base_plane_width) | |
689 | var->xres = base_plane_width; | |
690 | if ((mfbi->x_aoi_d + var->xres) > base_plane_width) | |
691 | mfbi->x_aoi_d = base_plane_width - var->xres; | |
692 | if (mfbi->y_aoi_d < 0) | |
693 | mfbi->y_aoi_d = 0; | |
694 | if (upper_aoi_is_open) { | |
695 | if (mfbi->y_aoi_d < upper_aoi_bottom) | |
696 | mfbi->y_aoi_d = upper_aoi_bottom; | |
697 | available_height = base_plane_height | |
698 | - upper_aoi_bottom; | |
699 | } else | |
700 | available_height = base_plane_height; | |
701 | if (var->yres > available_height) | |
702 | var->yres = available_height; | |
703 | if ((mfbi->y_aoi_d + var->yres) > base_plane_height) | |
704 | mfbi->y_aoi_d = base_plane_height - var->yres; | |
705 | break; | |
706 | } | |
707 | } | |
708 | /* | |
709 | * Checks to see if the hardware supports the state requested by var passed | |
710 | * in. This function does not alter the hardware state! If the var passed in | |
711 | * is slightly off by what the hardware can support then we alter the var | |
712 | * PASSED in to what we can do. If the hardware doesn't support mode change | |
713 | * a -EINVAL will be returned by the upper layers. | |
714 | */ | |
715 | static int fsl_diu_check_var(struct fb_var_screeninfo *var, | |
716 | struct fb_info *info) | |
717 | { | |
9b53a9e2 YS |
718 | if (var->xres_virtual < var->xres) |
719 | var->xres_virtual = var->xres; | |
720 | if (var->yres_virtual < var->yres) | |
721 | var->yres_virtual = var->yres; | |
722 | ||
723 | if (var->xoffset < 0) | |
724 | var->xoffset = 0; | |
725 | ||
726 | if (var->yoffset < 0) | |
727 | var->yoffset = 0; | |
728 | ||
729 | if (var->xoffset + info->var.xres > info->var.xres_virtual) | |
730 | var->xoffset = info->var.xres_virtual - info->var.xres; | |
731 | ||
732 | if (var->yoffset + info->var.yres > info->var.yres_virtual) | |
733 | var->yoffset = info->var.yres_virtual - info->var.yres; | |
734 | ||
735 | if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && | |
736 | (var->bits_per_pixel != 16)) | |
737 | var->bits_per_pixel = default_bpp; | |
738 | ||
739 | switch (var->bits_per_pixel) { | |
740 | case 16: | |
741 | var->red.length = 5; | |
742 | var->red.offset = 11; | |
743 | var->red.msb_right = 0; | |
744 | ||
745 | var->green.length = 6; | |
746 | var->green.offset = 5; | |
747 | var->green.msb_right = 0; | |
748 | ||
749 | var->blue.length = 5; | |
750 | var->blue.offset = 0; | |
751 | var->blue.msb_right = 0; | |
752 | ||
753 | var->transp.length = 0; | |
754 | var->transp.offset = 0; | |
755 | var->transp.msb_right = 0; | |
756 | break; | |
757 | case 24: | |
758 | var->red.length = 8; | |
759 | var->red.offset = 0; | |
760 | var->red.msb_right = 0; | |
761 | ||
762 | var->green.length = 8; | |
763 | var->green.offset = 8; | |
764 | var->green.msb_right = 0; | |
765 | ||
766 | var->blue.length = 8; | |
767 | var->blue.offset = 16; | |
768 | var->blue.msb_right = 0; | |
769 | ||
770 | var->transp.length = 0; | |
771 | var->transp.offset = 0; | |
772 | var->transp.msb_right = 0; | |
773 | break; | |
774 | case 32: | |
775 | var->red.length = 8; | |
776 | var->red.offset = 16; | |
777 | var->red.msb_right = 0; | |
778 | ||
779 | var->green.length = 8; | |
780 | var->green.offset = 8; | |
781 | var->green.msb_right = 0; | |
782 | ||
783 | var->blue.length = 8; | |
784 | var->blue.offset = 0; | |
785 | var->blue.msb_right = 0; | |
786 | ||
787 | var->transp.length = 8; | |
788 | var->transp.offset = 24; | |
789 | var->transp.msb_right = 0; | |
790 | ||
791 | break; | |
792 | } | |
9b53a9e2 YS |
793 | |
794 | var->height = -1; | |
795 | var->width = -1; | |
796 | var->grayscale = 0; | |
797 | ||
798 | /* Copy nonstd field to/from sync for fbset usage */ | |
799 | var->sync |= var->nonstd; | |
800 | var->nonstd |= var->sync; | |
801 | ||
802 | adjust_aoi_size_position(var, info); | |
803 | return 0; | |
804 | } | |
805 | ||
806 | static void set_fix(struct fb_info *info) | |
807 | { | |
808 | struct fb_fix_screeninfo *fix = &info->fix; | |
809 | struct fb_var_screeninfo *var = &info->var; | |
810 | struct mfb_info *mfbi = info->par; | |
811 | ||
ec02dd23 | 812 | strncpy(fix->id, mfbi->id, sizeof(fix->id)); |
9b53a9e2 YS |
813 | fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; |
814 | fix->type = FB_TYPE_PACKED_PIXELS; | |
815 | fix->accel = FB_ACCEL_NONE; | |
816 | fix->visual = FB_VISUAL_TRUECOLOR; | |
817 | fix->xpanstep = 1; | |
818 | fix->ypanstep = 1; | |
819 | } | |
820 | ||
821 | static void update_lcdc(struct fb_info *info) | |
822 | { | |
823 | struct fb_var_screeninfo *var = &info->var; | |
824 | struct mfb_info *mfbi = info->par; | |
b7795052 | 825 | struct fsl_diu_data *data = mfbi->parent; |
3c755b7c | 826 | struct diu __iomem *hw; |
9b53a9e2 | 827 | int i, j; |
ddd3d905 | 828 | u8 *gamma_table_base; |
9b53a9e2 YS |
829 | |
830 | u32 temp; | |
831 | ||
b7795052 | 832 | hw = data->diu_reg; |
9b53a9e2 | 833 | |
b7795052 TT |
834 | diu_ops.set_monitor_port(data->monitor_port); |
835 | gamma_table_base = data->gamma; | |
ddd3d905 | 836 | |
9b53a9e2 YS |
837 | /* Prep for DIU init - gamma table, cursor table */ |
838 | ||
839 | for (i = 0; i <= 2; i++) | |
4a85dc8b TT |
840 | for (j = 0; j <= 255; j++) |
841 | *gamma_table_base++ = j; | |
9b53a9e2 | 842 | |
b7795052 | 843 | diu_ops.set_gamma_table(data->monitor_port, data->gamma); |
9b53a9e2 | 844 | |
9b53a9e2 YS |
845 | disable_lcdc(info); |
846 | ||
847 | /* Program DIU registers */ | |
848 | ||
b7795052 TT |
849 | out_be32(&hw->gamma, DMA_ADDR(data, gamma)); |
850 | out_be32(&hw->cursor, DMA_ADDR(data, cursor)); | |
9b53a9e2 YS |
851 | |
852 | out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */ | |
853 | out_be32(&hw->bgnd_wb, 0); /* BGND_WB */ | |
854 | out_be32(&hw->disp_size, (var->yres << 16 | var->xres)); | |
855 | /* DISP SIZE */ | |
9b53a9e2 YS |
856 | out_be32(&hw->wb_size, 0); /* WB SIZE */ |
857 | out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */ | |
858 | ||
859 | /* Horizontal and vertical configuration register */ | |
860 | temp = var->left_margin << 22 | /* BP_H */ | |
861 | var->hsync_len << 11 | /* PW_H */ | |
862 | var->right_margin; /* FP_H */ | |
863 | ||
864 | out_be32(&hw->hsyn_para, temp); | |
865 | ||
866 | temp = var->upper_margin << 22 | /* BP_V */ | |
867 | var->vsync_len << 11 | /* PW_V */ | |
868 | var->lower_margin; /* FP_V */ | |
869 | ||
870 | out_be32(&hw->vsyn_para, temp); | |
871 | ||
9b53a9e2 YS |
872 | diu_ops.set_pixel_clock(var->pixclock); |
873 | ||
874 | out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */ | |
875 | out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */ | |
876 | out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */ | |
877 | out_be32(&hw->plut, 0x01F5F666); | |
878 | ||
879 | /* Enable the DIU */ | |
880 | enable_lcdc(info); | |
881 | } | |
882 | ||
883 | static int map_video_memory(struct fb_info *info) | |
884 | { | |
885 | phys_addr_t phys; | |
537a1bf0 | 886 | u32 smem_len = info->fix.line_length * info->var.yres_virtual; |
9b53a9e2 | 887 | |
537a1bf0 | 888 | info->screen_base = fsl_diu_alloc(smem_len, &phys); |
05946bce | 889 | if (info->screen_base == NULL) { |
154152ae | 890 | dev_err(info->dev, "unable to allocate fb memory\n"); |
9b53a9e2 YS |
891 | return -ENOMEM; |
892 | } | |
537a1bf0 | 893 | mutex_lock(&info->mm_lock); |
9b53a9e2 | 894 | info->fix.smem_start = (unsigned long) phys; |
537a1bf0 KH |
895 | info->fix.smem_len = smem_len; |
896 | mutex_unlock(&info->mm_lock); | |
9b53a9e2 YS |
897 | info->screen_size = info->fix.smem_len; |
898 | ||
9b53a9e2 YS |
899 | return 0; |
900 | } | |
901 | ||
902 | static void unmap_video_memory(struct fb_info *info) | |
903 | { | |
904 | fsl_diu_free(info->screen_base, info->fix.smem_len); | |
537a1bf0 | 905 | mutex_lock(&info->mm_lock); |
05946bce | 906 | info->screen_base = NULL; |
9b53a9e2 YS |
907 | info->fix.smem_start = 0; |
908 | info->fix.smem_len = 0; | |
537a1bf0 | 909 | mutex_unlock(&info->mm_lock); |
9b53a9e2 YS |
910 | } |
911 | ||
ae5591e3 YS |
912 | /* |
913 | * Using the fb_var_screeninfo in fb_info we set the aoi of this | |
914 | * particular framebuffer. It is a light version of fsl_diu_set_par. | |
915 | */ | |
916 | static int fsl_diu_set_aoi(struct fb_info *info) | |
917 | { | |
918 | struct fb_var_screeninfo *var = &info->var; | |
919 | struct mfb_info *mfbi = info->par; | |
920 | struct diu_ad *ad = mfbi->ad; | |
921 | ||
922 | /* AOI should not be greater than display size */ | |
923 | ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset); | |
924 | ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d); | |
925 | return 0; | |
926 | } | |
927 | ||
9b53a9e2 YS |
928 | /* |
929 | * Using the fb_var_screeninfo in fb_info we set the resolution of this | |
930 | * particular framebuffer. This function alters the fb_fix_screeninfo stored | |
931 | * in fb_info. It does not alter var in fb_info since we are using that | |
932 | * data. This means we depend on the data in var inside fb_info to be | |
933 | * supported by the hardware. fsl_diu_check_var is always called before | |
934 | * fsl_diu_set_par to ensure this. | |
935 | */ | |
936 | static int fsl_diu_set_par(struct fb_info *info) | |
937 | { | |
938 | unsigned long len; | |
939 | struct fb_var_screeninfo *var = &info->var; | |
940 | struct mfb_info *mfbi = info->par; | |
b7795052 | 941 | struct fsl_diu_data *data = mfbi->parent; |
9b53a9e2 | 942 | struct diu_ad *ad = mfbi->ad; |
3c755b7c | 943 | struct diu __iomem *hw; |
9b53a9e2 | 944 | |
b7795052 | 945 | hw = data->diu_reg; |
9b53a9e2 YS |
946 | |
947 | set_fix(info); | |
948 | mfbi->cursor_reset = 1; | |
949 | ||
950 | len = info->var.yres_virtual * info->fix.line_length; | |
951 | /* Alloc & dealloc each time resolution/bpp change */ | |
952 | if (len != info->fix.smem_len) { | |
953 | if (info->fix.smem_start) | |
954 | unmap_video_memory(info); | |
9b53a9e2 YS |
955 | |
956 | /* Memory allocation for framebuffer */ | |
957 | if (map_video_memory(info)) { | |
154152ae | 958 | dev_err(info->dev, "unable to allocate fb memory 1\n"); |
9b53a9e2 YS |
959 | return -ENOMEM; |
960 | } | |
961 | } | |
962 | ||
b7795052 | 963 | ad->pix_fmt = diu_ops.get_pixel_format(data->monitor_port, |
7653aaab | 964 | var->bits_per_pixel); |
9b53a9e2 | 965 | ad->addr = cpu_to_le32(info->fix.smem_start); |
ae5591e3 YS |
966 | ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) | |
967 | var->xres_virtual) | mfbi->g_alpha; | |
968 | /* AOI should not be greater than display size */ | |
9b53a9e2 | 969 | ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres); |
ae5591e3 | 970 | ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset); |
9b53a9e2 YS |
971 | ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d); |
972 | ||
973 | /* Disable chroma keying function */ | |
974 | ad->ckmax_r = 0; | |
975 | ad->ckmax_g = 0; | |
976 | ad->ckmax_b = 0; | |
977 | ||
978 | ad->ckmin_r = 255; | |
979 | ad->ckmin_g = 255; | |
980 | ad->ckmin_b = 255; | |
981 | ||
2572df91 | 982 | if (mfbi->index == PLANE0) |
9b53a9e2 YS |
983 | update_lcdc(info); |
984 | return 0; | |
985 | } | |
986 | ||
987 | static inline __u32 CNVT_TOHW(__u32 val, __u32 width) | |
988 | { | |
4a85dc8b | 989 | return ((val << width) + 0x7FFF - val) >> 16; |
9b53a9e2 YS |
990 | } |
991 | ||
992 | /* | |
993 | * Set a single color register. The values supplied have a 16 bit magnitude | |
994 | * which needs to be scaled in this function for the hardware. Things to take | |
995 | * into consideration are how many color registers, if any, are supported with | |
996 | * the current color visual. With truecolor mode no color palettes are | |
25985edc | 997 | * supported. Here a pseudo palette is created which we store the value in |
9b53a9e2 YS |
998 | * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited |
999 | * color palette. | |
1000 | */ | |
4a85dc8b TT |
1001 | static int fsl_diu_setcolreg(unsigned int regno, unsigned int red, |
1002 | unsigned int green, unsigned int blue, | |
1003 | unsigned int transp, struct fb_info *info) | |
9b53a9e2 YS |
1004 | { |
1005 | int ret = 1; | |
1006 | ||
1007 | /* | |
1008 | * If greyscale is true, then we convert the RGB value | |
1009 | * to greyscale no matter what visual we are using. | |
1010 | */ | |
1011 | if (info->var.grayscale) | |
1012 | red = green = blue = (19595 * red + 38470 * green + | |
1013 | 7471 * blue) >> 16; | |
1014 | switch (info->fix.visual) { | |
1015 | case FB_VISUAL_TRUECOLOR: | |
1016 | /* | |
1017 | * 16-bit True Colour. We encode the RGB value | |
1018 | * according to the RGB bitfield information. | |
1019 | */ | |
1020 | if (regno < 16) { | |
1021 | u32 *pal = info->pseudo_palette; | |
1022 | u32 v; | |
1023 | ||
1024 | red = CNVT_TOHW(red, info->var.red.length); | |
1025 | green = CNVT_TOHW(green, info->var.green.length); | |
1026 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
1027 | transp = CNVT_TOHW(transp, info->var.transp.length); | |
1028 | ||
1029 | v = (red << info->var.red.offset) | | |
1030 | (green << info->var.green.offset) | | |
1031 | (blue << info->var.blue.offset) | | |
1032 | (transp << info->var.transp.offset); | |
1033 | ||
1034 | pal[regno] = v; | |
1035 | ret = 0; | |
1036 | } | |
1037 | break; | |
9b53a9e2 YS |
1038 | } |
1039 | ||
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Pan (or wrap, depending on the `vmode' field) the display using the | |
1045 | * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values | |
1046 | * don't fit, return -EINVAL. | |
1047 | */ | |
1048 | static int fsl_diu_pan_display(struct fb_var_screeninfo *var, | |
1049 | struct fb_info *info) | |
1050 | { | |
1051 | if ((info->var.xoffset == var->xoffset) && | |
1052 | (info->var.yoffset == var->yoffset)) | |
1053 | return 0; /* No change, do nothing */ | |
1054 | ||
1055 | if (var->xoffset < 0 || var->yoffset < 0 | |
1056 | || var->xoffset + info->var.xres > info->var.xres_virtual | |
1057 | || var->yoffset + info->var.yres > info->var.yres_virtual) | |
1058 | return -EINVAL; | |
1059 | ||
1060 | info->var.xoffset = var->xoffset; | |
1061 | info->var.yoffset = var->yoffset; | |
1062 | ||
1063 | if (var->vmode & FB_VMODE_YWRAP) | |
1064 | info->var.vmode |= FB_VMODE_YWRAP; | |
1065 | else | |
1066 | info->var.vmode &= ~FB_VMODE_YWRAP; | |
1067 | ||
ae5591e3 YS |
1068 | fsl_diu_set_aoi(info); |
1069 | ||
9b53a9e2 YS |
1070 | return 0; |
1071 | } | |
1072 | ||
9b53a9e2 YS |
1073 | static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd, |
1074 | unsigned long arg) | |
1075 | { | |
1076 | struct mfb_info *mfbi = info->par; | |
1077 | struct diu_ad *ad = mfbi->ad; | |
1078 | struct mfb_chroma_key ck; | |
1079 | unsigned char global_alpha; | |
1080 | struct aoi_display_offset aoi_d; | |
1081 | __u32 pix_fmt; | |
1082 | void __user *buf = (void __user *)arg; | |
1083 | ||
1084 | if (!arg) | |
1085 | return -EINVAL; | |
1086 | switch (cmd) { | |
36b0b1d4 TT |
1087 | case MFB_SET_PIXFMT_OLD: |
1088 | dev_warn(info->dev, | |
1089 | "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n", | |
1090 | MFB_SET_PIXFMT_OLD); | |
9b53a9e2 YS |
1091 | case MFB_SET_PIXFMT: |
1092 | if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt))) | |
1093 | return -EFAULT; | |
1094 | ad->pix_fmt = pix_fmt; | |
9b53a9e2 | 1095 | break; |
36b0b1d4 TT |
1096 | case MFB_GET_PIXFMT_OLD: |
1097 | dev_warn(info->dev, | |
1098 | "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n", | |
1099 | MFB_GET_PIXFMT_OLD); | |
9b53a9e2 YS |
1100 | case MFB_GET_PIXFMT: |
1101 | pix_fmt = ad->pix_fmt; | |
1102 | if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt))) | |
1103 | return -EFAULT; | |
9b53a9e2 YS |
1104 | break; |
1105 | case MFB_SET_AOID: | |
1106 | if (copy_from_user(&aoi_d, buf, sizeof(aoi_d))) | |
1107 | return -EFAULT; | |
1108 | mfbi->x_aoi_d = aoi_d.x_aoi_d; | |
1109 | mfbi->y_aoi_d = aoi_d.y_aoi_d; | |
9b53a9e2 | 1110 | fsl_diu_check_var(&info->var, info); |
ae5591e3 | 1111 | fsl_diu_set_aoi(info); |
9b53a9e2 YS |
1112 | break; |
1113 | case MFB_GET_AOID: | |
1114 | aoi_d.x_aoi_d = mfbi->x_aoi_d; | |
1115 | aoi_d.y_aoi_d = mfbi->y_aoi_d; | |
1116 | if (copy_to_user(buf, &aoi_d, sizeof(aoi_d))) | |
1117 | return -EFAULT; | |
9b53a9e2 YS |
1118 | break; |
1119 | case MFB_GET_ALPHA: | |
1120 | global_alpha = mfbi->g_alpha; | |
1121 | if (copy_to_user(buf, &global_alpha, sizeof(global_alpha))) | |
1122 | return -EFAULT; | |
9b53a9e2 YS |
1123 | break; |
1124 | case MFB_SET_ALPHA: | |
1125 | /* set panel information */ | |
1126 | if (copy_from_user(&global_alpha, buf, sizeof(global_alpha))) | |
1127 | return -EFAULT; | |
1128 | ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) | | |
1129 | (global_alpha & 0xff); | |
1130 | mfbi->g_alpha = global_alpha; | |
9b53a9e2 YS |
1131 | break; |
1132 | case MFB_SET_CHROMA_KEY: | |
1133 | /* set panel winformation */ | |
1134 | if (copy_from_user(&ck, buf, sizeof(ck))) | |
1135 | return -EFAULT; | |
1136 | ||
1137 | if (ck.enable && | |
1138 | (ck.red_max < ck.red_min || | |
1139 | ck.green_max < ck.green_min || | |
1140 | ck.blue_max < ck.blue_min)) | |
1141 | return -EINVAL; | |
1142 | ||
1143 | if (!ck.enable) { | |
1144 | ad->ckmax_r = 0; | |
1145 | ad->ckmax_g = 0; | |
1146 | ad->ckmax_b = 0; | |
1147 | ad->ckmin_r = 255; | |
1148 | ad->ckmin_g = 255; | |
1149 | ad->ckmin_b = 255; | |
1150 | } else { | |
1151 | ad->ckmax_r = ck.red_max; | |
1152 | ad->ckmax_g = ck.green_max; | |
1153 | ad->ckmax_b = ck.blue_max; | |
1154 | ad->ckmin_r = ck.red_min; | |
1155 | ad->ckmin_g = ck.green_min; | |
1156 | ad->ckmin_b = ck.blue_min; | |
1157 | } | |
9b53a9e2 | 1158 | break; |
9b53a9e2 | 1159 | default: |
154152ae | 1160 | dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd); |
9b53a9e2 YS |
1161 | return -ENOIOCTLCMD; |
1162 | } | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /* turn on fb if count == 1 | |
1168 | */ | |
1169 | static int fsl_diu_open(struct fb_info *info, int user) | |
1170 | { | |
1171 | struct mfb_info *mfbi = info->par; | |
1172 | int res = 0; | |
1173 | ||
4b5006ec | 1174 | /* free boot splash memory on first /dev/fb0 open */ |
2572df91 | 1175 | if ((mfbi->index == PLANE0) && diu_ops.release_bootmem) |
4b5006ec AG |
1176 | diu_ops.release_bootmem(); |
1177 | ||
9b53a9e2 YS |
1178 | spin_lock(&diu_lock); |
1179 | mfbi->count++; | |
1180 | if (mfbi->count == 1) { | |
9b53a9e2 YS |
1181 | fsl_diu_check_var(&info->var, info); |
1182 | res = fsl_diu_set_par(info); | |
1183 | if (res < 0) | |
1184 | mfbi->count--; | |
7e47c211 TT |
1185 | else |
1186 | fsl_diu_enable_panel(info); | |
9b53a9e2 YS |
1187 | } |
1188 | ||
1189 | spin_unlock(&diu_lock); | |
1190 | return res; | |
1191 | } | |
1192 | ||
1193 | /* turn off fb if count == 0 | |
1194 | */ | |
1195 | static int fsl_diu_release(struct fb_info *info, int user) | |
1196 | { | |
1197 | struct mfb_info *mfbi = info->par; | |
1198 | int res = 0; | |
1199 | ||
1200 | spin_lock(&diu_lock); | |
1201 | mfbi->count--; | |
2572df91 TT |
1202 | if (mfbi->count == 0) |
1203 | fsl_diu_disable_panel(info); | |
1204 | ||
9b53a9e2 YS |
1205 | spin_unlock(&diu_lock); |
1206 | return res; | |
1207 | } | |
1208 | ||
1209 | static struct fb_ops fsl_diu_ops = { | |
1210 | .owner = THIS_MODULE, | |
1211 | .fb_check_var = fsl_diu_check_var, | |
1212 | .fb_set_par = fsl_diu_set_par, | |
1213 | .fb_setcolreg = fsl_diu_setcolreg, | |
9b53a9e2 YS |
1214 | .fb_pan_display = fsl_diu_pan_display, |
1215 | .fb_fillrect = cfb_fillrect, | |
1216 | .fb_copyarea = cfb_copyarea, | |
1217 | .fb_imageblit = cfb_imageblit, | |
1218 | .fb_ioctl = fsl_diu_ioctl, | |
1219 | .fb_open = fsl_diu_open, | |
1220 | .fb_release = fsl_diu_release, | |
1221 | }; | |
1222 | ||
05946bce | 1223 | static int __devinit install_fb(struct fb_info *info) |
9b53a9e2 YS |
1224 | { |
1225 | int rc; | |
1226 | struct mfb_info *mfbi = info->par; | |
1227 | const char *aoi_mode, *init_aoi_mode = "320x240"; | |
8b856f04 AG |
1228 | struct fb_videomode *db = fsl_diu_mode_db; |
1229 | unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db); | |
1230 | int has_default_mode = 1; | |
9b53a9e2 | 1231 | |
f934fbd6 TT |
1232 | info->var.activate = FB_ACTIVATE_NOW; |
1233 | info->fbops = &fsl_diu_ops; | |
1234 | info->flags = FBINFO_DEFAULT; | |
1235 | info->pseudo_palette = mfbi->pseudo_palette; | |
1236 | ||
1237 | rc = fb_alloc_cmap(&info->cmap, 16, 0); | |
1238 | if (rc) | |
1239 | return rc; | |
9b53a9e2 | 1240 | |
2572df91 | 1241 | if (mfbi->index == PLANE0) { |
8b856f04 AG |
1242 | if (mfbi->edid_data) { |
1243 | /* Now build modedb from EDID */ | |
1244 | fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs); | |
1245 | fb_videomode_to_modelist(info->monspecs.modedb, | |
1246 | info->monspecs.modedb_len, | |
1247 | &info->modelist); | |
1248 | db = info->monspecs.modedb; | |
1249 | dbsize = info->monspecs.modedb_len; | |
1250 | } | |
9b53a9e2 | 1251 | aoi_mode = fb_mode; |
8b856f04 | 1252 | } else { |
9b53a9e2 | 1253 | aoi_mode = init_aoi_mode; |
8b856f04 | 1254 | } |
63cf8df4 TT |
1255 | rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL, |
1256 | default_bpp); | |
154152ae | 1257 | if (!rc) { |
8b856f04 AG |
1258 | /* |
1259 | * For plane 0 we continue and look into | |
1260 | * driver's internal modedb. | |
1261 | */ | |
2572df91 | 1262 | if ((mfbi->index == PLANE0) && mfbi->edid_data) |
8b856f04 AG |
1263 | has_default_mode = 0; |
1264 | else | |
1265 | return -EINVAL; | |
9b53a9e2 YS |
1266 | } |
1267 | ||
8b856f04 AG |
1268 | if (!has_default_mode) { |
1269 | rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db, | |
63cf8df4 TT |
1270 | ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp); |
1271 | if (rc) | |
8b856f04 AG |
1272 | has_default_mode = 1; |
1273 | } | |
1274 | ||
1275 | /* Still not found, use preferred mode from database if any */ | |
1276 | if (!has_default_mode && info->monspecs.modedb) { | |
1277 | struct fb_monspecs *specs = &info->monspecs; | |
1278 | struct fb_videomode *modedb = &specs->modedb[0]; | |
1279 | ||
1280 | /* | |
1281 | * Get preferred timing. If not found, | |
1282 | * first mode in database will be used. | |
1283 | */ | |
1284 | if (specs->misc & FB_MISC_1ST_DETAIL) { | |
1285 | int i; | |
1286 | ||
1287 | for (i = 0; i < specs->modedb_len; i++) { | |
1288 | if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { | |
1289 | modedb = &specs->modedb[i]; | |
1290 | break; | |
1291 | } | |
1292 | } | |
1293 | } | |
1294 | ||
1295 | info->var.bits_per_pixel = default_bpp; | |
1296 | fb_videomode_to_var(&info->var, modedb); | |
1297 | } | |
1298 | ||
9b53a9e2 | 1299 | if (fsl_diu_check_var(&info->var, info)) { |
154152ae | 1300 | dev_err(info->dev, "fsl_diu_check_var failed\n"); |
589c7971 | 1301 | unmap_video_memory(info); |
9b53a9e2 YS |
1302 | fb_dealloc_cmap(&info->cmap); |
1303 | return -EINVAL; | |
1304 | } | |
1305 | ||
9b53a9e2 | 1306 | if (register_framebuffer(info) < 0) { |
154152ae | 1307 | dev_err(info->dev, "register_framebuffer failed\n"); |
9b53a9e2 YS |
1308 | unmap_video_memory(info); |
1309 | fb_dealloc_cmap(&info->cmap); | |
1310 | return -EINVAL; | |
1311 | } | |
1312 | ||
1313 | mfbi->registered = 1; | |
154152ae | 1314 | dev_info(info->dev, "%s registered successfully\n", mfbi->id); |
9b53a9e2 YS |
1315 | |
1316 | return 0; | |
1317 | } | |
1318 | ||
05946bce | 1319 | static void uninstall_fb(struct fb_info *info) |
9b53a9e2 YS |
1320 | { |
1321 | struct mfb_info *mfbi = info->par; | |
1322 | ||
1323 | if (!mfbi->registered) | |
1324 | return; | |
1325 | ||
2572df91 | 1326 | if (mfbi->index == PLANE0) |
8b856f04 AG |
1327 | kfree(mfbi->edid_data); |
1328 | ||
9b53a9e2 YS |
1329 | unregister_framebuffer(info); |
1330 | unmap_video_memory(info); | |
1331 | if (&info->cmap) | |
1332 | fb_dealloc_cmap(&info->cmap); | |
1333 | ||
1334 | mfbi->registered = 0; | |
1335 | } | |
1336 | ||
1337 | static irqreturn_t fsl_diu_isr(int irq, void *dev_id) | |
1338 | { | |
3c755b7c | 1339 | struct diu __iomem *hw = dev_id; |
9b53a9e2 YS |
1340 | unsigned int status = in_be32(&hw->int_status); |
1341 | ||
1342 | if (status) { | |
1343 | /* This is the workaround for underrun */ | |
1344 | if (status & INT_UNDRUN) { | |
1345 | out_be32(&hw->diu_mode, 0); | |
9b53a9e2 YS |
1346 | udelay(1); |
1347 | out_be32(&hw->diu_mode, 1); | |
1348 | } | |
1349 | #if defined(CONFIG_NOT_COHERENT_CACHE) | |
1350 | else if (status & INT_VSYNC) { | |
1351 | unsigned int i; | |
4a85dc8b | 1352 | |
9b53a9e2 YS |
1353 | for (i = 0; i < coherence_data_size; |
1354 | i += d_cache_line_size) | |
1355 | __asm__ __volatile__ ( | |
1356 | "dcbz 0, %[input]" | |
1357 | ::[input]"r"(&coherence_data[i])); | |
1358 | } | |
1359 | #endif | |
1360 | return IRQ_HANDLED; | |
1361 | } | |
1362 | return IRQ_NONE; | |
1363 | } | |
1364 | ||
b7795052 | 1365 | static int request_irq_local(struct fsl_diu_data *data) |
9b53a9e2 | 1366 | { |
b7795052 | 1367 | struct diu __iomem *hw = data->diu_reg; |
bada04fc | 1368 | u32 ints; |
9b53a9e2 YS |
1369 | int ret; |
1370 | ||
9b53a9e2 | 1371 | /* Read to clear the status */ |
bada04fc | 1372 | in_be32(&hw->int_status); |
9b53a9e2 | 1373 | |
b7795052 | 1374 | ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb", hw); |
154152ae | 1375 | if (!ret) { |
9b53a9e2 YS |
1376 | ints = INT_PARERR | INT_LS_BF_VS; |
1377 | #if !defined(CONFIG_NOT_COHERENT_CACHE) | |
1378 | ints |= INT_VSYNC; | |
1379 | #endif | |
4a85dc8b | 1380 | |
9b53a9e2 | 1381 | /* Read to clear the status */ |
bada04fc | 1382 | in_be32(&hw->int_status); |
9b53a9e2 YS |
1383 | out_be32(&hw->int_mask, ints); |
1384 | } | |
4a85dc8b | 1385 | |
9b53a9e2 YS |
1386 | return ret; |
1387 | } | |
1388 | ||
b7795052 | 1389 | static void free_irq_local(struct fsl_diu_data *data) |
9b53a9e2 | 1390 | { |
b7795052 | 1391 | struct diu __iomem *hw = data->diu_reg; |
9b53a9e2 YS |
1392 | |
1393 | /* Disable all LCDC interrupt */ | |
1394 | out_be32(&hw->int_mask, 0x1f); | |
1395 | ||
b7795052 | 1396 | free_irq(data->irq, NULL); |
9b53a9e2 YS |
1397 | } |
1398 | ||
1399 | #ifdef CONFIG_PM | |
1400 | /* | |
1401 | * Power management hooks. Note that we won't be called from IRQ context, | |
1402 | * unlike the blank functions above, so we may sleep. | |
1403 | */ | |
2dc11581 | 1404 | static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state) |
9b53a9e2 | 1405 | { |
b7795052 | 1406 | struct fsl_diu_data *data; |
9b53a9e2 | 1407 | |
b7795052 TT |
1408 | data = dev_get_drvdata(&ofdev->dev); |
1409 | disable_lcdc(data->fsl_diu_info[0]); | |
9b53a9e2 YS |
1410 | |
1411 | return 0; | |
1412 | } | |
1413 | ||
2dc11581 | 1414 | static int fsl_diu_resume(struct platform_device *ofdev) |
9b53a9e2 | 1415 | { |
b7795052 | 1416 | struct fsl_diu_data *data; |
9b53a9e2 | 1417 | |
b7795052 TT |
1418 | data = dev_get_drvdata(&ofdev->dev); |
1419 | enable_lcdc(data->fsl_diu_info[0]); | |
9b53a9e2 YS |
1420 | |
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | #else | |
1425 | #define fsl_diu_suspend NULL | |
1426 | #define fsl_diu_resume NULL | |
1427 | #endif /* CONFIG_PM */ | |
1428 | ||
9b53a9e2 YS |
1429 | static ssize_t store_monitor(struct device *device, |
1430 | struct device_attribute *attr, const char *buf, size_t count) | |
1431 | { | |
7653aaab | 1432 | enum fsl_diu_monitor_port old_monitor_port; |
b7795052 | 1433 | struct fsl_diu_data *data = |
9b53a9e2 YS |
1434 | container_of(attr, struct fsl_diu_data, dev_attr); |
1435 | ||
b7795052 TT |
1436 | old_monitor_port = data->monitor_port; |
1437 | data->monitor_port = fsl_diu_name_to_port(buf); | |
9b53a9e2 | 1438 | |
b7795052 | 1439 | if (old_monitor_port != data->monitor_port) { |
9b53a9e2 YS |
1440 | /* All AOIs need adjust pixel format |
1441 | * fsl_diu_set_par only change the pixsel format here | |
1442 | * unlikely to fail. */ | |
ddd3d905 TT |
1443 | unsigned int i; |
1444 | ||
1445 | for (i=0; i < NUM_AOIS; i++) | |
b7795052 | 1446 | fsl_diu_set_par(&data->fsl_diu_info[i]); |
9b53a9e2 YS |
1447 | } |
1448 | return count; | |
1449 | } | |
1450 | ||
1451 | static ssize_t show_monitor(struct device *device, | |
1452 | struct device_attribute *attr, char *buf) | |
1453 | { | |
b7795052 | 1454 | struct fsl_diu_data *data = |
9b53a9e2 | 1455 | container_of(attr, struct fsl_diu_data, dev_attr); |
7653aaab | 1456 | |
b7795052 | 1457 | switch (data->monitor_port) { |
7653aaab TT |
1458 | case FSL_DIU_PORT_DVI: |
1459 | return sprintf(buf, "DVI\n"); | |
1460 | case FSL_DIU_PORT_LVDS: | |
1461 | return sprintf(buf, "Single-link LVDS\n"); | |
1462 | case FSL_DIU_PORT_DLVDS: | |
1463 | return sprintf(buf, "Dual-link LVDS\n"); | |
1464 | } | |
1465 | ||
1466 | return 0; | |
9b53a9e2 YS |
1467 | } |
1468 | ||
9e52ba61 | 1469 | static int __devinit fsl_diu_probe(struct platform_device *pdev) |
9b53a9e2 | 1470 | { |
9e52ba61 | 1471 | struct device_node *np = pdev->dev.of_node; |
9b53a9e2 | 1472 | struct mfb_info *mfbi; |
b7795052 | 1473 | struct fsl_diu_data *data; |
4b5006ec | 1474 | int diu_mode; |
b7795052 | 1475 | dma_addr_t dma_addr; /* DMA addr of fsl_diu_data struct */ |
ddd3d905 TT |
1476 | unsigned int i; |
1477 | int ret; | |
9b53a9e2 | 1478 | |
b7795052 TT |
1479 | data = dma_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data), |
1480 | &dma_addr, GFP_DMA | __GFP_ZERO); | |
1481 | if (!data) | |
9b53a9e2 | 1482 | return -ENOMEM; |
b7795052 | 1483 | data->dma_addr = dma_addr; |
ddd3d905 TT |
1484 | |
1485 | /* | |
1486 | * dma_alloc_coherent() uses a page allocator, so the address is | |
1487 | * always page-aligned. We need the memory to be 32-byte aligned, | |
1488 | * so that's good. However, if one day the allocator changes, we | |
1489 | * need to catch that. It's not worth the effort to handle unaligned | |
1490 | * alloctions now because it's highly unlikely to ever be a problem. | |
1491 | */ | |
b7795052 | 1492 | if ((unsigned long)data & 31) { |
ddd3d905 TT |
1493 | dev_err(&pdev->dev, "misaligned allocation"); |
1494 | ret = -ENOMEM; | |
1495 | goto error; | |
1496 | } | |
9b53a9e2 | 1497 | |
b7795052 | 1498 | spin_lock_init(&data->reg_lock); |
3c755b7c | 1499 | |
ddd3d905 | 1500 | for (i = 0; i < NUM_AOIS; i++) { |
b7795052 | 1501 | struct fb_info *info = &data->fsl_diu_info[i]; |
ddd3d905 TT |
1502 | |
1503 | info->device = &pdev->dev; | |
b7795052 | 1504 | info->par = &data->mfb[i]; |
ddd3d905 TT |
1505 | |
1506 | /* | |
1507 | * We store the physical address of the AD in the reserved | |
1508 | * 'paddr' field of the AD itself. | |
1509 | */ | |
b7795052 | 1510 | data->ad[i].paddr = DMA_ADDR(data, ad[i]); |
ddd3d905 TT |
1511 | |
1512 | info->fix.smem_start = 0; | |
1513 | ||
1514 | /* Initialize the AOI data structure */ | |
1515 | mfbi = info->par; | |
9b53a9e2 | 1516 | memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info)); |
b7795052 TT |
1517 | mfbi->parent = data; |
1518 | mfbi->ad = &data->ad[i]; | |
8b856f04 | 1519 | |
2572df91 | 1520 | if (mfbi->index == PLANE0) { |
8b856f04 AG |
1521 | const u8 *prop; |
1522 | int len; | |
1523 | ||
1524 | /* Get EDID */ | |
1525 | prop = of_get_property(np, "edid", &len); | |
1526 | if (prop && len == EDID_LENGTH) | |
1527 | mfbi->edid_data = kmemdup(prop, EDID_LENGTH, | |
1528 | GFP_KERNEL); | |
1529 | } | |
9b53a9e2 YS |
1530 | } |
1531 | ||
b7795052 TT |
1532 | data->diu_reg = of_iomap(np, 0); |
1533 | if (!data->diu_reg) { | |
9e52ba61 | 1534 | dev_err(&pdev->dev, "cannot map DIU registers\n"); |
9b53a9e2 | 1535 | ret = -EFAULT; |
ddd3d905 | 1536 | goto error; |
9b53a9e2 YS |
1537 | } |
1538 | ||
b7795052 | 1539 | diu_mode = in_be32(&data->diu_reg->diu_mode); |
c4e5a023 | 1540 | if (diu_mode == MFB_MODE0) |
b7795052 | 1541 | out_be32(&data->diu_reg->diu_mode, 0); /* disable DIU */ |
9b53a9e2 YS |
1542 | |
1543 | /* Get the IRQ of the DIU */ | |
b7795052 | 1544 | data->irq = irq_of_parse_and_map(np, 0); |
9b53a9e2 | 1545 | |
b7795052 | 1546 | if (!data->irq) { |
9e52ba61 | 1547 | dev_err(&pdev->dev, "could not get DIU IRQ\n"); |
9b53a9e2 YS |
1548 | ret = -EINVAL; |
1549 | goto error; | |
1550 | } | |
b7795052 | 1551 | data->monitor_port = monitor_port; |
9b53a9e2 | 1552 | |
ddd3d905 | 1553 | /* Initialize the dummy Area Descriptor */ |
b7795052 TT |
1554 | data->dummy_ad.addr = cpu_to_le32(DMA_ADDR(data, dummy_aoi)); |
1555 | data->dummy_ad.pix_fmt = 0x88882317; | |
1556 | data->dummy_ad.src_size_g_alpha = cpu_to_le32((4 << 12) | 4); | |
1557 | data->dummy_ad.aoi_size = cpu_to_le32((4 << 16) | 2); | |
1558 | data->dummy_ad.offset_xyi = 0; | |
1559 | data->dummy_ad.offset_xyd = 0; | |
1560 | data->dummy_ad.next_ad = 0; | |
1561 | data->dummy_ad.paddr = DMA_ADDR(data, dummy_ad); | |
9b53a9e2 | 1562 | |
4b5006ec AG |
1563 | /* |
1564 | * Let DIU display splash screen if it was pre-initialized | |
1565 | * by the bootloader, set dummy area descriptor otherwise. | |
1566 | */ | |
c4e5a023 | 1567 | if (diu_mode == MFB_MODE0) |
b7795052 | 1568 | out_be32(&data->diu_reg->desc[0], data->dummy_ad.paddr); |
ddd3d905 | 1569 | |
b7795052 TT |
1570 | out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr); |
1571 | out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr); | |
ddd3d905 TT |
1572 | |
1573 | for (i = 0; i < NUM_AOIS; i++) { | |
b7795052 | 1574 | ret = install_fb(&data->fsl_diu_info[i]); |
9b53a9e2 | 1575 | if (ret) { |
9e52ba61 | 1576 | dev_err(&pdev->dev, "could not register fb %d\n", i); |
9b53a9e2 YS |
1577 | goto error; |
1578 | } | |
1579 | } | |
1580 | ||
b7795052 | 1581 | if (request_irq_local(data)) { |
9e52ba61 | 1582 | dev_err(&pdev->dev, "could not claim irq\n"); |
9b53a9e2 YS |
1583 | goto error; |
1584 | } | |
1585 | ||
b7795052 TT |
1586 | sysfs_attr_init(&data->dev_attr.attr); |
1587 | data->dev_attr.attr.name = "monitor"; | |
1588 | data->dev_attr.attr.mode = S_IRUGO|S_IWUSR; | |
1589 | data->dev_attr.show = show_monitor; | |
1590 | data->dev_attr.store = store_monitor; | |
1591 | ret = device_create_file(&pdev->dev, &data->dev_attr); | |
ddd3d905 | 1592 | if (ret) { |
9e52ba61 | 1593 | dev_err(&pdev->dev, "could not create sysfs file %s\n", |
b7795052 | 1594 | data->dev_attr.attr.name); |
9b53a9e2 YS |
1595 | } |
1596 | ||
b7795052 | 1597 | dev_set_drvdata(&pdev->dev, data); |
9b53a9e2 YS |
1598 | return 0; |
1599 | ||
1600 | error: | |
ddd3d905 | 1601 | for (i = 0; i < NUM_AOIS; i++) |
b7795052 | 1602 | uninstall_fb(&data->fsl_diu_info[i]); |
ddd3d905 | 1603 | |
b7795052 | 1604 | iounmap(data->diu_reg); |
9b53a9e2 | 1605 | |
b7795052 TT |
1606 | dma_free_coherent(&pdev->dev, sizeof(struct fsl_diu_data), data, |
1607 | data->dma_addr); | |
9b53a9e2 YS |
1608 | |
1609 | return ret; | |
1610 | } | |
1611 | ||
9e52ba61 | 1612 | static int fsl_diu_remove(struct platform_device *pdev) |
9b53a9e2 | 1613 | { |
b7795052 | 1614 | struct fsl_diu_data *data; |
9b53a9e2 YS |
1615 | int i; |
1616 | ||
b7795052 TT |
1617 | data = dev_get_drvdata(&pdev->dev); |
1618 | disable_lcdc(&data->fsl_diu_info[0]); | |
1619 | free_irq_local(data); | |
ddd3d905 TT |
1620 | |
1621 | for (i = 0; i < NUM_AOIS; i++) | |
b7795052 | 1622 | uninstall_fb(&data->fsl_diu_info[i]); |
ddd3d905 | 1623 | |
b7795052 | 1624 | iounmap(data->diu_reg); |
ddd3d905 | 1625 | |
b7795052 TT |
1626 | dma_free_coherent(&pdev->dev, sizeof(struct fsl_diu_data), data, |
1627 | data->dma_addr); | |
9b53a9e2 YS |
1628 | |
1629 | return 0; | |
1630 | } | |
1631 | ||
1632 | #ifndef MODULE | |
1633 | static int __init fsl_diu_setup(char *options) | |
1634 | { | |
1635 | char *opt; | |
1636 | unsigned long val; | |
1637 | ||
1638 | if (!options || !*options) | |
1639 | return 0; | |
1640 | ||
1641 | while ((opt = strsep(&options, ",")) != NULL) { | |
1642 | if (!*opt) | |
1643 | continue; | |
1644 | if (!strncmp(opt, "monitor=", 8)) { | |
7653aaab | 1645 | monitor_port = fsl_diu_name_to_port(opt + 8); |
9b53a9e2 YS |
1646 | } else if (!strncmp(opt, "bpp=", 4)) { |
1647 | if (!strict_strtoul(opt + 4, 10, &val)) | |
1648 | default_bpp = val; | |
1649 | } else | |
1650 | fb_mode = opt; | |
1651 | } | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | #endif | |
1656 | ||
1657 | static struct of_device_id fsl_diu_match[] = { | |
d24720a4 AG |
1658 | #ifdef CONFIG_PPC_MPC512x |
1659 | { | |
1660 | .compatible = "fsl,mpc5121-diu", | |
1661 | }, | |
1662 | #endif | |
9b53a9e2 YS |
1663 | { |
1664 | .compatible = "fsl,diu", | |
1665 | }, | |
1666 | {} | |
1667 | }; | |
1668 | MODULE_DEVICE_TABLE(of, fsl_diu_match); | |
1669 | ||
28541d0f | 1670 | static struct platform_driver fsl_diu_driver = { |
4018294b | 1671 | .driver = { |
f8c6bf6a | 1672 | .name = "fsl-diu-fb", |
4018294b GL |
1673 | .owner = THIS_MODULE, |
1674 | .of_match_table = fsl_diu_match, | |
1675 | }, | |
9b53a9e2 YS |
1676 | .probe = fsl_diu_probe, |
1677 | .remove = fsl_diu_remove, | |
1678 | .suspend = fsl_diu_suspend, | |
1679 | .resume = fsl_diu_resume, | |
1680 | }; | |
1681 | ||
1682 | static int __init fsl_diu_init(void) | |
1683 | { | |
1684 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
1685 | struct device_node *np; | |
1686 | const u32 *prop; | |
1687 | #endif | |
1688 | int ret; | |
1689 | #ifndef MODULE | |
1690 | char *option; | |
1691 | ||
1692 | /* | |
1693 | * For kernel boot options (in 'video=xxxfb:<options>' format) | |
1694 | */ | |
1695 | if (fb_get_options("fslfb", &option)) | |
1696 | return -ENODEV; | |
1697 | fsl_diu_setup(option); | |
7653aaab TT |
1698 | #else |
1699 | monitor_port = fsl_diu_name_to_port(monitor_string); | |
9b53a9e2 | 1700 | #endif |
154152ae | 1701 | pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n"); |
9b53a9e2 YS |
1702 | |
1703 | #ifdef CONFIG_NOT_COHERENT_CACHE | |
1704 | np = of_find_node_by_type(NULL, "cpu"); | |
1705 | if (!np) { | |
154152ae | 1706 | pr_err("fsl-diu-fb: can't find 'cpu' device node\n"); |
9b53a9e2 YS |
1707 | return -ENODEV; |
1708 | } | |
1709 | ||
1710 | prop = of_get_property(np, "d-cache-size", NULL); | |
5394ba0f | 1711 | if (prop == NULL) { |
154152ae TT |
1712 | pr_err("fsl-diu-fb: missing 'd-cache-size' property' " |
1713 | "in 'cpu' node\n"); | |
5394ba0f | 1714 | of_node_put(np); |
9b53a9e2 | 1715 | return -ENODEV; |
5394ba0f | 1716 | } |
9b53a9e2 | 1717 | |
4a85dc8b TT |
1718 | /* |
1719 | * Freescale PLRU requires 13/8 times the cache size to do a proper | |
1720 | * displacement flush | |
9b53a9e2 | 1721 | */ |
9e52ba61 | 1722 | coherence_data_size = be32_to_cpup(prop) * 13; |
9b53a9e2 YS |
1723 | coherence_data_size /= 8; |
1724 | ||
1725 | prop = of_get_property(np, "d-cache-line-size", NULL); | |
5394ba0f | 1726 | if (prop == NULL) { |
154152ae TT |
1727 | pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' " |
1728 | "in 'cpu' node\n"); | |
5394ba0f | 1729 | of_node_put(np); |
9b53a9e2 | 1730 | return -ENODEV; |
5394ba0f | 1731 | } |
9e52ba61 | 1732 | d_cache_line_size = be32_to_cpup(prop); |
9b53a9e2 YS |
1733 | |
1734 | of_node_put(np); | |
1735 | coherence_data = vmalloc(coherence_data_size); | |
1736 | if (!coherence_data) | |
1737 | return -ENOMEM; | |
1738 | #endif | |
4a85dc8b | 1739 | |
28541d0f | 1740 | ret = platform_driver_register(&fsl_diu_driver); |
9b53a9e2 | 1741 | if (ret) { |
154152ae | 1742 | pr_err("fsl-diu-fb: failed to register platform driver\n"); |
9b53a9e2 YS |
1743 | #if defined(CONFIG_NOT_COHERENT_CACHE) |
1744 | vfree(coherence_data); | |
1745 | #endif | |
9b53a9e2 YS |
1746 | } |
1747 | return ret; | |
1748 | } | |
1749 | ||
1750 | static void __exit fsl_diu_exit(void) | |
1751 | { | |
28541d0f | 1752 | platform_driver_unregister(&fsl_diu_driver); |
9b53a9e2 YS |
1753 | #if defined(CONFIG_NOT_COHERENT_CACHE) |
1754 | vfree(coherence_data); | |
1755 | #endif | |
1756 | } | |
1757 | ||
1758 | module_init(fsl_diu_init); | |
1759 | module_exit(fsl_diu_exit); | |
1760 | ||
1761 | MODULE_AUTHOR("York Sun <yorksun@freescale.com>"); | |
1762 | MODULE_DESCRIPTION("Freescale DIU framebuffer driver"); | |
1763 | MODULE_LICENSE("GPL"); | |
1764 | ||
1765 | module_param_named(mode, fb_mode, charp, 0); | |
1766 | MODULE_PARM_DESC(mode, | |
1767 | "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); | |
1768 | module_param_named(bpp, default_bpp, ulong, 0); | |
154152ae | 1769 | MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'"); |
7653aaab TT |
1770 | module_param_named(monitor, monitor_string, charp, 0); |
1771 | MODULE_PARM_DESC(monitor, "Specify the monitor port " | |
1772 | "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform"); | |
9b53a9e2 | 1773 |