Commit | Line | Data |
---|---|---|
fc4effc7 DV |
1 | /* |
2 | * Geode GX framebuffer driver. | |
3 | * | |
4 | * Copyright (C) 2006 Arcom Control Systems Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * | |
12 | * This driver assumes that the BIOS has created a virtual PCI device header | |
13 | * for the video device. The PCI header is assumed to contain the following | |
14 | * BARs: | |
15 | * | |
16 | * BAR0 - framebuffer memory | |
17 | * BAR1 - graphics processor registers | |
18 | * BAR2 - display controller registers | |
19 | * BAR3 - video processor and flat panel control registers. | |
20 | * | |
21 | * 16 MiB of framebuffer memory is assumed to be available. | |
22 | */ | |
23 | #include <linux/module.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/mm.h> | |
fc4effc7 DV |
28 | #include <linux/delay.h> |
29 | #include <linux/fb.h> | |
46fb6f11 | 30 | #include <linux/console.h> |
b6f448e9 | 31 | #include <linux/suspend.h> |
fc4effc7 DV |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
f3a57a60 | 34 | #include <linux/cs5535.h> |
fc4effc7 | 35 | |
ab06aaf6 | 36 | #include "gxfb.h" |
fc4effc7 | 37 | |
16ef9870 | 38 | static char *mode_option; |
fa20c8a6 | 39 | static int vram; |
b6f448e9 | 40 | static int vt_switch; |
fc4effc7 DV |
41 | |
42 | /* Modes relevant to the GX (taken from modedb.c) */ | |
500ebb82 | 43 | static struct fb_videomode gx_modedb[] __devinitdata = { |
fc4effc7 DV |
44 | /* 640x480-60 VESA */ |
45 | { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, | |
46 | 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
47 | /* 640x480-75 VESA */ | |
48 | { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, | |
49 | 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
50 | /* 640x480-85 VESA */ | |
51 | { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, | |
52 | 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
53 | /* 800x600-60 VESA */ | |
54 | { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, | |
55 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
56 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
57 | /* 800x600-75 VESA */ | |
58 | { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, | |
59 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
60 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
61 | /* 800x600-85 VESA */ | |
62 | { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, | |
63 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
64 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
65 | /* 1024x768-60 VESA */ | |
66 | { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, | |
67 | 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
68 | /* 1024x768-75 VESA */ | |
69 | { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, | |
70 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
71 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
72 | /* 1024x768-85 VESA */ | |
73 | { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, | |
74 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
75 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
76 | /* 1280x960-60 VESA */ | |
77 | { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, | |
78 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
79 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
80 | /* 1280x960-85 VESA */ | |
81 | { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, | |
82 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
83 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
84 | /* 1280x1024-60 VESA */ | |
85 | { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, | |
86 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
87 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
88 | /* 1280x1024-75 VESA */ | |
89 | { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, | |
90 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
91 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
92 | /* 1280x1024-85 VESA */ | |
93 | { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, | |
94 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
95 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
96 | /* 1600x1200-60 VESA */ | |
97 | { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, | |
98 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
99 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
100 | /* 1600x1200-75 VESA */ | |
101 | { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, | |
102 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
103 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
104 | /* 1600x1200-85 VESA */ | |
105 | { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, | |
106 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
107 | FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, | |
108 | }; | |
109 | ||
3553a2fa AS |
110 | #ifdef CONFIG_OLPC |
111 | #include <asm/olpc.h> | |
112 | ||
500ebb82 | 113 | static struct fb_videomode gx_dcon_modedb[] __devinitdata = { |
3553a2fa AS |
114 | /* The only mode the DCON has is 1200x900 */ |
115 | { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3, | |
116 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
117 | FB_VMODE_NONINTERLACED, 0 } | |
118 | }; | |
119 | ||
500ebb82 AS |
120 | static void __devinit get_modedb(struct fb_videomode **modedb, |
121 | unsigned int *size) | |
3553a2fa AS |
122 | { |
123 | if (olpc_has_dcon()) { | |
124 | *modedb = (struct fb_videomode *) gx_dcon_modedb; | |
125 | *size = ARRAY_SIZE(gx_dcon_modedb); | |
126 | } else { | |
127 | *modedb = (struct fb_videomode *) gx_modedb; | |
128 | *size = ARRAY_SIZE(gx_modedb); | |
129 | } | |
130 | } | |
131 | ||
132 | #else | |
500ebb82 AS |
133 | static void __devinit get_modedb(struct fb_videomode **modedb, |
134 | unsigned int *size) | |
3553a2fa AS |
135 | { |
136 | *modedb = (struct fb_videomode *) gx_modedb; | |
137 | *size = ARRAY_SIZE(gx_modedb); | |
138 | } | |
139 | #endif | |
140 | ||
fc4effc7 DV |
141 | static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
142 | { | |
143 | if (var->xres > 1600 || var->yres > 1200) | |
144 | return -EINVAL; | |
145 | if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16) | |
146 | return -EINVAL; | |
147 | ||
148 | if (var->bits_per_pixel == 32) { | |
149 | var->red.offset = 16; var->red.length = 8; | |
150 | var->green.offset = 8; var->green.length = 8; | |
151 | var->blue.offset = 0; var->blue.length = 8; | |
152 | } else if (var->bits_per_pixel == 16) { | |
153 | var->red.offset = 11; var->red.length = 5; | |
154 | var->green.offset = 5; var->green.length = 6; | |
155 | var->blue.offset = 0; var->blue.length = 5; | |
156 | } else if (var->bits_per_pixel == 8) { | |
157 | var->red.offset = 0; var->red.length = 8; | |
158 | var->green.offset = 0; var->green.length = 8; | |
159 | var->blue.offset = 0; var->blue.length = 8; | |
160 | } else | |
161 | return -EINVAL; | |
162 | var->transp.offset = 0; var->transp.length = 0; | |
163 | ||
164 | /* Enough video memory? */ | |
165 | if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len) | |
166 | return -EINVAL; | |
167 | ||
168 | /* FIXME: Check timing parameters here? */ | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
173 | static int gxfb_set_par(struct fb_info *info) | |
174 | { | |
b14caecd | 175 | if (info->var.bits_per_pixel > 8) |
fc4effc7 | 176 | info->fix.visual = FB_VISUAL_TRUECOLOR; |
b14caecd | 177 | else |
fc4effc7 | 178 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
fc4effc7 DV |
179 | |
180 | info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel); | |
181 | ||
d1b4cc3e | 182 | gx_set_mode(info); |
fc4effc7 DV |
183 | |
184 | return 0; | |
185 | } | |
186 | ||
187 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
188 | { | |
189 | chan &= 0xffff; | |
190 | chan >>= 16 - bf->length; | |
191 | return chan << bf->offset; | |
192 | } | |
193 | ||
194 | static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
195 | unsigned blue, unsigned transp, | |
196 | struct fb_info *info) | |
197 | { | |
fc4effc7 DV |
198 | if (info->var.grayscale) { |
199 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ | |
200 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; | |
201 | } | |
202 | ||
203 | /* Truecolor has hardware independent palette */ | |
204 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
205 | u32 *pal = info->pseudo_palette; | |
206 | u32 v; | |
207 | ||
208 | if (regno >= 16) | |
209 | return -EINVAL; | |
210 | ||
211 | v = chan_to_field(red, &info->var.red); | |
212 | v |= chan_to_field(green, &info->var.green); | |
213 | v |= chan_to_field(blue, &info->var.blue); | |
214 | ||
215 | pal[regno] = v; | |
216 | } else { | |
217 | if (regno >= 256) | |
218 | return -EINVAL; | |
219 | ||
d1b4cc3e | 220 | gx_set_hw_palette_reg(info, regno, red, green, blue); |
fc4effc7 DV |
221 | } |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static int gxfb_blank(int blank_mode, struct fb_info *info) | |
227 | { | |
d1b4cc3e | 228 | return gx_blank_display(info, blank_mode); |
fc4effc7 DV |
229 | } |
230 | ||
500ebb82 AS |
231 | static int __devinit gxfb_map_video_memory(struct fb_info *info, |
232 | struct pci_dev *dev) | |
fc4effc7 | 233 | { |
d1b4cc3e | 234 | struct gxfb_par *par = info->par; |
fc4effc7 DV |
235 | int ret; |
236 | ||
237 | ret = pci_enable_device(dev); | |
238 | if (ret < 0) | |
239 | return ret; | |
240 | ||
241 | ret = pci_request_region(dev, 3, "gxfb (video processor)"); | |
242 | if (ret < 0) | |
243 | return ret; | |
3c36aa5c | 244 | par->vid_regs = pci_ioremap_bar(dev, 3); |
fc4effc7 DV |
245 | if (!par->vid_regs) |
246 | return -ENOMEM; | |
247 | ||
248 | ret = pci_request_region(dev, 2, "gxfb (display controller)"); | |
249 | if (ret < 0) | |
250 | return ret; | |
3c36aa5c | 251 | par->dc_regs = pci_ioremap_bar(dev, 2); |
fc4effc7 DV |
252 | if (!par->dc_regs) |
253 | return -ENOMEM; | |
254 | ||
46fb6f11 AS |
255 | ret = pci_request_region(dev, 1, "gxfb (graphics processor)"); |
256 | if (ret < 0) | |
257 | return ret; | |
3c36aa5c | 258 | par->gp_regs = pci_ioremap_bar(dev, 1); |
46fb6f11 AS |
259 | |
260 | if (!par->gp_regs) | |
261 | return -ENOMEM; | |
262 | ||
fc4effc7 DV |
263 | ret = pci_request_region(dev, 0, "gxfb (framebuffer)"); |
264 | if (ret < 0) | |
265 | return ret; | |
fa20c8a6 | 266 | |
fc4effc7 | 267 | info->fix.smem_start = pci_resource_start(dev, 0); |
fa20c8a6 | 268 | info->fix.smem_len = vram ? vram : gx_frame_buffer_size(); |
fc4effc7 DV |
269 | info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); |
270 | if (!info->screen_base) | |
271 | return -ENOMEM; | |
272 | ||
fa20c8a6 | 273 | /* Set the 16MiB aligned base address of the graphics memory region |
f378819a JC |
274 | * in the display controller */ |
275 | ||
ab06aaf6 | 276 | write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000); |
f378819a | 277 | |
fa20c8a6 | 278 | dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n", |
fc4effc7 DV |
279 | info->fix.smem_len / 1024, info->fix.smem_start); |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
284 | static struct fb_ops gxfb_ops = { | |
285 | .owner = THIS_MODULE, | |
286 | .fb_check_var = gxfb_check_var, | |
287 | .fb_set_par = gxfb_set_par, | |
288 | .fb_setcolreg = gxfb_setcolreg, | |
289 | .fb_blank = gxfb_blank, | |
290 | /* No HW acceleration for now. */ | |
291 | .fb_fillrect = cfb_fillrect, | |
292 | .fb_copyarea = cfb_copyarea, | |
293 | .fb_imageblit = cfb_imageblit, | |
294 | }; | |
295 | ||
500ebb82 | 296 | static struct fb_info *__devinit gxfb_init_fbinfo(struct device *dev) |
fc4effc7 | 297 | { |
d1b4cc3e | 298 | struct gxfb_par *par; |
fc4effc7 DV |
299 | struct fb_info *info; |
300 | ||
301 | /* Alloc enough space for the pseudo palette. */ | |
d1b4cc3e AS |
302 | info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16, |
303 | dev); | |
fc4effc7 DV |
304 | if (!info) |
305 | return NULL; | |
306 | ||
307 | par = info->par; | |
308 | ||
309 | strcpy(info->fix.id, "Geode GX"); | |
310 | ||
311 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
312 | info->fix.type_aux = 0; | |
313 | info->fix.xpanstep = 0; | |
314 | info->fix.ypanstep = 0; | |
315 | info->fix.ywrapstep = 0; | |
316 | info->fix.accel = FB_ACCEL_NONE; | |
317 | ||
318 | info->var.nonstd = 0; | |
319 | info->var.activate = FB_ACTIVATE_NOW; | |
320 | info->var.height = -1; | |
321 | info->var.width = -1; | |
322 | info->var.accel_flags = 0; | |
323 | info->var.vmode = FB_VMODE_NONINTERLACED; | |
324 | ||
325 | info->fbops = &gxfb_ops; | |
326 | info->flags = FBINFO_DEFAULT; | |
327 | info->node = -1; | |
328 | ||
d1b4cc3e | 329 | info->pseudo_palette = (void *)par + sizeof(struct gxfb_par); |
fc4effc7 DV |
330 | |
331 | info->var.grayscale = 0; | |
332 | ||
b14caecd AS |
333 | if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { |
334 | framebuffer_release(info); | |
335 | return NULL; | |
336 | } | |
337 | ||
fc4effc7 DV |
338 | return info; |
339 | } | |
340 | ||
46fb6f11 AS |
341 | #ifdef CONFIG_PM |
342 | static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state) | |
343 | { | |
344 | struct fb_info *info = pci_get_drvdata(pdev); | |
345 | ||
346 | if (state.event == PM_EVENT_SUSPEND) { | |
347 | acquire_console_sem(); | |
348 | gx_powerdown(info); | |
349 | fb_set_suspend(info, 1); | |
350 | release_console_sem(); | |
351 | } | |
352 | ||
353 | /* there's no point in setting PCI states; we emulate PCI, so | |
354 | * we don't end up getting power savings anyways */ | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int gxfb_resume(struct pci_dev *pdev) | |
360 | { | |
361 | struct fb_info *info = pci_get_drvdata(pdev); | |
362 | int ret; | |
363 | ||
364 | acquire_console_sem(); | |
365 | ret = gx_powerup(info); | |
366 | if (ret) { | |
367 | printk(KERN_ERR "gxfb: power up failed!\n"); | |
368 | return ret; | |
369 | } | |
370 | ||
371 | fb_set_suspend(info, 0); | |
372 | release_console_sem(); | |
373 | return 0; | |
374 | } | |
375 | #endif | |
376 | ||
500ebb82 AS |
377 | static int __devinit gxfb_probe(struct pci_dev *pdev, |
378 | const struct pci_device_id *id) | |
fc4effc7 | 379 | { |
d1b4cc3e | 380 | struct gxfb_par *par; |
fc4effc7 DV |
381 | struct fb_info *info; |
382 | int ret; | |
ab1db0cf | 383 | unsigned long val; |
fc4effc7 | 384 | |
3553a2fa AS |
385 | struct fb_videomode *modedb_ptr; |
386 | unsigned int modedb_size; | |
387 | ||
fc4effc7 DV |
388 | info = gxfb_init_fbinfo(&pdev->dev); |
389 | if (!info) | |
390 | return -ENOMEM; | |
391 | par = info->par; | |
392 | ||
fc4effc7 DV |
393 | if ((ret = gxfb_map_video_memory(info, pdev)) < 0) { |
394 | dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n"); | |
395 | goto err; | |
396 | } | |
397 | ||
ab1db0cf JC |
398 | /* Figure out if this is a TFT or CRT part */ |
399 | ||
32bf87e3 | 400 | rdmsrl(MSR_GX_GLD_MSR_CONFIG, val); |
ab1db0cf | 401 | |
9f1277bd | 402 | if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP) |
ab1db0cf JC |
403 | par->enable_crt = 0; |
404 | else | |
405 | par->enable_crt = 1; | |
406 | ||
3553a2fa | 407 | get_modedb(&modedb_ptr, &modedb_size); |
fc4effc7 | 408 | ret = fb_find_mode(&info->var, info, mode_option, |
3553a2fa | 409 | modedb_ptr, modedb_size, NULL, 16); |
fc4effc7 DV |
410 | if (ret == 0 || ret == 4) { |
411 | dev_err(&pdev->dev, "could not find valid video mode\n"); | |
412 | ret = -EINVAL; | |
413 | goto err; | |
414 | } | |
415 | ||
16ef9870 JC |
416 | |
417 | /* Clear the frame buffer of garbage. */ | |
fc4effc7 DV |
418 | memset_io(info->screen_base, 0, info->fix.smem_len); |
419 | ||
420 | gxfb_check_var(&info->var, info); | |
421 | gxfb_set_par(info); | |
422 | ||
b6f448e9 AS |
423 | pm_set_vt_switch(vt_switch); |
424 | ||
fc4effc7 DV |
425 | if (register_framebuffer(info) < 0) { |
426 | ret = -EINVAL; | |
427 | goto err; | |
428 | } | |
429 | pci_set_drvdata(pdev, info); | |
430 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); | |
431 | return 0; | |
432 | ||
433 | err: | |
434 | if (info->screen_base) { | |
435 | iounmap(info->screen_base); | |
436 | pci_release_region(pdev, 0); | |
437 | } | |
438 | if (par->vid_regs) { | |
439 | iounmap(par->vid_regs); | |
440 | pci_release_region(pdev, 3); | |
441 | } | |
442 | if (par->dc_regs) { | |
443 | iounmap(par->dc_regs); | |
444 | pci_release_region(pdev, 2); | |
445 | } | |
46fb6f11 AS |
446 | if (par->gp_regs) { |
447 | iounmap(par->gp_regs); | |
448 | pci_release_region(pdev, 1); | |
449 | } | |
fc4effc7 | 450 | |
b14caecd AS |
451 | if (info) { |
452 | fb_dealloc_cmap(&info->cmap); | |
fc4effc7 | 453 | framebuffer_release(info); |
b14caecd | 454 | } |
fc4effc7 DV |
455 | return ret; |
456 | } | |
457 | ||
500ebb82 | 458 | static void __devexit gxfb_remove(struct pci_dev *pdev) |
fc4effc7 DV |
459 | { |
460 | struct fb_info *info = pci_get_drvdata(pdev); | |
d1b4cc3e | 461 | struct gxfb_par *par = info->par; |
fc4effc7 DV |
462 | |
463 | unregister_framebuffer(info); | |
464 | ||
465 | iounmap((void __iomem *)info->screen_base); | |
466 | pci_release_region(pdev, 0); | |
467 | ||
468 | iounmap(par->vid_regs); | |
469 | pci_release_region(pdev, 3); | |
470 | ||
471 | iounmap(par->dc_regs); | |
472 | pci_release_region(pdev, 2); | |
473 | ||
46fb6f11 AS |
474 | iounmap(par->gp_regs); |
475 | pci_release_region(pdev, 1); | |
476 | ||
b14caecd | 477 | fb_dealloc_cmap(&info->cmap); |
fc4effc7 DV |
478 | pci_set_drvdata(pdev, NULL); |
479 | ||
480 | framebuffer_release(info); | |
481 | } | |
482 | ||
483 | static struct pci_device_id gxfb_id_table[] = { | |
0a5e7909 | 484 | { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) }, |
fc4effc7 DV |
485 | { 0, } |
486 | }; | |
487 | ||
488 | MODULE_DEVICE_TABLE(pci, gxfb_id_table); | |
489 | ||
490 | static struct pci_driver gxfb_driver = { | |
491 | .name = "gxfb", | |
492 | .id_table = gxfb_id_table, | |
493 | .probe = gxfb_probe, | |
494 | .remove = gxfb_remove, | |
46fb6f11 AS |
495 | #ifdef CONFIG_PM |
496 | .suspend = gxfb_suspend, | |
497 | .resume = gxfb_resume, | |
498 | #endif | |
fc4effc7 DV |
499 | }; |
500 | ||
16ef9870 JC |
501 | #ifndef MODULE |
502 | static int __init gxfb_setup(char *options) | |
503 | { | |
504 | ||
505 | char *opt; | |
506 | ||
507 | if (!options || !*options) | |
508 | return 0; | |
509 | ||
510 | while ((opt = strsep(&options, ",")) != NULL) { | |
511 | if (!*opt) | |
512 | continue; | |
513 | ||
514 | mode_option = opt; | |
515 | } | |
516 | ||
517 | return 0; | |
518 | } | |
519 | #endif | |
520 | ||
fc4effc7 DV |
521 | static int __init gxfb_init(void) |
522 | { | |
523 | #ifndef MODULE | |
16ef9870 JC |
524 | char *option = NULL; |
525 | ||
526 | if (fb_get_options("gxfb", &option)) | |
fc4effc7 | 527 | return -ENODEV; |
16ef9870 JC |
528 | |
529 | gxfb_setup(option); | |
fc4effc7 DV |
530 | #endif |
531 | return pci_register_driver(&gxfb_driver); | |
532 | } | |
533 | ||
534 | static void __exit gxfb_cleanup(void) | |
535 | { | |
536 | pci_unregister_driver(&gxfb_driver); | |
537 | } | |
538 | ||
539 | module_init(gxfb_init); | |
540 | module_exit(gxfb_cleanup); | |
541 | ||
16ef9870 JC |
542 | module_param(mode_option, charp, 0); |
543 | MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])"); | |
fc4effc7 | 544 | |
fa20c8a6 AS |
545 | module_param(vram, int, 0); |
546 | MODULE_PARM_DESC(vram, "video memory size"); | |
547 | ||
b6f448e9 AS |
548 | module_param(vt_switch, int, 0); |
549 | MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume"); | |
550 | ||
fc4effc7 DV |
551 | MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX"); |
552 | MODULE_LICENSE("GPL"); |